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atomic.h: Work around gcc spurious "unused value" warning
[mirror_qemu.git] / tcg / tcg-op.h
CommitLineData
c896fe29
FB		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
951c6300 24
c896fe29 25#include "tcg.h"
944eea96 26#include "exec/helper-proto.h"
c017230d
RH		 27#include "exec/helper-gen.h"
28
951c6300 29/* Basic output routines. Not for general consumption. */
c896fe29 30
b7e8b17a
RH		 31void tcg_gen_op1(TCGOpcode, TCGArg);
32void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg);
33void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg);
34void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
35void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
36void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
951c6300 37
d2fd745f
RH		 38void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg);
39void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
40void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
41
951c6300 42static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
c896fe29 43{
ae8b75dc 44 tcg_gen_op1(opc, tcgv_i32_arg(a1));
a7812ae4
PB		 45}
46
951c6300 47static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
a7812ae4 48{
ae8b75dc 49 tcg_gen_op1(opc, tcgv_i64_arg(a1));
c896fe29
FB		 50}
51
951c6300 52static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
c896fe29 53{
b7e8b17a 54 tcg_gen_op1(opc, a1);
c896fe29
FB		 55}
56
951c6300 57static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
a7812ae4 58{
ae8b75dc 59 tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2));
a7812ae4
PB		 60}
61
951c6300 62static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
a7812ae4 63{
ae8b75dc 64 tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2));
a7812ae4
PB		 65}
66
951c6300 67static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
c896fe29 68{
ae8b75dc 69 tcg_gen_op2(opc, tcgv_i32_arg(a1), a2);
c896fe29
FB		 70}
71
951c6300 72static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
c896fe29 73{
ae8b75dc 74 tcg_gen_op2(opc, tcgv_i64_arg(a1), a2);
ac56dd48
PB		 75}
76
951c6300 77static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
bcb0126f 78{
b7e8b17a 79 tcg_gen_op2(opc, a1, a2);
bcb0126f
PB		 80}
81
951c6300
RH		 82static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
83 TCGv_i32 a2, TCGv_i32 a3)
a7812ae4 84{
ae8b75dc 85 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3));
a7812ae4
PB		 86}
87
951c6300
RH		 88static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
89 TCGv_i64 a2, TCGv_i64 a3)
a7812ae4 90{
ae8b75dc 91 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3));
a7812ae4
PB		 92}
93
951c6300
RH		 94static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
95 TCGv_i32 a2, TCGArg a3)
ac56dd48 96{
ae8b75dc 97 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3);
ac56dd48
PB		 98}
99
951c6300
RH		 100static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
101 TCGv_i64 a2, TCGArg a3)
ac56dd48 102{
ae8b75dc 103 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3);
ac56dd48
PB		 104}
105
a9751609
RH		 106static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
107 TCGv_ptr base, TCGArg offset)
a7812ae4 108{
ae8b75dc 109 tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset);
a7812ae4
PB		 110}
111
a9751609
RH		 112static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
113 TCGv_ptr base, TCGArg offset)
a7812ae4 114{
ae8b75dc 115 tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset);
a7812ae4
PB		 116}
117
951c6300
RH		 118static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
119 TCGv_i32 a3, TCGv_i32 a4)
a7812ae4 120{
ae8b75dc
RH		 121 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
122 tcgv_i32_arg(a3), tcgv_i32_arg(a4));
a7812ae4
PB		 123}
124
951c6300
RH		 125static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
126 TCGv_i64 a3, TCGv_i64 a4)
a7812ae4 127{
ae8b75dc
RH		 128 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
129 tcgv_i64_arg(a3), tcgv_i64_arg(a4));
a7812ae4
PB		 130}
131
951c6300
RH		 132static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
133 TCGv_i32 a3, TCGArg a4)
a7812ae4 134{
ae8b75dc
RH		 135 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
136 tcgv_i32_arg(a3), a4);
a7812ae4
PB		 137}
138
951c6300
RH		 139static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
140 TCGv_i64 a3, TCGArg a4)
ac56dd48 141{
ae8b75dc
RH		 142 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
143 tcgv_i64_arg(a3), a4);
ac56dd48
PB		 144}
145
951c6300
RH		 146static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
147 TCGArg a3, TCGArg a4)
ac56dd48 148{
ae8b75dc 149 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4);
c896fe29
FB		 150}
151
951c6300
RH		 152static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
153 TCGArg a3, TCGArg a4)
c896fe29 154{
ae8b75dc 155 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4);
ac56dd48
PB		 156}
157
951c6300
RH		 158static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
159 TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
a7812ae4 160{
ae8b75dc
RH		 161 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
162 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5));
a7812ae4
PB		 163}
164
951c6300
RH		 165static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
166 TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
a7812ae4 167{
ae8b75dc
RH		 168 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
169 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5));
a7812ae4
PB		 170}
171
951c6300
RH		 172static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
173 TCGv_i32 a3, TCGv_i32 a4, TCGArg a5)
ac56dd48 174{
ae8b75dc
RH		 175 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
176 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5);
ac56dd48
PB		 177}
178
951c6300
RH		 179static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
180 TCGv_i64 a3, TCGv_i64 a4, TCGArg a5)
ac56dd48 181{
ae8b75dc
RH		 182 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
183 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5);
c896fe29
FB		 184}
185
951c6300
RH		 186static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
187 TCGv_i32 a3, TCGArg a4, TCGArg a5)
b7767f0f 188{
ae8b75dc
RH		 189 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
190 tcgv_i32_arg(a3), a4, a5);
b7767f0f
RH		 191}
192
951c6300
RH		 193static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
194 TCGv_i64 a3, TCGArg a4, TCGArg a5)
b7767f0f 195{
ae8b75dc
RH		 196 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
197 tcgv_i64_arg(a3), a4, a5);
b7767f0f
RH		 198}
199
951c6300
RH		 200static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
201 TCGv_i32 a3, TCGv_i32 a4,
202 TCGv_i32 a5, TCGv_i32 a6)
a7812ae4 203{
ae8b75dc
RH		 204 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
205 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5),
206 tcgv_i32_arg(a6));
a7812ae4
PB		 207}
208
951c6300
RH		 209static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
210 TCGv_i64 a3, TCGv_i64 a4,
211 TCGv_i64 a5, TCGv_i64 a6)
c896fe29 212{
ae8b75dc
RH		 213 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
214 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5),
215 tcgv_i64_arg(a6));
ac56dd48
PB		 216}
217
951c6300
RH		 218static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
219 TCGv_i32 a3, TCGv_i32 a4,
220 TCGv_i32 a5, TCGArg a6)
be210acb 221{
ae8b75dc
RH		 222 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
223 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6);
be210acb
RH		 224}
225
951c6300
RH		 226static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
227 TCGv_i64 a3, TCGv_i64 a4,
228 TCGv_i64 a5, TCGArg a6)
be210acb 229{
ae8b75dc
RH		 230 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
231 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6);
be210acb
RH		 232}
233
951c6300
RH		 234static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
235 TCGv_i32 a3, TCGv_i32 a4,
236 TCGArg a5, TCGArg a6)
ac56dd48 237{
ae8b75dc
RH		 238 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
239 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6);
a7812ae4
PB		 240}
241
951c6300
RH		 242static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
243 TCGv_i64 a3, TCGv_i64 a4,
244 TCGArg a5, TCGArg a6)
a7812ae4 245{
ae8b75dc
RH		 246 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
247 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6);
c896fe29
FB		 248}
249
f713d6ad 250
951c6300
RH		 251/* Generic ops. */
252
42a268c2 253static inline void gen_set_label(TCGLabel *l)
c896fe29 254{
b7e8b17a 255 tcg_gen_op1(INDEX_op_set_label, label_arg(l));
c896fe29
FB		 256}
257
42a268c2 258static inline void tcg_gen_br(TCGLabel *l)
fb50d413 259{
b7e8b17a 260 tcg_gen_op1(INDEX_op_br, label_arg(l));
951c6300
RH		 261}
262
f65e19bc
PK		 263void tcg_gen_mb(TCGBar);
264
951c6300
RH		 265/* Helper calls. */
266
267/* 32 bit ops */
268
269void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
270void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2);
271void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
474b2e8f 272void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
951c6300
RH		 273void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
274void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
474b2e8f
RH		 275void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
276void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
277void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
951c6300
RH		 278void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
279void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
280void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
281void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
282void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
283void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
284void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
285void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
286void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
287void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
0e28d006
RH		 288void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
289void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
290void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
291void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
086920c2 292void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg);
a768e4e9 293void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2);
951c6300
RH		 294void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
295void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
296void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
297void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
298void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
299 unsigned int ofs, unsigned int len);
07cc68d5
RH		 300void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg,
301 unsigned int ofs, unsigned int len);
7ec8bab3
RH		 302void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
303 unsigned int ofs, unsigned int len);
304void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
305 unsigned int ofs, unsigned int len);
42a268c2
RH		 306void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
307void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
951c6300
RH		 308void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
309 TCGv_i32 arg1, TCGv_i32 arg2);
310void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
311 TCGv_i32 arg1, int32_t arg2);
312void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
313 TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2);
314void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
315 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
316void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
317 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
318void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
319void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
5087abfb 320void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
951c6300
RH		 321void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg);
322void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg);
323void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg);
324void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg);
325void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg);
326void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg);
327
328static inline void tcg_gen_discard_i32(TCGv_i32 arg)
329{
330 tcg_gen_op1_i32(INDEX_op_discard, arg);
fb50d413
BS		 331}
332
a7812ae4 333static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 334{
11f4e8f8 335 if (ret != arg) {
a7812ae4 336 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
951c6300 337 }
c896fe29
FB		 338}
339
a7812ae4 340static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
c896fe29 341{
a7812ae4 342 tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
c896fe29
FB		 343}
344
951c6300
RH		 345static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2,
346 tcg_target_long offset)
c896fe29 347{
a7812ae4 348 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
c896fe29
FB		 349}
350
951c6300
RH		 351static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2,
352 tcg_target_long offset)
c896fe29 353{
a7812ae4 354 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
c896fe29
FB		 355}
356
951c6300
RH		 357static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2,
358 tcg_target_long offset)
c896fe29 359{
a7812ae4 360 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
c896fe29
FB		 361}
362
951c6300
RH		 363static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2,
364 tcg_target_long offset)
c896fe29 365{
a7812ae4 366 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
c896fe29
FB		 367}
368
951c6300
RH		 369static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2,
370 tcg_target_long offset)
c896fe29 371{
a7812ae4 372 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
c896fe29
FB		 373}
374
951c6300
RH		 375static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2,
376 tcg_target_long offset)
c896fe29 377{
a7812ae4 378 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
c896fe29
FB		 379}
380
951c6300
RH		 381static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2,
382 tcg_target_long offset)
c896fe29 383{
a7812ae4 384 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
c896fe29
FB		 385}
386
951c6300
RH		 387static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2,
388 tcg_target_long offset)
c896fe29 389{
a7812ae4 390 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
c896fe29
FB		 391}
392
a7812ae4 393static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 394{
a7812ae4 395 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
c896fe29
FB		 396}
397
a7812ae4 398static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 399{
a7812ae4 400 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
c896fe29
FB		 401}
402
a7812ae4 403static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 404{
951c6300 405 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
c896fe29
FB		 406}
407
a7812ae4 408static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 409{
951c6300 410 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
c896fe29
FB		 411}
412
a7812ae4 413static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 414{
951c6300 415 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
c896fe29
FB		 416}
417
a7812ae4 418static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 419{
a7812ae4 420 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
c896fe29
FB		 421}
422
a7812ae4 423static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 424{
a7812ae4 425 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
c896fe29
FB		 426}
427
a7812ae4 428static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 429{
a7812ae4 430 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
c896fe29
FB		 431}
432
a7812ae4 433static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 434{
a7812ae4 435 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
c896fe29
FB		 436}
437
951c6300 438static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 439{
951c6300
RH		 440 if (TCG_TARGET_HAS_neg_i32) {
441 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
25c4d9cc 442 } else {
951c6300 443 tcg_gen_subfi_i32(ret, 0, arg);
25c4d9cc 444 }
31d66551
AJ		 445}
446
951c6300 447static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
31d66551 448{
951c6300
RH		 449 if (TCG_TARGET_HAS_not_i32) {
450 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
25c4d9cc 451 } else {
951c6300 452 tcg_gen_xori_i32(ret, arg, -1);
25c4d9cc 453 }
31d66551
AJ		 454}
455
951c6300
RH		 456/* 64 bit ops */
457
458void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
459void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2);
460void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474b2e8f 461void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
951c6300
RH		 462void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
463void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474b2e8f
RH		 464void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
465void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
466void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
951c6300
RH		 467void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
468void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
469void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
470void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
471void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
472void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
473void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
474void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
475void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
476void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
0e28d006
RH		 477void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
478void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
479void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
480void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
086920c2 481void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg);
a768e4e9 482void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2);
951c6300
RH		 483void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
484void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
485void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
486void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
487void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
488 unsigned int ofs, unsigned int len);
07cc68d5
RH		 489void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg,
490 unsigned int ofs, unsigned int len);
7ec8bab3
RH		 491void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
492 unsigned int ofs, unsigned int len);
493void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
494 unsigned int ofs, unsigned int len);
42a268c2
RH		 495void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
496void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
951c6300
RH		 497void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
498 TCGv_i64 arg1, TCGv_i64 arg2);
499void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
500 TCGv_i64 arg1, int64_t arg2);
501void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
502 TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2);
503void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
504 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
505void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
506 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
507void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
508void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
5087abfb 509void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
951c6300
RH		 510void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg);
511void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg);
512void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg);
513void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg);
514void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg);
515void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg);
516void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg);
517void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg);
518void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg);
519void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg);
c896fe29 520
951c6300
RH		 521#if TCG_TARGET_REG_BITS == 64
522static inline void tcg_gen_discard_i64(TCGv_i64 arg)
523{
524 tcg_gen_op1_i64(INDEX_op_discard, arg);
525}
c896fe29 526
a7812ae4 527static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 528{
11f4e8f8 529 if (ret != arg) {
951c6300 530 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
4d07272d 531 }
c896fe29
FB		 532}
533
a7812ae4 534static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
c896fe29 535{
951c6300 536 tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
c896fe29
FB		 537}
538
a7812ae4
PB		 539static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
540 tcg_target_long offset)
c896fe29 541{
951c6300 542 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
c896fe29
FB		 543}
544
a7812ae4
PB		 545static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
546 tcg_target_long offset)
c896fe29 547{
951c6300 548 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
c896fe29
FB		 549}
550
a7812ae4
PB		 551static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
552 tcg_target_long offset)
c896fe29 553{
951c6300 554 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
c896fe29
FB		 555}
556
a7812ae4
PB		 557static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
558 tcg_target_long offset)
c896fe29 559{
951c6300 560 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
c896fe29
FB		 561}
562
a7812ae4
PB		 563static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
564 tcg_target_long offset)
c896fe29 565{
951c6300 566 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
c896fe29
FB		 567}
568
a7812ae4
PB		 569static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
570 tcg_target_long offset)
c896fe29 571{
951c6300 572 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
c896fe29
FB		 573}
574
a7812ae4
PB		 575static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
576 tcg_target_long offset)
c896fe29 577{
951c6300 578 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
c896fe29
FB		 579}
580
a7812ae4
PB		 581static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
582 tcg_target_long offset)
c896fe29 583{
951c6300 584 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
c896fe29
FB		 585}
586
a7812ae4
PB		 587static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
588 tcg_target_long offset)
c896fe29 589{
951c6300 590 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
c896fe29
FB		 591}
592
a7812ae4
PB		 593static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
594 tcg_target_long offset)
c896fe29 595{
951c6300 596 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
c896fe29
FB		 597}
598
a7812ae4
PB		 599static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
600 tcg_target_long offset)
c896fe29 601{
951c6300 602 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
c896fe29
FB		 603}
604
a7812ae4 605static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 606{
951c6300 607 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
c896fe29
FB		 608}
609
a7812ae4 610static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 611{
951c6300 612 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
c896fe29
FB		 613}
614
a7812ae4 615static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 616{
951c6300 617 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
c896fe29
FB		 618}
619
a7812ae4 620static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 621{
951c6300 622 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
c896fe29
FB		 623}
624
a7812ae4 625static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 626{
951c6300 627 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
c896fe29
FB		 628}
629
a7812ae4 630static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 631{
951c6300 632 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
c896fe29
FB		 633}
634
a7812ae4 635static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 636{
951c6300 637 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
c896fe29
FB		 638}
639
a7812ae4 640static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 641{
951c6300 642 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
5105c556
AJ		 643}
644
a7812ae4 645static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 646{
951c6300 647 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
c896fe29 648}
951c6300
RH		 649#else /* TCG_TARGET_REG_BITS == 32 */
650static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
651 tcg_target_long offset)
c896fe29 652{
951c6300 653 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 654}
655
951c6300
RH		 656static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
657 tcg_target_long offset)
c896fe29 658{
951c6300 659 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 660}
661
951c6300
RH		 662static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
663 tcg_target_long offset)
c896fe29 664{
951c6300 665 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
c896fe29
FB		 666}
667
951c6300 668static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 669{
951c6300
RH		 670 tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
671 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
c896fe29
FB		 672}
673
951c6300 674static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 675{
951c6300
RH		 676 tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
677 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
678}
679
680void tcg_gen_discard_i64(TCGv_i64 arg);
681void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg);
682void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg);
683void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
684void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
685void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
686void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
687void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
688void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
689void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
690void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
691void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
692void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
693void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
694void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
695void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
696void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
697void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
698#endif /* TCG_TARGET_REG_BITS */
c896fe29 699
951c6300 700static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 701{
951c6300
RH		 702 if (TCG_TARGET_HAS_neg_i64) {
703 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
704 } else {
705 tcg_gen_subfi_i64(ret, 0, arg);
706 }
c896fe29
FB		 707}
708
951c6300 709/* Size changing operations. */
c896fe29 710
951c6300
RH		 711void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
712void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
713void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high);
609ad705
RH		 714void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
715void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
951c6300
RH		 716void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg);
717void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg);
c896fe29 718
951c6300 719static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
c896fe29 720{
951c6300 721 tcg_gen_deposit_i64(ret, lo, hi, 32, 32);
c896fe29
FB		 722}
723
951c6300 724/* QEMU specific operations. */
c896fe29 725
951c6300
RH		 726#ifndef TARGET_LONG_BITS
727#error must include QEMU headers
728#endif
c896fe29 729
9aef40ed
RH		 730#if TARGET_INSN_START_WORDS == 1
731# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
732static inline void tcg_gen_insn_start(target_ulong pc)
c896fe29 733{
b7e8b17a 734 tcg_gen_op1(INDEX_op_insn_start, pc);
9aef40ed
RH		 735}
736# else
737static inline void tcg_gen_insn_start(target_ulong pc)
738{
b7e8b17a 739 tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32));
9aef40ed
RH		 740}
741# endif
742#elif TARGET_INSN_START_WORDS == 2
743# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
744static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
745{
b7e8b17a 746 tcg_gen_op2(INDEX_op_insn_start, pc, a1);
9aef40ed
RH		 747}
748# else
749static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
750{
b7e8b17a 751 tcg_gen_op4(INDEX_op_insn_start,
9aef40ed
RH		 752 (uint32_t)pc, (uint32_t)(pc >> 32),
753 (uint32_t)a1, (uint32_t)(a1 >> 32));
754}
755# endif
756#elif TARGET_INSN_START_WORDS == 3
757# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
758static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
759 target_ulong a2)
760{
b7e8b17a 761 tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2);
9aef40ed
RH		 762}
763# else
764static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
765 target_ulong a2)
766{
b7e8b17a 767 tcg_gen_op6(INDEX_op_insn_start,
9aef40ed
RH		 768 (uint32_t)pc, (uint32_t)(pc >> 32),
769 (uint32_t)a1, (uint32_t)(a1 >> 32),
770 (uint32_t)a2, (uint32_t)(a2 >> 32));
771}
772# endif
951c6300 773#else
9aef40ed 774# error "Unhandled number of operands to insn_start"
951c6300 775#endif
c896fe29 776
951c6300 777static inline void tcg_gen_exit_tb(uintptr_t val)
c896fe29 778{
951c6300 779 tcg_gen_op1i(INDEX_op_exit_tb, val);
c896fe29
FB		 780}
781
5b053a4a
SF		 782/**
783 * tcg_gen_goto_tb() - output goto_tb TCG operation
784 * @idx: Direct jump slot index (0 or 1)
785 *
786 * See tcg/README for more info about this TCG operation.
787 *
90aa39a1
SF		 788 * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within
789 * the pages this TB resides in because we don't take care of direct jumps when
790 * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a
791 * static address translation, so the destination address is always valid, TBs
792 * are always invalidated properly, and direct jumps are reset when mapping
793 * changes.
5b053a4a 794 */
951c6300 795void tcg_gen_goto_tb(unsigned idx);
c896fe29 796
cedbcb01 797/**
7f11636d 798 * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid
cedbcb01
EC		 799 * @addr: Guest address of the target TB
800 *
801 * If the TB is not valid, jump to the epilogue.
802 *
803 * This operation is optional. If the TCG backend does not implement goto_ptr,
804 * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument.
805 */
7f11636d 806void tcg_gen_lookup_and_goto_ptr(void);
cedbcb01 807
a7812ae4 808#if TARGET_LONG_BITS == 32
a7812ae4
PB		 809#define tcg_temp_new() tcg_temp_new_i32()
810#define tcg_global_reg_new tcg_global_reg_new_i32
811#define tcg_global_mem_new tcg_global_mem_new_i32
df9247b2 812#define tcg_temp_local_new() tcg_temp_local_new_i32()
a7812ae4 813#define tcg_temp_free tcg_temp_free_i32
f713d6ad
RH		 814#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
815#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
a7812ae4 816#else
a7812ae4
PB		 817#define tcg_temp_new() tcg_temp_new_i64()
818#define tcg_global_reg_new tcg_global_reg_new_i64
819#define tcg_global_mem_new tcg_global_mem_new_i64
df9247b2 820#define tcg_temp_local_new() tcg_temp_local_new_i64()
a7812ae4 821#define tcg_temp_free tcg_temp_free_i64
f713d6ad
RH		 822#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
823#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
a7812ae4
PB		 824#endif
825
f713d6ad
RH		 826void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
827void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
828void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
829void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
c896fe29 830
ac56dd48 831static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
c896fe29 832{
f713d6ad 833 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
c896fe29
FB		 834}
835
ac56dd48 836static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
c896fe29 837{
f713d6ad 838 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
c896fe29
FB		 839}
840
ac56dd48 841static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
c896fe29 842{
f713d6ad 843 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
c896fe29
FB		 844}
845
ac56dd48 846static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
c896fe29 847{
f713d6ad 848 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
c896fe29
FB		 849}
850
ac56dd48 851static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
c896fe29 852{
f713d6ad 853 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
c896fe29
FB		 854}
855
ac56dd48 856static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
c896fe29 857{
f713d6ad 858 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
c896fe29
FB		 859}
860
a7812ae4 861static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
c896fe29 862{
f713d6ad 863 tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ);
c896fe29
FB		 864}
865
ac56dd48 866static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
c896fe29 867{
f713d6ad 868 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
c896fe29
FB		 869}
870
ac56dd48 871static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
c896fe29 872{
f713d6ad 873 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
c896fe29
FB		 874}
875
ac56dd48 876static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
c896fe29 877{
f713d6ad 878 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
c896fe29
FB		 879}
880
a7812ae4 881static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
c896fe29 882{
f713d6ad 883 tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ);
c896fe29
FB		 884}
885
c482cb11
RH		 886void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
887 TCGArg, TCGMemOp);
888void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
889 TCGArg, TCGMemOp);
890
891void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
892void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
893void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
894void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
895void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
896void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
897void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
898void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
899void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
900void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
901void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
902void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
903void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
904void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
905void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
906void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
907void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
908void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
909
d2fd745f
RH		 910void tcg_gen_mov_vec(TCGv_vec, TCGv_vec);
911void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32);
912void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64);
913void tcg_gen_dup8i_vec(TCGv_vec, uint32_t);
914void tcg_gen_dup16i_vec(TCGv_vec, uint32_t);
915void tcg_gen_dup32i_vec(TCGv_vec, uint32_t);
916void tcg_gen_dup64i_vec(TCGv_vec, uint64_t);
db432672 917void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t);
d2fd745f
RH		 918void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
919void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
3774030a 920void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
d2fd745f
RH		 921void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
922void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
923void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
924void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
925void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
926void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
927void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
928
d0ec9796
RH		 929void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
930void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
931void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
932
212be173
RH		 933void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
934 TCGv_vec a, TCGv_vec b);
935
d2fd745f
RH		 936void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
937void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
938void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
939
f8422f52 940#if TARGET_LONG_BITS == 64
f8422f52
BS		 941#define tcg_gen_movi_tl tcg_gen_movi_i64
942#define tcg_gen_mov_tl tcg_gen_mov_i64
943#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
944#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
945#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
946#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
947#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
948#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
949#define tcg_gen_ld_tl tcg_gen_ld_i64
950#define tcg_gen_st8_tl tcg_gen_st8_i64
951#define tcg_gen_st16_tl tcg_gen_st16_i64
952#define tcg_gen_st32_tl tcg_gen_st32_i64
953#define tcg_gen_st_tl tcg_gen_st_i64
954#define tcg_gen_add_tl tcg_gen_add_i64
955#define tcg_gen_addi_tl tcg_gen_addi_i64
956#define tcg_gen_sub_tl tcg_gen_sub_i64
390efc54 957#define tcg_gen_neg_tl tcg_gen_neg_i64
10460c8a 958#define tcg_gen_subfi_tl tcg_gen_subfi_i64
f8422f52
BS		 959#define tcg_gen_subi_tl tcg_gen_subi_i64
960#define tcg_gen_and_tl tcg_gen_and_i64
961#define tcg_gen_andi_tl tcg_gen_andi_i64
962#define tcg_gen_or_tl tcg_gen_or_i64
963#define tcg_gen_ori_tl tcg_gen_ori_i64
964#define tcg_gen_xor_tl tcg_gen_xor_i64
965#define tcg_gen_xori_tl tcg_gen_xori_i64
0b6ce4cf 966#define tcg_gen_not_tl tcg_gen_not_i64
f8422f52
BS		 967#define tcg_gen_shl_tl tcg_gen_shl_i64
968#define tcg_gen_shli_tl tcg_gen_shli_i64
969#define tcg_gen_shr_tl tcg_gen_shr_i64
970#define tcg_gen_shri_tl tcg_gen_shri_i64
971#define tcg_gen_sar_tl tcg_gen_sar_i64
972#define tcg_gen_sari_tl tcg_gen_sari_i64
0cf767d6 973#define tcg_gen_brcond_tl tcg_gen_brcond_i64
cb63669a 974#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
be210acb 975#define tcg_gen_setcond_tl tcg_gen_setcond_i64
add1e7ea 976#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
f730fd27
TS		 977#define tcg_gen_mul_tl tcg_gen_mul_i64
978#define tcg_gen_muli_tl tcg_gen_muli_i64
ab36421e
AJ		 979#define tcg_gen_div_tl tcg_gen_div_i64
980#define tcg_gen_rem_tl tcg_gen_rem_i64
864951af
AJ		 981#define tcg_gen_divu_tl tcg_gen_divu_i64
982#define tcg_gen_remu_tl tcg_gen_remu_i64
a768e4b2 983#define tcg_gen_discard_tl tcg_gen_discard_i64
ecc7b3aa 984#define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32
e429073d
BS		 985#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
986#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
987#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
988#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
989#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
0b6ce4cf
FB		 990#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
991#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
992#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
993#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
994#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
995#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
911d79ba
AJ		 996#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
997#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
998#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
945ca823 999#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
3c51a985 1000#define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
f24cb33e
AJ		 1001#define tcg_gen_andc_tl tcg_gen_andc_i64
1002#define tcg_gen_eqv_tl tcg_gen_eqv_i64
1003#define tcg_gen_nand_tl tcg_gen_nand_i64
1004#define tcg_gen_nor_tl tcg_gen_nor_i64
1005#define tcg_gen_orc_tl tcg_gen_orc_i64
0e28d006
RH		 1006#define tcg_gen_clz_tl tcg_gen_clz_i64
1007#define tcg_gen_ctz_tl tcg_gen_ctz_i64
1008#define tcg_gen_clzi_tl tcg_gen_clzi_i64
1009#define tcg_gen_ctzi_tl tcg_gen_ctzi_i64
086920c2 1010#define tcg_gen_clrsb_tl tcg_gen_clrsb_i64
a768e4e9 1011#define tcg_gen_ctpop_tl tcg_gen_ctpop_i64
15824571
AJ		 1012#define tcg_gen_rotl_tl tcg_gen_rotl_i64
1013#define tcg_gen_rotli_tl tcg_gen_rotli_i64
1014#define tcg_gen_rotr_tl tcg_gen_rotr_i64
1015#define tcg_gen_rotri_tl tcg_gen_rotri_i64
b7767f0f 1016#define tcg_gen_deposit_tl tcg_gen_deposit_i64
07cc68d5 1017#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
7ec8bab3
RH		 1018#define tcg_gen_extract_tl tcg_gen_extract_i64
1019#define tcg_gen_sextract_tl tcg_gen_sextract_i64
a98824ac 1020#define tcg_const_tl tcg_const_i64
bdffd4a9 1021#define tcg_const_local_tl tcg_const_local_i64
ffc5ea09 1022#define tcg_gen_movcond_tl tcg_gen_movcond_i64
f6953a73
RH		 1023#define tcg_gen_add2_tl tcg_gen_add2_i64
1024#define tcg_gen_sub2_tl tcg_gen_sub2_i64
696a8be6
RH		 1025#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
1026#define tcg_gen_muls2_tl tcg_gen_muls2_i64
5087abfb 1027#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64
c482cb11
RH		 1028#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64
1029#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64
1030#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64
1031#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64
1032#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64
1033#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64
1034#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64
1035#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64
1036#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64
1037#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64
d2fd745f 1038#define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec
f8422f52 1039#else
f8422f52
BS		 1040#define tcg_gen_movi_tl tcg_gen_movi_i32
1041#define tcg_gen_mov_tl tcg_gen_mov_i32
1042#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
1043#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
1044#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
1045#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
1046#define tcg_gen_ld32u_tl tcg_gen_ld_i32
1047#define tcg_gen_ld32s_tl tcg_gen_ld_i32
1048#define tcg_gen_ld_tl tcg_gen_ld_i32
1049#define tcg_gen_st8_tl tcg_gen_st8_i32
1050#define tcg_gen_st16_tl tcg_gen_st16_i32
1051#define tcg_gen_st32_tl tcg_gen_st_i32
1052#define tcg_gen_st_tl tcg_gen_st_i32
1053#define tcg_gen_add_tl tcg_gen_add_i32
1054#define tcg_gen_addi_tl tcg_gen_addi_i32
1055#define tcg_gen_sub_tl tcg_gen_sub_i32
390efc54 1056#define tcg_gen_neg_tl tcg_gen_neg_i32
0045734a 1057#define tcg_gen_subfi_tl tcg_gen_subfi_i32
f8422f52
BS		 1058#define tcg_gen_subi_tl tcg_gen_subi_i32
1059#define tcg_gen_and_tl tcg_gen_and_i32
1060#define tcg_gen_andi_tl tcg_gen_andi_i32
1061#define tcg_gen_or_tl tcg_gen_or_i32
1062#define tcg_gen_ori_tl tcg_gen_ori_i32
1063#define tcg_gen_xor_tl tcg_gen_xor_i32
1064#define tcg_gen_xori_tl tcg_gen_xori_i32
0b6ce4cf 1065#define tcg_gen_not_tl tcg_gen_not_i32
f8422f52
BS		 1066#define tcg_gen_shl_tl tcg_gen_shl_i32
1067#define tcg_gen_shli_tl tcg_gen_shli_i32
1068#define tcg_gen_shr_tl tcg_gen_shr_i32
1069#define tcg_gen_shri_tl tcg_gen_shri_i32
1070#define tcg_gen_sar_tl tcg_gen_sar_i32
1071#define tcg_gen_sari_tl tcg_gen_sari_i32
0cf767d6 1072#define tcg_gen_brcond_tl tcg_gen_brcond_i32
cb63669a 1073#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
be210acb 1074#define tcg_gen_setcond_tl tcg_gen_setcond_i32
add1e7ea 1075#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
f730fd27
TS		 1076#define tcg_gen_mul_tl tcg_gen_mul_i32
1077#define tcg_gen_muli_tl tcg_gen_muli_i32
ab36421e
AJ		 1078#define tcg_gen_div_tl tcg_gen_div_i32
1079#define tcg_gen_rem_tl tcg_gen_rem_i32
864951af
AJ		 1080#define tcg_gen_divu_tl tcg_gen_divu_i32
1081#define tcg_gen_remu_tl tcg_gen_remu_i32
a768e4b2 1082#define tcg_gen_discard_tl tcg_gen_discard_i32
e429073d 1083#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
ecc7b3aa 1084#define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32
e429073d
BS		 1085#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
1086#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
1087#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
1088#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
0b6ce4cf
FB		 1089#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
1090#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
1091#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
1092#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
1093#define tcg_gen_ext32u_tl tcg_gen_mov_i32
1094#define tcg_gen_ext32s_tl tcg_gen_mov_i32
911d79ba
AJ		 1095#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
1096#define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
945ca823 1097#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
e3eb9806 1098#define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
f24cb33e
AJ		 1099#define tcg_gen_andc_tl tcg_gen_andc_i32
1100#define tcg_gen_eqv_tl tcg_gen_eqv_i32
1101#define tcg_gen_nand_tl tcg_gen_nand_i32
1102#define tcg_gen_nor_tl tcg_gen_nor_i32
1103#define tcg_gen_orc_tl tcg_gen_orc_i32
0e28d006
RH		 1104#define tcg_gen_clz_tl tcg_gen_clz_i32
1105#define tcg_gen_ctz_tl tcg_gen_ctz_i32
1106#define tcg_gen_clzi_tl tcg_gen_clzi_i32
1107#define tcg_gen_ctzi_tl tcg_gen_ctzi_i32
086920c2 1108#define tcg_gen_clrsb_tl tcg_gen_clrsb_i32
a768e4e9 1109#define tcg_gen_ctpop_tl tcg_gen_ctpop_i32
15824571
AJ		 1110#define tcg_gen_rotl_tl tcg_gen_rotl_i32
1111#define tcg_gen_rotli_tl tcg_gen_rotli_i32
1112#define tcg_gen_rotr_tl tcg_gen_rotr_i32
1113#define tcg_gen_rotri_tl tcg_gen_rotri_i32
b7767f0f 1114#define tcg_gen_deposit_tl tcg_gen_deposit_i32
07cc68d5 1115#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
7ec8bab3
RH		 1116#define tcg_gen_extract_tl tcg_gen_extract_i32
1117#define tcg_gen_sextract_tl tcg_gen_sextract_i32
a98824ac 1118#define tcg_const_tl tcg_const_i32
bdffd4a9 1119#define tcg_const_local_tl tcg_const_local_i32
ffc5ea09 1120#define tcg_gen_movcond_tl tcg_gen_movcond_i32
f6953a73
RH		 1121#define tcg_gen_add2_tl tcg_gen_add2_i32
1122#define tcg_gen_sub2_tl tcg_gen_sub2_i32
696a8be6
RH		 1123#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
1124#define tcg_gen_muls2_tl tcg_gen_muls2_i32
5087abfb 1125#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32
c482cb11
RH		 1126#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32
1127#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32
1128#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32
1129#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32
1130#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32
1131#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32
1132#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32
1133#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32
1134#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32
1135#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32
d2fd745f 1136#define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec
f8422f52 1137#endif
6ddbc6e4 1138
71b92699 1139#if UINTPTR_MAX == UINT32_MAX
5bfa8034
RH		 1140# define PTR i32
1141# define NAT TCGv_i32
f713d6ad 1142#else
5bfa8034
RH		 1143# define PTR i64
1144# define NAT TCGv_i64
1145#endif
1146
1147static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o)
1148{
1149 glue(tcg_gen_ld_,PTR)((NAT)r, a, o);
1150}
1151
1152static inline void tcg_gen_discard_ptr(TCGv_ptr a)
1153{
1154 glue(tcg_gen_discard_,PTR)((NAT)a);
1155}
1156
1157static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b)
1158{
1159 glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b);
1160}
1161
1162static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b)
1163{
1164 glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b);
1165}
1166
1167static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a,
1168 intptr_t b, TCGLabel *label)
1169{
1170 glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label);
1171}
1172
1173static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a)
1174{
1175#if UINTPTR_MAX == UINT32_MAX
1176 tcg_gen_mov_i32((NAT)r, a);
1177#else
1178 tcg_gen_ext_i32_i64((NAT)r, a);
1179#endif
1180}
1181
1182static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a)
1183{
1184#if UINTPTR_MAX == UINT32_MAX
1185 tcg_gen_extrl_i64_i32((NAT)r, a);
1186#else
1187 tcg_gen_mov_i64((NAT)r, a);
1188#endif
1189}
1190
1191static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a)
1192{
1193#if UINTPTR_MAX == UINT32_MAX
1194 tcg_gen_extu_i32_i64(r, (NAT)a);
1195#else
1196 tcg_gen_mov_i64(r, (NAT)a);
1197#endif
1198}
1199
1200static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a)
1201{
1202#if UINTPTR_MAX == UINT32_MAX
1203 tcg_gen_mov_i32(r, (NAT)a);
1204#else
1205 tcg_gen_extrl_i64_i32(r, (NAT)a);
1206#endif
1207}
1208
1209#undef PTR
1210#undef NAT
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