]> git.proxmox.com Git - mirror_qemu.git/blame - tcg/tcg-opc.h
qapi-schema: add 'device_add'
[mirror_qemu.git] / tcg / tcg-opc.h
CommitLineData
c896fe29
FB
1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
c61aaf7a
AJ
24
25/*
26 * DEF(name, oargs, iargs, cargs, flags)
27 */
c896fe29
FB
28
29/* predefined ops */
c1a61f6c
RH
30DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
31DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)
32
33/* variable number of parameters */
96d0ee7f 34DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT)
5ff9d6a4 35
344028ba 36DEF(br, 0, 0, 1, TCG_OPF_BB_END)
c896fe29 37
4ef76952 38#define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0)
25c4d9cc
RH
39#if TCG_TARGET_REG_BITS == 32
40# define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
41#else
42# define IMPL64 TCG_OPF_64BIT
43#endif
44
f65e19bc
PK
45DEF(mb, 0, 0, 1, 0)
46
96d0ee7f
RH
47DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
48DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
c61aaf7a 49DEF(setcond_i32, 1, 2, 1, 0)
ffc5ea09 50DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
c896fe29 51/* load/store */
c61aaf7a
AJ
52DEF(ld8u_i32, 1, 1, 1, 0)
53DEF(ld8s_i32, 1, 1, 1, 0)
54DEF(ld16u_i32, 1, 1, 1, 0)
55DEF(ld16s_i32, 1, 1, 1, 0)
56DEF(ld_i32, 1, 1, 1, 0)
b202d41e
AJ
57DEF(st8_i32, 0, 2, 1, 0)
58DEF(st16_i32, 0, 2, 1, 0)
59DEF(st_i32, 0, 2, 1, 0)
c896fe29 60/* arith */
c61aaf7a
AJ
61DEF(add_i32, 1, 2, 0, 0)
62DEF(sub_i32, 1, 2, 0, 0)
63DEF(mul_i32, 1, 2, 0, 0)
25c4d9cc
RH
64DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
65DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
ca675f46
RH
66DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
67DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
25c4d9cc
RH
68DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
69DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
c61aaf7a
AJ
70DEF(and_i32, 1, 2, 0, 0)
71DEF(or_i32, 1, 2, 0, 0)
72DEF(xor_i32, 1, 2, 0, 0)
d42f183c 73/* shifts/rotates */
c61aaf7a
AJ
74DEF(shl_i32, 1, 2, 0, 0)
75DEF(shr_i32, 1, 2, 0, 0)
76DEF(sar_i32, 1, 2, 0, 0)
25c4d9cc
RH
77DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
78DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
79DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
c896fe29 80
344028ba 81DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
c896fe29 82
e6a72734
RH
83DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
84DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
85DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
4d3203fd 86DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
03271524
RH
87DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32))
88DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32))
344028ba 89DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32))
25c4d9cc
RH
90DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
91
92DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
93DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
94DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
95DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
96DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32))
97DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32))
98DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
99DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
100DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
101DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
102DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
103DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
104DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))
105
96d0ee7f
RH
106DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
107DEF(movi_i64, 1, 0, 1, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT)
25c4d9cc 108DEF(setcond_i64, 1, 2, 1, IMPL64)
ffc5ea09 109DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64))
c896fe29 110/* load/store */
25c4d9cc
RH
111DEF(ld8u_i64, 1, 1, 1, IMPL64)
112DEF(ld8s_i64, 1, 1, 1, IMPL64)
113DEF(ld16u_i64, 1, 1, 1, IMPL64)
114DEF(ld16s_i64, 1, 1, 1, IMPL64)
115DEF(ld32u_i64, 1, 1, 1, IMPL64)
116DEF(ld32s_i64, 1, 1, 1, IMPL64)
117DEF(ld_i64, 1, 1, 1, IMPL64)
b202d41e
AJ
118DEF(st8_i64, 0, 2, 1, IMPL64)
119DEF(st16_i64, 0, 2, 1, IMPL64)
120DEF(st32_i64, 0, 2, 1, IMPL64)
121DEF(st_i64, 0, 2, 1, IMPL64)
c896fe29 122/* arith */
25c4d9cc
RH
123DEF(add_i64, 1, 2, 0, IMPL64)
124DEF(sub_i64, 1, 2, 0, IMPL64)
125DEF(mul_i64, 1, 2, 0, IMPL64)
126DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
127DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
ca675f46
RH
128DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
129DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
25c4d9cc
RH
130DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
131DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
132DEF(and_i64, 1, 2, 0, IMPL64)
133DEF(or_i64, 1, 2, 0, IMPL64)
134DEF(xor_i64, 1, 2, 0, IMPL64)
d42f183c 135/* shifts/rotates */
25c4d9cc
RH
136DEF(shl_i64, 1, 2, 0, IMPL64)
137DEF(shr_i64, 1, 2, 0, IMPL64)
138DEF(sar_i64, 1, 2, 0, IMPL64)
139DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
140DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
141DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
c896fe29 142
4f2331e5
AJ
143/* size changing ops */
144DEF(ext_i32_i64, 1, 1, 0, IMPL64)
145DEF(extu_i32_i64, 1, 1, 0, IMPL64)
609ad705
RH
146DEF(extrl_i64_i32, 1, 1, 0,
147 IMPL(TCG_TARGET_HAS_extrl_i64_i32)
148 | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
149DEF(extrh_i64_i32, 1, 1, 0,
150 IMPL(TCG_TARGET_HAS_extrh_i64_i32)
4bb7a41e
RH
151 | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
152
344028ba 153DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)
25c4d9cc
RH
154DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
155DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
156DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
157DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
158DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
159DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
160DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
161DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
162DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
163DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
164DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
165DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
166DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64))
167DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
168DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64))
169DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64))
c896fe29 170
d7156f7c
RH
171DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
172DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
173DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
4d3203fd 174DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
03271524
RH
175DEF(muluh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i64))
176DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64))
d7156f7c 177
c0e40dbd
JH
178#define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
179#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
180
c896fe29 181/* QEMU specific */
c0e40dbd
JH
182DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS,
183 TCG_OPF_NOT_PRESENT)
344028ba
AJ
184DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
185DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)
f713d6ad 186
59227d5d 187DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1,
3d1b2ff6 188 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
59227d5d 189DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1,
3d1b2ff6 190 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
59227d5d 191DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1,
3d1b2ff6 192 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
59227d5d 193DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,
3d1b2ff6
RH
194 TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
195
196#undef TLADDR_ARGS
197#undef DATA64_ARGS
25c4d9cc
RH
198#undef IMPL
199#undef IMPL64
c61aaf7a 200#undef DEF