projects / mirror_qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| c896fe29 FB |
1 | /* |
| 2 | * Tiny Code Generator for QEMU | |
| 3 | * | |
| 4 | * Copyright (c) 2008 Fabrice Bellard | |
| 5 | * | |
| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
| 7 | * of this software and associated documentation files (the "Software"), to deal | |
| 8 | * in the Software without restriction, including without limitation the rights | |
| 9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
| 10 | * copies of the Software, and to permit persons to whom the Software is | |
| 11 | * furnished to do so, subject to the following conditions: | |
| 12 | * | |
| 13 | * The above copyright notice and this permission notice shall be included in | |
| 14 | * all copies or substantial portions of the Software. | |
| 15 | * | |
| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
| 21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
| 22 | * THE SOFTWARE. | |
| 23 | */ | |
| bf6247fb | 24 | #ifdef CONFIG_DYNGEN_OP |
| c896fe29 | 25 | #include "dyngen-opc.h" |
| cf2be984 | 26 | #endif |
| c896fe29 FB |
27 | |
| 28 | #ifndef DEF2 | |
| 29 | #define DEF2(name, oargs, iargs, cargs, flags) DEF(name, oargs + iargs + cargs, 0) | |
| 30 | #endif | |
| 31 | ||
| 32 | /* predefined ops */ | |
| 33 | DEF2(end, 0, 0, 0, 0) /* must be kept first */ | |
| 34 | DEF2(nop, 0, 0, 0, 0) | |
| 35 | DEF2(nop1, 0, 0, 1, 0) | |
| 36 | DEF2(nop2, 0, 0, 2, 0) | |
| 37 | DEF2(nop3, 0, 0, 3, 0) | |
| 38 | DEF2(nopn, 0, 0, 1, 0) /* variable number of parameters */ | |
| 39 | /* macro handling */ | |
| 40 | DEF2(macro_2, 2, 0, 1, 0) | |
| 41 | DEF2(macro_start, 0, 0, 2, 0) | |
| 42 | DEF2(macro_end, 0, 0, 2, 0) | |
| 43 | DEF2(macro_goto, 0, 0, 3, 0) | |
| 44 | ||
| 5ff9d6a4 FB |
45 | DEF2(discard, 1, 0, 0, 0) |
| 46 | ||
| c896fe29 | 47 | DEF2(set_label, 0, 0, 1, 0) |
| 5ff9d6a4 FB |
48 | DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */ |
| 49 | DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) | |
| 50 | DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) | |
| c896fe29 FB |
51 | |
| 52 | DEF2(mov_i32, 1, 1, 0, 0) | |
| 53 | DEF2(movi_i32, 1, 0, 1, 0) | |
| 54 | /* load/store */ | |
| 55 | DEF2(ld8u_i32, 1, 1, 1, 0) | |
| 56 | DEF2(ld8s_i32, 1, 1, 1, 0) | |
| 57 | DEF2(ld16u_i32, 1, 1, 1, 0) | |
| 58 | DEF2(ld16s_i32, 1, 1, 1, 0) | |
| 59 | DEF2(ld_i32, 1, 1, 1, 0) | |
| 5ff9d6a4 FB |
60 | DEF2(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
| 61 | DEF2(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) | |
| 62 | DEF2(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) | |
| c896fe29 FB |
63 | /* arith */ |
| 64 | DEF2(add_i32, 1, 2, 0, 0) | |
| 65 | DEF2(sub_i32, 1, 2, 0, 0) | |
| 66 | DEF2(mul_i32, 1, 2, 0, 0) | |
| 67 | #ifdef TCG_TARGET_HAS_div_i32 | |
| 68 | DEF2(div_i32, 1, 2, 0, 0) | |
| 69 | DEF2(divu_i32, 1, 2, 0, 0) | |
| 70 | DEF2(rem_i32, 1, 2, 0, 0) | |
| 71 | DEF2(remu_i32, 1, 2, 0, 0) | |
| 72 | #else | |
| 73 | DEF2(div2_i32, 2, 3, 0, 0) | |
| 74 | DEF2(divu2_i32, 2, 3, 0, 0) | |
| 75 | #endif | |
| 76 | DEF2(and_i32, 1, 2, 0, 0) | |
| 77 | DEF2(or_i32, 1, 2, 0, 0) | |
| 78 | DEF2(xor_i32, 1, 2, 0, 0) | |
| 79 | /* shifts */ | |
| 80 | DEF2(shl_i32, 1, 2, 0, 0) | |
| 81 | DEF2(shr_i32, 1, 2, 0, 0) | |
| 82 | DEF2(sar_i32, 1, 2, 0, 0) | |
| 83 | ||
| 5ff9d6a4 | 84 | DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
85 | #if TCG_TARGET_REG_BITS == 32 |
| 86 | DEF2(add2_i32, 2, 4, 0, 0) | |
| 87 | DEF2(sub2_i32, 2, 4, 0, 0) | |
| 5ff9d6a4 | 88 | DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
89 | DEF2(mulu2_i32, 2, 2, 0, 0) |
| 90 | #endif | |
| 91 | #ifdef TCG_TARGET_HAS_ext8s_i32 | |
| 92 | DEF2(ext8s_i32, 1, 1, 0, 0) | |
| 93 | #endif | |
| 94 | #ifdef TCG_TARGET_HAS_ext16s_i32 | |
| 95 | DEF2(ext16s_i32, 1, 1, 0, 0) | |
| 96 | #endif | |
| 97 | #ifdef TCG_TARGET_HAS_bswap_i32 | |
| 98 | DEF2(bswap_i32, 1, 1, 0, 0) | |
| 99 | #endif | |
| 100 | ||
| 101 | #if TCG_TARGET_REG_BITS == 64 | |
| 102 | DEF2(mov_i64, 1, 1, 0, 0) | |
| 103 | DEF2(movi_i64, 1, 0, 1, 0) | |
| 104 | /* load/store */ | |
| 105 | DEF2(ld8u_i64, 1, 1, 1, 0) | |
| 106 | DEF2(ld8s_i64, 1, 1, 1, 0) | |
| 107 | DEF2(ld16u_i64, 1, 1, 1, 0) | |
| 108 | DEF2(ld16s_i64, 1, 1, 1, 0) | |
| 109 | DEF2(ld32u_i64, 1, 1, 1, 0) | |
| 110 | DEF2(ld32s_i64, 1, 1, 1, 0) | |
| 111 | DEF2(ld_i64, 1, 1, 1, 0) | |
| 5ff9d6a4 FB |
112 | DEF2(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
| 113 | DEF2(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) | |
| 114 | DEF2(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) | |
| 115 | DEF2(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) | |
| c896fe29 FB |
116 | /* arith */ |
| 117 | DEF2(add_i64, 1, 2, 0, 0) | |
| 118 | DEF2(sub_i64, 1, 2, 0, 0) | |
| 119 | DEF2(mul_i64, 1, 2, 0, 0) | |
| 120 | #ifdef TCG_TARGET_HAS_div_i64 | |
| 121 | DEF2(div_i64, 1, 2, 0, 0) | |
| 122 | DEF2(divu_i64, 1, 2, 0, 0) | |
| 123 | DEF2(rem_i64, 1, 2, 0, 0) | |
| 124 | DEF2(remu_i64, 1, 2, 0, 0) | |
| 125 | #else | |
| 126 | DEF2(div2_i64, 2, 3, 0, 0) | |
| 127 | DEF2(divu2_i64, 2, 3, 0, 0) | |
| 128 | #endif | |
| 129 | DEF2(and_i64, 1, 2, 0, 0) | |
| 130 | DEF2(or_i64, 1, 2, 0, 0) | |
| 131 | DEF2(xor_i64, 1, 2, 0, 0) | |
| 132 | /* shifts */ | |
| 133 | DEF2(shl_i64, 1, 2, 0, 0) | |
| 134 | DEF2(shr_i64, 1, 2, 0, 0) | |
| 135 | DEF2(sar_i64, 1, 2, 0, 0) | |
| 136 | ||
| 5ff9d6a4 | 137 | DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
138 | #ifdef TCG_TARGET_HAS_ext8s_i64 |
| 139 | DEF2(ext8s_i64, 1, 1, 0, 0) | |
| 140 | #endif | |
| 141 | #ifdef TCG_TARGET_HAS_ext16s_i64 | |
| 142 | DEF2(ext16s_i64, 1, 1, 0, 0) | |
| 143 | #endif | |
| 144 | #ifdef TCG_TARGET_HAS_ext32s_i64 | |
| 145 | DEF2(ext32s_i64, 1, 1, 0, 0) | |
| 146 | #endif | |
| 147 | #ifdef TCG_TARGET_HAS_bswap_i64 | |
| 148 | DEF2(bswap_i64, 1, 1, 0, 0) | |
| 149 | #endif | |
| 150 | #endif | |
| 390efc54 PB |
151 | #ifdef TCG_TARGET_HAS_neg_i32 |
| 152 | DEF2(neg_i32, 1, 1, 0, 0) | |
| 153 | #endif | |
| 154 | #ifdef TCG_TARGET_HAS_neg_i64 | |
| 155 | DEF2(neg_i64, 1, 1, 0, 0) | |
| 156 | #endif | |
| c896fe29 FB |
157 | |
| 158 | /* QEMU specific */ | |
| 5ff9d6a4 FB |
159 | DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
| 160 | DEF2(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) | |
| c896fe29 FB |
161 | /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op |
| 162 | constants must be defined */ | |
| 163 | #if TCG_TARGET_REG_BITS == 32 | |
| 164 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 165 | DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 166 | #else |
| 5ff9d6a4 | 167 | DEF2(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
168 | #endif |
| 169 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 170 | DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 171 | #else |
| 5ff9d6a4 | 172 | DEF2(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
173 | #endif |
| 174 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 175 | DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 176 | #else |
| 5ff9d6a4 | 177 | DEF2(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
178 | #endif |
| 179 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 180 | DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 181 | #else |
| 5ff9d6a4 | 182 | DEF2(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
183 | #endif |
| 184 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 185 | DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 186 | #else |
| 5ff9d6a4 | 187 | DEF2(qemu_ld32u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
188 | #endif |
| 189 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 190 | DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 191 | #else |
| 5ff9d6a4 | 192 | DEF2(qemu_ld32s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
193 | #endif |
| 194 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 195 | DEF2(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 196 | #else |
| 5ff9d6a4 | 197 | DEF2(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
198 | #endif |
| 199 | ||
| 200 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 201 | DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 202 | #else |
| 5ff9d6a4 | 203 | DEF2(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
204 | #endif |
| 205 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 206 | DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 207 | #else |
| 5ff9d6a4 | 208 | DEF2(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
209 | #endif |
| 210 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 211 | DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 212 | #else |
| 5ff9d6a4 | 213 | DEF2(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
214 | #endif |
| 215 | #if TARGET_LONG_BITS == 32 | |
| 5ff9d6a4 | 216 | DEF2(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 | 217 | #else |
| 5ff9d6a4 | 218 | DEF2(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| c896fe29 FB |
219 | #endif |
| 220 | ||
| 221 | #else /* TCG_TARGET_REG_BITS == 32 */ | |
| 222 | ||
| 5ff9d6a4 FB |
223 | DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 224 | DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| 225 | DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| 226 | DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| 227 | DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| 228 | DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| 229 | DEF2(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| c896fe29 | 230 | |
| 5ff9d6a4 FB |
231 | DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
| 232 | DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| 233 | DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| 234 | DEF2(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) | |
| c896fe29 FB |
235 | |
| 236 | #endif /* TCG_TARGET_REG_BITS != 32 */ | |
| 237 | ||
| 238 | #undef DEF2 |