[mirror_qemu.git] / tcg / tcg-opc.h

/*
 * Tiny Code Generator for QEMU
 *
 * Copyright (c) 2008 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

/*
 * DEF(name, oargs, iargs, cargs, flags)
 */

/* predefined ops */
DEF(end, 0, 0, 0, TCG_OPF_NOT_PRESENT) /* must be kept first */
DEF(nop, 0, 0, 0, TCG_OPF_NOT_PRESENT)
DEF(nop1, 0, 0, 1, TCG_OPF_NOT_PRESENT)
DEF(nop2, 0, 0, 2, TCG_OPF_NOT_PRESENT)
DEF(nop3, 0, 0, 3, TCG_OPF_NOT_PRESENT)

/* variable number of parameters */
DEF(nopn, 0, 0, 1, TCG_OPF_NOT_PRESENT)

DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT)

/* variable number of parameters */
DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER)

DEF(br, 0, 0, 1, TCG_OPF_BB_END)

#define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0)
#if TCG_TARGET_REG_BITS == 32
# define IMPL64  TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT
#else
# define IMPL64  TCG_OPF_64BIT
#endif

DEF(mov_i32, 1, 1, 0, 0)
DEF(movi_i32, 1, 0, 1, 0)
DEF(setcond_i32, 1, 2, 1, 0)
DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
/* load/store */
DEF(ld8u_i32, 1, 1, 1, 0)
DEF(ld8s_i32, 1, 1, 1, 0)
DEF(ld16u_i32, 1, 1, 1, 0)
DEF(ld16s_i32, 1, 1, 1, 0)
DEF(ld_i32, 1, 1, 1, 0)
DEF(st8_i32, 0, 2, 1, 0)
DEF(st16_i32, 0, 2, 1, 0)
DEF(st_i32, 0, 2, 1, 0)
/* arith */
DEF(add_i32, 1, 2, 0, 0)
DEF(sub_i32, 1, 2, 0, 0)
DEF(mul_i32, 1, 2, 0, 0)
DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
DEF(and_i32, 1, 2, 0, 0)
DEF(or_i32, 1, 2, 0, 0)
DEF(xor_i32, 1, 2, 0, 0)
/* shifts/rotates */
DEF(shl_i32, 1, 2, 0, 0)
DEF(shr_i32, 1, 2, 0, 0)
DEF(sar_i32, 1, 2, 0, 0)
DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))

DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)

DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32))
DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32))
DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | IMPL(TCG_TARGET_REG_BITS == 32))
DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))

DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32))
DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32))
DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))

DEF(mov_i64, 1, 1, 0, IMPL64)
DEF(movi_i64, 1, 0, 1, IMPL64)
DEF(setcond_i64, 1, 2, 1, IMPL64)
DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64))
/* load/store */
DEF(ld8u_i64, 1, 1, 1, IMPL64)
DEF(ld8s_i64, 1, 1, 1, IMPL64)
DEF(ld16u_i64, 1, 1, 1, IMPL64)
DEF(ld16s_i64, 1, 1, 1, IMPL64)
DEF(ld32u_i64, 1, 1, 1, IMPL64)
DEF(ld32s_i64, 1, 1, 1, IMPL64)
DEF(ld_i64, 1, 1, 1, IMPL64)
DEF(st8_i64, 0, 2, 1, IMPL64)
DEF(st16_i64, 0, 2, 1, IMPL64)
DEF(st32_i64, 0, 2, 1, IMPL64)
DEF(st_i64, 0, 2, 1, IMPL64)
/* arith */
DEF(add_i64, 1, 2, 0, IMPL64)
DEF(sub_i64, 1, 2, 0, IMPL64)
DEF(mul_i64, 1, 2, 0, IMPL64)
DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64))
DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64))
DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64))
DEF(and_i64, 1, 2, 0, IMPL64)
DEF(or_i64, 1, 2, 0, IMPL64)
DEF(xor_i64, 1, 2, 0, IMPL64)
/* shifts/rotates */
DEF(shl_i64, 1, 2, 0, IMPL64)
DEF(shr_i64, 1, 2, 0, IMPL64)
DEF(sar_i64, 1, 2, 0, IMPL64)
DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))

DEF(trunc_shr_i32, 1, 1, 1,
    IMPL(TCG_TARGET_HAS_trunc_shr_i32)
    | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))

DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | IMPL64)
DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64))
DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64))
DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64))
DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64))
DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64))
DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64))
DEF(bswap16_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64))
DEF(bswap32_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64))
DEF(bswap64_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64))
DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64))
DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64))
DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64))
DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64))
DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64))
DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64))
DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64))

DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64))
DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64))
DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64))
DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64))
DEF(muluh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i64))
DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64))

/* QEMU specific */
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
DEF(debug_insn_start, 0, 0, 2, TCG_OPF_NOT_PRESENT)
#else
DEF(debug_insn_start, 0, 0, 1, TCG_OPF_NOT_PRESENT)
#endif
DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)

#define IMPL_NEW_LDST \
    (TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS \
     | IMPL(TCG_TARGET_HAS_new_ldst))

#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
DEF(qemu_ld_i32, 1, 1, 2, IMPL_NEW_LDST)
DEF(qemu_st_i32, 0, 2, 2, IMPL_NEW_LDST)
# if TCG_TARGET_REG_BITS == 64
DEF(qemu_ld_i64, 1, 1, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
DEF(qemu_st_i64, 0, 2, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
# else
DEF(qemu_ld_i64, 2, 1, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
DEF(qemu_st_i64, 0, 3, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
# endif
#else
DEF(qemu_ld_i32, 1, 2, 2, IMPL_NEW_LDST)
DEF(qemu_st_i32, 0, 3, 2, IMPL_NEW_LDST)
DEF(qemu_ld_i64, 2, 2, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
DEF(qemu_st_i64, 0, 4, 2, IMPL_NEW_LDST | TCG_OPF_64BIT)
#endif

#undef IMPL_NEW_LDST

#define IMPL_OLD_LDST \
    (TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS \
     | IMPL(!TCG_TARGET_HAS_new_ldst))

#if TCG_TARGET_REG_BITS == 32
#if TARGET_LONG_BITS == 32
DEF(qemu_ld8u, 1, 1, 1, IMPL_OLD_LDST)
#else
DEF(qemu_ld8u, 1, 2, 1, IMPL_OLD_LDST)
#endif
#if TARGET_LONG_BITS == 32
DEF(qemu_ld8s, 1, 1, 1, IMPL_OLD_LDST)
#else
DEF(qemu_ld8s, 1, 2, 1, IMPL_OLD_LDST)
#endif
#if TARGET_LONG_BITS == 32
DEF(qemu_ld16u, 1, 1, 1, IMPL_OLD_LDST)
#else
DEF(qemu_ld16u, 1, 2, 1, IMPL_OLD_LDST)
#endif
#if TARGET_LONG_BITS == 32
DEF(qemu_ld16s, 1, 1, 1, IMPL_OLD_LDST)
#else
DEF(qemu_ld16s, 1, 2, 1, IMPL_OLD_LDST)
#endif
#if TARGET_LONG_BITS == 32
DEF(qemu_ld32, 1, 1, 1, IMPL_OLD_LDST)
#else
DEF(qemu_ld32, 1, 2, 1, IMPL_OLD_LDST)
#endif
#if TARGET_LONG_BITS == 32
DEF(qemu_ld64, 2, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
#else
DEF(qemu_ld64, 2, 2, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
#endif

#if TARGET_LONG_BITS == 32
DEF(qemu_st8, 0, 2, 1, IMPL_OLD_LDST)
#else
DEF(qemu_st8, 0, 3, 1, IMPL_OLD_LDST)
#endif
#if TARGET_LONG_BITS == 32
DEF(qemu_st16, 0, 2, 1, IMPL_OLD_LDST)
#else
DEF(qemu_st16, 0, 3, 1, IMPL_OLD_LDST)
#endif
#if TARGET_LONG_BITS == 32
DEF(qemu_st32, 0, 2, 1, IMPL_OLD_LDST)
#else
DEF(qemu_st32, 0, 3, 1, IMPL_OLD_LDST)
#endif
#if TARGET_LONG_BITS == 32
DEF(qemu_st64, 0, 3, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
#else
DEF(qemu_st64, 0, 4, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
#endif

#else /* TCG_TARGET_REG_BITS == 32 */

DEF(qemu_ld8u, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
DEF(qemu_ld8s, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
DEF(qemu_ld16u, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
DEF(qemu_ld16s, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
DEF(qemu_ld32, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
DEF(qemu_ld32u, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
DEF(qemu_ld32s, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
DEF(qemu_ld64, 1, 1, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)

DEF(qemu_st8, 0, 2, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
DEF(qemu_st16, 0, 2, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
DEF(qemu_st32, 0, 2, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)
DEF(qemu_st64, 0, 2, 1, IMPL_OLD_LDST | TCG_OPF_64BIT)

#endif /* TCG_TARGET_REG_BITS != 32 */

#undef IMPL_OLD_LDST

#undef IMPL
#undef IMPL64
#undef DEF
Commit	Line	Data
c896fe29 FB	1	/*
	2	* Tiny Code Generator for QEMU
	3	*
	4	* Copyright (c) 2008 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
c61aaf7a AJ	24
	25	/*
	26	* DEF(name, oargs, iargs, cargs, flags)
	27	*/
c896fe29 FB	28
c896fe29 FB	29	/* predefined ops */
c1a61f6c RH	30	DEF(end, 0, 0, 0, TCG_OPF_NOT_PRESENT) /* must be kept first */
	31	DEF(nop, 0, 0, 0, TCG_OPF_NOT_PRESENT)
	32	DEF(nop1, 0, 0, 1, TCG_OPF_NOT_PRESENT)
	33	DEF(nop2, 0, 0, 2, TCG_OPF_NOT_PRESENT)
	34	DEF(nop3, 0, 0, 3, TCG_OPF_NOT_PRESENT)
c896fe29	35
c1a61f6c RH	36	/* variable number of parameters */
	37	DEF(nopn, 0, 0, 1, TCG_OPF_NOT_PRESENT)
	38
	39	DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT)
	40	DEF(set_label, 0, 0, 1, TCG_OPF_BB_END \| TCG_OPF_NOT_PRESENT)
	41
	42	/* variable number of parameters */
cf066674	43	DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER)
5ff9d6a4	44
344028ba	45	DEF(br, 0, 0, 1, TCG_OPF_BB_END)
c896fe29	46
4ef76952	47	#define IMPL(X) (__builtin_constant_p(X) && !(X) ? TCG_OPF_NOT_PRESENT : 0)
25c4d9cc RH	48	#if TCG_TARGET_REG_BITS == 32
	49	# define IMPL64 TCG_OPF_64BIT \| TCG_OPF_NOT_PRESENT
	50	#else
	51	# define IMPL64 TCG_OPF_64BIT
	52	#endif
	53
c61aaf7a AJ	54	DEF(mov_i32, 1, 1, 0, 0)
	55	DEF(movi_i32, 1, 0, 1, 0)
	56	DEF(setcond_i32, 1, 2, 1, 0)
ffc5ea09	57	DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32))
c896fe29	58	/* load/store */
c61aaf7a AJ	59	DEF(ld8u_i32, 1, 1, 1, 0)
	60	DEF(ld8s_i32, 1, 1, 1, 0)
	61	DEF(ld16u_i32, 1, 1, 1, 0)
	62	DEF(ld16s_i32, 1, 1, 1, 0)
	63	DEF(ld_i32, 1, 1, 1, 0)
b202d41e AJ	64	DEF(st8_i32, 0, 2, 1, 0)
	65	DEF(st16_i32, 0, 2, 1, 0)
	66	DEF(st_i32, 0, 2, 1, 0)
c896fe29	67	/* arith */
c61aaf7a AJ	68	DEF(add_i32, 1, 2, 0, 0)
	69	DEF(sub_i32, 1, 2, 0, 0)
	70	DEF(mul_i32, 1, 2, 0, 0)
25c4d9cc RH	71	DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
25c4d9cc RH	72	DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32))
ca675f46 RH	73	DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
ca675f46 RH	74	DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32))
25c4d9cc RH	75	DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
25c4d9cc RH	76	DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32))
c61aaf7a AJ	77	DEF(and_i32, 1, 2, 0, 0)
	78	DEF(or_i32, 1, 2, 0, 0)
	79	DEF(xor_i32, 1, 2, 0, 0)
d42f183c	80	/* shifts/rotates */
c61aaf7a AJ	81	DEF(shl_i32, 1, 2, 0, 0)
	82	DEF(shr_i32, 1, 2, 0, 0)
	83	DEF(sar_i32, 1, 2, 0, 0)
25c4d9cc RH	84	DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
	85	DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
	86	DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
c896fe29	87
344028ba	88	DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
c896fe29	89
e6a72734 RH	90	DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32))
	91	DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32))
	92	DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32))
4d3203fd	93	DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32))
03271524 RH	94	DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32))
03271524 RH	95	DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32))
344028ba	96	DEF(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END \| IMPL(TCG_TARGET_REG_BITS == 32))
25c4d9cc RH	97	DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32))
	98
	99	DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32))
	100	DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32))
	101	DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32))
	102	DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32))
	103	DEF(bswap16_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap16_i32))
	104	DEF(bswap32_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_bswap32_i32))
	105	DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32))
	106	DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32))
	107	DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32))
	108	DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32))
	109	DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32))
	110	DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32))
	111	DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32))
	112
	113	DEF(mov_i64, 1, 1, 0, IMPL64)
	114	DEF(movi_i64, 1, 0, 1, IMPL64)
	115	DEF(setcond_i64, 1, 2, 1, IMPL64)
ffc5ea09	116	DEF(movcond_i64, 1, 4, 1, IMPL64 \| IMPL(TCG_TARGET_HAS_movcond_i64))
c896fe29	117	/* load/store */
25c4d9cc RH	118	DEF(ld8u_i64, 1, 1, 1, IMPL64)
	119	DEF(ld8s_i64, 1, 1, 1, IMPL64)
	120	DEF(ld16u_i64, 1, 1, 1, IMPL64)
	121	DEF(ld16s_i64, 1, 1, 1, IMPL64)
	122	DEF(ld32u_i64, 1, 1, 1, IMPL64)
	123	DEF(ld32s_i64, 1, 1, 1, IMPL64)
	124	DEF(ld_i64, 1, 1, 1, IMPL64)
b202d41e AJ	125	DEF(st8_i64, 0, 2, 1, IMPL64)
	126	DEF(st16_i64, 0, 2, 1, IMPL64)
	127	DEF(st32_i64, 0, 2, 1, IMPL64)
	128	DEF(st_i64, 0, 2, 1, IMPL64)
c896fe29	129	/* arith */
25c4d9cc RH	130	DEF(add_i64, 1, 2, 0, IMPL64)
	131	DEF(sub_i64, 1, 2, 0, IMPL64)
	132	DEF(mul_i64, 1, 2, 0, IMPL64)
	133	DEF(div_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_div_i64))
	134	DEF(divu_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_div_i64))
ca675f46 RH	135	DEF(rem_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_rem_i64))
ca675f46 RH	136	DEF(remu_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_rem_i64))
25c4d9cc RH	137	DEF(div2_i64, 2, 3, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_div2_i64))
	138	DEF(divu2_i64, 2, 3, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_div2_i64))
	139	DEF(and_i64, 1, 2, 0, IMPL64)
	140	DEF(or_i64, 1, 2, 0, IMPL64)
	141	DEF(xor_i64, 1, 2, 0, IMPL64)
d42f183c	142	/* shifts/rotates */
25c4d9cc RH	143	DEF(shl_i64, 1, 2, 0, IMPL64)
	144	DEF(shr_i64, 1, 2, 0, IMPL64)
	145	DEF(sar_i64, 1, 2, 0, IMPL64)
	146	DEF(rotl_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_rot_i64))
	147	DEF(rotr_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_rot_i64))
	148	DEF(deposit_i64, 1, 2, 2, IMPL64 \| IMPL(TCG_TARGET_HAS_deposit_i64))
c896fe29	149
4bb7a41e RH	150	DEF(trunc_shr_i32, 1, 1, 1,
	151	IMPL(TCG_TARGET_HAS_trunc_shr_i32)
	152	\| (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0))
	153
344028ba	154	DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END \| IMPL64)
25c4d9cc RH	155	DEF(ext8s_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_ext8s_i64))
	156	DEF(ext16s_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_ext16s_i64))
	157	DEF(ext32s_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_ext32s_i64))
	158	DEF(ext8u_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_ext8u_i64))
	159	DEF(ext16u_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_ext16u_i64))
	160	DEF(ext32u_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_ext32u_i64))
	161	DEF(bswap16_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_bswap16_i64))
	162	DEF(bswap32_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_bswap32_i64))
	163	DEF(bswap64_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_bswap64_i64))
	164	DEF(not_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_not_i64))
	165	DEF(neg_i64, 1, 1, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_neg_i64))
	166	DEF(andc_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_andc_i64))
	167	DEF(orc_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_orc_i64))
	168	DEF(eqv_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_eqv_i64))
	169	DEF(nand_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_nand_i64))
	170	DEF(nor_i64, 1, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_nor_i64))
c896fe29	171
d7156f7c RH	172	DEF(add2_i64, 2, 4, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_add2_i64))
	173	DEF(sub2_i64, 2, 4, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_sub2_i64))
	174	DEF(mulu2_i64, 2, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_mulu2_i64))
4d3203fd	175	DEF(muls2_i64, 2, 2, 0, IMPL64 \| IMPL(TCG_TARGET_HAS_muls2_i64))
03271524 RH	176	DEF(muluh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i64))
03271524 RH	177	DEF(mulsh_i64, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i64))
d7156f7c	178
c896fe29	179	/* QEMU specific */
7e4597d7	180	#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
c1a61f6c	181	DEF(debug_insn_start, 0, 0, 2, TCG_OPF_NOT_PRESENT)
7e4597d7	182	#else
c1a61f6c	183	DEF(debug_insn_start, 0, 0, 1, TCG_OPF_NOT_PRESENT)
7e4597d7	184	#endif
344028ba AJ	185	DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END)
344028ba AJ	186	DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)
f713d6ad RH	187
	188	#define IMPL_NEW_LDST \
	189	(TCG_OPF_CALL_CLOBBER \| TCG_OPF_SIDE_EFFECTS \
	190	\| IMPL(TCG_TARGET_HAS_new_ldst))
	191
	192	#if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
	193	DEF(qemu_ld_i32, 1, 1, 2, IMPL_NEW_LDST)
	194	DEF(qemu_st_i32, 0, 2, 2, IMPL_NEW_LDST)
	195	# if TCG_TARGET_REG_BITS == 64
	196	DEF(qemu_ld_i64, 1, 1, 2, IMPL_NEW_LDST \| TCG_OPF_64BIT)
	197	DEF(qemu_st_i64, 0, 2, 2, IMPL_NEW_LDST \| TCG_OPF_64BIT)
	198	# else
	199	DEF(qemu_ld_i64, 2, 1, 2, IMPL_NEW_LDST \| TCG_OPF_64BIT)
	200	DEF(qemu_st_i64, 0, 3, 2, IMPL_NEW_LDST \| TCG_OPF_64BIT)
	201	# endif
	202	#else
	203	DEF(qemu_ld_i32, 1, 2, 2, IMPL_NEW_LDST)
	204	DEF(qemu_st_i32, 0, 3, 2, IMPL_NEW_LDST)
	205	DEF(qemu_ld_i64, 2, 2, 2, IMPL_NEW_LDST \| TCG_OPF_64BIT)
	206	DEF(qemu_st_i64, 0, 4, 2, IMPL_NEW_LDST \| TCG_OPF_64BIT)
	207	#endif
	208
	209	#undef IMPL_NEW_LDST
	210
	211	#define IMPL_OLD_LDST \
	212	(TCG_OPF_CALL_CLOBBER \| TCG_OPF_SIDE_EFFECTS \
	213	\| IMPL(!TCG_TARGET_HAS_new_ldst))
	214
c896fe29 FB	215	#if TCG_TARGET_REG_BITS == 32
c896fe29 FB	216	#if TARGET_LONG_BITS == 32
f713d6ad	217	DEF(qemu_ld8u, 1, 1, 1, IMPL_OLD_LDST)
c896fe29	218	#else
f713d6ad	219	DEF(qemu_ld8u, 1, 2, 1, IMPL_OLD_LDST)
c896fe29 FB	220	#endif
c896fe29 FB	221	#if TARGET_LONG_BITS == 32
f713d6ad	222	DEF(qemu_ld8s, 1, 1, 1, IMPL_OLD_LDST)
c896fe29	223	#else
f713d6ad	224	DEF(qemu_ld8s, 1, 2, 1, IMPL_OLD_LDST)
c896fe29 FB	225	#endif
c896fe29 FB	226	#if TARGET_LONG_BITS == 32
f713d6ad	227	DEF(qemu_ld16u, 1, 1, 1, IMPL_OLD_LDST)
c896fe29	228	#else
f713d6ad	229	DEF(qemu_ld16u, 1, 2, 1, IMPL_OLD_LDST)
c896fe29 FB	230	#endif
c896fe29 FB	231	#if TARGET_LONG_BITS == 32
f713d6ad	232	DEF(qemu_ld16s, 1, 1, 1, IMPL_OLD_LDST)
c896fe29	233	#else
f713d6ad	234	DEF(qemu_ld16s, 1, 2, 1, IMPL_OLD_LDST)
c896fe29 FB	235	#endif
c896fe29 FB	236	#if TARGET_LONG_BITS == 32
f713d6ad	237	DEF(qemu_ld32, 1, 1, 1, IMPL_OLD_LDST)
c896fe29	238	#else
f713d6ad	239	DEF(qemu_ld32, 1, 2, 1, IMPL_OLD_LDST)
c896fe29 FB	240	#endif
c896fe29 FB	241	#if TARGET_LONG_BITS == 32
f713d6ad	242	DEF(qemu_ld64, 2, 1, 1, IMPL_OLD_LDST \| TCG_OPF_64BIT)
c896fe29	243	#else
f713d6ad	244	DEF(qemu_ld64, 2, 2, 1, IMPL_OLD_LDST \| TCG_OPF_64BIT)
c896fe29 FB	245	#endif
	246
	247	#if TARGET_LONG_BITS == 32
f713d6ad	248	DEF(qemu_st8, 0, 2, 1, IMPL_OLD_LDST)
c896fe29	249	#else
f713d6ad	250	DEF(qemu_st8, 0, 3, 1, IMPL_OLD_LDST)
c896fe29 FB	251	#endif
c896fe29 FB	252	#if TARGET_LONG_BITS == 32
f713d6ad	253	DEF(qemu_st16, 0, 2, 1, IMPL_OLD_LDST)
c896fe29	254	#else
f713d6ad	255	DEF(qemu_st16, 0, 3, 1, IMPL_OLD_LDST)
c896fe29 FB	256	#endif
c896fe29 FB	257	#if TARGET_LONG_BITS == 32
f713d6ad	258	DEF(qemu_st32, 0, 2, 1, IMPL_OLD_LDST)
c896fe29	259	#else
f713d6ad	260	DEF(qemu_st32, 0, 3, 1, IMPL_OLD_LDST)
c896fe29 FB	261	#endif
c896fe29 FB	262	#if TARGET_LONG_BITS == 32
f713d6ad	263	DEF(qemu_st64, 0, 3, 1, IMPL_OLD_LDST \| TCG_OPF_64BIT)
c896fe29	264	#else
f713d6ad	265	DEF(qemu_st64, 0, 4, 1, IMPL_OLD_LDST \| TCG_OPF_64BIT)
c896fe29 FB	266	#endif
	267
	268	#else /* TCG_TARGET_REG_BITS == 32 */
	269
f713d6ad RH	270	DEF(qemu_ld8u, 1, 1, 1, IMPL_OLD_LDST \| TCG_OPF_64BIT)
	271	DEF(qemu_ld8s, 1, 1, 1, IMPL_OLD_LDST \| TCG_OPF_64BIT)
	272	DEF(qemu_ld16u, 1, 1, 1, IMPL_OLD_LDST \| TCG_OPF_64BIT)
	273	DEF(qemu_ld16s, 1, 1, 1, IMPL_OLD_LDST \| TCG_OPF_64BIT)
	274	DEF(qemu_ld32, 1, 1, 1, IMPL_OLD_LDST \| TCG_OPF_64BIT)
	275	DEF(qemu_ld32u, 1, 1, 1, IMPL_OLD_LDST \| TCG_OPF_64BIT)
	276	DEF(qemu_ld32s, 1, 1, 1, IMPL_OLD_LDST \| TCG_OPF_64BIT)
	277	DEF(qemu_ld64, 1, 1, 1, IMPL_OLD_LDST \| TCG_OPF_64BIT)
c896fe29	278
f713d6ad RH	279	DEF(qemu_st8, 0, 2, 1, IMPL_OLD_LDST \| TCG_OPF_64BIT)
	280	DEF(qemu_st16, 0, 2, 1, IMPL_OLD_LDST \| TCG_OPF_64BIT)
	281	DEF(qemu_st32, 0, 2, 1, IMPL_OLD_LDST \| TCG_OPF_64BIT)
	282	DEF(qemu_st64, 0, 2, 1, IMPL_OLD_LDST \| TCG_OPF_64BIT)
c896fe29 FB	283
	284	#endif /* TCG_TARGET_REG_BITS != 32 */
	285
f713d6ad RH	286	#undef IMPL_OLD_LDST
f713d6ad RH	287
25c4d9cc RH	288	#undef IMPL
25c4d9cc RH	289	#undef IMPL64
c61aaf7a	290	#undef DEF