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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | #include "dyngen-opc.h" | |
25 | ||
26 | #ifndef DEF2 | |
27 | #define DEF2(name, oargs, iargs, cargs, flags) DEF(name, oargs + iargs + cargs, 0) | |
28 | #endif | |
29 | ||
30 | /* predefined ops */ | |
31 | DEF2(end, 0, 0, 0, 0) /* must be kept first */ | |
32 | DEF2(nop, 0, 0, 0, 0) | |
33 | DEF2(nop1, 0, 0, 1, 0) | |
34 | DEF2(nop2, 0, 0, 2, 0) | |
35 | DEF2(nop3, 0, 0, 3, 0) | |
36 | DEF2(nopn, 0, 0, 1, 0) /* variable number of parameters */ | |
37 | /* macro handling */ | |
38 | DEF2(macro_2, 2, 0, 1, 0) | |
39 | DEF2(macro_start, 0, 0, 2, 0) | |
40 | DEF2(macro_end, 0, 0, 2, 0) | |
41 | DEF2(macro_goto, 0, 0, 3, 0) | |
42 | ||
43 | DEF2(set_label, 0, 0, 1, 0) | |
44 | DEF2(call, 0, 1, 2, 0) /* variable number of parameters */ | |
45 | DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END) | |
46 | DEF2(br, 0, 0, 1, TCG_OPF_BB_END) | |
47 | ||
48 | DEF2(mov_i32, 1, 1, 0, 0) | |
49 | DEF2(movi_i32, 1, 0, 1, 0) | |
50 | /* load/store */ | |
51 | DEF2(ld8u_i32, 1, 1, 1, 0) | |
52 | DEF2(ld8s_i32, 1, 1, 1, 0) | |
53 | DEF2(ld16u_i32, 1, 1, 1, 0) | |
54 | DEF2(ld16s_i32, 1, 1, 1, 0) | |
55 | DEF2(ld_i32, 1, 1, 1, 0) | |
56 | DEF2(st8_i32, 0, 2, 1, 0) | |
57 | DEF2(st16_i32, 0, 2, 1, 0) | |
58 | DEF2(st_i32, 0, 2, 1, 0) | |
59 | /* arith */ | |
60 | DEF2(add_i32, 1, 2, 0, 0) | |
61 | DEF2(sub_i32, 1, 2, 0, 0) | |
62 | DEF2(mul_i32, 1, 2, 0, 0) | |
63 | #ifdef TCG_TARGET_HAS_div_i32 | |
64 | DEF2(div_i32, 1, 2, 0, 0) | |
65 | DEF2(divu_i32, 1, 2, 0, 0) | |
66 | DEF2(rem_i32, 1, 2, 0, 0) | |
67 | DEF2(remu_i32, 1, 2, 0, 0) | |
68 | #else | |
69 | DEF2(div2_i32, 2, 3, 0, 0) | |
70 | DEF2(divu2_i32, 2, 3, 0, 0) | |
71 | #endif | |
72 | DEF2(and_i32, 1, 2, 0, 0) | |
73 | DEF2(or_i32, 1, 2, 0, 0) | |
74 | DEF2(xor_i32, 1, 2, 0, 0) | |
75 | /* shifts */ | |
76 | DEF2(shl_i32, 1, 2, 0, 0) | |
77 | DEF2(shr_i32, 1, 2, 0, 0) | |
78 | DEF2(sar_i32, 1, 2, 0, 0) | |
79 | ||
80 | DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END) | |
81 | #if TCG_TARGET_REG_BITS == 32 | |
82 | DEF2(add2_i32, 2, 4, 0, 0) | |
83 | DEF2(sub2_i32, 2, 4, 0, 0) | |
84 | DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END) | |
85 | DEF2(mulu2_i32, 2, 2, 0, 0) | |
86 | #endif | |
87 | #ifdef TCG_TARGET_HAS_ext8s_i32 | |
88 | DEF2(ext8s_i32, 1, 1, 0, 0) | |
89 | #endif | |
90 | #ifdef TCG_TARGET_HAS_ext16s_i32 | |
91 | DEF2(ext16s_i32, 1, 1, 0, 0) | |
92 | #endif | |
93 | #ifdef TCG_TARGET_HAS_bswap_i32 | |
94 | DEF2(bswap_i32, 1, 1, 0, 0) | |
95 | #endif | |
96 | ||
97 | #if TCG_TARGET_REG_BITS == 64 | |
98 | DEF2(mov_i64, 1, 1, 0, 0) | |
99 | DEF2(movi_i64, 1, 0, 1, 0) | |
100 | /* load/store */ | |
101 | DEF2(ld8u_i64, 1, 1, 1, 0) | |
102 | DEF2(ld8s_i64, 1, 1, 1, 0) | |
103 | DEF2(ld16u_i64, 1, 1, 1, 0) | |
104 | DEF2(ld16s_i64, 1, 1, 1, 0) | |
105 | DEF2(ld32u_i64, 1, 1, 1, 0) | |
106 | DEF2(ld32s_i64, 1, 1, 1, 0) | |
107 | DEF2(ld_i64, 1, 1, 1, 0) | |
108 | DEF2(st8_i64, 0, 2, 1, 0) | |
109 | DEF2(st16_i64, 0, 2, 1, 0) | |
110 | DEF2(st32_i64, 0, 2, 1, 0) | |
111 | DEF2(st_i64, 0, 2, 1, 0) | |
112 | /* arith */ | |
113 | DEF2(add_i64, 1, 2, 0, 0) | |
114 | DEF2(sub_i64, 1, 2, 0, 0) | |
115 | DEF2(mul_i64, 1, 2, 0, 0) | |
116 | #ifdef TCG_TARGET_HAS_div_i64 | |
117 | DEF2(div_i64, 1, 2, 0, 0) | |
118 | DEF2(divu_i64, 1, 2, 0, 0) | |
119 | DEF2(rem_i64, 1, 2, 0, 0) | |
120 | DEF2(remu_i64, 1, 2, 0, 0) | |
121 | #else | |
122 | DEF2(div2_i64, 2, 3, 0, 0) | |
123 | DEF2(divu2_i64, 2, 3, 0, 0) | |
124 | #endif | |
125 | DEF2(and_i64, 1, 2, 0, 0) | |
126 | DEF2(or_i64, 1, 2, 0, 0) | |
127 | DEF2(xor_i64, 1, 2, 0, 0) | |
128 | /* shifts */ | |
129 | DEF2(shl_i64, 1, 2, 0, 0) | |
130 | DEF2(shr_i64, 1, 2, 0, 0) | |
131 | DEF2(sar_i64, 1, 2, 0, 0) | |
132 | ||
133 | DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END) | |
134 | #ifdef TCG_TARGET_HAS_ext8s_i64 | |
135 | DEF2(ext8s_i64, 1, 1, 0, 0) | |
136 | #endif | |
137 | #ifdef TCG_TARGET_HAS_ext16s_i64 | |
138 | DEF2(ext16s_i64, 1, 1, 0, 0) | |
139 | #endif | |
140 | #ifdef TCG_TARGET_HAS_ext32s_i64 | |
141 | DEF2(ext32s_i64, 1, 1, 0, 0) | |
142 | #endif | |
143 | #ifdef TCG_TARGET_HAS_bswap_i64 | |
144 | DEF2(bswap_i64, 1, 1, 0, 0) | |
145 | #endif | |
146 | #endif | |
147 | ||
148 | /* QEMU specific */ | |
149 | DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END) | |
150 | DEF2(goto_tb, 0, 0, 1, TCG_OPF_BB_END) | |
151 | /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op | |
152 | constants must be defined */ | |
153 | #if TCG_TARGET_REG_BITS == 32 | |
154 | #if TARGET_LONG_BITS == 32 | |
155 | DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER) | |
156 | #else | |
157 | DEF2(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER) | |
158 | #endif | |
159 | #if TARGET_LONG_BITS == 32 | |
160 | DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER) | |
161 | #else | |
162 | DEF2(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER) | |
163 | #endif | |
164 | #if TARGET_LONG_BITS == 32 | |
165 | DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER) | |
166 | #else | |
167 | DEF2(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER) | |
168 | #endif | |
169 | #if TARGET_LONG_BITS == 32 | |
170 | DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER) | |
171 | #else | |
172 | DEF2(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER) | |
173 | #endif | |
174 | #if TARGET_LONG_BITS == 32 | |
175 | DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER) | |
176 | #else | |
177 | DEF2(qemu_ld32u, 1, 2, 1, TCG_OPF_CALL_CLOBBER) | |
178 | #endif | |
179 | #if TARGET_LONG_BITS == 32 | |
180 | DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER) | |
181 | #else | |
182 | DEF2(qemu_ld32s, 1, 2, 1, TCG_OPF_CALL_CLOBBER) | |
183 | #endif | |
184 | #if TARGET_LONG_BITS == 32 | |
185 | DEF2(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER) | |
186 | #else | |
187 | DEF2(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER) | |
188 | #endif | |
189 | ||
190 | #if TARGET_LONG_BITS == 32 | |
191 | DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER) | |
192 | #else | |
193 | DEF2(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER) | |
194 | #endif | |
195 | #if TARGET_LONG_BITS == 32 | |
196 | DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER) | |
197 | #else | |
198 | DEF2(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER) | |
199 | #endif | |
200 | #if TARGET_LONG_BITS == 32 | |
201 | DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER) | |
202 | #else | |
203 | DEF2(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER) | |
204 | #endif | |
205 | #if TARGET_LONG_BITS == 32 | |
206 | DEF2(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER) | |
207 | #else | |
208 | DEF2(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER) | |
209 | #endif | |
210 | ||
211 | #else /* TCG_TARGET_REG_BITS == 32 */ | |
212 | ||
213 | DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER) | |
214 | DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER) | |
215 | DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER) | |
216 | DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER) | |
217 | DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER) | |
218 | DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER) | |
219 | DEF2(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER) | |
220 | ||
221 | DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER) | |
222 | DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER) | |
223 | DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER) | |
224 | DEF2(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER) | |
225 | ||
226 | #endif /* TCG_TARGET_REG_BITS != 32 */ | |
227 | ||
228 | #undef DEF2 |