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Commit | Line | Data |
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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
757e725b | 25 | #include "qemu/osdep.h" |
cca82982 | 26 | |
813da627 RH |
27 | /* Define to jump the ELF file used to communicate with GDB. */ |
28 | #undef DEBUG_JIT | |
29 | ||
72fd2efb | 30 | #include "qemu/error-report.h" |
f348b6d1 | 31 | #include "qemu/cutils.h" |
1de7afc9 | 32 | #include "qemu/host-utils.h" |
d4c51a0a | 33 | #include "qemu/qemu-print.h" |
084cfca1 | 34 | #include "qemu/cacheflush.h" |
ad768e6f | 35 | #include "qemu/cacheinfo.h" |
533206f0 | 36 | #include "qemu/timer.h" |
c896fe29 | 37 | |
c5d3c498 | 38 | /* Note: the long term plan is to reduce the dependencies on the QEMU |
c896fe29 FB |
39 | CPU definitions. Currently they are used for qemu_ld/st |
40 | instructions */ | |
41 | #define NO_CPU_IO_DEFS | |
c896fe29 | 42 | |
63c91552 | 43 | #include "exec/exec-all.h" |
d0a9bb5e | 44 | #include "exec/tlb-common.h" |
ad3d0e4d | 45 | #include "tcg/tcg-op-common.h" |
813da627 | 46 | |
edee2579 | 47 | #if UINTPTR_MAX == UINT32_MAX |
813da627 | 48 | # define ELF_CLASS ELFCLASS32 |
edee2579 RH |
49 | #else |
50 | # define ELF_CLASS ELFCLASS64 | |
813da627 | 51 | #endif |
e03b5686 | 52 | #if HOST_BIG_ENDIAN |
813da627 RH |
53 | # define ELF_DATA ELFDATA2MSB |
54 | #else | |
55 | # define ELF_DATA ELFDATA2LSB | |
56 | #endif | |
57 | ||
c896fe29 | 58 | #include "elf.h" |
508127e2 | 59 | #include "exec/log.h" |
d2ba8026 | 60 | #include "tcg/tcg-ldst.h" |
47f7313d | 61 | #include "tcg/tcg-temp-internal.h" |
5ff7258c | 62 | #include "tcg-internal.h" |
5584e2db | 63 | #include "accel/tcg/perf.h" |
7d478306 RH |
64 | #ifdef CONFIG_USER_ONLY |
65 | #include "exec/user/guest-base.h" | |
66 | #endif | |
c896fe29 | 67 | |
139c1837 | 68 | /* Forward declarations for functions declared in tcg-target.c.inc and |
ce151109 | 69 | used here. */ |
e4d58b41 RH |
70 | static void tcg_target_init(TCGContext *s); |
71 | static void tcg_target_qemu_prologue(TCGContext *s); | |
6ac17786 | 72 | static bool patch_reloc(tcg_insn_unit *code_ptr, int type, |
2ba7fae2 | 73 | intptr_t value, intptr_t addend); |
c896fe29 | 74 | |
497a22eb RH |
75 | /* The CIE and FDE header definitions will be common to all hosts. */ |
76 | typedef struct { | |
77 | uint32_t len __attribute__((aligned((sizeof(void *))))); | |
78 | uint32_t id; | |
79 | uint8_t version; | |
80 | char augmentation[1]; | |
81 | uint8_t code_align; | |
82 | uint8_t data_align; | |
83 | uint8_t return_column; | |
84 | } DebugFrameCIE; | |
85 | ||
86 | typedef struct QEMU_PACKED { | |
87 | uint32_t len __attribute__((aligned((sizeof(void *))))); | |
88 | uint32_t cie_offset; | |
edee2579 RH |
89 | uintptr_t func_start; |
90 | uintptr_t func_len; | |
497a22eb RH |
91 | } DebugFrameFDEHeader; |
92 | ||
2c90784a RH |
93 | typedef struct QEMU_PACKED { |
94 | DebugFrameCIE cie; | |
95 | DebugFrameFDEHeader fde; | |
96 | } DebugFrameHeader; | |
97 | ||
2528f771 RH |
98 | typedef struct TCGLabelQemuLdst { |
99 | bool is_ld; /* qemu_ld: true, qemu_st: false */ | |
100 | MemOpIdx oi; | |
101 | TCGType type; /* result type of a load */ | |
102 | TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */ | |
103 | TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */ | |
104 | TCGReg datalo_reg; /* reg index for low word to be loaded or stored */ | |
105 | TCGReg datahi_reg; /* reg index for high word to be loaded or stored */ | |
106 | const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR */ | |
107 | tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */ | |
108 | QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next; | |
109 | } TCGLabelQemuLdst; | |
110 | ||
755bf9e5 | 111 | static void tcg_register_jit_int(const void *buf, size_t size, |
2c90784a RH |
112 | const void *debug_frame, |
113 | size_t debug_frame_size) | |
813da627 RH |
114 | __attribute__((unused)); |
115 | ||
139c1837 | 116 | /* Forward declarations for functions declared and used in tcg-target.c.inc. */ |
2a534aff | 117 | static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, |
a05b5b9b | 118 | intptr_t arg2); |
78113e83 | 119 | static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); |
c0ad3001 | 120 | static void tcg_out_movi(TCGContext *s, TCGType type, |
2a534aff | 121 | TCGReg ret, tcg_target_long arg); |
678155b2 | 122 | static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); |
753e42ea | 123 | static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); |
d0e66c89 | 124 | static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg); |
379afdff | 125 | static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg); |
52bf3398 | 126 | static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg); |
9ecf5f61 | 127 | static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg); |
9c6aa274 | 128 | static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); |
b9bfe000 | 129 | static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); |
b8b94ac6 | 130 | static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg); |
313bdea8 | 131 | static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long); |
129f1f9e | 132 | static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2); |
b55a8d9d | 133 | static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); |
cf7d6b8e | 134 | static void tcg_out_goto_tb(TCGContext *s, int which); |
5e8892db MR |
135 | static void tcg_out_op(TCGContext *s, TCGOpcode opc, |
136 | const TCGArg args[TCG_MAX_OP_ARGS], | |
137 | const int const_args[TCG_MAX_OP_ARGS]); | |
d2fd745f | 138 | #if TCG_TARGET_MAYBE_vec |
e7632cfa RH |
139 | static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, |
140 | TCGReg dst, TCGReg src); | |
d6ecb4a9 RH |
141 | static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, |
142 | TCGReg dst, TCGReg base, intptr_t offset); | |
4e186175 RH |
143 | static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, |
144 | TCGReg dst, int64_t arg); | |
5e8892db MR |
145 | static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, |
146 | unsigned vecl, unsigned vece, | |
147 | const TCGArg args[TCG_MAX_OP_ARGS], | |
148 | const int const_args[TCG_MAX_OP_ARGS]); | |
d2fd745f | 149 | #else |
e7632cfa RH |
150 | static inline bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, |
151 | TCGReg dst, TCGReg src) | |
152 | { | |
153 | g_assert_not_reached(); | |
154 | } | |
d6ecb4a9 RH |
155 | static inline bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, |
156 | TCGReg dst, TCGReg base, intptr_t offset) | |
157 | { | |
158 | g_assert_not_reached(); | |
159 | } | |
4e186175 RH |
160 | static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, |
161 | TCGReg dst, int64_t arg) | |
e7632cfa RH |
162 | { |
163 | g_assert_not_reached(); | |
164 | } | |
5e8892db MR |
165 | static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, |
166 | unsigned vecl, unsigned vece, | |
167 | const TCGArg args[TCG_MAX_OP_ARGS], | |
168 | const int const_args[TCG_MAX_OP_ARGS]) | |
d2fd745f RH |
169 | { |
170 | g_assert_not_reached(); | |
171 | } | |
172 | #endif | |
2a534aff | 173 | static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, |
a05b5b9b | 174 | intptr_t arg2); |
59d7c14e RH |
175 | static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, |
176 | TCGReg base, intptr_t ofs); | |
7b7d8b2d | 177 | static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, |
cee44b03 | 178 | const TCGHelperInfo *info); |
5e3d0c19 | 179 | static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot); |
a4fbbd77 | 180 | static bool tcg_target_const_match(int64_t val, TCGType type, int ct); |
659ef5cb | 181 | #ifdef TCG_TARGET_NEED_LDST_LABELS |
aeee05f5 | 182 | static int tcg_out_ldst_finalize(TCGContext *s); |
659ef5cb | 183 | #endif |
c896fe29 | 184 | |
8429a1ca RH |
185 | typedef struct TCGLdstHelperParam { |
186 | TCGReg (*ra_gen)(TCGContext *s, const TCGLabelQemuLdst *l, int arg_reg); | |
187 | unsigned ntmp; | |
188 | int tmp[3]; | |
189 | } TCGLdstHelperParam; | |
190 | ||
191 | static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *l, | |
192 | const TCGLdstHelperParam *p) | |
193 | __attribute__((unused)); | |
194 | static void tcg_out_ld_helper_ret(TCGContext *s, const TCGLabelQemuLdst *l, | |
195 | bool load_sign, const TCGLdstHelperParam *p) | |
196 | __attribute__((unused)); | |
197 | static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *l, | |
198 | const TCGLdstHelperParam *p) | |
199 | __attribute__((unused)); | |
200 | ||
de95016d | 201 | static void * const qemu_ld_helpers[MO_SSIZE + 1] __attribute__((unused)) = { |
0cadc1ed RH |
202 | [MO_UB] = helper_ldub_mmu, |
203 | [MO_SB] = helper_ldsb_mmu, | |
204 | [MO_UW] = helper_lduw_mmu, | |
205 | [MO_SW] = helper_ldsw_mmu, | |
206 | [MO_UL] = helper_ldul_mmu, | |
207 | [MO_UQ] = helper_ldq_mmu, | |
208 | #if TCG_TARGET_REG_BITS == 64 | |
209 | [MO_SL] = helper_ldsl_mmu, | |
ebebea53 | 210 | [MO_128] = helper_ld16_mmu, |
0cadc1ed RH |
211 | #endif |
212 | }; | |
213 | ||
de95016d | 214 | static void * const qemu_st_helpers[MO_SIZE + 1] __attribute__((unused)) = { |
0cadc1ed RH |
215 | [MO_8] = helper_stb_mmu, |
216 | [MO_16] = helper_stw_mmu, | |
217 | [MO_32] = helper_stl_mmu, | |
218 | [MO_64] = helper_stq_mmu, | |
ebebea53 RH |
219 | #if TCG_TARGET_REG_BITS == 64 |
220 | [MO_128] = helper_st16_mmu, | |
221 | #endif | |
0cadc1ed | 222 | }; |
0cadc1ed | 223 | |
e63b8a29 RH |
224 | typedef struct { |
225 | MemOp atom; /* lg2 bits of atomicity required */ | |
226 | MemOp align; /* lg2 bits of alignment to use */ | |
227 | } TCGAtomAlign; | |
228 | ||
229 | static TCGAtomAlign atom_and_align_for_opc(TCGContext *s, MemOp opc, | |
230 | MemOp host_atom, bool allow_two_ops) | |
231 | __attribute__((unused)); | |
232 | ||
42eb6dfc RH |
233 | TCGContext tcg_init_ctx; |
234 | __thread TCGContext *tcg_ctx; | |
235 | ||
5ff7258c | 236 | TCGContext **tcg_ctxs; |
0e2d61cf RH |
237 | unsigned int tcg_cur_ctxs; |
238 | unsigned int tcg_max_ctxs; | |
1c2adb95 | 239 | TCGv_env cpu_env = 0; |
c8bc1168 | 240 | const void *tcg_code_gen_epilogue; |
db0c51a3 | 241 | uintptr_t tcg_splitwx_diff; |
df2cce29 | 242 | |
b91ccb31 RH |
243 | #ifndef CONFIG_TCG_INTERPRETER |
244 | tcg_prologue_fn *tcg_qemu_tb_exec; | |
245 | #endif | |
246 | ||
d2fd745f | 247 | static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; |
b1d8e52e | 248 | static TCGRegSet tcg_target_call_clobber_regs; |
c896fe29 | 249 | |
1813e175 | 250 | #if TCG_TARGET_INSN_UNIT_SIZE == 1 |
4196dca6 | 251 | static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v) |
c896fe29 FB |
252 | { |
253 | *s->code_ptr++ = v; | |
254 | } | |
255 | ||
4196dca6 PM |
256 | static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p, |
257 | uint8_t v) | |
5c53bb81 | 258 | { |
1813e175 | 259 | *p = v; |
5c53bb81 | 260 | } |
1813e175 | 261 | #endif |
5c53bb81 | 262 | |
1813e175 | 263 | #if TCG_TARGET_INSN_UNIT_SIZE <= 2 |
4196dca6 | 264 | static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v) |
c896fe29 | 265 | { |
1813e175 RH |
266 | if (TCG_TARGET_INSN_UNIT_SIZE == 2) { |
267 | *s->code_ptr++ = v; | |
268 | } else { | |
269 | tcg_insn_unit *p = s->code_ptr; | |
270 | memcpy(p, &v, sizeof(v)); | |
271 | s->code_ptr = p + (2 / TCG_TARGET_INSN_UNIT_SIZE); | |
272 | } | |
c896fe29 FB |
273 | } |
274 | ||
4196dca6 PM |
275 | static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p, |
276 | uint16_t v) | |
5c53bb81 | 277 | { |
1813e175 RH |
278 | if (TCG_TARGET_INSN_UNIT_SIZE == 2) { |
279 | *p = v; | |
280 | } else { | |
281 | memcpy(p, &v, sizeof(v)); | |
282 | } | |
5c53bb81 | 283 | } |
1813e175 | 284 | #endif |
5c53bb81 | 285 | |
1813e175 | 286 | #if TCG_TARGET_INSN_UNIT_SIZE <= 4 |
4196dca6 | 287 | static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v) |
c896fe29 | 288 | { |
1813e175 RH |
289 | if (TCG_TARGET_INSN_UNIT_SIZE == 4) { |
290 | *s->code_ptr++ = v; | |
291 | } else { | |
292 | tcg_insn_unit *p = s->code_ptr; | |
293 | memcpy(p, &v, sizeof(v)); | |
294 | s->code_ptr = p + (4 / TCG_TARGET_INSN_UNIT_SIZE); | |
295 | } | |
c896fe29 FB |
296 | } |
297 | ||
4196dca6 PM |
298 | static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p, |
299 | uint32_t v) | |
5c53bb81 | 300 | { |
1813e175 RH |
301 | if (TCG_TARGET_INSN_UNIT_SIZE == 4) { |
302 | *p = v; | |
303 | } else { | |
304 | memcpy(p, &v, sizeof(v)); | |
305 | } | |
5c53bb81 | 306 | } |
1813e175 | 307 | #endif |
5c53bb81 | 308 | |
1813e175 | 309 | #if TCG_TARGET_INSN_UNIT_SIZE <= 8 |
4196dca6 | 310 | static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v) |
ac26eb69 | 311 | { |
1813e175 RH |
312 | if (TCG_TARGET_INSN_UNIT_SIZE == 8) { |
313 | *s->code_ptr++ = v; | |
314 | } else { | |
315 | tcg_insn_unit *p = s->code_ptr; | |
316 | memcpy(p, &v, sizeof(v)); | |
317 | s->code_ptr = p + (8 / TCG_TARGET_INSN_UNIT_SIZE); | |
318 | } | |
ac26eb69 RH |
319 | } |
320 | ||
4196dca6 PM |
321 | static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p, |
322 | uint64_t v) | |
5c53bb81 | 323 | { |
1813e175 RH |
324 | if (TCG_TARGET_INSN_UNIT_SIZE == 8) { |
325 | *p = v; | |
326 | } else { | |
327 | memcpy(p, &v, sizeof(v)); | |
328 | } | |
5c53bb81 | 329 | } |
1813e175 | 330 | #endif |
5c53bb81 | 331 | |
c896fe29 FB |
332 | /* label relocation processing */ |
333 | ||
1813e175 | 334 | static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, |
bec16311 | 335 | TCGLabel *l, intptr_t addend) |
c896fe29 | 336 | { |
7ecd02a0 | 337 | TCGRelocation *r = tcg_malloc(sizeof(TCGRelocation)); |
c896fe29 | 338 | |
7ecd02a0 RH |
339 | r->type = type; |
340 | r->ptr = code_ptr; | |
341 | r->addend = addend; | |
342 | QSIMPLEQ_INSERT_TAIL(&l->relocs, r, next); | |
c896fe29 FB |
343 | } |
344 | ||
92ab8e7d | 345 | static void tcg_out_label(TCGContext *s, TCGLabel *l) |
c896fe29 | 346 | { |
eabb7b91 | 347 | tcg_debug_assert(!l->has_value); |
c896fe29 | 348 | l->has_value = 1; |
92ab8e7d | 349 | l->u.value_ptr = tcg_splitwx_to_rx(s->code_ptr); |
c896fe29 FB |
350 | } |
351 | ||
42a268c2 | 352 | TCGLabel *gen_new_label(void) |
c896fe29 | 353 | { |
b1311c4a | 354 | TCGContext *s = tcg_ctx; |
51e3972c | 355 | TCGLabel *l = tcg_malloc(sizeof(TCGLabel)); |
c896fe29 | 356 | |
7ecd02a0 RH |
357 | memset(l, 0, sizeof(TCGLabel)); |
358 | l->id = s->nb_labels++; | |
f85b1fc4 | 359 | QSIMPLEQ_INIT(&l->branches); |
7ecd02a0 RH |
360 | QSIMPLEQ_INIT(&l->relocs); |
361 | ||
bef16ab4 | 362 | QSIMPLEQ_INSERT_TAIL(&s->labels, l, next); |
42a268c2 RH |
363 | |
364 | return l; | |
c896fe29 FB |
365 | } |
366 | ||
7ecd02a0 RH |
367 | static bool tcg_resolve_relocs(TCGContext *s) |
368 | { | |
369 | TCGLabel *l; | |
370 | ||
371 | QSIMPLEQ_FOREACH(l, &s->labels, next) { | |
372 | TCGRelocation *r; | |
373 | uintptr_t value = l->u.value; | |
374 | ||
375 | QSIMPLEQ_FOREACH(r, &l->relocs, next) { | |
376 | if (!patch_reloc(r->ptr, r->type, value, r->addend)) { | |
377 | return false; | |
378 | } | |
379 | } | |
380 | } | |
381 | return true; | |
382 | } | |
383 | ||
9f754620 RH |
384 | static void set_jmp_reset_offset(TCGContext *s, int which) |
385 | { | |
f14bed3f RH |
386 | /* |
387 | * We will check for overflow at the end of the opcode loop in | |
388 | * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX. | |
389 | */ | |
b7e4afbd | 390 | s->gen_tb->jmp_reset_offset[which] = tcg_current_code_size(s); |
9f754620 RH |
391 | } |
392 | ||
b52a2c03 RH |
393 | static void G_GNUC_UNUSED set_jmp_insn_offset(TCGContext *s, int which) |
394 | { | |
395 | /* | |
396 | * We will check for overflow at the end of the opcode loop in | |
397 | * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX. | |
398 | */ | |
9da6079b | 399 | s->gen_tb->jmp_insn_offset[which] = tcg_current_code_size(s); |
b52a2c03 RH |
400 | } |
401 | ||
becc452a RH |
402 | static uintptr_t G_GNUC_UNUSED get_jmp_target_addr(TCGContext *s, int which) |
403 | { | |
404 | /* | |
405 | * Return the read-execute version of the pointer, for the benefit | |
406 | * of any pc-relative addressing mode. | |
407 | */ | |
9da6079b | 408 | return (uintptr_t)tcg_splitwx_to_rx(&s->gen_tb->jmp_target_addr[which]); |
becc452a RH |
409 | } |
410 | ||
d0a9bb5e RH |
411 | #if defined(CONFIG_SOFTMMU) && !defined(CONFIG_TCG_INTERPRETER) |
412 | static int tlb_mask_table_ofs(TCGContext *s, int which) | |
413 | { | |
414 | return s->tlb_fast_offset + which * sizeof(CPUTLBDescFast); | |
415 | } | |
416 | #endif | |
417 | ||
db6b7d0c | 418 | /* Signal overflow, starting over with fewer guest insns. */ |
8905770b MAL |
419 | static G_NORETURN |
420 | void tcg_raise_tb_overflow(TCGContext *s) | |
db6b7d0c RH |
421 | { |
422 | siglongjmp(s->jmp_trans, -2); | |
423 | } | |
424 | ||
8429a1ca RH |
425 | /* |
426 | * Used by tcg_out_movext{1,2} to hold the arguments for tcg_out_movext. | |
427 | * By the time we arrive at tcg_out_movext1, @dst is always a TCGReg. | |
428 | * | |
429 | * However, tcg_out_helper_load_slots reuses this field to hold an | |
430 | * argument slot number (which may designate a argument register or an | |
431 | * argument stack slot), converting to TCGReg once all arguments that | |
432 | * are destined for the stack are processed. | |
433 | */ | |
129f1f9e | 434 | typedef struct TCGMovExtend { |
8429a1ca | 435 | unsigned dst; |
129f1f9e RH |
436 | TCGReg src; |
437 | TCGType dst_type; | |
438 | TCGType src_type; | |
439 | MemOp src_ext; | |
440 | } TCGMovExtend; | |
441 | ||
b3dfd5fc RH |
442 | /** |
443 | * tcg_out_movext -- move and extend | |
444 | * @s: tcg context | |
445 | * @dst_type: integral type for destination | |
446 | * @dst: destination register | |
447 | * @src_type: integral type for source | |
448 | * @src_ext: extension to apply to source | |
449 | * @src: source register | |
450 | * | |
451 | * Move or extend @src into @dst, depending on @src_ext and the types. | |
452 | */ | |
129f1f9e RH |
453 | static void tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg dst, |
454 | TCGType src_type, MemOp src_ext, TCGReg src) | |
b3dfd5fc RH |
455 | { |
456 | switch (src_ext) { | |
457 | case MO_UB: | |
458 | tcg_out_ext8u(s, dst, src); | |
459 | break; | |
460 | case MO_SB: | |
461 | tcg_out_ext8s(s, dst_type, dst, src); | |
462 | break; | |
463 | case MO_UW: | |
464 | tcg_out_ext16u(s, dst, src); | |
465 | break; | |
466 | case MO_SW: | |
467 | tcg_out_ext16s(s, dst_type, dst, src); | |
468 | break; | |
469 | case MO_UL: | |
470 | case MO_SL: | |
471 | if (dst_type == TCG_TYPE_I32) { | |
472 | if (src_type == TCG_TYPE_I32) { | |
473 | tcg_out_mov(s, TCG_TYPE_I32, dst, src); | |
474 | } else { | |
475 | tcg_out_extrl_i64_i32(s, dst, src); | |
476 | } | |
477 | } else if (src_type == TCG_TYPE_I32) { | |
478 | if (src_ext & MO_SIGN) { | |
479 | tcg_out_exts_i32_i64(s, dst, src); | |
480 | } else { | |
481 | tcg_out_extu_i32_i64(s, dst, src); | |
482 | } | |
483 | } else { | |
484 | if (src_ext & MO_SIGN) { | |
485 | tcg_out_ext32s(s, dst, src); | |
486 | } else { | |
487 | tcg_out_ext32u(s, dst, src); | |
488 | } | |
489 | } | |
490 | break; | |
491 | case MO_UQ: | |
492 | tcg_debug_assert(TCG_TARGET_REG_BITS == 64); | |
493 | if (dst_type == TCG_TYPE_I32) { | |
494 | tcg_out_extrl_i64_i32(s, dst, src); | |
495 | } else { | |
496 | tcg_out_mov(s, TCG_TYPE_I64, dst, src); | |
497 | } | |
498 | break; | |
499 | default: | |
500 | g_assert_not_reached(); | |
501 | } | |
502 | } | |
503 | ||
129f1f9e RH |
504 | /* Minor variations on a theme, using a structure. */ |
505 | static void tcg_out_movext1_new_src(TCGContext *s, const TCGMovExtend *i, | |
506 | TCGReg src) | |
507 | { | |
508 | tcg_out_movext(s, i->dst_type, i->dst, i->src_type, i->src_ext, src); | |
509 | } | |
510 | ||
511 | static void tcg_out_movext1(TCGContext *s, const TCGMovExtend *i) | |
512 | { | |
513 | tcg_out_movext1_new_src(s, i, i->src); | |
514 | } | |
515 | ||
516 | /** | |
517 | * tcg_out_movext2 -- move and extend two pair | |
518 | * @s: tcg context | |
519 | * @i1: first move description | |
520 | * @i2: second move description | |
521 | * @scratch: temporary register, or -1 for none | |
522 | * | |
523 | * As tcg_out_movext, for both @i1 and @i2, caring for overlap | |
524 | * between the sources and destinations. | |
525 | */ | |
526 | ||
8429a1ca RH |
527 | static void tcg_out_movext2(TCGContext *s, const TCGMovExtend *i1, |
528 | const TCGMovExtend *i2, int scratch) | |
129f1f9e RH |
529 | { |
530 | TCGReg src1 = i1->src; | |
531 | TCGReg src2 = i2->src; | |
532 | ||
533 | if (i1->dst != src2) { | |
534 | tcg_out_movext1(s, i1); | |
535 | tcg_out_movext1(s, i2); | |
536 | return; | |
537 | } | |
538 | if (i2->dst == src1) { | |
539 | TCGType src1_type = i1->src_type; | |
540 | TCGType src2_type = i2->src_type; | |
541 | ||
542 | if (tcg_out_xchg(s, MAX(src1_type, src2_type), src1, src2)) { | |
543 | /* The data is now in the correct registers, now extend. */ | |
544 | src1 = i2->src; | |
545 | src2 = i1->src; | |
546 | } else { | |
547 | tcg_debug_assert(scratch >= 0); | |
548 | tcg_out_mov(s, src1_type, scratch, src1); | |
549 | src1 = scratch; | |
550 | } | |
551 | } | |
552 | tcg_out_movext1_new_src(s, i2, src2); | |
553 | tcg_out_movext1_new_src(s, i1, src1); | |
554 | } | |
555 | ||
2462e30e RH |
556 | /** |
557 | * tcg_out_movext3 -- move and extend three pair | |
558 | * @s: tcg context | |
559 | * @i1: first move description | |
560 | * @i2: second move description | |
561 | * @i3: third move description | |
562 | * @scratch: temporary register, or -1 for none | |
563 | * | |
564 | * As tcg_out_movext, for all of @i1, @i2 and @i3, caring for overlap | |
565 | * between the sources and destinations. | |
566 | */ | |
567 | ||
568 | static void tcg_out_movext3(TCGContext *s, const TCGMovExtend *i1, | |
569 | const TCGMovExtend *i2, const TCGMovExtend *i3, | |
570 | int scratch) | |
571 | { | |
572 | TCGReg src1 = i1->src; | |
573 | TCGReg src2 = i2->src; | |
574 | TCGReg src3 = i3->src; | |
575 | ||
576 | if (i1->dst != src2 && i1->dst != src3) { | |
577 | tcg_out_movext1(s, i1); | |
578 | tcg_out_movext2(s, i2, i3, scratch); | |
579 | return; | |
580 | } | |
581 | if (i2->dst != src1 && i2->dst != src3) { | |
582 | tcg_out_movext1(s, i2); | |
583 | tcg_out_movext2(s, i1, i3, scratch); | |
584 | return; | |
585 | } | |
586 | if (i3->dst != src1 && i3->dst != src2) { | |
587 | tcg_out_movext1(s, i3); | |
588 | tcg_out_movext2(s, i1, i2, scratch); | |
589 | return; | |
590 | } | |
591 | ||
592 | /* | |
593 | * There is a cycle. Since there are only 3 nodes, the cycle is | |
594 | * either "clockwise" or "anti-clockwise", and can be solved with | |
595 | * a single scratch or two xchg. | |
596 | */ | |
597 | if (i1->dst == src2 && i2->dst == src3 && i3->dst == src1) { | |
598 | /* "Clockwise" */ | |
599 | if (tcg_out_xchg(s, MAX(i1->src_type, i2->src_type), src1, src2)) { | |
600 | tcg_out_xchg(s, MAX(i2->src_type, i3->src_type), src2, src3); | |
601 | /* The data is now in the correct registers, now extend. */ | |
602 | tcg_out_movext1_new_src(s, i1, i1->dst); | |
603 | tcg_out_movext1_new_src(s, i2, i2->dst); | |
604 | tcg_out_movext1_new_src(s, i3, i3->dst); | |
605 | } else { | |
606 | tcg_debug_assert(scratch >= 0); | |
607 | tcg_out_mov(s, i1->src_type, scratch, src1); | |
608 | tcg_out_movext1(s, i3); | |
609 | tcg_out_movext1(s, i2); | |
610 | tcg_out_movext1_new_src(s, i1, scratch); | |
611 | } | |
612 | } else if (i1->dst == src3 && i2->dst == src1 && i3->dst == src2) { | |
613 | /* "Anti-clockwise" */ | |
614 | if (tcg_out_xchg(s, MAX(i2->src_type, i3->src_type), src2, src3)) { | |
615 | tcg_out_xchg(s, MAX(i1->src_type, i2->src_type), src1, src2); | |
616 | /* The data is now in the correct registers, now extend. */ | |
617 | tcg_out_movext1_new_src(s, i1, i1->dst); | |
618 | tcg_out_movext1_new_src(s, i2, i2->dst); | |
619 | tcg_out_movext1_new_src(s, i3, i3->dst); | |
620 | } else { | |
621 | tcg_debug_assert(scratch >= 0); | |
622 | tcg_out_mov(s, i1->src_type, scratch, src1); | |
623 | tcg_out_movext1(s, i2); | |
624 | tcg_out_movext1(s, i3); | |
625 | tcg_out_movext1_new_src(s, i1, scratch); | |
626 | } | |
627 | } else { | |
628 | g_assert_not_reached(); | |
629 | } | |
630 | } | |
631 | ||
4c22e840 RH |
632 | #define C_PFX1(P, A) P##A |
633 | #define C_PFX2(P, A, B) P##A##_##B | |
634 | #define C_PFX3(P, A, B, C) P##A##_##B##_##C | |
635 | #define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D | |
636 | #define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E | |
637 | #define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F | |
638 | ||
639 | /* Define an enumeration for the various combinations. */ | |
640 | ||
641 | #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1), | |
642 | #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2), | |
643 | #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3), | |
644 | #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4), | |
645 | ||
646 | #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1), | |
647 | #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2), | |
648 | #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3), | |
649 | #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4), | |
650 | ||
651 | #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2), | |
652 | ||
653 | #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1), | |
654 | #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2), | |
655 | #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3), | |
656 | #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4), | |
657 | ||
658 | typedef enum { | |
659 | #include "tcg-target-con-set.h" | |
660 | } TCGConstraintSetIndex; | |
661 | ||
662 | static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode); | |
663 | ||
664 | #undef C_O0_I1 | |
665 | #undef C_O0_I2 | |
666 | #undef C_O0_I3 | |
667 | #undef C_O0_I4 | |
668 | #undef C_O1_I1 | |
669 | #undef C_O1_I2 | |
670 | #undef C_O1_I3 | |
671 | #undef C_O1_I4 | |
672 | #undef C_N1_I2 | |
673 | #undef C_O2_I1 | |
674 | #undef C_O2_I2 | |
675 | #undef C_O2_I3 | |
676 | #undef C_O2_I4 | |
677 | ||
678 | /* Put all of the constraint sets into an array, indexed by the enum. */ | |
679 | ||
680 | #define C_O0_I1(I1) { .args_ct_str = { #I1 } }, | |
681 | #define C_O0_I2(I1, I2) { .args_ct_str = { #I1, #I2 } }, | |
682 | #define C_O0_I3(I1, I2, I3) { .args_ct_str = { #I1, #I2, #I3 } }, | |
683 | #define C_O0_I4(I1, I2, I3, I4) { .args_ct_str = { #I1, #I2, #I3, #I4 } }, | |
684 | ||
685 | #define C_O1_I1(O1, I1) { .args_ct_str = { #O1, #I1 } }, | |
686 | #define C_O1_I2(O1, I1, I2) { .args_ct_str = { #O1, #I1, #I2 } }, | |
687 | #define C_O1_I3(O1, I1, I2, I3) { .args_ct_str = { #O1, #I1, #I2, #I3 } }, | |
688 | #define C_O1_I4(O1, I1, I2, I3, I4) { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } }, | |
689 | ||
690 | #define C_N1_I2(O1, I1, I2) { .args_ct_str = { "&" #O1, #I1, #I2 } }, | |
691 | ||
692 | #define C_O2_I1(O1, O2, I1) { .args_ct_str = { #O1, #O2, #I1 } }, | |
693 | #define C_O2_I2(O1, O2, I1, I2) { .args_ct_str = { #O1, #O2, #I1, #I2 } }, | |
694 | #define C_O2_I3(O1, O2, I1, I2, I3) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3 } }, | |
695 | #define C_O2_I4(O1, O2, I1, I2, I3, I4) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3, #I4 } }, | |
696 | ||
697 | static const TCGTargetOpDef constraint_sets[] = { | |
698 | #include "tcg-target-con-set.h" | |
699 | }; | |
700 | ||
701 | ||
702 | #undef C_O0_I1 | |
703 | #undef C_O0_I2 | |
704 | #undef C_O0_I3 | |
705 | #undef C_O0_I4 | |
706 | #undef C_O1_I1 | |
707 | #undef C_O1_I2 | |
708 | #undef C_O1_I3 | |
709 | #undef C_O1_I4 | |
710 | #undef C_N1_I2 | |
711 | #undef C_O2_I1 | |
712 | #undef C_O2_I2 | |
713 | #undef C_O2_I3 | |
714 | #undef C_O2_I4 | |
715 | ||
716 | /* Expand the enumerator to be returned from tcg_target_op_def(). */ | |
717 | ||
718 | #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1) | |
719 | #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2) | |
720 | #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3) | |
721 | #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4) | |
722 | ||
723 | #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1) | |
724 | #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2) | |
725 | #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3) | |
726 | #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4) | |
727 | ||
728 | #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2) | |
729 | ||
730 | #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1) | |
731 | #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2) | |
732 | #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3) | |
733 | #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4) | |
734 | ||
139c1837 | 735 | #include "tcg-target.c.inc" |
c896fe29 | 736 | |
38b47b19 EC |
737 | static void alloc_tcg_plugin_context(TCGContext *s) |
738 | { | |
739 | #ifdef CONFIG_PLUGIN | |
740 | s->plugin_tb = g_new0(struct qemu_plugin_tb, 1); | |
741 | s->plugin_tb->insns = | |
742 | g_ptr_array_new_with_free_func(qemu_plugin_insn_cleanup_fn); | |
743 | #endif | |
744 | } | |
745 | ||
3468b59e EC |
746 | /* |
747 | * All TCG threads except the parent (i.e. the one that called tcg_context_init | |
748 | * and registered the target's TCG globals) must register with this function | |
749 | * before initiating translation. | |
750 | * | |
751 | * In user-mode we just point tcg_ctx to tcg_init_ctx. See the documentation | |
752 | * of tcg_region_init() for the reasoning behind this. | |
753 | * | |
754 | * In softmmu each caller registers its context in tcg_ctxs[]. Note that in | |
755 | * softmmu tcg_ctxs[] does not track tcg_ctx_init, since the initial context | |
756 | * is not used anymore for translation once this function is called. | |
757 | * | |
758 | * Not tracking tcg_init_ctx in tcg_ctxs[] in softmmu keeps code that iterates | |
759 | * over the array (e.g. tcg_code_size() the same for both softmmu and user-mode. | |
760 | */ | |
761 | #ifdef CONFIG_USER_ONLY | |
762 | void tcg_register_thread(void) | |
763 | { | |
764 | tcg_ctx = &tcg_init_ctx; | |
765 | } | |
766 | #else | |
767 | void tcg_register_thread(void) | |
768 | { | |
769 | TCGContext *s = g_malloc(sizeof(*s)); | |
770 | unsigned int i, n; | |
3468b59e EC |
771 | |
772 | *s = tcg_init_ctx; | |
773 | ||
774 | /* Relink mem_base. */ | |
775 | for (i = 0, n = tcg_init_ctx.nb_globals; i < n; ++i) { | |
776 | if (tcg_init_ctx.temps[i].mem_base) { | |
777 | ptrdiff_t b = tcg_init_ctx.temps[i].mem_base - tcg_init_ctx.temps; | |
778 | tcg_debug_assert(b >= 0 && b < n); | |
779 | s->temps[i].mem_base = &s->temps[b]; | |
780 | } | |
781 | } | |
782 | ||
783 | /* Claim an entry in tcg_ctxs */ | |
0e2d61cf RH |
784 | n = qatomic_fetch_inc(&tcg_cur_ctxs); |
785 | g_assert(n < tcg_max_ctxs); | |
d73415a3 | 786 | qatomic_set(&tcg_ctxs[n], s); |
3468b59e | 787 | |
38b47b19 EC |
788 | if (n > 0) { |
789 | alloc_tcg_plugin_context(s); | |
bf042e8e | 790 | tcg_region_initial_alloc(s); |
38b47b19 EC |
791 | } |
792 | ||
3468b59e | 793 | tcg_ctx = s; |
e8feb96f | 794 | } |
3468b59e | 795 | #endif /* !CONFIG_USER_ONLY */ |
e8feb96f | 796 | |
c896fe29 FB |
797 | /* pool based memory allocation */ |
798 | void *tcg_malloc_internal(TCGContext *s, int size) | |
799 | { | |
800 | TCGPool *p; | |
801 | int pool_size; | |
a813e36f | 802 | |
c896fe29 FB |
803 | if (size > TCG_POOL_CHUNK_SIZE) { |
804 | /* big malloc: insert a new pool (XXX: could optimize) */ | |
7267c094 | 805 | p = g_malloc(sizeof(TCGPool) + size); |
c896fe29 | 806 | p->size = size; |
4055299e KB |
807 | p->next = s->pool_first_large; |
808 | s->pool_first_large = p; | |
809 | return p->data; | |
c896fe29 FB |
810 | } else { |
811 | p = s->pool_current; | |
812 | if (!p) { | |
813 | p = s->pool_first; | |
814 | if (!p) | |
815 | goto new_pool; | |
816 | } else { | |
817 | if (!p->next) { | |
818 | new_pool: | |
819 | pool_size = TCG_POOL_CHUNK_SIZE; | |
7267c094 | 820 | p = g_malloc(sizeof(TCGPool) + pool_size); |
c896fe29 FB |
821 | p->size = pool_size; |
822 | p->next = NULL; | |
a813e36f | 823 | if (s->pool_current) { |
c896fe29 | 824 | s->pool_current->next = p; |
a813e36f | 825 | } else { |
c896fe29 | 826 | s->pool_first = p; |
a813e36f | 827 | } |
c896fe29 FB |
828 | } else { |
829 | p = p->next; | |
830 | } | |
831 | } | |
832 | } | |
833 | s->pool_current = p; | |
834 | s->pool_cur = p->data + size; | |
835 | s->pool_end = p->data + p->size; | |
836 | return p->data; | |
837 | } | |
838 | ||
839 | void tcg_pool_reset(TCGContext *s) | |
840 | { | |
4055299e KB |
841 | TCGPool *p, *t; |
842 | for (p = s->pool_first_large; p; p = t) { | |
843 | t = p->next; | |
844 | g_free(p); | |
845 | } | |
846 | s->pool_first_large = NULL; | |
c896fe29 FB |
847 | s->pool_cur = s->pool_end = NULL; |
848 | s->pool_current = NULL; | |
849 | } | |
850 | ||
8429a1ca RH |
851 | /* |
852 | * Create TCGHelperInfo structures for "tcg/tcg-ldst.h" functions, | |
853 | * akin to what "exec/helper-tcg.h" does with DEF_HELPER_FLAGS_N. | |
854 | * We only use these for layout in tcg_out_ld_helper_ret and | |
855 | * tcg_out_st_helper_args, and share them between several of | |
856 | * the helpers, with the end result that it's easier to build manually. | |
857 | */ | |
858 | ||
859 | #if TCG_TARGET_REG_BITS == 32 | |
860 | # define dh_typecode_ttl dh_typecode_i32 | |
861 | #else | |
862 | # define dh_typecode_ttl dh_typecode_i64 | |
863 | #endif | |
864 | ||
865 | static TCGHelperInfo info_helper_ld32_mmu = { | |
866 | .flags = TCG_CALL_NO_WG, | |
867 | .typemask = dh_typemask(ttl, 0) /* return tcg_target_ulong */ | |
868 | | dh_typemask(env, 1) | |
24e46e6c | 869 | | dh_typemask(i64, 2) /* uint64_t addr */ |
8429a1ca RH |
870 | | dh_typemask(i32, 3) /* unsigned oi */ |
871 | | dh_typemask(ptr, 4) /* uintptr_t ra */ | |
872 | }; | |
873 | ||
874 | static TCGHelperInfo info_helper_ld64_mmu = { | |
875 | .flags = TCG_CALL_NO_WG, | |
876 | .typemask = dh_typemask(i64, 0) /* return uint64_t */ | |
877 | | dh_typemask(env, 1) | |
24e46e6c | 878 | | dh_typemask(i64, 2) /* uint64_t addr */ |
8429a1ca RH |
879 | | dh_typemask(i32, 3) /* unsigned oi */ |
880 | | dh_typemask(ptr, 4) /* uintptr_t ra */ | |
881 | }; | |
882 | ||
ebebea53 RH |
883 | static TCGHelperInfo info_helper_ld128_mmu = { |
884 | .flags = TCG_CALL_NO_WG, | |
885 | .typemask = dh_typemask(i128, 0) /* return Int128 */ | |
886 | | dh_typemask(env, 1) | |
24e46e6c | 887 | | dh_typemask(i64, 2) /* uint64_t addr */ |
ebebea53 RH |
888 | | dh_typemask(i32, 3) /* unsigned oi */ |
889 | | dh_typemask(ptr, 4) /* uintptr_t ra */ | |
890 | }; | |
891 | ||
8429a1ca RH |
892 | static TCGHelperInfo info_helper_st32_mmu = { |
893 | .flags = TCG_CALL_NO_WG, | |
894 | .typemask = dh_typemask(void, 0) | |
895 | | dh_typemask(env, 1) | |
24e46e6c | 896 | | dh_typemask(i64, 2) /* uint64_t addr */ |
8429a1ca RH |
897 | | dh_typemask(i32, 3) /* uint32_t data */ |
898 | | dh_typemask(i32, 4) /* unsigned oi */ | |
899 | | dh_typemask(ptr, 5) /* uintptr_t ra */ | |
900 | }; | |
901 | ||
902 | static TCGHelperInfo info_helper_st64_mmu = { | |
903 | .flags = TCG_CALL_NO_WG, | |
904 | .typemask = dh_typemask(void, 0) | |
905 | | dh_typemask(env, 1) | |
24e46e6c | 906 | | dh_typemask(i64, 2) /* uint64_t addr */ |
8429a1ca RH |
907 | | dh_typemask(i64, 3) /* uint64_t data */ |
908 | | dh_typemask(i32, 4) /* unsigned oi */ | |
909 | | dh_typemask(ptr, 5) /* uintptr_t ra */ | |
910 | }; | |
911 | ||
ebebea53 RH |
912 | static TCGHelperInfo info_helper_st128_mmu = { |
913 | .flags = TCG_CALL_NO_WG, | |
914 | .typemask = dh_typemask(void, 0) | |
915 | | dh_typemask(env, 1) | |
24e46e6c | 916 | | dh_typemask(i64, 2) /* uint64_t addr */ |
ebebea53 RH |
917 | | dh_typemask(i128, 3) /* Int128 data */ |
918 | | dh_typemask(i32, 4) /* unsigned oi */ | |
919 | | dh_typemask(ptr, 5) /* uintptr_t ra */ | |
920 | }; | |
921 | ||
22f15579 | 922 | #ifdef CONFIG_TCG_INTERPRETER |
c6ef8c7b PMD |
923 | static ffi_type *typecode_to_ffi(int argmask) |
924 | { | |
e9709e17 RH |
925 | /* |
926 | * libffi does not support __int128_t, so we have forced Int128 | |
927 | * to use the structure definition instead of the builtin type. | |
928 | */ | |
929 | static ffi_type *ffi_type_i128_elements[3] = { | |
930 | &ffi_type_uint64, | |
931 | &ffi_type_uint64, | |
932 | NULL | |
933 | }; | |
934 | static ffi_type ffi_type_i128 = { | |
935 | .size = 16, | |
936 | .alignment = __alignof__(Int128), | |
937 | .type = FFI_TYPE_STRUCT, | |
938 | .elements = ffi_type_i128_elements, | |
939 | }; | |
940 | ||
c6ef8c7b PMD |
941 | switch (argmask) { |
942 | case dh_typecode_void: | |
943 | return &ffi_type_void; | |
944 | case dh_typecode_i32: | |
945 | return &ffi_type_uint32; | |
946 | case dh_typecode_s32: | |
947 | return &ffi_type_sint32; | |
948 | case dh_typecode_i64: | |
949 | return &ffi_type_uint64; | |
950 | case dh_typecode_s64: | |
951 | return &ffi_type_sint64; | |
952 | case dh_typecode_ptr: | |
953 | return &ffi_type_pointer; | |
e9709e17 RH |
954 | case dh_typecode_i128: |
955 | return &ffi_type_i128; | |
c6ef8c7b PMD |
956 | } |
957 | g_assert_not_reached(); | |
958 | } | |
0c22e176 | 959 | |
d53106c9 | 960 | static ffi_cif *init_ffi_layout(TCGHelperInfo *info) |
0c22e176 | 961 | { |
d53106c9 RH |
962 | unsigned typemask = info->typemask; |
963 | struct { | |
964 | ffi_cif cif; | |
965 | ffi_type *args[]; | |
966 | } *ca; | |
967 | ffi_status status; | |
968 | int nargs; | |
969 | ||
970 | /* Ignoring the return type, find the last non-zero field. */ | |
971 | nargs = 32 - clz32(typemask >> 3); | |
972 | nargs = DIV_ROUND_UP(nargs, 3); | |
973 | assert(nargs <= MAX_CALL_IARGS); | |
974 | ||
975 | ca = g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *)); | |
976 | ca->cif.rtype = typecode_to_ffi(typemask & 7); | |
977 | ca->cif.nargs = nargs; | |
978 | ||
979 | if (nargs != 0) { | |
980 | ca->cif.arg_types = ca->args; | |
981 | for (int j = 0; j < nargs; ++j) { | |
982 | int typecode = extract32(typemask, (j + 1) * 3, 3); | |
983 | ca->args[j] = typecode_to_ffi(typecode); | |
0c22e176 | 984 | } |
0c22e176 | 985 | } |
f9c4bb80 | 986 | |
d53106c9 RH |
987 | status = ffi_prep_cif(&ca->cif, FFI_DEFAULT_ABI, nargs, |
988 | ca->cif.rtype, ca->cif.arg_types); | |
989 | assert(status == FFI_OK); | |
990 | ||
991 | return &ca->cif; | |
0c22e176 | 992 | } |
d53106c9 RH |
993 | |
994 | #define HELPER_INFO_INIT(I) (&(I)->cif) | |
995 | #define HELPER_INFO_INIT_VAL(I) init_ffi_layout(I) | |
996 | #else | |
997 | #define HELPER_INFO_INIT(I) (&(I)->init) | |
998 | #define HELPER_INFO_INIT_VAL(I) 1 | |
0c22e176 | 999 | #endif /* CONFIG_TCG_INTERPRETER */ |
22f15579 | 1000 | |
338b61e9 RH |
1001 | static inline bool arg_slot_reg_p(unsigned arg_slot) |
1002 | { | |
1003 | /* | |
1004 | * Split the sizeof away from the comparison to avoid Werror from | |
1005 | * "unsigned < 0 is always false", when iarg_regs is empty. | |
1006 | */ | |
1007 | unsigned nreg = ARRAY_SIZE(tcg_target_call_iarg_regs); | |
1008 | return arg_slot < nreg; | |
1009 | } | |
1010 | ||
d78e4a4f RH |
1011 | static inline int arg_slot_stk_ofs(unsigned arg_slot) |
1012 | { | |
1013 | unsigned max = TCG_STATIC_CALL_ARGS_SIZE / sizeof(tcg_target_long); | |
1014 | unsigned stk_slot = arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs); | |
1015 | ||
1016 | tcg_debug_assert(stk_slot < max); | |
1017 | return TCG_TARGET_CALL_STACK_OFFSET + stk_slot * sizeof(tcg_target_long); | |
1018 | } | |
1019 | ||
39004a71 RH |
1020 | typedef struct TCGCumulativeArgs { |
1021 | int arg_idx; /* tcg_gen_callN args[] */ | |
1022 | int info_in_idx; /* TCGHelperInfo in[] */ | |
1023 | int arg_slot; /* regs+stack slot */ | |
1024 | int ref_slot; /* stack slots for references */ | |
1025 | } TCGCumulativeArgs; | |
1026 | ||
1027 | static void layout_arg_even(TCGCumulativeArgs *cum) | |
1028 | { | |
1029 | cum->arg_slot += cum->arg_slot & 1; | |
1030 | } | |
1031 | ||
1032 | static void layout_arg_1(TCGCumulativeArgs *cum, TCGHelperInfo *info, | |
1033 | TCGCallArgumentKind kind) | |
1034 | { | |
1035 | TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; | |
1036 | ||
1037 | *loc = (TCGCallArgumentLoc){ | |
1038 | .kind = kind, | |
1039 | .arg_idx = cum->arg_idx, | |
1040 | .arg_slot = cum->arg_slot, | |
1041 | }; | |
1042 | cum->info_in_idx++; | |
1043 | cum->arg_slot++; | |
1044 | } | |
1045 | ||
1046 | static void layout_arg_normal_n(TCGCumulativeArgs *cum, | |
1047 | TCGHelperInfo *info, int n) | |
1048 | { | |
1049 | TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; | |
1050 | ||
1051 | for (int i = 0; i < n; ++i) { | |
1052 | /* Layout all using the same arg_idx, adjusting the subindex. */ | |
1053 | loc[i] = (TCGCallArgumentLoc){ | |
1054 | .kind = TCG_CALL_ARG_NORMAL, | |
1055 | .arg_idx = cum->arg_idx, | |
1056 | .tmp_subindex = i, | |
1057 | .arg_slot = cum->arg_slot + i, | |
1058 | }; | |
1059 | } | |
1060 | cum->info_in_idx += n; | |
1061 | cum->arg_slot += n; | |
1062 | } | |
1063 | ||
313bdea8 RH |
1064 | static void layout_arg_by_ref(TCGCumulativeArgs *cum, TCGHelperInfo *info) |
1065 | { | |
1066 | TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; | |
1067 | int n = 128 / TCG_TARGET_REG_BITS; | |
1068 | ||
1069 | /* The first subindex carries the pointer. */ | |
1070 | layout_arg_1(cum, info, TCG_CALL_ARG_BY_REF); | |
1071 | ||
1072 | /* | |
1073 | * The callee is allowed to clobber memory associated with | |
1074 | * structure pass by-reference. Therefore we must make copies. | |
1075 | * Allocate space from "ref_slot", which will be adjusted to | |
1076 | * follow the parameters on the stack. | |
1077 | */ | |
1078 | loc[0].ref_slot = cum->ref_slot; | |
1079 | ||
1080 | /* | |
1081 | * Subsequent words also go into the reference slot, but | |
1082 | * do not accumulate into the regular arguments. | |
1083 | */ | |
1084 | for (int i = 1; i < n; ++i) { | |
1085 | loc[i] = (TCGCallArgumentLoc){ | |
1086 | .kind = TCG_CALL_ARG_BY_REF_N, | |
1087 | .arg_idx = cum->arg_idx, | |
1088 | .tmp_subindex = i, | |
1089 | .ref_slot = cum->ref_slot + i, | |
1090 | }; | |
1091 | } | |
1092 | cum->info_in_idx += n; | |
1093 | cum->ref_slot += n; | |
1094 | } | |
1095 | ||
39004a71 RH |
1096 | static void init_call_layout(TCGHelperInfo *info) |
1097 | { | |
1098 | int max_reg_slots = ARRAY_SIZE(tcg_target_call_iarg_regs); | |
1099 | int max_stk_slots = TCG_STATIC_CALL_ARGS_SIZE / sizeof(tcg_target_long); | |
1100 | unsigned typemask = info->typemask; | |
1101 | unsigned typecode; | |
1102 | TCGCumulativeArgs cum = { }; | |
1103 | ||
1104 | /* | |
1105 | * Parse and place any function return value. | |
1106 | */ | |
1107 | typecode = typemask & 7; | |
1108 | switch (typecode) { | |
1109 | case dh_typecode_void: | |
1110 | info->nr_out = 0; | |
1111 | break; | |
1112 | case dh_typecode_i32: | |
1113 | case dh_typecode_s32: | |
1114 | case dh_typecode_ptr: | |
1115 | info->nr_out = 1; | |
1116 | info->out_kind = TCG_CALL_RET_NORMAL; | |
1117 | break; | |
1118 | case dh_typecode_i64: | |
1119 | case dh_typecode_s64: | |
1120 | info->nr_out = 64 / TCG_TARGET_REG_BITS; | |
1121 | info->out_kind = TCG_CALL_RET_NORMAL; | |
5e3d0c19 RH |
1122 | /* Query the last register now to trigger any assert early. */ |
1123 | tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); | |
466d3759 RH |
1124 | break; |
1125 | case dh_typecode_i128: | |
1126 | info->nr_out = 128 / TCG_TARGET_REG_BITS; | |
5427a9a7 RH |
1127 | info->out_kind = TCG_TARGET_CALL_RET_I128; |
1128 | switch (TCG_TARGET_CALL_RET_I128) { | |
466d3759 | 1129 | case TCG_CALL_RET_NORMAL: |
5e3d0c19 RH |
1130 | /* Query the last register now to trigger any assert early. */ |
1131 | tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); | |
466d3759 | 1132 | break; |
c6556aa0 RH |
1133 | case TCG_CALL_RET_BY_VEC: |
1134 | /* Query the single register now to trigger any assert early. */ | |
1135 | tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0); | |
1136 | break; | |
313bdea8 RH |
1137 | case TCG_CALL_RET_BY_REF: |
1138 | /* | |
1139 | * Allocate the first argument to the output. | |
1140 | * We don't need to store this anywhere, just make it | |
1141 | * unavailable for use in the input loop below. | |
1142 | */ | |
1143 | cum.arg_slot = 1; | |
1144 | break; | |
466d3759 RH |
1145 | default: |
1146 | qemu_build_not_reached(); | |
1147 | } | |
39004a71 RH |
1148 | break; |
1149 | default: | |
1150 | g_assert_not_reached(); | |
1151 | } | |
39004a71 RH |
1152 | |
1153 | /* | |
1154 | * Parse and place function arguments. | |
1155 | */ | |
1156 | for (typemask >>= 3; typemask; typemask >>= 3, cum.arg_idx++) { | |
1157 | TCGCallArgumentKind kind; | |
1158 | TCGType type; | |
1159 | ||
1160 | typecode = typemask & 7; | |
1161 | switch (typecode) { | |
1162 | case dh_typecode_i32: | |
1163 | case dh_typecode_s32: | |
1164 | type = TCG_TYPE_I32; | |
1165 | break; | |
1166 | case dh_typecode_i64: | |
1167 | case dh_typecode_s64: | |
1168 | type = TCG_TYPE_I64; | |
1169 | break; | |
1170 | case dh_typecode_ptr: | |
1171 | type = TCG_TYPE_PTR; | |
1172 | break; | |
466d3759 RH |
1173 | case dh_typecode_i128: |
1174 | type = TCG_TYPE_I128; | |
1175 | break; | |
39004a71 RH |
1176 | default: |
1177 | g_assert_not_reached(); | |
1178 | } | |
1179 | ||
1180 | switch (type) { | |
1181 | case TCG_TYPE_I32: | |
1182 | switch (TCG_TARGET_CALL_ARG_I32) { | |
1183 | case TCG_CALL_ARG_EVEN: | |
1184 | layout_arg_even(&cum); | |
1185 | /* fall through */ | |
1186 | case TCG_CALL_ARG_NORMAL: | |
1187 | layout_arg_1(&cum, info, TCG_CALL_ARG_NORMAL); | |
1188 | break; | |
1189 | case TCG_CALL_ARG_EXTEND: | |
1190 | kind = TCG_CALL_ARG_EXTEND_U + (typecode & 1); | |
1191 | layout_arg_1(&cum, info, kind); | |
1192 | break; | |
1193 | default: | |
1194 | qemu_build_not_reached(); | |
1195 | } | |
1196 | break; | |
1197 | ||
1198 | case TCG_TYPE_I64: | |
1199 | switch (TCG_TARGET_CALL_ARG_I64) { | |
1200 | case TCG_CALL_ARG_EVEN: | |
1201 | layout_arg_even(&cum); | |
1202 | /* fall through */ | |
1203 | case TCG_CALL_ARG_NORMAL: | |
1204 | if (TCG_TARGET_REG_BITS == 32) { | |
1205 | layout_arg_normal_n(&cum, info, 2); | |
1206 | } else { | |
1207 | layout_arg_1(&cum, info, TCG_CALL_ARG_NORMAL); | |
1208 | } | |
1209 | break; | |
1210 | default: | |
1211 | qemu_build_not_reached(); | |
1212 | } | |
1213 | break; | |
1214 | ||
466d3759 | 1215 | case TCG_TYPE_I128: |
5427a9a7 | 1216 | switch (TCG_TARGET_CALL_ARG_I128) { |
466d3759 RH |
1217 | case TCG_CALL_ARG_EVEN: |
1218 | layout_arg_even(&cum); | |
1219 | /* fall through */ | |
1220 | case TCG_CALL_ARG_NORMAL: | |
1221 | layout_arg_normal_n(&cum, info, 128 / TCG_TARGET_REG_BITS); | |
1222 | break; | |
313bdea8 RH |
1223 | case TCG_CALL_ARG_BY_REF: |
1224 | layout_arg_by_ref(&cum, info); | |
1225 | break; | |
466d3759 RH |
1226 | default: |
1227 | qemu_build_not_reached(); | |
1228 | } | |
1229 | break; | |
1230 | ||
39004a71 RH |
1231 | default: |
1232 | g_assert_not_reached(); | |
1233 | } | |
1234 | } | |
1235 | info->nr_in = cum.info_in_idx; | |
1236 | ||
1237 | /* Validate that we didn't overrun the input array. */ | |
1238 | assert(cum.info_in_idx <= ARRAY_SIZE(info->in)); | |
1239 | /* Validate the backend has enough argument space. */ | |
1240 | assert(cum.arg_slot <= max_reg_slots + max_stk_slots); | |
313bdea8 RH |
1241 | |
1242 | /* | |
1243 | * Relocate the "ref_slot" area to the end of the parameters. | |
1244 | * Minimizing this stack offset helps code size for x86, | |
1245 | * which has a signed 8-bit offset encoding. | |
1246 | */ | |
1247 | if (cum.ref_slot != 0) { | |
1248 | int ref_base = 0; | |
1249 | ||
1250 | if (cum.arg_slot > max_reg_slots) { | |
1251 | int align = __alignof(Int128) / sizeof(tcg_target_long); | |
1252 | ||
1253 | ref_base = cum.arg_slot - max_reg_slots; | |
1254 | if (align > 1) { | |
1255 | ref_base = ROUND_UP(ref_base, align); | |
1256 | } | |
1257 | } | |
1258 | assert(ref_base + cum.ref_slot <= max_stk_slots); | |
d78e4a4f | 1259 | ref_base += max_reg_slots; |
313bdea8 RH |
1260 | |
1261 | if (ref_base != 0) { | |
1262 | for (int i = cum.info_in_idx - 1; i >= 0; --i) { | |
1263 | TCGCallArgumentLoc *loc = &info->in[i]; | |
1264 | switch (loc->kind) { | |
1265 | case TCG_CALL_ARG_BY_REF: | |
1266 | case TCG_CALL_ARG_BY_REF_N: | |
1267 | loc->ref_slot += ref_base; | |
1268 | break; | |
1269 | default: | |
1270 | break; | |
1271 | } | |
1272 | } | |
1273 | } | |
1274 | } | |
39004a71 RH |
1275 | } |
1276 | ||
91478cef | 1277 | static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)]; |
f69d277e | 1278 | static void process_op_defs(TCGContext *s); |
1c2adb95 RH |
1279 | static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, |
1280 | TCGReg reg, const char *name); | |
91478cef | 1281 | |
43b972b7 | 1282 | static void tcg_context_init(unsigned max_cpus) |
c896fe29 | 1283 | { |
a76aabd3 | 1284 | TCGContext *s = &tcg_init_ctx; |
100b5e01 | 1285 | int op, total_args, n, i; |
c896fe29 FB |
1286 | TCGOpDef *def; |
1287 | TCGArgConstraint *args_ct; | |
1c2adb95 | 1288 | TCGTemp *ts; |
c896fe29 FB |
1289 | |
1290 | memset(s, 0, sizeof(*s)); | |
c896fe29 | 1291 | s->nb_globals = 0; |
c70fbf0a | 1292 | |
c896fe29 FB |
1293 | /* Count total number of arguments and allocate the corresponding |
1294 | space */ | |
1295 | total_args = 0; | |
1296 | for(op = 0; op < NB_OPS; op++) { | |
1297 | def = &tcg_op_defs[op]; | |
1298 | n = def->nb_iargs + def->nb_oargs; | |
1299 | total_args += n; | |
1300 | } | |
1301 | ||
bc2b17e6 | 1302 | args_ct = g_new0(TCGArgConstraint, total_args); |
c896fe29 FB |
1303 | |
1304 | for(op = 0; op < NB_OPS; op++) { | |
1305 | def = &tcg_op_defs[op]; | |
1306 | def->args_ct = args_ct; | |
c896fe29 | 1307 | n = def->nb_iargs + def->nb_oargs; |
c896fe29 FB |
1308 | args_ct += n; |
1309 | } | |
5cd8f621 | 1310 | |
8429a1ca RH |
1311 | init_call_layout(&info_helper_ld32_mmu); |
1312 | init_call_layout(&info_helper_ld64_mmu); | |
ebebea53 | 1313 | init_call_layout(&info_helper_ld128_mmu); |
8429a1ca RH |
1314 | init_call_layout(&info_helper_st32_mmu); |
1315 | init_call_layout(&info_helper_st64_mmu); | |
ebebea53 | 1316 | init_call_layout(&info_helper_st128_mmu); |
8429a1ca | 1317 | |
c896fe29 | 1318 | tcg_target_init(s); |
f69d277e | 1319 | process_op_defs(s); |
91478cef RH |
1320 | |
1321 | /* Reverse the order of the saved registers, assuming they're all at | |
1322 | the start of tcg_target_reg_alloc_order. */ | |
1323 | for (n = 0; n < ARRAY_SIZE(tcg_target_reg_alloc_order); ++n) { | |
1324 | int r = tcg_target_reg_alloc_order[n]; | |
1325 | if (tcg_regset_test_reg(tcg_target_call_clobber_regs, r)) { | |
1326 | break; | |
1327 | } | |
1328 | } | |
1329 | for (i = 0; i < n; ++i) { | |
1330 | indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[n - 1 - i]; | |
1331 | } | |
1332 | for (; i < ARRAY_SIZE(tcg_target_reg_alloc_order); ++i) { | |
1333 | indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[i]; | |
1334 | } | |
b1311c4a | 1335 | |
38b47b19 EC |
1336 | alloc_tcg_plugin_context(s); |
1337 | ||
b1311c4a | 1338 | tcg_ctx = s; |
3468b59e EC |
1339 | /* |
1340 | * In user-mode we simply share the init context among threads, since we | |
1341 | * use a single region. See the documentation tcg_region_init() for the | |
1342 | * reasoning behind this. | |
1343 | * In softmmu we will have at most max_cpus TCG threads. | |
1344 | */ | |
1345 | #ifdef CONFIG_USER_ONLY | |
df2cce29 | 1346 | tcg_ctxs = &tcg_ctx; |
0e2d61cf RH |
1347 | tcg_cur_ctxs = 1; |
1348 | tcg_max_ctxs = 1; | |
3468b59e | 1349 | #else |
0e2d61cf RH |
1350 | tcg_max_ctxs = max_cpus; |
1351 | tcg_ctxs = g_new0(TCGContext *, max_cpus); | |
3468b59e | 1352 | #endif |
1c2adb95 RH |
1353 | |
1354 | tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0)); | |
1355 | ts = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env"); | |
1356 | cpu_env = temp_tcgv_ptr(ts); | |
9002ec79 | 1357 | } |
b03cce8e | 1358 | |
43b972b7 | 1359 | void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus) |
a76aabd3 | 1360 | { |
43b972b7 RH |
1361 | tcg_context_init(max_cpus); |
1362 | tcg_region_init(tb_size, splitwx, max_cpus); | |
a76aabd3 RH |
1363 | } |
1364 | ||
6e3b2bfd EC |
1365 | /* |
1366 | * Allocate TBs right before their corresponding translated code, making | |
1367 | * sure that TBs and code are on different cache lines. | |
1368 | */ | |
1369 | TranslationBlock *tcg_tb_alloc(TCGContext *s) | |
1370 | { | |
1371 | uintptr_t align = qemu_icache_linesize; | |
1372 | TranslationBlock *tb; | |
1373 | void *next; | |
1374 | ||
e8feb96f | 1375 | retry: |
6e3b2bfd EC |
1376 | tb = (void *)ROUND_UP((uintptr_t)s->code_gen_ptr, align); |
1377 | next = (void *)ROUND_UP((uintptr_t)(tb + 1), align); | |
1378 | ||
1379 | if (unlikely(next > s->code_gen_highwater)) { | |
e8feb96f EC |
1380 | if (tcg_region_alloc(s)) { |
1381 | return NULL; | |
1382 | } | |
1383 | goto retry; | |
6e3b2bfd | 1384 | } |
d73415a3 | 1385 | qatomic_set(&s->code_gen_ptr, next); |
57a26946 | 1386 | s->data_gen_ptr = NULL; |
6e3b2bfd EC |
1387 | return tb; |
1388 | } | |
1389 | ||
9002ec79 RH |
1390 | void tcg_prologue_init(TCGContext *s) |
1391 | { | |
b0a0794a | 1392 | size_t prologue_size; |
8163b749 | 1393 | |
b0a0794a RH |
1394 | s->code_ptr = s->code_gen_ptr; |
1395 | s->code_buf = s->code_gen_ptr; | |
5b38ee31 | 1396 | s->data_gen_ptr = NULL; |
b91ccb31 RH |
1397 | |
1398 | #ifndef CONFIG_TCG_INTERPRETER | |
b0a0794a | 1399 | tcg_qemu_tb_exec = (tcg_prologue_fn *)tcg_splitwx_to_rx(s->code_ptr); |
b91ccb31 | 1400 | #endif |
8163b749 | 1401 | |
5b38ee31 RH |
1402 | #ifdef TCG_TARGET_NEED_POOL_LABELS |
1403 | s->pool_labels = NULL; | |
1404 | #endif | |
1405 | ||
653b87eb | 1406 | qemu_thread_jit_write(); |
8163b749 | 1407 | /* Generate the prologue. */ |
b03cce8e | 1408 | tcg_target_qemu_prologue(s); |
5b38ee31 RH |
1409 | |
1410 | #ifdef TCG_TARGET_NEED_POOL_LABELS | |
1411 | /* Allow the prologue to put e.g. guest_base into a pool entry. */ | |
1412 | { | |
1768987b RH |
1413 | int result = tcg_out_pool_finalize(s); |
1414 | tcg_debug_assert(result == 0); | |
5b38ee31 RH |
1415 | } |
1416 | #endif | |
1417 | ||
b0a0794a | 1418 | prologue_size = tcg_current_code_size(s); |
5584e2db | 1419 | perf_report_prologue(s->code_gen_ptr, prologue_size); |
b0a0794a | 1420 | |
df5d2b16 | 1421 | #ifndef CONFIG_TCG_INTERPRETER |
b0a0794a RH |
1422 | flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s->code_buf), |
1423 | (uintptr_t)s->code_buf, prologue_size); | |
df5d2b16 | 1424 | #endif |
8163b749 | 1425 | |
d6b64b2b | 1426 | if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) { |
c60f599b | 1427 | FILE *logfile = qemu_log_trylock(); |
78b54858 RH |
1428 | if (logfile) { |
1429 | fprintf(logfile, "PROLOGUE: [size=%zu]\n", prologue_size); | |
1430 | if (s->data_gen_ptr) { | |
1431 | size_t code_size = s->data_gen_ptr - s->code_gen_ptr; | |
1432 | size_t data_size = prologue_size - code_size; | |
1433 | size_t i; | |
1434 | ||
1435 | disas(logfile, s->code_gen_ptr, code_size); | |
1436 | ||
1437 | for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) { | |
1438 | if (sizeof(tcg_target_ulong) == 8) { | |
1439 | fprintf(logfile, | |
1440 | "0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n", | |
1441 | (uintptr_t)s->data_gen_ptr + i, | |
1442 | *(uint64_t *)(s->data_gen_ptr + i)); | |
1443 | } else { | |
1444 | fprintf(logfile, | |
1445 | "0x%08" PRIxPTR ": .long 0x%08x\n", | |
1446 | (uintptr_t)s->data_gen_ptr + i, | |
1447 | *(uint32_t *)(s->data_gen_ptr + i)); | |
1448 | } | |
5b38ee31 | 1449 | } |
78b54858 RH |
1450 | } else { |
1451 | disas(logfile, s->code_gen_ptr, prologue_size); | |
5b38ee31 | 1452 | } |
78b54858 | 1453 | fprintf(logfile, "\n"); |
78b54858 | 1454 | qemu_log_unlock(logfile); |
5b38ee31 | 1455 | } |
d6b64b2b | 1456 | } |
cedbcb01 | 1457 | |
6eea0434 RH |
1458 | #ifndef CONFIG_TCG_INTERPRETER |
1459 | /* | |
1460 | * Assert that goto_ptr is implemented completely, setting an epilogue. | |
1461 | * For tci, we use NULL as the signal to return from the interpreter, | |
1462 | * so skip this check. | |
1463 | */ | |
f4e01e30 | 1464 | tcg_debug_assert(tcg_code_gen_epilogue != NULL); |
6eea0434 | 1465 | #endif |
d1c74ab3 RH |
1466 | |
1467 | tcg_region_prologue_set(s); | |
c896fe29 FB |
1468 | } |
1469 | ||
c896fe29 FB |
1470 | void tcg_func_start(TCGContext *s) |
1471 | { | |
1472 | tcg_pool_reset(s); | |
1473 | s->nb_temps = s->nb_globals; | |
0ec9eabc RH |
1474 | |
1475 | /* No temps have been previously allocated for size or locality. */ | |
1476 | memset(s->free_temps, 0, sizeof(s->free_temps)); | |
1477 | ||
c0522136 RH |
1478 | /* No constant temps have been previously allocated. */ |
1479 | for (int i = 0; i < TCG_TYPE_COUNT; ++i) { | |
1480 | if (s->const_table[i]) { | |
1481 | g_hash_table_remove_all(s->const_table[i]); | |
1482 | } | |
1483 | } | |
1484 | ||
abebf925 | 1485 | s->nb_ops = 0; |
c896fe29 FB |
1486 | s->nb_labels = 0; |
1487 | s->current_frame_offset = s->frame_start; | |
1488 | ||
0a209d4b RH |
1489 | #ifdef CONFIG_DEBUG_TCG |
1490 | s->goto_tb_issue_mask = 0; | |
1491 | #endif | |
1492 | ||
15fa08f8 RH |
1493 | QTAILQ_INIT(&s->ops); |
1494 | QTAILQ_INIT(&s->free_ops); | |
bef16ab4 | 1495 | QSIMPLEQ_INIT(&s->labels); |
4baf3978 RH |
1496 | |
1497 | tcg_debug_assert(s->addr_type == TCG_TYPE_I32 || | |
1498 | s->addr_type == TCG_TYPE_I64); | |
d0a9bb5e RH |
1499 | |
1500 | #if defined(CONFIG_SOFTMMU) && !defined(CONFIG_TCG_INTERPRETER) | |
1501 | tcg_debug_assert(s->tlb_fast_offset < 0); | |
1502 | tcg_debug_assert(s->tlb_fast_offset >= MIN_TLB_MASK_TABLE_OFS); | |
1503 | #endif | |
c896fe29 FB |
1504 | } |
1505 | ||
ae30e866 | 1506 | static TCGTemp *tcg_temp_alloc(TCGContext *s) |
7ca4b752 RH |
1507 | { |
1508 | int n = s->nb_temps++; | |
ae30e866 RH |
1509 | |
1510 | if (n >= TCG_MAX_TEMPS) { | |
db6b7d0c | 1511 | tcg_raise_tb_overflow(s); |
ae30e866 | 1512 | } |
7ca4b752 RH |
1513 | return memset(&s->temps[n], 0, sizeof(TCGTemp)); |
1514 | } | |
1515 | ||
ae30e866 | 1516 | static TCGTemp *tcg_global_alloc(TCGContext *s) |
7ca4b752 | 1517 | { |
fa477d25 RH |
1518 | TCGTemp *ts; |
1519 | ||
7ca4b752 | 1520 | tcg_debug_assert(s->nb_globals == s->nb_temps); |
ae30e866 | 1521 | tcg_debug_assert(s->nb_globals < TCG_MAX_TEMPS); |
7ca4b752 | 1522 | s->nb_globals++; |
fa477d25 | 1523 | ts = tcg_temp_alloc(s); |
ee17db83 | 1524 | ts->kind = TEMP_GLOBAL; |
fa477d25 RH |
1525 | |
1526 | return ts; | |
c896fe29 FB |
1527 | } |
1528 | ||
085272b3 RH |
1529 | static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, |
1530 | TCGReg reg, const char *name) | |
c896fe29 | 1531 | { |
c896fe29 | 1532 | TCGTemp *ts; |
c896fe29 | 1533 | |
1a057554 | 1534 | tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); |
7ca4b752 RH |
1535 | |
1536 | ts = tcg_global_alloc(s); | |
c896fe29 FB |
1537 | ts->base_type = type; |
1538 | ts->type = type; | |
ee17db83 | 1539 | ts->kind = TEMP_FIXED; |
c896fe29 | 1540 | ts->reg = reg; |
c896fe29 | 1541 | ts->name = name; |
c896fe29 | 1542 | tcg_regset_set_reg(s->reserved_regs, reg); |
7ca4b752 | 1543 | |
085272b3 | 1544 | return ts; |
a7812ae4 PB |
1545 | } |
1546 | ||
b6638662 | 1547 | void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size) |
b3a62939 | 1548 | { |
b3a62939 RH |
1549 | s->frame_start = start; |
1550 | s->frame_end = start + size; | |
085272b3 RH |
1551 | s->frame_temp |
1552 | = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame"); | |
b3a62939 RH |
1553 | } |
1554 | ||
085272b3 RH |
1555 | TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, |
1556 | intptr_t offset, const char *name) | |
c896fe29 | 1557 | { |
b1311c4a | 1558 | TCGContext *s = tcg_ctx; |
dc41aa7d | 1559 | TCGTemp *base_ts = tcgv_ptr_temp(base); |
7ca4b752 | 1560 | TCGTemp *ts = tcg_global_alloc(s); |
aef85402 | 1561 | int indirect_reg = 0; |
c896fe29 | 1562 | |
c0522136 RH |
1563 | switch (base_ts->kind) { |
1564 | case TEMP_FIXED: | |
1565 | break; | |
1566 | case TEMP_GLOBAL: | |
5a18407f RH |
1567 | /* We do not support double-indirect registers. */ |
1568 | tcg_debug_assert(!base_ts->indirect_reg); | |
b3915dbb | 1569 | base_ts->indirect_base = 1; |
5a18407f RH |
1570 | s->nb_indirects += (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64 |
1571 | ? 2 : 1); | |
1572 | indirect_reg = 1; | |
c0522136 RH |
1573 | break; |
1574 | default: | |
1575 | g_assert_not_reached(); | |
b3915dbb RH |
1576 | } |
1577 | ||
7ca4b752 RH |
1578 | if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { |
1579 | TCGTemp *ts2 = tcg_global_alloc(s); | |
c896fe29 | 1580 | char buf[64]; |
7ca4b752 RH |
1581 | |
1582 | ts->base_type = TCG_TYPE_I64; | |
c896fe29 | 1583 | ts->type = TCG_TYPE_I32; |
b3915dbb | 1584 | ts->indirect_reg = indirect_reg; |
c896fe29 | 1585 | ts->mem_allocated = 1; |
b3a62939 | 1586 | ts->mem_base = base_ts; |
aef85402 | 1587 | ts->mem_offset = offset; |
c896fe29 FB |
1588 | pstrcpy(buf, sizeof(buf), name); |
1589 | pstrcat(buf, sizeof(buf), "_0"); | |
1590 | ts->name = strdup(buf); | |
c896fe29 | 1591 | |
7ca4b752 RH |
1592 | tcg_debug_assert(ts2 == ts + 1); |
1593 | ts2->base_type = TCG_TYPE_I64; | |
1594 | ts2->type = TCG_TYPE_I32; | |
b3915dbb | 1595 | ts2->indirect_reg = indirect_reg; |
7ca4b752 RH |
1596 | ts2->mem_allocated = 1; |
1597 | ts2->mem_base = base_ts; | |
aef85402 | 1598 | ts2->mem_offset = offset + 4; |
fac87bd2 | 1599 | ts2->temp_subindex = 1; |
c896fe29 FB |
1600 | pstrcpy(buf, sizeof(buf), name); |
1601 | pstrcat(buf, sizeof(buf), "_1"); | |
120c1084 | 1602 | ts2->name = strdup(buf); |
7ca4b752 | 1603 | } else { |
c896fe29 FB |
1604 | ts->base_type = type; |
1605 | ts->type = type; | |
b3915dbb | 1606 | ts->indirect_reg = indirect_reg; |
c896fe29 | 1607 | ts->mem_allocated = 1; |
b3a62939 | 1608 | ts->mem_base = base_ts; |
c896fe29 | 1609 | ts->mem_offset = offset; |
c896fe29 | 1610 | ts->name = name; |
c896fe29 | 1611 | } |
085272b3 | 1612 | return ts; |
a7812ae4 PB |
1613 | } |
1614 | ||
bbf989bf | 1615 | TCGTemp *tcg_temp_new_internal(TCGType type, TCGTempKind kind) |
c896fe29 | 1616 | { |
b1311c4a | 1617 | TCGContext *s = tcg_ctx; |
c896fe29 | 1618 | TCGTemp *ts; |
e1c08b00 | 1619 | int n; |
7ca4b752 | 1620 | |
e1c08b00 RH |
1621 | if (kind == TEMP_EBB) { |
1622 | int idx = find_first_bit(s->free_temps[type].l, TCG_MAX_TEMPS); | |
1623 | ||
1624 | if (idx < TCG_MAX_TEMPS) { | |
1625 | /* There is already an available temp with the right type. */ | |
1626 | clear_bit(idx, s->free_temps[type].l); | |
1627 | ||
1628 | ts = &s->temps[idx]; | |
1629 | ts->temp_allocated = 1; | |
1630 | tcg_debug_assert(ts->base_type == type); | |
1631 | tcg_debug_assert(ts->kind == kind); | |
2f2e911d | 1632 | return ts; |
43eef72f | 1633 | } |
e1c08b00 RH |
1634 | } else { |
1635 | tcg_debug_assert(kind == TEMP_TB); | |
1636 | } | |
7ca4b752 | 1637 | |
e1c08b00 RH |
1638 | switch (type) { |
1639 | case TCG_TYPE_I32: | |
1640 | case TCG_TYPE_V64: | |
1641 | case TCG_TYPE_V128: | |
1642 | case TCG_TYPE_V256: | |
1643 | n = 1; | |
1644 | break; | |
1645 | case TCG_TYPE_I64: | |
1646 | n = 64 / TCG_TARGET_REG_BITS; | |
1647 | break; | |
1648 | case TCG_TYPE_I128: | |
1649 | n = 128 / TCG_TARGET_REG_BITS; | |
1650 | break; | |
1651 | default: | |
1652 | g_assert_not_reached(); | |
1653 | } | |
43eef72f | 1654 | |
e1c08b00 RH |
1655 | ts = tcg_temp_alloc(s); |
1656 | ts->base_type = type; | |
1657 | ts->temp_allocated = 1; | |
1658 | ts->kind = kind; | |
1659 | ||
1660 | if (n == 1) { | |
1661 | ts->type = type; | |
1662 | } else { | |
1663 | ts->type = TCG_TYPE_REG; | |
43eef72f | 1664 | |
e1c08b00 RH |
1665 | for (int i = 1; i < n; ++i) { |
1666 | TCGTemp *ts2 = tcg_temp_alloc(s); | |
43eef72f | 1667 | |
e1c08b00 RH |
1668 | tcg_debug_assert(ts2 == ts + i); |
1669 | ts2->base_type = type; | |
1670 | ts2->type = TCG_TYPE_REG; | |
1671 | ts2->temp_allocated = 1; | |
1672 | ts2->temp_subindex = i; | |
1673 | ts2->kind = kind; | |
e8996ee0 | 1674 | } |
c896fe29 | 1675 | } |
085272b3 | 1676 | return ts; |
c896fe29 FB |
1677 | } |
1678 | ||
d2fd745f RH |
1679 | TCGv_vec tcg_temp_new_vec(TCGType type) |
1680 | { | |
1681 | TCGTemp *t; | |
1682 | ||
1683 | #ifdef CONFIG_DEBUG_TCG | |
1684 | switch (type) { | |
1685 | case TCG_TYPE_V64: | |
1686 | assert(TCG_TARGET_HAS_v64); | |
1687 | break; | |
1688 | case TCG_TYPE_V128: | |
1689 | assert(TCG_TARGET_HAS_v128); | |
1690 | break; | |
1691 | case TCG_TYPE_V256: | |
1692 | assert(TCG_TARGET_HAS_v256); | |
1693 | break; | |
1694 | default: | |
1695 | g_assert_not_reached(); | |
1696 | } | |
1697 | #endif | |
1698 | ||
bbf989bf | 1699 | t = tcg_temp_new_internal(type, TEMP_EBB); |
d2fd745f RH |
1700 | return temp_tcgv_vec(t); |
1701 | } | |
1702 | ||
1703 | /* Create a new temp of the same type as an existing temp. */ | |
1704 | TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match) | |
1705 | { | |
1706 | TCGTemp *t = tcgv_vec_temp(match); | |
1707 | ||
1708 | tcg_debug_assert(t->temp_allocated != 0); | |
1709 | ||
bbf989bf | 1710 | t = tcg_temp_new_internal(t->base_type, TEMP_EBB); |
d2fd745f RH |
1711 | return temp_tcgv_vec(t); |
1712 | } | |
1713 | ||
5bfa8034 | 1714 | void tcg_temp_free_internal(TCGTemp *ts) |
c896fe29 | 1715 | { |
b1311c4a | 1716 | TCGContext *s = tcg_ctx; |
c896fe29 | 1717 | |
c7482438 RH |
1718 | switch (ts->kind) { |
1719 | case TEMP_CONST: | |
f57c6915 | 1720 | case TEMP_TB: |
2f2e911d RH |
1721 | /* Silently ignore free. */ |
1722 | break; | |
1723 | case TEMP_EBB: | |
1724 | tcg_debug_assert(ts->temp_allocated != 0); | |
1725 | ts->temp_allocated = 0; | |
1726 | set_bit(temp_idx(ts), s->free_temps[ts->base_type].l); | |
c7482438 RH |
1727 | break; |
1728 | default: | |
2f2e911d | 1729 | /* It never made sense to free TEMP_FIXED or TEMP_GLOBAL. */ |
c7482438 | 1730 | g_assert_not_reached(); |
c0522136 | 1731 | } |
c896fe29 FB |
1732 | } |
1733 | ||
c0522136 RH |
1734 | TCGTemp *tcg_constant_internal(TCGType type, int64_t val) |
1735 | { | |
1736 | TCGContext *s = tcg_ctx; | |
1737 | GHashTable *h = s->const_table[type]; | |
1738 | TCGTemp *ts; | |
1739 | ||
1740 | if (h == NULL) { | |
1741 | h = g_hash_table_new(g_int64_hash, g_int64_equal); | |
1742 | s->const_table[type] = h; | |
1743 | } | |
1744 | ||
1745 | ts = g_hash_table_lookup(h, &val); | |
1746 | if (ts == NULL) { | |
aef85402 RH |
1747 | int64_t *val_ptr; |
1748 | ||
c0522136 RH |
1749 | ts = tcg_temp_alloc(s); |
1750 | ||
1751 | if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { | |
1752 | TCGTemp *ts2 = tcg_temp_alloc(s); | |
1753 | ||
aef85402 RH |
1754 | tcg_debug_assert(ts2 == ts + 1); |
1755 | ||
c0522136 RH |
1756 | ts->base_type = TCG_TYPE_I64; |
1757 | ts->type = TCG_TYPE_I32; | |
1758 | ts->kind = TEMP_CONST; | |
1759 | ts->temp_allocated = 1; | |
c0522136 | 1760 | |
c0522136 RH |
1761 | ts2->base_type = TCG_TYPE_I64; |
1762 | ts2->type = TCG_TYPE_I32; | |
1763 | ts2->kind = TEMP_CONST; | |
1764 | ts2->temp_allocated = 1; | |
fac87bd2 | 1765 | ts2->temp_subindex = 1; |
aef85402 RH |
1766 | |
1767 | /* | |
1768 | * Retain the full value of the 64-bit constant in the low | |
1769 | * part, so that the hash table works. Actual uses will | |
1770 | * truncate the value to the low part. | |
1771 | */ | |
1772 | ts[HOST_BIG_ENDIAN].val = val; | |
1773 | ts[!HOST_BIG_ENDIAN].val = val >> 32; | |
1774 | val_ptr = &ts[HOST_BIG_ENDIAN].val; | |
c0522136 RH |
1775 | } else { |
1776 | ts->base_type = type; | |
1777 | ts->type = type; | |
1778 | ts->kind = TEMP_CONST; | |
1779 | ts->temp_allocated = 1; | |
1780 | ts->val = val; | |
aef85402 | 1781 | val_ptr = &ts->val; |
c0522136 | 1782 | } |
aef85402 | 1783 | g_hash_table_insert(h, val_ptr, ts); |
c0522136 RH |
1784 | } |
1785 | ||
1786 | return ts; | |
1787 | } | |
1788 | ||
1789 | TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val) | |
1790 | { | |
1791 | val = dup_const(vece, val); | |
1792 | return temp_tcgv_vec(tcg_constant_internal(type, val)); | |
1793 | } | |
1794 | ||
88d4005b RH |
1795 | TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val) |
1796 | { | |
1797 | TCGTemp *t = tcgv_vec_temp(match); | |
1798 | ||
1799 | tcg_debug_assert(t->temp_allocated != 0); | |
1800 | return tcg_constant_vec(t->base_type, vece, val); | |
1801 | } | |
1802 | ||
177f648f RH |
1803 | #ifdef CONFIG_DEBUG_TCG |
1804 | size_t temp_idx(TCGTemp *ts) | |
1805 | { | |
1806 | ptrdiff_t n = ts - tcg_ctx->temps; | |
1807 | assert(n >= 0 && n < tcg_ctx->nb_temps); | |
1808 | return n; | |
1809 | } | |
1810 | ||
1811 | TCGTemp *tcgv_i32_temp(TCGv_i32 v) | |
1812 | { | |
1813 | uintptr_t o = (uintptr_t)v - offsetof(TCGContext, temps); | |
1814 | ||
1815 | assert(o < sizeof(TCGTemp) * tcg_ctx->nb_temps); | |
1816 | assert(o % sizeof(TCGTemp) == 0); | |
1817 | ||
1818 | return (void *)tcg_ctx + (uintptr_t)v; | |
1819 | } | |
1820 | #endif /* CONFIG_DEBUG_TCG */ | |
1821 | ||
be0f34b5 RH |
1822 | /* Return true if OP may appear in the opcode stream. |
1823 | Test the runtime variable that controls each opcode. */ | |
1824 | bool tcg_op_supported(TCGOpcode op) | |
1825 | { | |
d2fd745f RH |
1826 | const bool have_vec |
1827 | = TCG_TARGET_HAS_v64 | TCG_TARGET_HAS_v128 | TCG_TARGET_HAS_v256; | |
1828 | ||
be0f34b5 RH |
1829 | switch (op) { |
1830 | case INDEX_op_discard: | |
1831 | case INDEX_op_set_label: | |
1832 | case INDEX_op_call: | |
1833 | case INDEX_op_br: | |
1834 | case INDEX_op_mb: | |
1835 | case INDEX_op_insn_start: | |
1836 | case INDEX_op_exit_tb: | |
1837 | case INDEX_op_goto_tb: | |
f4e01e30 | 1838 | case INDEX_op_goto_ptr: |
fecccfcc RH |
1839 | case INDEX_op_qemu_ld_a32_i32: |
1840 | case INDEX_op_qemu_ld_a64_i32: | |
1841 | case INDEX_op_qemu_st_a32_i32: | |
1842 | case INDEX_op_qemu_st_a64_i32: | |
1843 | case INDEX_op_qemu_ld_a32_i64: | |
1844 | case INDEX_op_qemu_ld_a64_i64: | |
1845 | case INDEX_op_qemu_st_a32_i64: | |
1846 | case INDEX_op_qemu_st_a64_i64: | |
be0f34b5 RH |
1847 | return true; |
1848 | ||
fecccfcc RH |
1849 | case INDEX_op_qemu_st8_a32_i32: |
1850 | case INDEX_op_qemu_st8_a64_i32: | |
07ce0b05 RH |
1851 | return TCG_TARGET_HAS_qemu_st8_i32; |
1852 | ||
fecccfcc RH |
1853 | case INDEX_op_qemu_ld_a32_i128: |
1854 | case INDEX_op_qemu_ld_a64_i128: | |
1855 | case INDEX_op_qemu_st_a32_i128: | |
1856 | case INDEX_op_qemu_st_a64_i128: | |
12fde9bc RH |
1857 | return TCG_TARGET_HAS_qemu_ldst_i128; |
1858 | ||
be0f34b5 | 1859 | case INDEX_op_mov_i32: |
be0f34b5 RH |
1860 | case INDEX_op_setcond_i32: |
1861 | case INDEX_op_brcond_i32: | |
1862 | case INDEX_op_ld8u_i32: | |
1863 | case INDEX_op_ld8s_i32: | |
1864 | case INDEX_op_ld16u_i32: | |
1865 | case INDEX_op_ld16s_i32: | |
1866 | case INDEX_op_ld_i32: | |
1867 | case INDEX_op_st8_i32: | |
1868 | case INDEX_op_st16_i32: | |
1869 | case INDEX_op_st_i32: | |
1870 | case INDEX_op_add_i32: | |
1871 | case INDEX_op_sub_i32: | |
1872 | case INDEX_op_mul_i32: | |
1873 | case INDEX_op_and_i32: | |
1874 | case INDEX_op_or_i32: | |
1875 | case INDEX_op_xor_i32: | |
1876 | case INDEX_op_shl_i32: | |
1877 | case INDEX_op_shr_i32: | |
1878 | case INDEX_op_sar_i32: | |
1879 | return true; | |
1880 | ||
1881 | case INDEX_op_movcond_i32: | |
1882 | return TCG_TARGET_HAS_movcond_i32; | |
1883 | case INDEX_op_div_i32: | |
1884 | case INDEX_op_divu_i32: | |
1885 | return TCG_TARGET_HAS_div_i32; | |
1886 | case INDEX_op_rem_i32: | |
1887 | case INDEX_op_remu_i32: | |
1888 | return TCG_TARGET_HAS_rem_i32; | |
1889 | case INDEX_op_div2_i32: | |
1890 | case INDEX_op_divu2_i32: | |
1891 | return TCG_TARGET_HAS_div2_i32; | |
1892 | case INDEX_op_rotl_i32: | |
1893 | case INDEX_op_rotr_i32: | |
1894 | return TCG_TARGET_HAS_rot_i32; | |
1895 | case INDEX_op_deposit_i32: | |
1896 | return TCG_TARGET_HAS_deposit_i32; | |
1897 | case INDEX_op_extract_i32: | |
1898 | return TCG_TARGET_HAS_extract_i32; | |
1899 | case INDEX_op_sextract_i32: | |
1900 | return TCG_TARGET_HAS_sextract_i32; | |
fce1296f RH |
1901 | case INDEX_op_extract2_i32: |
1902 | return TCG_TARGET_HAS_extract2_i32; | |
be0f34b5 RH |
1903 | case INDEX_op_add2_i32: |
1904 | return TCG_TARGET_HAS_add2_i32; | |
1905 | case INDEX_op_sub2_i32: | |
1906 | return TCG_TARGET_HAS_sub2_i32; | |
1907 | case INDEX_op_mulu2_i32: | |
1908 | return TCG_TARGET_HAS_mulu2_i32; | |
1909 | case INDEX_op_muls2_i32: | |
1910 | return TCG_TARGET_HAS_muls2_i32; | |
1911 | case INDEX_op_muluh_i32: | |
1912 | return TCG_TARGET_HAS_muluh_i32; | |
1913 | case INDEX_op_mulsh_i32: | |
1914 | return TCG_TARGET_HAS_mulsh_i32; | |
1915 | case INDEX_op_ext8s_i32: | |
1916 | return TCG_TARGET_HAS_ext8s_i32; | |
1917 | case INDEX_op_ext16s_i32: | |
1918 | return TCG_TARGET_HAS_ext16s_i32; | |
1919 | case INDEX_op_ext8u_i32: | |
1920 | return TCG_TARGET_HAS_ext8u_i32; | |
1921 | case INDEX_op_ext16u_i32: | |
1922 | return TCG_TARGET_HAS_ext16u_i32; | |
1923 | case INDEX_op_bswap16_i32: | |
1924 | return TCG_TARGET_HAS_bswap16_i32; | |
1925 | case INDEX_op_bswap32_i32: | |
1926 | return TCG_TARGET_HAS_bswap32_i32; | |
1927 | case INDEX_op_not_i32: | |
1928 | return TCG_TARGET_HAS_not_i32; | |
1929 | case INDEX_op_neg_i32: | |
1930 | return TCG_TARGET_HAS_neg_i32; | |
1931 | case INDEX_op_andc_i32: | |
1932 | return TCG_TARGET_HAS_andc_i32; | |
1933 | case INDEX_op_orc_i32: | |
1934 | return TCG_TARGET_HAS_orc_i32; | |
1935 | case INDEX_op_eqv_i32: | |
1936 | return TCG_TARGET_HAS_eqv_i32; | |
1937 | case INDEX_op_nand_i32: | |
1938 | return TCG_TARGET_HAS_nand_i32; | |
1939 | case INDEX_op_nor_i32: | |
1940 | return TCG_TARGET_HAS_nor_i32; | |
1941 | case INDEX_op_clz_i32: | |
1942 | return TCG_TARGET_HAS_clz_i32; | |
1943 | case INDEX_op_ctz_i32: | |
1944 | return TCG_TARGET_HAS_ctz_i32; | |
1945 | case INDEX_op_ctpop_i32: | |
1946 | return TCG_TARGET_HAS_ctpop_i32; | |
1947 | ||
1948 | case INDEX_op_brcond2_i32: | |
1949 | case INDEX_op_setcond2_i32: | |
1950 | return TCG_TARGET_REG_BITS == 32; | |
1951 | ||
1952 | case INDEX_op_mov_i64: | |
be0f34b5 RH |
1953 | case INDEX_op_setcond_i64: |
1954 | case INDEX_op_brcond_i64: | |
1955 | case INDEX_op_ld8u_i64: | |
1956 | case INDEX_op_ld8s_i64: | |
1957 | case INDEX_op_ld16u_i64: | |
1958 | case INDEX_op_ld16s_i64: | |
1959 | case INDEX_op_ld32u_i64: | |
1960 | case INDEX_op_ld32s_i64: | |
1961 | case INDEX_op_ld_i64: | |
1962 | case INDEX_op_st8_i64: | |
1963 | case INDEX_op_st16_i64: | |
1964 | case INDEX_op_st32_i64: | |
1965 | case INDEX_op_st_i64: | |
1966 | case INDEX_op_add_i64: | |
1967 | case INDEX_op_sub_i64: | |
1968 | case INDEX_op_mul_i64: | |
1969 | case INDEX_op_and_i64: | |
1970 | case INDEX_op_or_i64: | |
1971 | case INDEX_op_xor_i64: | |
1972 | case INDEX_op_shl_i64: | |
1973 | case INDEX_op_shr_i64: | |
1974 | case INDEX_op_sar_i64: | |
1975 | case INDEX_op_ext_i32_i64: | |
1976 | case INDEX_op_extu_i32_i64: | |
1977 | return TCG_TARGET_REG_BITS == 64; | |
1978 | ||
1979 | case INDEX_op_movcond_i64: | |
1980 | return TCG_TARGET_HAS_movcond_i64; | |
1981 | case INDEX_op_div_i64: | |
1982 | case INDEX_op_divu_i64: | |
1983 | return TCG_TARGET_HAS_div_i64; | |
1984 | case INDEX_op_rem_i64: | |
1985 | case INDEX_op_remu_i64: | |
1986 | return TCG_TARGET_HAS_rem_i64; | |
1987 | case INDEX_op_div2_i64: | |
1988 | case INDEX_op_divu2_i64: | |
1989 | return TCG_TARGET_HAS_div2_i64; | |
1990 | case INDEX_op_rotl_i64: | |
1991 | case INDEX_op_rotr_i64: | |
1992 | return TCG_TARGET_HAS_rot_i64; | |
1993 | case INDEX_op_deposit_i64: | |
1994 | return TCG_TARGET_HAS_deposit_i64; | |
1995 | case INDEX_op_extract_i64: | |
1996 | return TCG_TARGET_HAS_extract_i64; | |
1997 | case INDEX_op_sextract_i64: | |
1998 | return TCG_TARGET_HAS_sextract_i64; | |
fce1296f RH |
1999 | case INDEX_op_extract2_i64: |
2000 | return TCG_TARGET_HAS_extract2_i64; | |
be0f34b5 RH |
2001 | case INDEX_op_extrl_i64_i32: |
2002 | return TCG_TARGET_HAS_extrl_i64_i32; | |
2003 | case INDEX_op_extrh_i64_i32: | |
2004 | return TCG_TARGET_HAS_extrh_i64_i32; | |
2005 | case INDEX_op_ext8s_i64: | |
2006 | return TCG_TARGET_HAS_ext8s_i64; | |
2007 | case INDEX_op_ext16s_i64: | |
2008 | return TCG_TARGET_HAS_ext16s_i64; | |
2009 | case INDEX_op_ext32s_i64: | |
2010 | return TCG_TARGET_HAS_ext32s_i64; | |
2011 | case INDEX_op_ext8u_i64: | |
2012 | return TCG_TARGET_HAS_ext8u_i64; | |
2013 | case INDEX_op_ext16u_i64: | |
2014 | return TCG_TARGET_HAS_ext16u_i64; | |
2015 | case INDEX_op_ext32u_i64: | |
2016 | return TCG_TARGET_HAS_ext32u_i64; | |
2017 | case INDEX_op_bswap16_i64: | |
2018 | return TCG_TARGET_HAS_bswap16_i64; | |
2019 | case INDEX_op_bswap32_i64: | |
2020 | return TCG_TARGET_HAS_bswap32_i64; | |
2021 | case INDEX_op_bswap64_i64: | |
2022 | return TCG_TARGET_HAS_bswap64_i64; | |
2023 | case INDEX_op_not_i64: | |
2024 | return TCG_TARGET_HAS_not_i64; | |
2025 | case INDEX_op_neg_i64: | |
2026 | return TCG_TARGET_HAS_neg_i64; | |
2027 | case INDEX_op_andc_i64: | |
2028 | return TCG_TARGET_HAS_andc_i64; | |
2029 | case INDEX_op_orc_i64: | |
2030 | return TCG_TARGET_HAS_orc_i64; | |
2031 | case INDEX_op_eqv_i64: | |
2032 | return TCG_TARGET_HAS_eqv_i64; | |
2033 | case INDEX_op_nand_i64: | |
2034 | return TCG_TARGET_HAS_nand_i64; | |
2035 | case INDEX_op_nor_i64: | |
2036 | return TCG_TARGET_HAS_nor_i64; | |
2037 | case INDEX_op_clz_i64: | |
2038 | return TCG_TARGET_HAS_clz_i64; | |
2039 | case INDEX_op_ctz_i64: | |
2040 | return TCG_TARGET_HAS_ctz_i64; | |
2041 | case INDEX_op_ctpop_i64: | |
2042 | return TCG_TARGET_HAS_ctpop_i64; | |
2043 | case INDEX_op_add2_i64: | |
2044 | return TCG_TARGET_HAS_add2_i64; | |
2045 | case INDEX_op_sub2_i64: | |
2046 | return TCG_TARGET_HAS_sub2_i64; | |
2047 | case INDEX_op_mulu2_i64: | |
2048 | return TCG_TARGET_HAS_mulu2_i64; | |
2049 | case INDEX_op_muls2_i64: | |
2050 | return TCG_TARGET_HAS_muls2_i64; | |
2051 | case INDEX_op_muluh_i64: | |
2052 | return TCG_TARGET_HAS_muluh_i64; | |
2053 | case INDEX_op_mulsh_i64: | |
2054 | return TCG_TARGET_HAS_mulsh_i64; | |
2055 | ||
d2fd745f RH |
2056 | case INDEX_op_mov_vec: |
2057 | case INDEX_op_dup_vec: | |
37ee55a0 | 2058 | case INDEX_op_dupm_vec: |
d2fd745f RH |
2059 | case INDEX_op_ld_vec: |
2060 | case INDEX_op_st_vec: | |
2061 | case INDEX_op_add_vec: | |
2062 | case INDEX_op_sub_vec: | |
2063 | case INDEX_op_and_vec: | |
2064 | case INDEX_op_or_vec: | |
2065 | case INDEX_op_xor_vec: | |
212be173 | 2066 | case INDEX_op_cmp_vec: |
d2fd745f RH |
2067 | return have_vec; |
2068 | case INDEX_op_dup2_vec: | |
2069 | return have_vec && TCG_TARGET_REG_BITS == 32; | |
2070 | case INDEX_op_not_vec: | |
2071 | return have_vec && TCG_TARGET_HAS_not_vec; | |
2072 | case INDEX_op_neg_vec: | |
2073 | return have_vec && TCG_TARGET_HAS_neg_vec; | |
bcefc902 RH |
2074 | case INDEX_op_abs_vec: |
2075 | return have_vec && TCG_TARGET_HAS_abs_vec; | |
d2fd745f RH |
2076 | case INDEX_op_andc_vec: |
2077 | return have_vec && TCG_TARGET_HAS_andc_vec; | |
2078 | case INDEX_op_orc_vec: | |
2079 | return have_vec && TCG_TARGET_HAS_orc_vec; | |
ed523473 RH |
2080 | case INDEX_op_nand_vec: |
2081 | return have_vec && TCG_TARGET_HAS_nand_vec; | |
2082 | case INDEX_op_nor_vec: | |
2083 | return have_vec && TCG_TARGET_HAS_nor_vec; | |
2084 | case INDEX_op_eqv_vec: | |
2085 | return have_vec && TCG_TARGET_HAS_eqv_vec; | |
3774030a RH |
2086 | case INDEX_op_mul_vec: |
2087 | return have_vec && TCG_TARGET_HAS_mul_vec; | |
d0ec9796 RH |
2088 | case INDEX_op_shli_vec: |
2089 | case INDEX_op_shri_vec: | |
2090 | case INDEX_op_sari_vec: | |
2091 | return have_vec && TCG_TARGET_HAS_shi_vec; | |
2092 | case INDEX_op_shls_vec: | |
2093 | case INDEX_op_shrs_vec: | |
2094 | case INDEX_op_sars_vec: | |
2095 | return have_vec && TCG_TARGET_HAS_shs_vec; | |
2096 | case INDEX_op_shlv_vec: | |
2097 | case INDEX_op_shrv_vec: | |
2098 | case INDEX_op_sarv_vec: | |
2099 | return have_vec && TCG_TARGET_HAS_shv_vec; | |
b0f7e744 RH |
2100 | case INDEX_op_rotli_vec: |
2101 | return have_vec && TCG_TARGET_HAS_roti_vec; | |
23850a74 RH |
2102 | case INDEX_op_rotls_vec: |
2103 | return have_vec && TCG_TARGET_HAS_rots_vec; | |
5d0ceda9 RH |
2104 | case INDEX_op_rotlv_vec: |
2105 | case INDEX_op_rotrv_vec: | |
2106 | return have_vec && TCG_TARGET_HAS_rotv_vec; | |
8afaf050 RH |
2107 | case INDEX_op_ssadd_vec: |
2108 | case INDEX_op_usadd_vec: | |
2109 | case INDEX_op_sssub_vec: | |
2110 | case INDEX_op_ussub_vec: | |
2111 | return have_vec && TCG_TARGET_HAS_sat_vec; | |
dd0a0fcd RH |
2112 | case INDEX_op_smin_vec: |
2113 | case INDEX_op_umin_vec: | |
2114 | case INDEX_op_smax_vec: | |
2115 | case INDEX_op_umax_vec: | |
2116 | return have_vec && TCG_TARGET_HAS_minmax_vec; | |
38dc1294 RH |
2117 | case INDEX_op_bitsel_vec: |
2118 | return have_vec && TCG_TARGET_HAS_bitsel_vec; | |
f75da298 RH |
2119 | case INDEX_op_cmpsel_vec: |
2120 | return have_vec && TCG_TARGET_HAS_cmpsel_vec; | |
d2fd745f | 2121 | |
db432672 RH |
2122 | default: |
2123 | tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS); | |
2124 | return true; | |
be0f34b5 | 2125 | } |
be0f34b5 RH |
2126 | } |
2127 | ||
39004a71 RH |
2128 | static TCGOp *tcg_op_alloc(TCGOpcode opc, unsigned nargs); |
2129 | ||
d53106c9 | 2130 | void tcg_gen_callN(TCGHelperInfo *info, TCGTemp *ret, int nargs, TCGTemp **args) |
c896fe29 | 2131 | { |
39004a71 RH |
2132 | TCGv_i64 extend_free[MAX_CALL_IARGS]; |
2133 | int n_extend = 0; | |
75e8b9b7 | 2134 | TCGOp *op; |
39004a71 | 2135 | int i, n, pi = 0, total_args; |
afb49896 | 2136 | |
d53106c9 RH |
2137 | if (unlikely(g_once_init_enter(HELPER_INFO_INIT(info)))) { |
2138 | init_call_layout(info); | |
2139 | g_once_init_leave(HELPER_INFO_INIT(info), HELPER_INFO_INIT_VAL(info)); | |
2140 | } | |
2141 | ||
39004a71 RH |
2142 | total_args = info->nr_out + info->nr_in + 2; |
2143 | op = tcg_op_alloc(INDEX_op_call, total_args); | |
2bece2c8 | 2144 | |
38b47b19 | 2145 | #ifdef CONFIG_PLUGIN |
17083f6f EC |
2146 | /* Flag helpers that may affect guest state */ |
2147 | if (tcg_ctx->plugin_insn && | |
2148 | !(info->flags & TCG_CALL_PLUGIN) && | |
2149 | !(info->flags & TCG_CALL_NO_SIDE_EFFECTS)) { | |
38b47b19 EC |
2150 | tcg_ctx->plugin_insn->calls_helpers = true; |
2151 | } | |
2152 | #endif | |
2153 | ||
39004a71 RH |
2154 | TCGOP_CALLO(op) = n = info->nr_out; |
2155 | switch (n) { | |
2156 | case 0: | |
2157 | tcg_debug_assert(ret == NULL); | |
2158 | break; | |
2159 | case 1: | |
2160 | tcg_debug_assert(ret != NULL); | |
2161 | op->args[pi++] = temp_arg(ret); | |
2162 | break; | |
2163 | case 2: | |
466d3759 | 2164 | case 4: |
39004a71 | 2165 | tcg_debug_assert(ret != NULL); |
466d3759 | 2166 | tcg_debug_assert(ret->base_type == ret->type + ctz32(n)); |
39004a71 | 2167 | tcg_debug_assert(ret->temp_subindex == 0); |
466d3759 RH |
2168 | for (i = 0; i < n; ++i) { |
2169 | op->args[pi++] = temp_arg(ret + i); | |
2170 | } | |
39004a71 RH |
2171 | break; |
2172 | default: | |
2173 | g_assert_not_reached(); | |
2174 | } | |
2175 | ||
2176 | TCGOP_CALLI(op) = n = info->nr_in; | |
2177 | for (i = 0; i < n; i++) { | |
2178 | const TCGCallArgumentLoc *loc = &info->in[i]; | |
2179 | TCGTemp *ts = args[loc->arg_idx] + loc->tmp_subindex; | |
2180 | ||
2181 | switch (loc->kind) { | |
2182 | case TCG_CALL_ARG_NORMAL: | |
313bdea8 RH |
2183 | case TCG_CALL_ARG_BY_REF: |
2184 | case TCG_CALL_ARG_BY_REF_N: | |
39004a71 RH |
2185 | op->args[pi++] = temp_arg(ts); |
2186 | break; | |
eb8b0224 | 2187 | |
39004a71 RH |
2188 | case TCG_CALL_ARG_EXTEND_U: |
2189 | case TCG_CALL_ARG_EXTEND_S: | |
2190 | { | |
5dd48602 | 2191 | TCGv_i64 temp = tcg_temp_ebb_new_i64(); |
39004a71 RH |
2192 | TCGv_i32 orig = temp_tcgv_i32(ts); |
2193 | ||
2194 | if (loc->kind == TCG_CALL_ARG_EXTEND_S) { | |
eb8b0224 RH |
2195 | tcg_gen_ext_i32_i64(temp, orig); |
2196 | } else { | |
2197 | tcg_gen_extu_i32_i64(temp, orig); | |
2198 | } | |
39004a71 RH |
2199 | op->args[pi++] = tcgv_i64_arg(temp); |
2200 | extend_free[n_extend++] = temp; | |
2bece2c8 | 2201 | } |
e2a9dd6b | 2202 | break; |
7b7d8b2d | 2203 | |
e2a9dd6b RH |
2204 | default: |
2205 | g_assert_not_reached(); | |
c896fe29 FB |
2206 | } |
2207 | } | |
d53106c9 | 2208 | op->args[pi++] = (uintptr_t)info->func; |
3e92aa34 | 2209 | op->args[pi++] = (uintptr_t)info; |
39004a71 | 2210 | tcg_debug_assert(pi == total_args); |
a7812ae4 | 2211 | |
39004a71 | 2212 | QTAILQ_INSERT_TAIL(&tcg_ctx->ops, op, link); |
7319d83a | 2213 | |
39004a71 RH |
2214 | tcg_debug_assert(n_extend < ARRAY_SIZE(extend_free)); |
2215 | for (i = 0; i < n_extend; ++i) { | |
2216 | tcg_temp_free_i64(extend_free[i]); | |
2bece2c8 | 2217 | } |
c896fe29 | 2218 | } |
c896fe29 | 2219 | |
8fcd3692 | 2220 | static void tcg_reg_alloc_start(TCGContext *s) |
c896fe29 | 2221 | { |
ac3b8891 | 2222 | int i, n; |
ac3b8891 | 2223 | |
ee17db83 RH |
2224 | for (i = 0, n = s->nb_temps; i < n; i++) { |
2225 | TCGTemp *ts = &s->temps[i]; | |
2226 | TCGTempVal val = TEMP_VAL_MEM; | |
2227 | ||
2228 | switch (ts->kind) { | |
c0522136 RH |
2229 | case TEMP_CONST: |
2230 | val = TEMP_VAL_CONST; | |
2231 | break; | |
ee17db83 RH |
2232 | case TEMP_FIXED: |
2233 | val = TEMP_VAL_REG; | |
2234 | break; | |
2235 | case TEMP_GLOBAL: | |
2236 | break; | |
c7482438 | 2237 | case TEMP_EBB: |
ee17db83 RH |
2238 | val = TEMP_VAL_DEAD; |
2239 | /* fall through */ | |
f57c6915 | 2240 | case TEMP_TB: |
ee17db83 RH |
2241 | ts->mem_allocated = 0; |
2242 | break; | |
2243 | default: | |
2244 | g_assert_not_reached(); | |
2245 | } | |
2246 | ts->val_type = val; | |
e8996ee0 | 2247 | } |
f8b2f202 RH |
2248 | |
2249 | memset(s->reg_to_temp, 0, sizeof(s->reg_to_temp)); | |
c896fe29 FB |
2250 | } |
2251 | ||
f8b2f202 RH |
2252 | static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, |
2253 | TCGTemp *ts) | |
c896fe29 | 2254 | { |
1807f4c4 | 2255 | int idx = temp_idx(ts); |
ac56dd48 | 2256 | |
ee17db83 RH |
2257 | switch (ts->kind) { |
2258 | case TEMP_FIXED: | |
2259 | case TEMP_GLOBAL: | |
ac56dd48 | 2260 | pstrcpy(buf, buf_size, ts->name); |
ee17db83 | 2261 | break; |
f57c6915 | 2262 | case TEMP_TB: |
f8b2f202 | 2263 | snprintf(buf, buf_size, "loc%d", idx - s->nb_globals); |
ee17db83 | 2264 | break; |
c7482438 | 2265 | case TEMP_EBB: |
f8b2f202 | 2266 | snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals); |
ee17db83 | 2267 | break; |
c0522136 RH |
2268 | case TEMP_CONST: |
2269 | switch (ts->type) { | |
2270 | case TCG_TYPE_I32: | |
2271 | snprintf(buf, buf_size, "$0x%x", (int32_t)ts->val); | |
2272 | break; | |
2273 | #if TCG_TARGET_REG_BITS > 32 | |
2274 | case TCG_TYPE_I64: | |
2275 | snprintf(buf, buf_size, "$0x%" PRIx64, ts->val); | |
2276 | break; | |
2277 | #endif | |
2278 | case TCG_TYPE_V64: | |
2279 | case TCG_TYPE_V128: | |
2280 | case TCG_TYPE_V256: | |
2281 | snprintf(buf, buf_size, "v%d$0x%" PRIx64, | |
2282 | 64 << (ts->type - TCG_TYPE_V64), ts->val); | |
2283 | break; | |
2284 | default: | |
2285 | g_assert_not_reached(); | |
2286 | } | |
2287 | break; | |
c896fe29 FB |
2288 | } |
2289 | return buf; | |
2290 | } | |
2291 | ||
43439139 RH |
2292 | static char *tcg_get_arg_str(TCGContext *s, char *buf, |
2293 | int buf_size, TCGArg arg) | |
f8b2f202 | 2294 | { |
43439139 | 2295 | return tcg_get_arg_str_ptr(s, buf, buf_size, arg_temp(arg)); |
f8b2f202 RH |
2296 | } |
2297 | ||
f48f3ede BS |
2298 | static const char * const cond_name[] = |
2299 | { | |
0aed257f RH |
2300 | [TCG_COND_NEVER] = "never", |
2301 | [TCG_COND_ALWAYS] = "always", | |
f48f3ede BS |
2302 | [TCG_COND_EQ] = "eq", |
2303 | [TCG_COND_NE] = "ne", | |
2304 | [TCG_COND_LT] = "lt", | |
2305 | [TCG_COND_GE] = "ge", | |
2306 | [TCG_COND_LE] = "le", | |
2307 | [TCG_COND_GT] = "gt", | |
2308 | [TCG_COND_LTU] = "ltu", | |
2309 | [TCG_COND_GEU] = "geu", | |
2310 | [TCG_COND_LEU] = "leu", | |
2311 | [TCG_COND_GTU] = "gtu" | |
2312 | }; | |
2313 | ||
12fde9bc | 2314 | static const char * const ldst_name[(MO_BSWAP | MO_SSIZE) + 1] = |
f713d6ad RH |
2315 | { |
2316 | [MO_UB] = "ub", | |
2317 | [MO_SB] = "sb", | |
2318 | [MO_LEUW] = "leuw", | |
2319 | [MO_LESW] = "lesw", | |
2320 | [MO_LEUL] = "leul", | |
2321 | [MO_LESL] = "lesl", | |
fc313c64 | 2322 | [MO_LEUQ] = "leq", |
f713d6ad RH |
2323 | [MO_BEUW] = "beuw", |
2324 | [MO_BESW] = "besw", | |
2325 | [MO_BEUL] = "beul", | |
2326 | [MO_BESL] = "besl", | |
fc313c64 | 2327 | [MO_BEUQ] = "beq", |
12fde9bc RH |
2328 | [MO_128 + MO_BE] = "beo", |
2329 | [MO_128 + MO_LE] = "leo", | |
f713d6ad RH |
2330 | }; |
2331 | ||
1f00b27f | 2332 | static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = { |
1f00b27f | 2333 | [MO_UNALN >> MO_ASHIFT] = "un+", |
1f00b27f | 2334 | [MO_ALIGN >> MO_ASHIFT] = "al+", |
1f00b27f SS |
2335 | [MO_ALIGN_2 >> MO_ASHIFT] = "al2+", |
2336 | [MO_ALIGN_4 >> MO_ASHIFT] = "al4+", | |
2337 | [MO_ALIGN_8 >> MO_ASHIFT] = "al8+", | |
2338 | [MO_ALIGN_16 >> MO_ASHIFT] = "al16+", | |
2339 | [MO_ALIGN_32 >> MO_ASHIFT] = "al32+", | |
2340 | [MO_ALIGN_64 >> MO_ASHIFT] = "al64+", | |
2341 | }; | |
2342 | ||
37031fef RH |
2343 | static const char * const atom_name[(MO_ATOM_MASK >> MO_ATOM_SHIFT) + 1] = { |
2344 | [MO_ATOM_IFALIGN >> MO_ATOM_SHIFT] = "", | |
2345 | [MO_ATOM_IFALIGN_PAIR >> MO_ATOM_SHIFT] = "pair+", | |
2346 | [MO_ATOM_WITHIN16 >> MO_ATOM_SHIFT] = "w16+", | |
2347 | [MO_ATOM_WITHIN16_PAIR >> MO_ATOM_SHIFT] = "w16p+", | |
2348 | [MO_ATOM_SUBALIGN >> MO_ATOM_SHIFT] = "sub+", | |
2349 | [MO_ATOM_NONE >> MO_ATOM_SHIFT] = "noat+", | |
2350 | }; | |
2351 | ||
587195bd RH |
2352 | static const char bswap_flag_name[][6] = { |
2353 | [TCG_BSWAP_IZ] = "iz", | |
2354 | [TCG_BSWAP_OZ] = "oz", | |
2355 | [TCG_BSWAP_OS] = "os", | |
2356 | [TCG_BSWAP_IZ | TCG_BSWAP_OZ] = "iz,oz", | |
2357 | [TCG_BSWAP_IZ | TCG_BSWAP_OS] = "iz,os", | |
2358 | }; | |
2359 | ||
b016486e RH |
2360 | static inline bool tcg_regset_single(TCGRegSet d) |
2361 | { | |
2362 | return (d & (d - 1)) == 0; | |
2363 | } | |
2364 | ||
2365 | static inline TCGReg tcg_regset_first(TCGRegSet d) | |
2366 | { | |
2367 | if (TCG_TARGET_NB_REGS <= 32) { | |
2368 | return ctz32(d); | |
2369 | } else { | |
2370 | return ctz64(d); | |
2371 | } | |
2372 | } | |
2373 | ||
b7a83ff8 RH |
2374 | /* Return only the number of characters output -- no error return. */ |
2375 | #define ne_fprintf(...) \ | |
2376 | ({ int ret_ = fprintf(__VA_ARGS__); ret_ >= 0 ? ret_ : 0; }) | |
2377 | ||
2378 | static void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs) | |
c896fe29 | 2379 | { |
c896fe29 | 2380 | char buf[128]; |
c45cb8bb | 2381 | TCGOp *op; |
c45cb8bb | 2382 | |
15fa08f8 | 2383 | QTAILQ_FOREACH(op, &s->ops, link) { |
c45cb8bb RH |
2384 | int i, k, nb_oargs, nb_iargs, nb_cargs; |
2385 | const TCGOpDef *def; | |
c45cb8bb | 2386 | TCGOpcode c; |
bdfb460e | 2387 | int col = 0; |
c896fe29 | 2388 | |
c45cb8bb | 2389 | c = op->opc; |
c896fe29 | 2390 | def = &tcg_op_defs[c]; |
c45cb8bb | 2391 | |
765b842a | 2392 | if (c == INDEX_op_insn_start) { |
b016486e | 2393 | nb_oargs = 0; |
b7a83ff8 | 2394 | col += ne_fprintf(f, "\n ----"); |
9aef40ed RH |
2395 | |
2396 | for (i = 0; i < TARGET_INSN_START_WORDS; ++i) { | |
c9ad8d27 RH |
2397 | col += ne_fprintf(f, " %016" PRIx64, |
2398 | tcg_get_insn_start_param(op, i)); | |
eeacee4d | 2399 | } |
7e4597d7 | 2400 | } else if (c == INDEX_op_call) { |
3e92aa34 | 2401 | const TCGHelperInfo *info = tcg_call_info(op); |
fa52e660 | 2402 | void *func = tcg_call_func(op); |
3e92aa34 | 2403 | |
c896fe29 | 2404 | /* variable number of arguments */ |
cd9090aa RH |
2405 | nb_oargs = TCGOP_CALLO(op); |
2406 | nb_iargs = TCGOP_CALLI(op); | |
c896fe29 | 2407 | nb_cargs = def->nb_cargs; |
c896fe29 | 2408 | |
b7a83ff8 | 2409 | col += ne_fprintf(f, " %s ", def->name); |
3e92aa34 RH |
2410 | |
2411 | /* | |
2412 | * Print the function name from TCGHelperInfo, if available. | |
2413 | * Note that plugins have a template function for the info, | |
2414 | * but the actual function pointer comes from the plugin. | |
2415 | */ | |
3e92aa34 | 2416 | if (func == info->func) { |
b7a83ff8 | 2417 | col += ne_fprintf(f, "%s", info->name); |
3e92aa34 | 2418 | } else { |
b7a83ff8 | 2419 | col += ne_fprintf(f, "plugin(%p)", func); |
3e92aa34 RH |
2420 | } |
2421 | ||
b7a83ff8 | 2422 | col += ne_fprintf(f, ",$0x%x,$%d", info->flags, nb_oargs); |
cf066674 | 2423 | for (i = 0; i < nb_oargs; i++) { |
b7a83ff8 RH |
2424 | col += ne_fprintf(f, ",%s", tcg_get_arg_str(s, buf, sizeof(buf), |
2425 | op->args[i])); | |
b03cce8e | 2426 | } |
cf066674 | 2427 | for (i = 0; i < nb_iargs; i++) { |
efee3746 | 2428 | TCGArg arg = op->args[nb_oargs + i]; |
39004a71 | 2429 | const char *t = tcg_get_arg_str(s, buf, sizeof(buf), arg); |
b7a83ff8 | 2430 | col += ne_fprintf(f, ",%s", t); |
e8996ee0 | 2431 | } |
b03cce8e | 2432 | } else { |
b7a83ff8 | 2433 | col += ne_fprintf(f, " %s ", def->name); |
c45cb8bb RH |
2434 | |
2435 | nb_oargs = def->nb_oargs; | |
2436 | nb_iargs = def->nb_iargs; | |
2437 | nb_cargs = def->nb_cargs; | |
2438 | ||
d2fd745f | 2439 | if (def->flags & TCG_OPF_VECTOR) { |
b7a83ff8 RH |
2440 | col += ne_fprintf(f, "v%d,e%d,", 64 << TCGOP_VECL(op), |
2441 | 8 << TCGOP_VECE(op)); | |
d2fd745f RH |
2442 | } |
2443 | ||
b03cce8e | 2444 | k = 0; |
c45cb8bb | 2445 | for (i = 0; i < nb_oargs; i++) { |
b7a83ff8 RH |
2446 | const char *sep = k ? "," : ""; |
2447 | col += ne_fprintf(f, "%s%s", sep, | |
2448 | tcg_get_arg_str(s, buf, sizeof(buf), | |
2449 | op->args[k++])); | |
b03cce8e | 2450 | } |
c45cb8bb | 2451 | for (i = 0; i < nb_iargs; i++) { |
b7a83ff8 RH |
2452 | const char *sep = k ? "," : ""; |
2453 | col += ne_fprintf(f, "%s%s", sep, | |
2454 | tcg_get_arg_str(s, buf, sizeof(buf), | |
2455 | op->args[k++])); | |
b03cce8e | 2456 | } |
be210acb RH |
2457 | switch (c) { |
2458 | case INDEX_op_brcond_i32: | |
be210acb | 2459 | case INDEX_op_setcond_i32: |
ffc5ea09 | 2460 | case INDEX_op_movcond_i32: |
ffc5ea09 | 2461 | case INDEX_op_brcond2_i32: |
be210acb | 2462 | case INDEX_op_setcond2_i32: |
ffc5ea09 | 2463 | case INDEX_op_brcond_i64: |
be210acb | 2464 | case INDEX_op_setcond_i64: |
ffc5ea09 | 2465 | case INDEX_op_movcond_i64: |
212be173 | 2466 | case INDEX_op_cmp_vec: |
f75da298 | 2467 | case INDEX_op_cmpsel_vec: |
efee3746 RH |
2468 | if (op->args[k] < ARRAY_SIZE(cond_name) |
2469 | && cond_name[op->args[k]]) { | |
b7a83ff8 | 2470 | col += ne_fprintf(f, ",%s", cond_name[op->args[k++]]); |
eeacee4d | 2471 | } else { |
b7a83ff8 | 2472 | col += ne_fprintf(f, ",$0x%" TCG_PRIlx, op->args[k++]); |
eeacee4d | 2473 | } |
f48f3ede | 2474 | i = 1; |
be210acb | 2475 | break; |
fecccfcc RH |
2476 | case INDEX_op_qemu_ld_a32_i32: |
2477 | case INDEX_op_qemu_ld_a64_i32: | |
2478 | case INDEX_op_qemu_st_a32_i32: | |
2479 | case INDEX_op_qemu_st_a64_i32: | |
2480 | case INDEX_op_qemu_st8_a32_i32: | |
2481 | case INDEX_op_qemu_st8_a64_i32: | |
2482 | case INDEX_op_qemu_ld_a32_i64: | |
2483 | case INDEX_op_qemu_ld_a64_i64: | |
2484 | case INDEX_op_qemu_st_a32_i64: | |
2485 | case INDEX_op_qemu_st_a64_i64: | |
2486 | case INDEX_op_qemu_ld_a32_i128: | |
2487 | case INDEX_op_qemu_ld_a64_i128: | |
2488 | case INDEX_op_qemu_st_a32_i128: | |
2489 | case INDEX_op_qemu_st_a64_i128: | |
59227d5d | 2490 | { |
37031fef | 2491 | const char *s_al, *s_op, *s_at; |
9002ffcb | 2492 | MemOpIdx oi = op->args[k++]; |
14776ab5 | 2493 | MemOp op = get_memop(oi); |
59227d5d RH |
2494 | unsigned ix = get_mmuidx(oi); |
2495 | ||
37031fef RH |
2496 | s_al = alignment_name[(op & MO_AMASK) >> MO_ASHIFT]; |
2497 | s_op = ldst_name[op & (MO_BSWAP | MO_SSIZE)]; | |
2498 | s_at = atom_name[(op & MO_ATOM_MASK) >> MO_ATOM_SHIFT]; | |
2499 | op &= ~(MO_AMASK | MO_BSWAP | MO_SSIZE | MO_ATOM_MASK); | |
2500 | ||
2501 | /* If all fields are accounted for, print symbolically. */ | |
2502 | if (!op && s_al && s_op && s_at) { | |
2503 | col += ne_fprintf(f, ",%s%s%s,%u", | |
2504 | s_at, s_al, s_op, ix); | |
59c4b7e8 | 2505 | } else { |
37031fef RH |
2506 | op = get_memop(oi); |
2507 | col += ne_fprintf(f, ",$0x%x,%u", op, ix); | |
59227d5d RH |
2508 | } |
2509 | i = 1; | |
f713d6ad | 2510 | } |
f713d6ad | 2511 | break; |
587195bd RH |
2512 | case INDEX_op_bswap16_i32: |
2513 | case INDEX_op_bswap16_i64: | |
2514 | case INDEX_op_bswap32_i32: | |
2515 | case INDEX_op_bswap32_i64: | |
2516 | case INDEX_op_bswap64_i64: | |
2517 | { | |
2518 | TCGArg flags = op->args[k]; | |
2519 | const char *name = NULL; | |
2520 | ||
2521 | if (flags < ARRAY_SIZE(bswap_flag_name)) { | |
2522 | name = bswap_flag_name[flags]; | |
2523 | } | |
2524 | if (name) { | |
b7a83ff8 | 2525 | col += ne_fprintf(f, ",%s", name); |
587195bd | 2526 | } else { |
b7a83ff8 | 2527 | col += ne_fprintf(f, ",$0x%" TCG_PRIlx, flags); |
587195bd RH |
2528 | } |
2529 | i = k = 1; | |
2530 | } | |
2531 | break; | |
be210acb | 2532 | default: |
f48f3ede | 2533 | i = 0; |
be210acb RH |
2534 | break; |
2535 | } | |
51e3972c RH |
2536 | switch (c) { |
2537 | case INDEX_op_set_label: | |
2538 | case INDEX_op_br: | |
2539 | case INDEX_op_brcond_i32: | |
2540 | case INDEX_op_brcond_i64: | |
2541 | case INDEX_op_brcond2_i32: | |
b7a83ff8 RH |
2542 | col += ne_fprintf(f, "%s$L%d", k ? "," : "", |
2543 | arg_label(op->args[k])->id); | |
51e3972c RH |
2544 | i++, k++; |
2545 | break; | |
3470867b RH |
2546 | case INDEX_op_mb: |
2547 | { | |
2548 | TCGBar membar = op->args[k]; | |
2549 | const char *b_op, *m_op; | |
2550 | ||
2551 | switch (membar & TCG_BAR_SC) { | |
2552 | case 0: | |
2553 | b_op = "none"; | |
2554 | break; | |
2555 | case TCG_BAR_LDAQ: | |
2556 | b_op = "acq"; | |
2557 | break; | |
2558 | case TCG_BAR_STRL: | |
2559 | b_op = "rel"; | |
2560 | break; | |
2561 | case TCG_BAR_SC: | |
2562 | b_op = "seq"; | |
2563 | break; | |
2564 | default: | |
2565 | g_assert_not_reached(); | |
2566 | } | |
2567 | ||
2568 | switch (membar & TCG_MO_ALL) { | |
2569 | case 0: | |
2570 | m_op = "none"; | |
2571 | break; | |
2572 | case TCG_MO_LD_LD: | |
2573 | m_op = "rr"; | |
2574 | break; | |
2575 | case TCG_MO_LD_ST: | |
2576 | m_op = "rw"; | |
2577 | break; | |
2578 | case TCG_MO_ST_LD: | |
2579 | m_op = "wr"; | |
2580 | break; | |
2581 | case TCG_MO_ST_ST: | |
2582 | m_op = "ww"; | |
2583 | break; | |
2584 | case TCG_MO_LD_LD | TCG_MO_LD_ST: | |
2585 | m_op = "rr+rw"; | |
2586 | break; | |
2587 | case TCG_MO_LD_LD | TCG_MO_ST_LD: | |
2588 | m_op = "rr+wr"; | |
2589 | break; | |
2590 | case TCG_MO_LD_LD | TCG_MO_ST_ST: | |
2591 | m_op = "rr+ww"; | |
2592 | break; | |
2593 | case TCG_MO_LD_ST | TCG_MO_ST_LD: | |
2594 | m_op = "rw+wr"; | |
2595 | break; | |
2596 | case TCG_MO_LD_ST | TCG_MO_ST_ST: | |
2597 | m_op = "rw+ww"; | |
2598 | break; | |
2599 | case TCG_MO_ST_LD | TCG_MO_ST_ST: | |
2600 | m_op = "wr+ww"; | |
2601 | break; | |
2602 | case TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_LD: | |
2603 | m_op = "rr+rw+wr"; | |
2604 | break; | |
2605 | case TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST: | |
2606 | m_op = "rr+rw+ww"; | |
2607 | break; | |
2608 | case TCG_MO_LD_LD | TCG_MO_ST_LD | TCG_MO_ST_ST: | |
2609 | m_op = "rr+wr+ww"; | |
2610 | break; | |
2611 | case TCG_MO_LD_ST | TCG_MO_ST_LD | TCG_MO_ST_ST: | |
2612 | m_op = "rw+wr+ww"; | |
2613 | break; | |
2614 | case TCG_MO_ALL: | |
2615 | m_op = "all"; | |
2616 | break; | |
2617 | default: | |
2618 | g_assert_not_reached(); | |
2619 | } | |
2620 | ||
2621 | col += ne_fprintf(f, "%s%s:%s", (k ? "," : ""), b_op, m_op); | |
2622 | i++, k++; | |
2623 | } | |
2624 | break; | |
51e3972c RH |
2625 | default: |
2626 | break; | |
2627 | } | |
2628 | for (; i < nb_cargs; i++, k++) { | |
b7a83ff8 RH |
2629 | col += ne_fprintf(f, "%s$0x%" TCG_PRIlx, k ? "," : "", |
2630 | op->args[k]); | |
bdfb460e RH |
2631 | } |
2632 | } | |
bdfb460e | 2633 | |
1894f69a | 2634 | if (have_prefs || op->life) { |
b7a83ff8 RH |
2635 | for (; col < 40; ++col) { |
2636 | putc(' ', f); | |
bdfb460e | 2637 | } |
1894f69a RH |
2638 | } |
2639 | ||
2640 | if (op->life) { | |
2641 | unsigned life = op->life; | |
bdfb460e RH |
2642 | |
2643 | if (life & (SYNC_ARG * 3)) { | |
b7a83ff8 | 2644 | ne_fprintf(f, " sync:"); |
bdfb460e RH |
2645 | for (i = 0; i < 2; ++i) { |
2646 | if (life & (SYNC_ARG << i)) { | |
b7a83ff8 | 2647 | ne_fprintf(f, " %d", i); |
bdfb460e RH |
2648 | } |
2649 | } | |
2650 | } | |
2651 | life /= DEAD_ARG; | |
2652 | if (life) { | |
b7a83ff8 | 2653 | ne_fprintf(f, " dead:"); |
bdfb460e RH |
2654 | for (i = 0; life; ++i, life >>= 1) { |
2655 | if (life & 1) { | |
b7a83ff8 | 2656 | ne_fprintf(f, " %d", i); |
bdfb460e RH |
2657 | } |
2658 | } | |
b03cce8e | 2659 | } |
c896fe29 | 2660 | } |
1894f69a RH |
2661 | |
2662 | if (have_prefs) { | |
2663 | for (i = 0; i < nb_oargs; ++i) { | |
31fd884b | 2664 | TCGRegSet set = output_pref(op, i); |
1894f69a RH |
2665 | |
2666 | if (i == 0) { | |
b7a83ff8 | 2667 | ne_fprintf(f, " pref="); |
1894f69a | 2668 | } else { |
b7a83ff8 | 2669 | ne_fprintf(f, ","); |
1894f69a RH |
2670 | } |
2671 | if (set == 0) { | |
b7a83ff8 | 2672 | ne_fprintf(f, "none"); |
1894f69a | 2673 | } else if (set == MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS)) { |
b7a83ff8 | 2674 | ne_fprintf(f, "all"); |
1894f69a RH |
2675 | #ifdef CONFIG_DEBUG_TCG |
2676 | } else if (tcg_regset_single(set)) { | |
2677 | TCGReg reg = tcg_regset_first(set); | |
b7a83ff8 | 2678 | ne_fprintf(f, "%s", tcg_target_reg_names[reg]); |
1894f69a RH |
2679 | #endif |
2680 | } else if (TCG_TARGET_NB_REGS <= 32) { | |
b7a83ff8 | 2681 | ne_fprintf(f, "0x%x", (uint32_t)set); |
1894f69a | 2682 | } else { |
b7a83ff8 | 2683 | ne_fprintf(f, "0x%" PRIx64, (uint64_t)set); |
1894f69a RH |
2684 | } |
2685 | } | |
2686 | } | |
2687 | ||
b7a83ff8 | 2688 | putc('\n', f); |
c896fe29 FB |
2689 | } |
2690 | } | |
2691 | ||
2692 | /* we give more priority to constraints with less registers */ | |
2693 | static int get_constraint_priority(const TCGOpDef *def, int k) | |
2694 | { | |
74a11790 | 2695 | const TCGArgConstraint *arg_ct = &def->args_ct[k]; |
29f5e925 | 2696 | int n = ctpop64(arg_ct->regs); |
c896fe29 | 2697 | |
29f5e925 RH |
2698 | /* |
2699 | * Sort constraints of a single register first, which includes output | |
2700 | * aliases (which must exactly match the input already allocated). | |
2701 | */ | |
2702 | if (n == 1 || arg_ct->oalias) { | |
2703 | return INT_MAX; | |
2704 | } | |
2705 | ||
2706 | /* | |
2707 | * Sort register pairs next, first then second immediately after. | |
2708 | * Arbitrarily sort multiple pairs by the index of the first reg; | |
2709 | * there shouldn't be many pairs. | |
2710 | */ | |
2711 | switch (arg_ct->pair) { | |
2712 | case 1: | |
2713 | case 3: | |
2714 | return (k + 1) * 2; | |
2715 | case 2: | |
2716 | return (arg_ct->pair_index + 1) * 2 - 1; | |
c896fe29 | 2717 | } |
29f5e925 RH |
2718 | |
2719 | /* Finally, sort by decreasing register count. */ | |
2720 | assert(n > 1); | |
2721 | return -n; | |
c896fe29 FB |
2722 | } |
2723 | ||
2724 | /* sort from highest priority to lowest */ | |
2725 | static void sort_constraints(TCGOpDef *def, int start, int n) | |
2726 | { | |
66792f90 RH |
2727 | int i, j; |
2728 | TCGArgConstraint *a = def->args_ct; | |
c896fe29 | 2729 | |
66792f90 RH |
2730 | for (i = 0; i < n; i++) { |
2731 | a[start + i].sort_index = start + i; | |
2732 | } | |
2733 | if (n <= 1) { | |
c896fe29 | 2734 | return; |
66792f90 RH |
2735 | } |
2736 | for (i = 0; i < n - 1; i++) { | |
2737 | for (j = i + 1; j < n; j++) { | |
2738 | int p1 = get_constraint_priority(def, a[start + i].sort_index); | |
2739 | int p2 = get_constraint_priority(def, a[start + j].sort_index); | |
c896fe29 | 2740 | if (p1 < p2) { |
66792f90 RH |
2741 | int tmp = a[start + i].sort_index; |
2742 | a[start + i].sort_index = a[start + j].sort_index; | |
2743 | a[start + j].sort_index = tmp; | |
c896fe29 FB |
2744 | } |
2745 | } | |
2746 | } | |
2747 | } | |
2748 | ||
f69d277e | 2749 | static void process_op_defs(TCGContext *s) |
c896fe29 | 2750 | { |
a9751609 | 2751 | TCGOpcode op; |
c896fe29 | 2752 | |
f69d277e RH |
2753 | for (op = 0; op < NB_OPS; op++) { |
2754 | TCGOpDef *def = &tcg_op_defs[op]; | |
2755 | const TCGTargetOpDef *tdefs; | |
29f5e925 RH |
2756 | bool saw_alias_pair = false; |
2757 | int i, o, i2, o2, nb_args; | |
f69d277e RH |
2758 | |
2759 | if (def->flags & TCG_OPF_NOT_PRESENT) { | |
2760 | continue; | |
2761 | } | |
2762 | ||
c896fe29 | 2763 | nb_args = def->nb_iargs + def->nb_oargs; |
f69d277e RH |
2764 | if (nb_args == 0) { |
2765 | continue; | |
2766 | } | |
2767 | ||
4c22e840 RH |
2768 | /* |
2769 | * Macro magic should make it impossible, but double-check that | |
2770 | * the array index is in range. Since the signness of an enum | |
2771 | * is implementation defined, force the result to unsigned. | |
2772 | */ | |
2773 | unsigned con_set = tcg_target_op_def(op); | |
2774 | tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets)); | |
2775 | tdefs = &constraint_sets[con_set]; | |
f69d277e RH |
2776 | |
2777 | for (i = 0; i < nb_args; i++) { | |
2778 | const char *ct_str = tdefs->args_ct_str[i]; | |
8940ea0d PMD |
2779 | bool input_p = i >= def->nb_oargs; |
2780 | ||
f69d277e | 2781 | /* Incomplete TCGTargetOpDef entry. */ |
eabb7b91 | 2782 | tcg_debug_assert(ct_str != NULL); |
f69d277e | 2783 | |
8940ea0d PMD |
2784 | switch (*ct_str) { |
2785 | case '0' ... '9': | |
2786 | o = *ct_str - '0'; | |
2787 | tcg_debug_assert(input_p); | |
2788 | tcg_debug_assert(o < def->nb_oargs); | |
2789 | tcg_debug_assert(def->args_ct[o].regs != 0); | |
2790 | tcg_debug_assert(!def->args_ct[o].oalias); | |
2791 | def->args_ct[i] = def->args_ct[o]; | |
2792 | /* The output sets oalias. */ | |
2793 | def->args_ct[o].oalias = 1; | |
2794 | def->args_ct[o].alias_index = i; | |
2795 | /* The input sets ialias. */ | |
2796 | def->args_ct[i].ialias = 1; | |
2797 | def->args_ct[i].alias_index = o; | |
29f5e925 RH |
2798 | if (def->args_ct[i].pair) { |
2799 | saw_alias_pair = true; | |
2800 | } | |
8940ea0d PMD |
2801 | tcg_debug_assert(ct_str[1] == '\0'); |
2802 | continue; | |
2803 | ||
2804 | case '&': | |
2805 | tcg_debug_assert(!input_p); | |
2806 | def->args_ct[i].newreg = true; | |
2807 | ct_str++; | |
2808 | break; | |
29f5e925 RH |
2809 | |
2810 | case 'p': /* plus */ | |
2811 | /* Allocate to the register after the previous. */ | |
2812 | tcg_debug_assert(i > (input_p ? def->nb_oargs : 0)); | |
2813 | o = i - 1; | |
2814 | tcg_debug_assert(!def->args_ct[o].pair); | |
2815 | tcg_debug_assert(!def->args_ct[o].ct); | |
2816 | def->args_ct[i] = (TCGArgConstraint){ | |
2817 | .pair = 2, | |
2818 | .pair_index = o, | |
2819 | .regs = def->args_ct[o].regs << 1, | |
2820 | }; | |
2821 | def->args_ct[o].pair = 1; | |
2822 | def->args_ct[o].pair_index = i; | |
2823 | tcg_debug_assert(ct_str[1] == '\0'); | |
2824 | continue; | |
2825 | ||
2826 | case 'm': /* minus */ | |
2827 | /* Allocate to the register before the previous. */ | |
2828 | tcg_debug_assert(i > (input_p ? def->nb_oargs : 0)); | |
2829 | o = i - 1; | |
2830 | tcg_debug_assert(!def->args_ct[o].pair); | |
2831 | tcg_debug_assert(!def->args_ct[o].ct); | |
2832 | def->args_ct[i] = (TCGArgConstraint){ | |
2833 | .pair = 1, | |
2834 | .pair_index = o, | |
2835 | .regs = def->args_ct[o].regs >> 1, | |
2836 | }; | |
2837 | def->args_ct[o].pair = 2; | |
2838 | def->args_ct[o].pair_index = i; | |
2839 | tcg_debug_assert(ct_str[1] == '\0'); | |
2840 | continue; | |
8940ea0d PMD |
2841 | } |
2842 | ||
2843 | do { | |
2844 | switch (*ct_str) { | |
17280ff4 RH |
2845 | case 'i': |
2846 | def->args_ct[i].ct |= TCG_CT_CONST; | |
17280ff4 | 2847 | break; |
358b4923 | 2848 | |
358b4923 RH |
2849 | /* Include all of the target-specific constraints. */ |
2850 | ||
2851 | #undef CONST | |
2852 | #define CONST(CASE, MASK) \ | |
8940ea0d | 2853 | case CASE: def->args_ct[i].ct |= MASK; break; |
358b4923 | 2854 | #define REGS(CASE, MASK) \ |
8940ea0d | 2855 | case CASE: def->args_ct[i].regs |= MASK; break; |
358b4923 RH |
2856 | |
2857 | #include "tcg-target-con-str.h" | |
2858 | ||
2859 | #undef REGS | |
2860 | #undef CONST | |
17280ff4 | 2861 | default: |
8940ea0d PMD |
2862 | case '0' ... '9': |
2863 | case '&': | |
29f5e925 RH |
2864 | case 'p': |
2865 | case 'm': | |
17280ff4 | 2866 | /* Typo in TCGTargetOpDef constraint. */ |
358b4923 | 2867 | g_assert_not_reached(); |
c896fe29 | 2868 | } |
8940ea0d | 2869 | } while (*++ct_str != '\0'); |
c896fe29 FB |
2870 | } |
2871 | ||
c68aaa18 | 2872 | /* TCGTargetOpDef entry with too much information? */ |
eabb7b91 | 2873 | tcg_debug_assert(i == TCG_MAX_OP_ARGS || tdefs->args_ct_str[i] == NULL); |
c68aaa18 | 2874 | |
29f5e925 RH |
2875 | /* |
2876 | * Fix up output pairs that are aliased with inputs. | |
2877 | * When we created the alias, we copied pair from the output. | |
2878 | * There are three cases: | |
2879 | * (1a) Pairs of inputs alias pairs of outputs. | |
2880 | * (1b) One input aliases the first of a pair of outputs. | |
2881 | * (2) One input aliases the second of a pair of outputs. | |
2882 | * | |
2883 | * Case 1a is handled by making sure that the pair_index'es are | |
2884 | * properly updated so that they appear the same as a pair of inputs. | |
2885 | * | |
2886 | * Case 1b is handled by setting the pair_index of the input to | |
2887 | * itself, simply so it doesn't point to an unrelated argument. | |
2888 | * Since we don't encounter the "second" during the input allocation | |
2889 | * phase, nothing happens with the second half of the input pair. | |
2890 | * | |
2891 | * Case 2 is handled by setting the second input to pair=3, the | |
2892 | * first output to pair=3, and the pair_index'es to match. | |
2893 | */ | |
2894 | if (saw_alias_pair) { | |
2895 | for (i = def->nb_oargs; i < nb_args; i++) { | |
2896 | /* | |
2897 | * Since [0-9pm] must be alone in the constraint string, | |
2898 | * the only way they can both be set is if the pair comes | |
2899 | * from the output alias. | |
2900 | */ | |
2901 | if (!def->args_ct[i].ialias) { | |
2902 | continue; | |
2903 | } | |
2904 | switch (def->args_ct[i].pair) { | |
2905 | case 0: | |
2906 | break; | |
2907 | case 1: | |
2908 | o = def->args_ct[i].alias_index; | |
2909 | o2 = def->args_ct[o].pair_index; | |
2910 | tcg_debug_assert(def->args_ct[o].pair == 1); | |
2911 | tcg_debug_assert(def->args_ct[o2].pair == 2); | |
2912 | if (def->args_ct[o2].oalias) { | |
2913 | /* Case 1a */ | |
2914 | i2 = def->args_ct[o2].alias_index; | |
2915 | tcg_debug_assert(def->args_ct[i2].pair == 2); | |
2916 | def->args_ct[i2].pair_index = i; | |
2917 | def->args_ct[i].pair_index = i2; | |
2918 | } else { | |
2919 | /* Case 1b */ | |
2920 | def->args_ct[i].pair_index = i; | |
2921 | } | |
2922 | break; | |
2923 | case 2: | |
2924 | o = def->args_ct[i].alias_index; | |
2925 | o2 = def->args_ct[o].pair_index; | |
2926 | tcg_debug_assert(def->args_ct[o].pair == 2); | |
2927 | tcg_debug_assert(def->args_ct[o2].pair == 1); | |
2928 | if (def->args_ct[o2].oalias) { | |
2929 | /* Case 1a */ | |
2930 | i2 = def->args_ct[o2].alias_index; | |
2931 | tcg_debug_assert(def->args_ct[i2].pair == 1); | |
2932 | def->args_ct[i2].pair_index = i; | |
2933 | def->args_ct[i].pair_index = i2; | |
2934 | } else { | |
2935 | /* Case 2 */ | |
2936 | def->args_ct[i].pair = 3; | |
2937 | def->args_ct[o2].pair = 3; | |
2938 | def->args_ct[i].pair_index = o2; | |
2939 | def->args_ct[o2].pair_index = i; | |
2940 | } | |
2941 | break; | |
2942 | default: | |
2943 | g_assert_not_reached(); | |
2944 | } | |
2945 | } | |
2946 | } | |
2947 | ||
c896fe29 FB |
2948 | /* sort the constraints (XXX: this is just an heuristic) */ |
2949 | sort_constraints(def, 0, def->nb_oargs); | |
2950 | sort_constraints(def, def->nb_oargs, def->nb_iargs); | |
a9751609 | 2951 | } |
c896fe29 FB |
2952 | } |
2953 | ||
f85b1fc4 | 2954 | static void remove_label_use(TCGOp *op, int idx) |
0c627cdc | 2955 | { |
f85b1fc4 RH |
2956 | TCGLabel *label = arg_label(op->args[idx]); |
2957 | TCGLabelUse *use; | |
d88a117e | 2958 | |
f85b1fc4 RH |
2959 | QSIMPLEQ_FOREACH(use, &label->branches, next) { |
2960 | if (use->op == op) { | |
2961 | QSIMPLEQ_REMOVE(&label->branches, use, TCGLabelUse, next); | |
2962 | return; | |
2963 | } | |
2964 | } | |
2965 | g_assert_not_reached(); | |
2966 | } | |
2967 | ||
2968 | void tcg_op_remove(TCGContext *s, TCGOp *op) | |
2969 | { | |
d88a117e RH |
2970 | switch (op->opc) { |
2971 | case INDEX_op_br: | |
f85b1fc4 | 2972 | remove_label_use(op, 0); |
d88a117e RH |
2973 | break; |
2974 | case INDEX_op_brcond_i32: | |
2975 | case INDEX_op_brcond_i64: | |
f85b1fc4 | 2976 | remove_label_use(op, 3); |
d88a117e RH |
2977 | break; |
2978 | case INDEX_op_brcond2_i32: | |
f85b1fc4 | 2979 | remove_label_use(op, 5); |
d88a117e RH |
2980 | break; |
2981 | default: | |
2982 | break; | |
2983 | } | |
2984 | ||
15fa08f8 RH |
2985 | QTAILQ_REMOVE(&s->ops, op, link); |
2986 | QTAILQ_INSERT_TAIL(&s->free_ops, op, link); | |
abebf925 | 2987 | s->nb_ops--; |
0c627cdc RH |
2988 | |
2989 | #ifdef CONFIG_PROFILER | |
d73415a3 | 2990 | qatomic_set(&s->prof.del_op_count, s->prof.del_op_count + 1); |
0c627cdc RH |
2991 | #endif |
2992 | } | |
2993 | ||
a80cdd31 RH |
2994 | void tcg_remove_ops_after(TCGOp *op) |
2995 | { | |
2996 | TCGContext *s = tcg_ctx; | |
2997 | ||
2998 | while (true) { | |
2999 | TCGOp *last = tcg_last_op(); | |
3000 | if (last == op) { | |
3001 | return; | |
3002 | } | |
3003 | tcg_op_remove(s, last); | |
3004 | } | |
3005 | } | |
3006 | ||
d4478943 | 3007 | static TCGOp *tcg_op_alloc(TCGOpcode opc, unsigned nargs) |
5a18407f | 3008 | { |
15fa08f8 | 3009 | TCGContext *s = tcg_ctx; |
cb10bc63 RH |
3010 | TCGOp *op = NULL; |
3011 | ||
3012 | if (unlikely(!QTAILQ_EMPTY(&s->free_ops))) { | |
3013 | QTAILQ_FOREACH(op, &s->free_ops, link) { | |
3014 | if (nargs <= op->nargs) { | |
3015 | QTAILQ_REMOVE(&s->free_ops, op, link); | |
3016 | nargs = op->nargs; | |
3017 | goto found; | |
3018 | } | |
3019 | } | |
15fa08f8 | 3020 | } |
cb10bc63 RH |
3021 | |
3022 | /* Most opcodes have 3 or 4 operands: reduce fragmentation. */ | |
3023 | nargs = MAX(4, nargs); | |
3024 | op = tcg_malloc(sizeof(TCGOp) + sizeof(TCGArg) * nargs); | |
3025 | ||
3026 | found: | |
15fa08f8 RH |
3027 | memset(op, 0, offsetof(TCGOp, link)); |
3028 | op->opc = opc; | |
cb10bc63 RH |
3029 | op->nargs = nargs; |
3030 | ||
3031 | /* Check for bitfield overflow. */ | |
3032 | tcg_debug_assert(op->nargs == nargs); | |
5a18407f | 3033 | |
cb10bc63 | 3034 | s->nb_ops++; |
15fa08f8 RH |
3035 | return op; |
3036 | } | |
3037 | ||
d4478943 | 3038 | TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs) |
15fa08f8 | 3039 | { |
d4478943 | 3040 | TCGOp *op = tcg_op_alloc(opc, nargs); |
15fa08f8 RH |
3041 | QTAILQ_INSERT_TAIL(&tcg_ctx->ops, op, link); |
3042 | return op; | |
3043 | } | |
5a18407f | 3044 | |
d4478943 PMD |
3045 | TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op, |
3046 | TCGOpcode opc, unsigned nargs) | |
15fa08f8 | 3047 | { |
d4478943 | 3048 | TCGOp *new_op = tcg_op_alloc(opc, nargs); |
15fa08f8 | 3049 | QTAILQ_INSERT_BEFORE(old_op, new_op, link); |
5a18407f RH |
3050 | return new_op; |
3051 | } | |
3052 | ||
d4478943 PMD |
3053 | TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op, |
3054 | TCGOpcode opc, unsigned nargs) | |
5a18407f | 3055 | { |
d4478943 | 3056 | TCGOp *new_op = tcg_op_alloc(opc, nargs); |
15fa08f8 | 3057 | QTAILQ_INSERT_AFTER(&s->ops, old_op, new_op, link); |
5a18407f RH |
3058 | return new_op; |
3059 | } | |
3060 | ||
968f305e RH |
3061 | static void move_label_uses(TCGLabel *to, TCGLabel *from) |
3062 | { | |
3063 | TCGLabelUse *u; | |
3064 | ||
3065 | QSIMPLEQ_FOREACH(u, &from->branches, next) { | |
3066 | TCGOp *op = u->op; | |
3067 | switch (op->opc) { | |
3068 | case INDEX_op_br: | |
3069 | op->args[0] = label_arg(to); | |
3070 | break; | |
3071 | case INDEX_op_brcond_i32: | |
3072 | case INDEX_op_brcond_i64: | |
3073 | op->args[3] = label_arg(to); | |
3074 | break; | |
3075 | case INDEX_op_brcond2_i32: | |
3076 | op->args[5] = label_arg(to); | |
3077 | break; | |
3078 | default: | |
3079 | g_assert_not_reached(); | |
3080 | } | |
3081 | } | |
3082 | ||
3083 | QSIMPLEQ_CONCAT(&to->branches, &from->branches); | |
3084 | } | |
3085 | ||
b4fc67c7 | 3086 | /* Reachable analysis : remove unreachable code. */ |
9bbee4c0 RH |
3087 | static void __attribute__((noinline)) |
3088 | reachable_code_pass(TCGContext *s) | |
b4fc67c7 | 3089 | { |
4d89d0bb | 3090 | TCGOp *op, *op_next, *op_prev; |
b4fc67c7 RH |
3091 | bool dead = false; |
3092 | ||
3093 | QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { | |
3094 | bool remove = dead; | |
3095 | TCGLabel *label; | |
b4fc67c7 RH |
3096 | |
3097 | switch (op->opc) { | |
3098 | case INDEX_op_set_label: | |
3099 | label = arg_label(op->args[0]); | |
4d89d0bb | 3100 | |
968f305e RH |
3101 | /* |
3102 | * Note that the first op in the TB is always a load, | |
3103 | * so there is always something before a label. | |
3104 | */ | |
3105 | op_prev = QTAILQ_PREV(op, link); | |
3106 | ||
3107 | /* | |
3108 | * If we find two sequential labels, move all branches to | |
3109 | * reference the second label and remove the first label. | |
3110 | * Do this before branch to next optimization, so that the | |
3111 | * middle label is out of the way. | |
3112 | */ | |
3113 | if (op_prev->opc == INDEX_op_set_label) { | |
3114 | move_label_uses(label, arg_label(op_prev->args[0])); | |
3115 | tcg_op_remove(s, op_prev); | |
3116 | op_prev = QTAILQ_PREV(op, link); | |
3117 | } | |
3118 | ||
4d89d0bb RH |
3119 | /* |
3120 | * Optimization can fold conditional branches to unconditional. | |
3121 | * If we find a label which is preceded by an unconditional | |
3122 | * branch to next, remove the branch. We couldn't do this when | |
3123 | * processing the branch because any dead code between the branch | |
3124 | * and label had not yet been removed. | |
3125 | */ | |
4d89d0bb RH |
3126 | if (op_prev->opc == INDEX_op_br && |
3127 | label == arg_label(op_prev->args[0])) { | |
3128 | tcg_op_remove(s, op_prev); | |
3129 | /* Fall through means insns become live again. */ | |
3130 | dead = false; | |
3131 | } | |
3132 | ||
f85b1fc4 | 3133 | if (QSIMPLEQ_EMPTY(&label->branches)) { |
b4fc67c7 RH |
3134 | /* |
3135 | * While there is an occasional backward branch, virtually | |
3136 | * all branches generated by the translators are forward. | |
3137 | * Which means that generally we will have already removed | |
3138 | * all references to the label that will be, and there is | |
3139 | * little to be gained by iterating. | |
3140 | */ | |
3141 | remove = true; | |
3142 | } else { | |
3143 | /* Once we see a label, insns become live again. */ | |
3144 | dead = false; | |
3145 | remove = false; | |
b4fc67c7 RH |
3146 | } |
3147 | break; | |
3148 | ||
3149 | case INDEX_op_br: | |
3150 | case INDEX_op_exit_tb: | |
3151 | case INDEX_op_goto_ptr: | |
3152 | /* Unconditional branches; everything following is dead. */ | |
3153 | dead = true; | |
3154 | break; | |
3155 | ||
3156 | case INDEX_op_call: | |
3157 | /* Notice noreturn helper calls, raising exceptions. */ | |
90163900 | 3158 | if (tcg_call_flags(op) & TCG_CALL_NO_RETURN) { |
b4fc67c7 RH |
3159 | dead = true; |
3160 | } | |
3161 | break; | |
3162 | ||
3163 | case INDEX_op_insn_start: | |
3164 | /* Never remove -- we need to keep these for unwind. */ | |
3165 | remove = false; | |
3166 | break; | |
3167 | ||
3168 | default: | |
3169 | break; | |
3170 | } | |
3171 | ||
3172 | if (remove) { | |
3173 | tcg_op_remove(s, op); | |
3174 | } | |
3175 | } | |
3176 | } | |
3177 | ||
c70fbf0a RH |
3178 | #define TS_DEAD 1 |
3179 | #define TS_MEM 2 | |
3180 | ||
5a18407f RH |
3181 | #define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n))) |
3182 | #define NEED_SYNC_ARG(n) (arg_life & (SYNC_ARG << (n))) | |
3183 | ||
25f49c5f RH |
3184 | /* For liveness_pass_1, the register preferences for a given temp. */ |
3185 | static inline TCGRegSet *la_temp_pref(TCGTemp *ts) | |
3186 | { | |
3187 | return ts->state_ptr; | |
3188 | } | |
3189 | ||
3190 | /* For liveness_pass_1, reset the preferences for a given temp to the | |
3191 | * maximal regset for its type. | |
3192 | */ | |
3193 | static inline void la_reset_pref(TCGTemp *ts) | |
3194 | { | |
3195 | *la_temp_pref(ts) | |
3196 | = (ts->state == TS_DEAD ? 0 : tcg_target_available_regs[ts->type]); | |
3197 | } | |
3198 | ||
9c43b68d AJ |
3199 | /* liveness analysis: end of function: all temps are dead, and globals |
3200 | should be in memory. */ | |
2616c808 | 3201 | static void la_func_end(TCGContext *s, int ng, int nt) |
c896fe29 | 3202 | { |
b83eabea RH |
3203 | int i; |
3204 | ||
3205 | for (i = 0; i < ng; ++i) { | |
3206 | s->temps[i].state = TS_DEAD | TS_MEM; | |
25f49c5f | 3207 | la_reset_pref(&s->temps[i]); |
b83eabea RH |
3208 | } |
3209 | for (i = ng; i < nt; ++i) { | |
3210 | s->temps[i].state = TS_DEAD; | |
25f49c5f | 3211 | la_reset_pref(&s->temps[i]); |
b83eabea | 3212 | } |
c896fe29 FB |
3213 | } |
3214 | ||
9c43b68d AJ |
3215 | /* liveness analysis: end of basic block: all temps are dead, globals |
3216 | and local temps should be in memory. */ | |
2616c808 | 3217 | static void la_bb_end(TCGContext *s, int ng, int nt) |
641d5fbe | 3218 | { |
b83eabea | 3219 | int i; |
641d5fbe | 3220 | |
ee17db83 RH |
3221 | for (i = 0; i < nt; ++i) { |
3222 | TCGTemp *ts = &s->temps[i]; | |
3223 | int state; | |
3224 | ||
3225 | switch (ts->kind) { | |
3226 | case TEMP_FIXED: | |
3227 | case TEMP_GLOBAL: | |
f57c6915 | 3228 | case TEMP_TB: |
ee17db83 RH |
3229 | state = TS_DEAD | TS_MEM; |
3230 | break; | |
c7482438 | 3231 | case TEMP_EBB: |
c0522136 | 3232 | case TEMP_CONST: |
ee17db83 RH |
3233 | state = TS_DEAD; |
3234 | break; | |
3235 | default: | |
3236 | g_assert_not_reached(); | |
3237 | } | |
3238 | ts->state = state; | |
3239 | la_reset_pref(ts); | |
641d5fbe FB |
3240 | } |
3241 | } | |
3242 | ||
f65a061c RH |
3243 | /* liveness analysis: sync globals back to memory. */ |
3244 | static void la_global_sync(TCGContext *s, int ng) | |
3245 | { | |
3246 | int i; | |
3247 | ||
3248 | for (i = 0; i < ng; ++i) { | |
25f49c5f RH |
3249 | int state = s->temps[i].state; |
3250 | s->temps[i].state = state | TS_MEM; | |
3251 | if (state == TS_DEAD) { | |
3252 | /* If the global was previously dead, reset prefs. */ | |
3253 | la_reset_pref(&s->temps[i]); | |
3254 | } | |
f65a061c RH |
3255 | } |
3256 | } | |
3257 | ||
b4cb76e6 | 3258 | /* |
c7482438 RH |
3259 | * liveness analysis: conditional branch: all temps are dead unless |
3260 | * explicitly live-across-conditional-branch, globals and local temps | |
3261 | * should be synced. | |
b4cb76e6 RH |
3262 | */ |
3263 | static void la_bb_sync(TCGContext *s, int ng, int nt) | |
3264 | { | |
3265 | la_global_sync(s, ng); | |
3266 | ||
3267 | for (int i = ng; i < nt; ++i) { | |
c0522136 RH |
3268 | TCGTemp *ts = &s->temps[i]; |
3269 | int state; | |
3270 | ||
3271 | switch (ts->kind) { | |
f57c6915 | 3272 | case TEMP_TB: |
c0522136 RH |
3273 | state = ts->state; |
3274 | ts->state = state | TS_MEM; | |
b4cb76e6 RH |
3275 | if (state != TS_DEAD) { |
3276 | continue; | |
3277 | } | |
c0522136 | 3278 | break; |
c7482438 | 3279 | case TEMP_EBB: |
c0522136 RH |
3280 | case TEMP_CONST: |
3281 | continue; | |
3282 | default: | |
3283 | g_assert_not_reached(); | |
b4cb76e6 RH |
3284 | } |
3285 | la_reset_pref(&s->temps[i]); | |
3286 | } | |
3287 | } | |
3288 | ||
f65a061c RH |
3289 | /* liveness analysis: sync globals back to memory and kill. */ |
3290 | static void la_global_kill(TCGContext *s, int ng) | |
3291 | { | |
3292 | int i; | |
3293 | ||
3294 | for (i = 0; i < ng; i++) { | |
3295 | s->temps[i].state = TS_DEAD | TS_MEM; | |
25f49c5f RH |
3296 | la_reset_pref(&s->temps[i]); |
3297 | } | |
3298 | } | |
3299 | ||
3300 | /* liveness analysis: note live globals crossing calls. */ | |
3301 | static void la_cross_call(TCGContext *s, int nt) | |
3302 | { | |
3303 | TCGRegSet mask = ~tcg_target_call_clobber_regs; | |
3304 | int i; | |
3305 | ||
3306 | for (i = 0; i < nt; i++) { | |
3307 | TCGTemp *ts = &s->temps[i]; | |
3308 | if (!(ts->state & TS_DEAD)) { | |
3309 | TCGRegSet *pset = la_temp_pref(ts); | |
3310 | TCGRegSet set = *pset; | |
3311 | ||
3312 | set &= mask; | |
3313 | /* If the combination is not possible, restart. */ | |
3314 | if (set == 0) { | |
3315 | set = tcg_target_available_regs[ts->type] & mask; | |
3316 | } | |
3317 | *pset = set; | |
3318 | } | |
f65a061c RH |
3319 | } |
3320 | } | |
3321 | ||
874b8574 RH |
3322 | /* |
3323 | * Liveness analysis: Verify the lifetime of TEMP_TB, and reduce | |
3324 | * to TEMP_EBB, if possible. | |
3325 | */ | |
3326 | static void __attribute__((noinline)) | |
3327 | liveness_pass_0(TCGContext *s) | |
3328 | { | |
3329 | void * const multiple_ebb = (void *)(uintptr_t)-1; | |
3330 | int nb_temps = s->nb_temps; | |
3331 | TCGOp *op, *ebb; | |
3332 | ||
3333 | for (int i = s->nb_globals; i < nb_temps; ++i) { | |
3334 | s->temps[i].state_ptr = NULL; | |
3335 | } | |
3336 | ||
3337 | /* | |
3338 | * Represent each EBB by the op at which it begins. In the case of | |
3339 | * the first EBB, this is the first op, otherwise it is a label. | |
3340 | * Collect the uses of each TEMP_TB: NULL for unused, EBB for use | |
3341 | * within a single EBB, else MULTIPLE_EBB. | |
3342 | */ | |
3343 | ebb = QTAILQ_FIRST(&s->ops); | |
3344 | QTAILQ_FOREACH(op, &s->ops, link) { | |
3345 | const TCGOpDef *def; | |
3346 | int nb_oargs, nb_iargs; | |
3347 | ||
3348 | switch (op->opc) { | |
3349 | case INDEX_op_set_label: | |
3350 | ebb = op; | |
3351 | continue; | |
3352 | case INDEX_op_discard: | |
3353 | continue; | |
3354 | case INDEX_op_call: | |
3355 | nb_oargs = TCGOP_CALLO(op); | |
3356 | nb_iargs = TCGOP_CALLI(op); | |
3357 | break; | |
3358 | default: | |
3359 | def = &tcg_op_defs[op->opc]; | |
3360 | nb_oargs = def->nb_oargs; | |
3361 | nb_iargs = def->nb_iargs; | |
3362 | break; | |
3363 | } | |
3364 | ||
3365 | for (int i = 0; i < nb_oargs + nb_iargs; ++i) { | |
3366 | TCGTemp *ts = arg_temp(op->args[i]); | |
3367 | ||
3368 | if (ts->kind != TEMP_TB) { | |
3369 | continue; | |
3370 | } | |
3371 | if (ts->state_ptr == NULL) { | |
3372 | ts->state_ptr = ebb; | |
3373 | } else if (ts->state_ptr != ebb) { | |
3374 | ts->state_ptr = multiple_ebb; | |
3375 | } | |
3376 | } | |
3377 | } | |
3378 | ||
3379 | /* | |
3380 | * For TEMP_TB that turned out not to be used beyond one EBB, | |
3381 | * reduce the liveness to TEMP_EBB. | |
3382 | */ | |
3383 | for (int i = s->nb_globals; i < nb_temps; ++i) { | |
3384 | TCGTemp *ts = &s->temps[i]; | |
3385 | if (ts->kind == TEMP_TB && ts->state_ptr != multiple_ebb) { | |
3386 | ts->kind = TEMP_EBB; | |
3387 | } | |
3388 | } | |
3389 | } | |
3390 | ||
a1b3c48d | 3391 | /* Liveness analysis : update the opc_arg_life array to tell if a |
c896fe29 FB |
3392 | given input arguments is dead. Instructions updating dead |
3393 | temporaries are removed. */ | |
9bbee4c0 RH |
3394 | static void __attribute__((noinline)) |
3395 | liveness_pass_1(TCGContext *s) | |
c896fe29 | 3396 | { |
c70fbf0a | 3397 | int nb_globals = s->nb_globals; |
2616c808 | 3398 | int nb_temps = s->nb_temps; |
15fa08f8 | 3399 | TCGOp *op, *op_prev; |
25f49c5f RH |
3400 | TCGRegSet *prefs; |
3401 | int i; | |
3402 | ||
3403 | prefs = tcg_malloc(sizeof(TCGRegSet) * nb_temps); | |
3404 | for (i = 0; i < nb_temps; ++i) { | |
3405 | s->temps[i].state_ptr = prefs + i; | |
3406 | } | |
a1b3c48d | 3407 | |
ae36a246 | 3408 | /* ??? Should be redundant with the exit_tb that ends the TB. */ |
2616c808 | 3409 | la_func_end(s, nb_globals, nb_temps); |
c896fe29 | 3410 | |
eae3eb3e | 3411 | QTAILQ_FOREACH_REVERSE_SAFE(op, &s->ops, link, op_prev) { |
25f49c5f | 3412 | int nb_iargs, nb_oargs; |
c45cb8bb RH |
3413 | TCGOpcode opc_new, opc_new2; |
3414 | bool have_opc_new2; | |
a1b3c48d | 3415 | TCGLifeData arg_life = 0; |
25f49c5f | 3416 | TCGTemp *ts; |
c45cb8bb RH |
3417 | TCGOpcode opc = op->opc; |
3418 | const TCGOpDef *def = &tcg_op_defs[opc]; | |
3419 | ||
c45cb8bb | 3420 | switch (opc) { |
c896fe29 | 3421 | case INDEX_op_call: |
c6e113f5 | 3422 | { |
39004a71 RH |
3423 | const TCGHelperInfo *info = tcg_call_info(op); |
3424 | int call_flags = tcg_call_flags(op); | |
c896fe29 | 3425 | |
cd9090aa RH |
3426 | nb_oargs = TCGOP_CALLO(op); |
3427 | nb_iargs = TCGOP_CALLI(op); | |
c6e113f5 | 3428 | |
c45cb8bb | 3429 | /* pure functions can be removed if their result is unused */ |
78505279 | 3430 | if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) { |
cf066674 | 3431 | for (i = 0; i < nb_oargs; i++) { |
25f49c5f RH |
3432 | ts = arg_temp(op->args[i]); |
3433 | if (ts->state != TS_DEAD) { | |
c6e113f5 | 3434 | goto do_not_remove_call; |
9c43b68d | 3435 | } |
c6e113f5 | 3436 | } |
c45cb8bb | 3437 | goto do_remove; |
152c35aa RH |
3438 | } |
3439 | do_not_remove_call: | |
c896fe29 | 3440 | |
25f49c5f | 3441 | /* Output args are dead. */ |
152c35aa | 3442 | for (i = 0; i < nb_oargs; i++) { |
25f49c5f RH |
3443 | ts = arg_temp(op->args[i]); |
3444 | if (ts->state & TS_DEAD) { | |
152c35aa RH |
3445 | arg_life |= DEAD_ARG << i; |
3446 | } | |
25f49c5f | 3447 | if (ts->state & TS_MEM) { |
152c35aa | 3448 | arg_life |= SYNC_ARG << i; |
c6e113f5 | 3449 | } |
25f49c5f RH |
3450 | ts->state = TS_DEAD; |
3451 | la_reset_pref(ts); | |
152c35aa | 3452 | } |
78505279 | 3453 | |
31fd884b RH |
3454 | /* Not used -- it will be tcg_target_call_oarg_reg(). */ |
3455 | memset(op->output_pref, 0, sizeof(op->output_pref)); | |
3456 | ||
152c35aa RH |
3457 | if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS | |
3458 | TCG_CALL_NO_READ_GLOBALS))) { | |
f65a061c | 3459 | la_global_kill(s, nb_globals); |
152c35aa | 3460 | } else if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) { |
f65a061c | 3461 | la_global_sync(s, nb_globals); |
152c35aa | 3462 | } |
b9c18f56 | 3463 | |
25f49c5f | 3464 | /* Record arguments that die in this helper. */ |
152c35aa | 3465 | for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { |
25f49c5f | 3466 | ts = arg_temp(op->args[i]); |
39004a71 | 3467 | if (ts->state & TS_DEAD) { |
152c35aa | 3468 | arg_life |= DEAD_ARG << i; |
c6e113f5 | 3469 | } |
152c35aa | 3470 | } |
25f49c5f RH |
3471 | |
3472 | /* For all live registers, remove call-clobbered prefs. */ | |
3473 | la_cross_call(s, nb_temps); | |
3474 | ||
39004a71 RH |
3475 | /* |
3476 | * Input arguments are live for preceding opcodes. | |
3477 | * | |
3478 | * For those arguments that die, and will be allocated in | |
3479 | * registers, clear the register set for that arg, to be | |
3480 | * filled in below. For args that will be on the stack, | |
3481 | * reset to any available reg. Process arguments in reverse | |
3482 | * order so that if a temp is used more than once, the stack | |
3483 | * reset to max happens before the register reset to 0. | |
3484 | */ | |
3485 | for (i = nb_iargs - 1; i >= 0; i--) { | |
3486 | const TCGCallArgumentLoc *loc = &info->in[i]; | |
3487 | ts = arg_temp(op->args[nb_oargs + i]); | |
25f49c5f | 3488 | |
39004a71 RH |
3489 | if (ts->state & TS_DEAD) { |
3490 | switch (loc->kind) { | |
3491 | case TCG_CALL_ARG_NORMAL: | |
3492 | case TCG_CALL_ARG_EXTEND_U: | |
3493 | case TCG_CALL_ARG_EXTEND_S: | |
338b61e9 | 3494 | if (arg_slot_reg_p(loc->arg_slot)) { |
39004a71 RH |
3495 | *la_temp_pref(ts) = 0; |
3496 | break; | |
3497 | } | |
3498 | /* fall through */ | |
3499 | default: | |
3500 | *la_temp_pref(ts) = | |
3501 | tcg_target_available_regs[ts->type]; | |
3502 | break; | |
3503 | } | |
25f49c5f RH |
3504 | ts->state &= ~TS_DEAD; |
3505 | } | |
3506 | } | |
3507 | ||
39004a71 RH |
3508 | /* |
3509 | * For each input argument, add its input register to prefs. | |
3510 | * If a temp is used once, this produces a single set bit; | |
3511 | * if a temp is used multiple times, this produces a set. | |
3512 | */ | |
3513 | for (i = 0; i < nb_iargs; i++) { | |
3514 | const TCGCallArgumentLoc *loc = &info->in[i]; | |
3515 | ts = arg_temp(op->args[nb_oargs + i]); | |
3516 | ||
3517 | switch (loc->kind) { | |
3518 | case TCG_CALL_ARG_NORMAL: | |
3519 | case TCG_CALL_ARG_EXTEND_U: | |
3520 | case TCG_CALL_ARG_EXTEND_S: | |
338b61e9 | 3521 | if (arg_slot_reg_p(loc->arg_slot)) { |
39004a71 RH |
3522 | tcg_regset_set_reg(*la_temp_pref(ts), |
3523 | tcg_target_call_iarg_regs[loc->arg_slot]); | |
3524 | } | |
3525 | break; | |
3526 | default: | |
3527 | break; | |
c19f47bf | 3528 | } |
c896fe29 | 3529 | } |
c896fe29 | 3530 | } |
c896fe29 | 3531 | break; |
765b842a | 3532 | case INDEX_op_insn_start: |
c896fe29 | 3533 | break; |
5ff9d6a4 | 3534 | case INDEX_op_discard: |
5ff9d6a4 | 3535 | /* mark the temporary as dead */ |
25f49c5f RH |
3536 | ts = arg_temp(op->args[0]); |
3537 | ts->state = TS_DEAD; | |
3538 | la_reset_pref(ts); | |
5ff9d6a4 | 3539 | break; |
1305c451 RH |
3540 | |
3541 | case INDEX_op_add2_i32: | |
c45cb8bb | 3542 | opc_new = INDEX_op_add_i32; |
f1fae40c | 3543 | goto do_addsub2; |
1305c451 | 3544 | case INDEX_op_sub2_i32: |
c45cb8bb | 3545 | opc_new = INDEX_op_sub_i32; |
f1fae40c RH |
3546 | goto do_addsub2; |
3547 | case INDEX_op_add2_i64: | |
c45cb8bb | 3548 | opc_new = INDEX_op_add_i64; |
f1fae40c RH |
3549 | goto do_addsub2; |
3550 | case INDEX_op_sub2_i64: | |
c45cb8bb | 3551 | opc_new = INDEX_op_sub_i64; |
f1fae40c | 3552 | do_addsub2: |
1305c451 RH |
3553 | nb_iargs = 4; |
3554 | nb_oargs = 2; | |
3555 | /* Test if the high part of the operation is dead, but not | |
3556 | the low part. The result can be optimized to a simple | |
3557 | add or sub. This happens often for x86_64 guest when the | |
3558 | cpu mode is set to 32 bit. */ | |
b83eabea RH |
3559 | if (arg_temp(op->args[1])->state == TS_DEAD) { |
3560 | if (arg_temp(op->args[0])->state == TS_DEAD) { | |
1305c451 RH |
3561 | goto do_remove; |
3562 | } | |
c45cb8bb RH |
3563 | /* Replace the opcode and adjust the args in place, |
3564 | leaving 3 unused args at the end. */ | |
3565 | op->opc = opc = opc_new; | |
efee3746 RH |
3566 | op->args[1] = op->args[2]; |
3567 | op->args[2] = op->args[4]; | |
1305c451 RH |
3568 | /* Fall through and mark the single-word operation live. */ |
3569 | nb_iargs = 2; | |
3570 | nb_oargs = 1; | |
3571 | } | |
3572 | goto do_not_remove; | |
3573 | ||
1414968a | 3574 | case INDEX_op_mulu2_i32: |
c45cb8bb RH |
3575 | opc_new = INDEX_op_mul_i32; |
3576 | opc_new2 = INDEX_op_muluh_i32; | |
3577 | have_opc_new2 = TCG_TARGET_HAS_muluh_i32; | |
03271524 | 3578 | goto do_mul2; |
f1fae40c | 3579 | case INDEX_op_muls2_i32: |
c45cb8bb RH |
3580 | opc_new = INDEX_op_mul_i32; |
3581 | opc_new2 = INDEX_op_mulsh_i32; | |
3582 | have_opc_new2 = TCG_TARGET_HAS_mulsh_i32; | |
f1fae40c RH |
3583 | goto do_mul2; |
3584 | case INDEX_op_mulu2_i64: | |
c45cb8bb RH |
3585 | opc_new = INDEX_op_mul_i64; |
3586 | opc_new2 = INDEX_op_muluh_i64; | |
3587 | have_opc_new2 = TCG_TARGET_HAS_muluh_i64; | |
03271524 | 3588 | goto do_mul2; |
f1fae40c | 3589 | case INDEX_op_muls2_i64: |
c45cb8bb RH |
3590 | opc_new = INDEX_op_mul_i64; |
3591 | opc_new2 = INDEX_op_mulsh_i64; | |
3592 | have_opc_new2 = TCG_TARGET_HAS_mulsh_i64; | |
03271524 | 3593 | goto do_mul2; |
f1fae40c | 3594 | do_mul2: |
1414968a RH |
3595 | nb_iargs = 2; |
3596 | nb_oargs = 2; | |
b83eabea RH |
3597 | if (arg_temp(op->args[1])->state == TS_DEAD) { |
3598 | if (arg_temp(op->args[0])->state == TS_DEAD) { | |
03271524 | 3599 | /* Both parts of the operation are dead. */ |
1414968a RH |
3600 | goto do_remove; |
3601 | } | |
03271524 | 3602 | /* The high part of the operation is dead; generate the low. */ |
c45cb8bb | 3603 | op->opc = opc = opc_new; |
efee3746 RH |
3604 | op->args[1] = op->args[2]; |
3605 | op->args[2] = op->args[3]; | |
b83eabea | 3606 | } else if (arg_temp(op->args[0])->state == TS_DEAD && have_opc_new2) { |
c45cb8bb RH |
3607 | /* The low part of the operation is dead; generate the high. */ |
3608 | op->opc = opc = opc_new2; | |
efee3746 RH |
3609 | op->args[0] = op->args[1]; |
3610 | op->args[1] = op->args[2]; | |
3611 | op->args[2] = op->args[3]; | |
03271524 RH |
3612 | } else { |
3613 | goto do_not_remove; | |
1414968a | 3614 | } |
03271524 RH |
3615 | /* Mark the single-word operation live. */ |
3616 | nb_oargs = 1; | |
1414968a RH |
3617 | goto do_not_remove; |
3618 | ||
c896fe29 | 3619 | default: |
1305c451 | 3620 | /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */ |
49516bc0 AJ |
3621 | nb_iargs = def->nb_iargs; |
3622 | nb_oargs = def->nb_oargs; | |
c896fe29 | 3623 | |
49516bc0 AJ |
3624 | /* Test if the operation can be removed because all |
3625 | its outputs are dead. We assume that nb_oargs == 0 | |
3626 | implies side effects */ | |
3627 | if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) { | |
c45cb8bb | 3628 | for (i = 0; i < nb_oargs; i++) { |
b83eabea | 3629 | if (arg_temp(op->args[i])->state != TS_DEAD) { |
49516bc0 | 3630 | goto do_not_remove; |
9c43b68d | 3631 | } |
49516bc0 | 3632 | } |
152c35aa RH |
3633 | goto do_remove; |
3634 | } | |
3635 | goto do_not_remove; | |
49516bc0 | 3636 | |
152c35aa RH |
3637 | do_remove: |
3638 | tcg_op_remove(s, op); | |
3639 | break; | |
3640 | ||
3641 | do_not_remove: | |
152c35aa | 3642 | for (i = 0; i < nb_oargs; i++) { |
25f49c5f RH |
3643 | ts = arg_temp(op->args[i]); |
3644 | ||
3645 | /* Remember the preference of the uses that followed. */ | |
31fd884b RH |
3646 | if (i < ARRAY_SIZE(op->output_pref)) { |
3647 | op->output_pref[i] = *la_temp_pref(ts); | |
3648 | } | |
25f49c5f RH |
3649 | |
3650 | /* Output args are dead. */ | |
3651 | if (ts->state & TS_DEAD) { | |
152c35aa | 3652 | arg_life |= DEAD_ARG << i; |
49516bc0 | 3653 | } |
25f49c5f | 3654 | if (ts->state & TS_MEM) { |
152c35aa RH |
3655 | arg_life |= SYNC_ARG << i; |
3656 | } | |
25f49c5f RH |
3657 | ts->state = TS_DEAD; |
3658 | la_reset_pref(ts); | |
152c35aa | 3659 | } |
49516bc0 | 3660 | |
25f49c5f | 3661 | /* If end of basic block, update. */ |
ae36a246 RH |
3662 | if (def->flags & TCG_OPF_BB_EXIT) { |
3663 | la_func_end(s, nb_globals, nb_temps); | |
b4cb76e6 RH |
3664 | } else if (def->flags & TCG_OPF_COND_BRANCH) { |
3665 | la_bb_sync(s, nb_globals, nb_temps); | |
ae36a246 | 3666 | } else if (def->flags & TCG_OPF_BB_END) { |
2616c808 | 3667 | la_bb_end(s, nb_globals, nb_temps); |
152c35aa | 3668 | } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { |
f65a061c | 3669 | la_global_sync(s, nb_globals); |
25f49c5f RH |
3670 | if (def->flags & TCG_OPF_CALL_CLOBBER) { |
3671 | la_cross_call(s, nb_temps); | |
3672 | } | |
152c35aa RH |
3673 | } |
3674 | ||
25f49c5f | 3675 | /* Record arguments that die in this opcode. */ |
152c35aa | 3676 | for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { |
25f49c5f RH |
3677 | ts = arg_temp(op->args[i]); |
3678 | if (ts->state & TS_DEAD) { | |
152c35aa | 3679 | arg_life |= DEAD_ARG << i; |
c896fe29 | 3680 | } |
c896fe29 | 3681 | } |
25f49c5f RH |
3682 | |
3683 | /* Input arguments are live for preceding opcodes. */ | |
152c35aa | 3684 | for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { |
25f49c5f RH |
3685 | ts = arg_temp(op->args[i]); |
3686 | if (ts->state & TS_DEAD) { | |
3687 | /* For operands that were dead, initially allow | |
3688 | all regs for the type. */ | |
3689 | *la_temp_pref(ts) = tcg_target_available_regs[ts->type]; | |
3690 | ts->state &= ~TS_DEAD; | |
3691 | } | |
3692 | } | |
3693 | ||
3694 | /* Incorporate constraints for this operand. */ | |
3695 | switch (opc) { | |
3696 | case INDEX_op_mov_i32: | |
3697 | case INDEX_op_mov_i64: | |
3698 | /* Note that these are TCG_OPF_NOT_PRESENT and do not | |
3699 | have proper constraints. That said, special case | |
3700 | moves to propagate preferences backward. */ | |
3701 | if (IS_DEAD_ARG(1)) { | |
3702 | *la_temp_pref(arg_temp(op->args[0])) | |
3703 | = *la_temp_pref(arg_temp(op->args[1])); | |
3704 | } | |
3705 | break; | |
3706 | ||
3707 | default: | |
3708 | for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { | |
3709 | const TCGArgConstraint *ct = &def->args_ct[i]; | |
3710 | TCGRegSet set, *pset; | |
3711 | ||
3712 | ts = arg_temp(op->args[i]); | |
3713 | pset = la_temp_pref(ts); | |
3714 | set = *pset; | |
3715 | ||
9be0d080 | 3716 | set &= ct->regs; |
bc2b17e6 | 3717 | if (ct->ialias) { |
31fd884b | 3718 | set &= output_pref(op, ct->alias_index); |
25f49c5f RH |
3719 | } |
3720 | /* If the combination is not possible, restart. */ | |
3721 | if (set == 0) { | |
9be0d080 | 3722 | set = ct->regs; |
25f49c5f RH |
3723 | } |
3724 | *pset = set; | |
3725 | } | |
3726 | break; | |
152c35aa | 3727 | } |
c896fe29 FB |
3728 | break; |
3729 | } | |
bee158cb | 3730 | op->life = arg_life; |
1ff0a2c5 | 3731 | } |
c896fe29 | 3732 | } |
c896fe29 | 3733 | |
5a18407f | 3734 | /* Liveness analysis: Convert indirect regs to direct temporaries. */ |
9bbee4c0 RH |
3735 | static bool __attribute__((noinline)) |
3736 | liveness_pass_2(TCGContext *s) | |
5a18407f RH |
3737 | { |
3738 | int nb_globals = s->nb_globals; | |
15fa08f8 | 3739 | int nb_temps, i; |
5a18407f | 3740 | bool changes = false; |
15fa08f8 | 3741 | TCGOp *op, *op_next; |
5a18407f | 3742 | |
5a18407f RH |
3743 | /* Create a temporary for each indirect global. */ |
3744 | for (i = 0; i < nb_globals; ++i) { | |
3745 | TCGTemp *its = &s->temps[i]; | |
3746 | if (its->indirect_reg) { | |
3747 | TCGTemp *dts = tcg_temp_alloc(s); | |
3748 | dts->type = its->type; | |
3749 | dts->base_type = its->base_type; | |
e1e64652 | 3750 | dts->temp_subindex = its->temp_subindex; |
c7482438 | 3751 | dts->kind = TEMP_EBB; |
b83eabea RH |
3752 | its->state_ptr = dts; |
3753 | } else { | |
3754 | its->state_ptr = NULL; | |
5a18407f | 3755 | } |
b83eabea RH |
3756 | /* All globals begin dead. */ |
3757 | its->state = TS_DEAD; | |
3758 | } | |
3759 | for (nb_temps = s->nb_temps; i < nb_temps; ++i) { | |
3760 | TCGTemp *its = &s->temps[i]; | |
3761 | its->state_ptr = NULL; | |
3762 | its->state = TS_DEAD; | |
5a18407f | 3763 | } |
5a18407f | 3764 | |
15fa08f8 | 3765 | QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { |
5a18407f RH |
3766 | TCGOpcode opc = op->opc; |
3767 | const TCGOpDef *def = &tcg_op_defs[opc]; | |
3768 | TCGLifeData arg_life = op->life; | |
3769 | int nb_iargs, nb_oargs, call_flags; | |
b83eabea | 3770 | TCGTemp *arg_ts, *dir_ts; |
5a18407f | 3771 | |
5a18407f | 3772 | if (opc == INDEX_op_call) { |
cd9090aa RH |
3773 | nb_oargs = TCGOP_CALLO(op); |
3774 | nb_iargs = TCGOP_CALLI(op); | |
90163900 | 3775 | call_flags = tcg_call_flags(op); |
5a18407f RH |
3776 | } else { |
3777 | nb_iargs = def->nb_iargs; | |
3778 | nb_oargs = def->nb_oargs; | |
3779 | ||
3780 | /* Set flags similar to how calls require. */ | |
b4cb76e6 RH |
3781 | if (def->flags & TCG_OPF_COND_BRANCH) { |
3782 | /* Like reading globals: sync_globals */ | |
3783 | call_flags = TCG_CALL_NO_WRITE_GLOBALS; | |
3784 | } else if (def->flags & TCG_OPF_BB_END) { | |
5a18407f RH |
3785 | /* Like writing globals: save_globals */ |
3786 | call_flags = 0; | |
3787 | } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { | |
3788 | /* Like reading globals: sync_globals */ | |
3789 | call_flags = TCG_CALL_NO_WRITE_GLOBALS; | |
3790 | } else { | |
3791 | /* No effect on globals. */ | |
3792 | call_flags = (TCG_CALL_NO_READ_GLOBALS | | |
3793 | TCG_CALL_NO_WRITE_GLOBALS); | |
3794 | } | |
3795 | } | |
3796 | ||
3797 | /* Make sure that input arguments are available. */ | |
3798 | for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { | |
b83eabea | 3799 | arg_ts = arg_temp(op->args[i]); |
39004a71 RH |
3800 | dir_ts = arg_ts->state_ptr; |
3801 | if (dir_ts && arg_ts->state == TS_DEAD) { | |
3802 | TCGOpcode lopc = (arg_ts->type == TCG_TYPE_I32 | |
3803 | ? INDEX_op_ld_i32 | |
3804 | : INDEX_op_ld_i64); | |
3805 | TCGOp *lop = tcg_op_insert_before(s, op, lopc, 3); | |
3806 | ||
3807 | lop->args[0] = temp_arg(dir_ts); | |
3808 | lop->args[1] = temp_arg(arg_ts->mem_base); | |
3809 | lop->args[2] = arg_ts->mem_offset; | |
3810 | ||
3811 | /* Loaded, but synced with memory. */ | |
3812 | arg_ts->state = TS_MEM; | |
5a18407f RH |
3813 | } |
3814 | } | |
3815 | ||
3816 | /* Perform input replacement, and mark inputs that became dead. | |
3817 | No action is required except keeping temp_state up to date | |
3818 | so that we reload when needed. */ | |
3819 | for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { | |
b83eabea | 3820 | arg_ts = arg_temp(op->args[i]); |
39004a71 RH |
3821 | dir_ts = arg_ts->state_ptr; |
3822 | if (dir_ts) { | |
3823 | op->args[i] = temp_arg(dir_ts); | |
3824 | changes = true; | |
3825 | if (IS_DEAD_ARG(i)) { | |
3826 | arg_ts->state = TS_DEAD; | |
5a18407f RH |
3827 | } |
3828 | } | |
3829 | } | |
3830 | ||
3831 | /* Liveness analysis should ensure that the following are | |
3832 | all correct, for call sites and basic block end points. */ | |
3833 | if (call_flags & TCG_CALL_NO_READ_GLOBALS) { | |
3834 | /* Nothing to do */ | |
3835 | } else if (call_flags & TCG_CALL_NO_WRITE_GLOBALS) { | |
3836 | for (i = 0; i < nb_globals; ++i) { | |
3837 | /* Liveness should see that globals are synced back, | |
3838 | that is, either TS_DEAD or TS_MEM. */ | |
b83eabea RH |
3839 | arg_ts = &s->temps[i]; |
3840 | tcg_debug_assert(arg_ts->state_ptr == 0 | |
3841 | || arg_ts->state != 0); | |
5a18407f RH |
3842 | } |
3843 | } else { | |
3844 | for (i = 0; i < nb_globals; ++i) { | |
3845 | /* Liveness should see that globals are saved back, | |
3846 | that is, TS_DEAD, waiting to be reloaded. */ | |
b83eabea RH |
3847 | arg_ts = &s->temps[i]; |
3848 | tcg_debug_assert(arg_ts->state_ptr == 0 | |
3849 | || arg_ts->state == TS_DEAD); | |
5a18407f RH |
3850 | } |
3851 | } | |
3852 | ||
3853 | /* Outputs become available. */ | |
61f15c48 RH |
3854 | if (opc == INDEX_op_mov_i32 || opc == INDEX_op_mov_i64) { |
3855 | arg_ts = arg_temp(op->args[0]); | |
b83eabea | 3856 | dir_ts = arg_ts->state_ptr; |
61f15c48 RH |
3857 | if (dir_ts) { |
3858 | op->args[0] = temp_arg(dir_ts); | |
3859 | changes = true; | |
3860 | ||
3861 | /* The output is now live and modified. */ | |
3862 | arg_ts->state = 0; | |
3863 | ||
3864 | if (NEED_SYNC_ARG(0)) { | |
3865 | TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 | |
3866 | ? INDEX_op_st_i32 | |
3867 | : INDEX_op_st_i64); | |
d4478943 | 3868 | TCGOp *sop = tcg_op_insert_after(s, op, sopc, 3); |
61f15c48 RH |
3869 | TCGTemp *out_ts = dir_ts; |
3870 | ||
3871 | if (IS_DEAD_ARG(0)) { | |
3872 | out_ts = arg_temp(op->args[1]); | |
3873 | arg_ts->state = TS_DEAD; | |
3874 | tcg_op_remove(s, op); | |
3875 | } else { | |
3876 | arg_ts->state = TS_MEM; | |
3877 | } | |
3878 | ||
3879 | sop->args[0] = temp_arg(out_ts); | |
3880 | sop->args[1] = temp_arg(arg_ts->mem_base); | |
3881 | sop->args[2] = arg_ts->mem_offset; | |
3882 | } else { | |
3883 | tcg_debug_assert(!IS_DEAD_ARG(0)); | |
3884 | } | |
5a18407f | 3885 | } |
61f15c48 RH |
3886 | } else { |
3887 | for (i = 0; i < nb_oargs; i++) { | |
3888 | arg_ts = arg_temp(op->args[i]); | |
3889 | dir_ts = arg_ts->state_ptr; | |
3890 | if (!dir_ts) { | |
3891 | continue; | |
3892 | } | |
3893 | op->args[i] = temp_arg(dir_ts); | |
3894 | changes = true; | |
5a18407f | 3895 | |
61f15c48 RH |
3896 | /* The output is now live and modified. */ |
3897 | arg_ts->state = 0; | |
5a18407f | 3898 | |
61f15c48 RH |
3899 | /* Sync outputs upon their last write. */ |
3900 | if (NEED_SYNC_ARG(i)) { | |
3901 | TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 | |
3902 | ? INDEX_op_st_i32 | |
3903 | : INDEX_op_st_i64); | |
d4478943 | 3904 | TCGOp *sop = tcg_op_insert_after(s, op, sopc, 3); |
5a18407f | 3905 | |
61f15c48 RH |
3906 | sop->args[0] = temp_arg(dir_ts); |
3907 | sop->args[1] = temp_arg(arg_ts->mem_base); | |
3908 | sop->args[2] = arg_ts->mem_offset; | |
5a18407f | 3909 | |
61f15c48 RH |
3910 | arg_ts->state = TS_MEM; |
3911 | } | |
3912 | /* Drop outputs that are dead. */ | |
3913 | if (IS_DEAD_ARG(i)) { | |
3914 | arg_ts->state = TS_DEAD; | |
3915 | } | |
5a18407f RH |
3916 | } |
3917 | } | |
3918 | } | |
3919 | ||
3920 | return changes; | |
3921 | } | |
3922 | ||
2272e4a7 | 3923 | static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) |
c896fe29 | 3924 | { |
31c96417 | 3925 | intptr_t off; |
273eb50c | 3926 | int size, align; |
c1c09194 | 3927 | |
273eb50c RH |
3928 | /* When allocating an object, look at the full type. */ |
3929 | size = tcg_type_size(ts->base_type); | |
3930 | switch (ts->base_type) { | |
c1c09194 | 3931 | case TCG_TYPE_I32: |
31c96417 | 3932 | align = 4; |
c1c09194 RH |
3933 | break; |
3934 | case TCG_TYPE_I64: | |
3935 | case TCG_TYPE_V64: | |
31c96417 | 3936 | align = 8; |
c1c09194 | 3937 | break; |
43eef72f | 3938 | case TCG_TYPE_I128: |
c1c09194 | 3939 | case TCG_TYPE_V128: |
c1c09194 | 3940 | case TCG_TYPE_V256: |
43eef72f RH |
3941 | /* |
3942 | * Note that we do not require aligned storage for V256, | |
3943 | * and that we provide alignment for I128 to match V128, | |
3944 | * even if that's above what the host ABI requires. | |
3945 | */ | |
31c96417 | 3946 | align = 16; |
c1c09194 RH |
3947 | break; |
3948 | default: | |
3949 | g_assert_not_reached(); | |
b591dc59 | 3950 | } |
c1c09194 | 3951 | |
b9537d59 RH |
3952 | /* |
3953 | * Assume the stack is sufficiently aligned. | |
3954 | * This affects e.g. ARM NEON, where we have 8 byte stack alignment | |
3955 | * and do not require 16 byte vector alignment. This seems slightly | |
3956 | * easier than fully parameterizing the above switch statement. | |
3957 | */ | |
3958 | align = MIN(TCG_TARGET_STACK_ALIGN, align); | |
c1c09194 | 3959 | off = ROUND_UP(s->current_frame_offset, align); |
732d5897 RH |
3960 | |
3961 | /* If we've exhausted the stack frame, restart with a smaller TB. */ | |
3962 | if (off + size > s->frame_end) { | |
3963 | tcg_raise_tb_overflow(s); | |
3964 | } | |
c1c09194 | 3965 | s->current_frame_offset = off + size; |
9defd1bd | 3966 | #if defined(__sparc__) |
273eb50c | 3967 | off += TCG_TARGET_STACK_BIAS; |
9defd1bd | 3968 | #endif |
273eb50c RH |
3969 | |
3970 | /* If the object was subdivided, assign memory to all the parts. */ | |
3971 | if (ts->base_type != ts->type) { | |
3972 | int part_size = tcg_type_size(ts->type); | |
3973 | int part_count = size / part_size; | |
3974 | ||
3975 | /* | |
3976 | * Each part is allocated sequentially in tcg_temp_new_internal. | |
3977 | * Jump back to the first part by subtracting the current index. | |
3978 | */ | |
3979 | ts -= ts->temp_subindex; | |
3980 | for (int i = 0; i < part_count; ++i) { | |
3981 | ts[i].mem_offset = off + i * part_size; | |
3982 | ts[i].mem_base = s->frame_temp; | |
3983 | ts[i].mem_allocated = 1; | |
3984 | } | |
3985 | } else { | |
3986 | ts->mem_offset = off; | |
3987 | ts->mem_base = s->frame_temp; | |
3988 | ts->mem_allocated = 1; | |
3989 | } | |
c896fe29 FB |
3990 | } |
3991 | ||
098859f1 RH |
3992 | /* Assign @reg to @ts, and update reg_to_temp[]. */ |
3993 | static void set_temp_val_reg(TCGContext *s, TCGTemp *ts, TCGReg reg) | |
3994 | { | |
3995 | if (ts->val_type == TEMP_VAL_REG) { | |
3996 | TCGReg old = ts->reg; | |
3997 | tcg_debug_assert(s->reg_to_temp[old] == ts); | |
3998 | if (old == reg) { | |
3999 | return; | |
4000 | } | |
4001 | s->reg_to_temp[old] = NULL; | |
4002 | } | |
4003 | tcg_debug_assert(s->reg_to_temp[reg] == NULL); | |
4004 | s->reg_to_temp[reg] = ts; | |
4005 | ts->val_type = TEMP_VAL_REG; | |
4006 | ts->reg = reg; | |
4007 | } | |
4008 | ||
4009 | /* Assign a non-register value type to @ts, and update reg_to_temp[]. */ | |
4010 | static void set_temp_val_nonreg(TCGContext *s, TCGTemp *ts, TCGTempVal type) | |
4011 | { | |
4012 | tcg_debug_assert(type != TEMP_VAL_REG); | |
4013 | if (ts->val_type == TEMP_VAL_REG) { | |
4014 | TCGReg reg = ts->reg; | |
4015 | tcg_debug_assert(s->reg_to_temp[reg] == ts); | |
4016 | s->reg_to_temp[reg] = NULL; | |
4017 | } | |
4018 | ts->val_type = type; | |
4019 | } | |
4020 | ||
b722452a | 4021 | static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); |
b3915dbb | 4022 | |
59d7c14e RH |
4023 | /* Mark a temporary as free or dead. If 'free_or_dead' is negative, |
4024 | mark it free; otherwise mark it dead. */ | |
4025 | static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) | |
7f6ceedf | 4026 | { |
c0522136 RH |
4027 | TCGTempVal new_type; |
4028 | ||
4029 | switch (ts->kind) { | |
4030 | case TEMP_FIXED: | |
59d7c14e | 4031 | return; |
c0522136 | 4032 | case TEMP_GLOBAL: |
f57c6915 | 4033 | case TEMP_TB: |
c0522136 RH |
4034 | new_type = TEMP_VAL_MEM; |
4035 | break; | |
c7482438 | 4036 | case TEMP_EBB: |
c0522136 RH |
4037 | new_type = free_or_dead < 0 ? TEMP_VAL_MEM : TEMP_VAL_DEAD; |
4038 | break; | |
4039 | case TEMP_CONST: | |
4040 | new_type = TEMP_VAL_CONST; | |
4041 | break; | |
4042 | default: | |
4043 | g_assert_not_reached(); | |
59d7c14e | 4044 | } |
098859f1 | 4045 | set_temp_val_nonreg(s, ts, new_type); |
59d7c14e | 4046 | } |
7f6ceedf | 4047 | |
59d7c14e RH |
4048 | /* Mark a temporary as dead. */ |
4049 | static inline void temp_dead(TCGContext *s, TCGTemp *ts) | |
4050 | { | |
4051 | temp_free_or_dead(s, ts, 1); | |
4052 | } | |
4053 | ||
4054 | /* Sync a temporary to memory. 'allocated_regs' is used in case a temporary | |
4055 | registers needs to be allocated to store a constant. If 'free_or_dead' | |
4056 | is non-zero, subsequently release the temporary; if it is positive, the | |
4057 | temp is dead; if it is negative, the temp is free. */ | |
98b4e186 RH |
4058 | static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, |
4059 | TCGRegSet preferred_regs, int free_or_dead) | |
59d7c14e | 4060 | { |
c0522136 | 4061 | if (!temp_readonly(ts) && !ts->mem_coherent) { |
7f6ceedf | 4062 | if (!ts->mem_allocated) { |
2272e4a7 | 4063 | temp_allocate_frame(s, ts); |
59d7c14e | 4064 | } |
59d7c14e RH |
4065 | switch (ts->val_type) { |
4066 | case TEMP_VAL_CONST: | |
4067 | /* If we're going to free the temp immediately, then we won't | |
4068 | require it later in a register, so attempt to store the | |
4069 | constant to memory directly. */ | |
4070 | if (free_or_dead | |
4071 | && tcg_out_sti(s, ts->type, ts->val, | |
4072 | ts->mem_base->reg, ts->mem_offset)) { | |
4073 | break; | |
4074 | } | |
4075 | temp_load(s, ts, tcg_target_available_regs[ts->type], | |
98b4e186 | 4076 | allocated_regs, preferred_regs); |
59d7c14e RH |
4077 | /* fallthrough */ |
4078 | ||
4079 | case TEMP_VAL_REG: | |
4080 | tcg_out_st(s, ts->type, ts->reg, | |
4081 | ts->mem_base->reg, ts->mem_offset); | |
4082 | break; | |
4083 | ||
4084 | case TEMP_VAL_MEM: | |
4085 | break; | |
4086 | ||
4087 | case TEMP_VAL_DEAD: | |
4088 | default: | |
732e89f4 | 4089 | g_assert_not_reached(); |
59d7c14e RH |
4090 | } |
4091 | ts->mem_coherent = 1; | |
4092 | } | |
4093 | if (free_or_dead) { | |
4094 | temp_free_or_dead(s, ts, free_or_dead); | |
7f6ceedf | 4095 | } |
7f6ceedf AJ |
4096 | } |
4097 | ||
c896fe29 | 4098 | /* free register 'reg' by spilling the corresponding temporary if necessary */ |
b3915dbb | 4099 | static void tcg_reg_free(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs) |
c896fe29 | 4100 | { |
f8b2f202 | 4101 | TCGTemp *ts = s->reg_to_temp[reg]; |
f8b2f202 | 4102 | if (ts != NULL) { |
98b4e186 | 4103 | temp_sync(s, ts, allocated_regs, 0, -1); |
c896fe29 FB |
4104 | } |
4105 | } | |
4106 | ||
b016486e RH |
4107 | /** |
4108 | * tcg_reg_alloc: | |
4109 | * @required_regs: Set of registers in which we must allocate. | |
4110 | * @allocated_regs: Set of registers which must be avoided. | |
4111 | * @preferred_regs: Set of registers we should prefer. | |
4112 | * @rev: True if we search the registers in "indirect" order. | |
4113 | * | |
4114 | * The allocated register must be in @required_regs & ~@allocated_regs, | |
4115 | * but if we can put it in @preferred_regs we may save a move later. | |
4116 | */ | |
4117 | static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet required_regs, | |
4118 | TCGRegSet allocated_regs, | |
4119 | TCGRegSet preferred_regs, bool rev) | |
c896fe29 | 4120 | { |
b016486e RH |
4121 | int i, j, f, n = ARRAY_SIZE(tcg_target_reg_alloc_order); |
4122 | TCGRegSet reg_ct[2]; | |
91478cef | 4123 | const int *order; |
c896fe29 | 4124 | |
b016486e RH |
4125 | reg_ct[1] = required_regs & ~allocated_regs; |
4126 | tcg_debug_assert(reg_ct[1] != 0); | |
4127 | reg_ct[0] = reg_ct[1] & preferred_regs; | |
4128 | ||
4129 | /* Skip the preferred_regs option if it cannot be satisfied, | |
4130 | or if the preference made no difference. */ | |
4131 | f = reg_ct[0] == 0 || reg_ct[0] == reg_ct[1]; | |
4132 | ||
91478cef | 4133 | order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; |
c896fe29 | 4134 | |
b016486e RH |
4135 | /* Try free registers, preferences first. */ |
4136 | for (j = f; j < 2; j++) { | |
4137 | TCGRegSet set = reg_ct[j]; | |
4138 | ||
4139 | if (tcg_regset_single(set)) { | |
4140 | /* One register in the set. */ | |
4141 | TCGReg reg = tcg_regset_first(set); | |
4142 | if (s->reg_to_temp[reg] == NULL) { | |
4143 | return reg; | |
4144 | } | |
4145 | } else { | |
4146 | for (i = 0; i < n; i++) { | |
4147 | TCGReg reg = order[i]; | |
4148 | if (s->reg_to_temp[reg] == NULL && | |
4149 | tcg_regset_test_reg(set, reg)) { | |
4150 | return reg; | |
4151 | } | |
4152 | } | |
4153 | } | |
c896fe29 FB |
4154 | } |
4155 | ||
b016486e RH |
4156 | /* We must spill something. */ |
4157 | for (j = f; j < 2; j++) { | |
4158 | TCGRegSet set = reg_ct[j]; | |
4159 | ||
4160 | if (tcg_regset_single(set)) { | |
4161 | /* One register in the set. */ | |
4162 | TCGReg reg = tcg_regset_first(set); | |
b3915dbb | 4163 | tcg_reg_free(s, reg, allocated_regs); |
c896fe29 | 4164 | return reg; |
b016486e RH |
4165 | } else { |
4166 | for (i = 0; i < n; i++) { | |
4167 | TCGReg reg = order[i]; | |
4168 | if (tcg_regset_test_reg(set, reg)) { | |
4169 | tcg_reg_free(s, reg, allocated_regs); | |
4170 | return reg; | |
4171 | } | |
4172 | } | |
c896fe29 FB |
4173 | } |
4174 | } | |
4175 | ||
732e89f4 | 4176 | g_assert_not_reached(); |
c896fe29 FB |
4177 | } |
4178 | ||
29f5e925 RH |
4179 | static TCGReg tcg_reg_alloc_pair(TCGContext *s, TCGRegSet required_regs, |
4180 | TCGRegSet allocated_regs, | |
4181 | TCGRegSet preferred_regs, bool rev) | |
4182 | { | |
4183 | int i, j, k, fmin, n = ARRAY_SIZE(tcg_target_reg_alloc_order); | |
4184 | TCGRegSet reg_ct[2]; | |
4185 | const int *order; | |
4186 | ||
4187 | /* Ensure that if I is not in allocated_regs, I+1 is not either. */ | |
4188 | reg_ct[1] = required_regs & ~(allocated_regs | (allocated_regs >> 1)); | |
4189 | tcg_debug_assert(reg_ct[1] != 0); | |
4190 | reg_ct[0] = reg_ct[1] & preferred_regs; | |
4191 | ||
4192 | order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; | |
4193 | ||
4194 | /* | |
4195 | * Skip the preferred_regs option if it cannot be satisfied, | |
4196 | * or if the preference made no difference. | |
4197 | */ | |
4198 | k = reg_ct[0] == 0 || reg_ct[0] == reg_ct[1]; | |
4199 | ||
4200 | /* | |
4201 | * Minimize the number of flushes by looking for 2 free registers first, | |
4202 | * then a single flush, then two flushes. | |
4203 | */ | |
4204 | for (fmin = 2; fmin >= 0; fmin--) { | |
4205 | for (j = k; j < 2; j++) { | |
4206 | TCGRegSet set = reg_ct[j]; | |
4207 | ||
4208 | for (i = 0; i < n; i++) { | |
4209 | TCGReg reg = order[i]; | |
4210 | ||
4211 | if (tcg_regset_test_reg(set, reg)) { | |
4212 | int f = !s->reg_to_temp[reg] + !s->reg_to_temp[reg + 1]; | |
4213 | if (f >= fmin) { | |
4214 | tcg_reg_free(s, reg, allocated_regs); | |
4215 | tcg_reg_free(s, reg + 1, allocated_regs); | |
4216 | return reg; | |
4217 | } | |
4218 | } | |
4219 | } | |
4220 | } | |
4221 | } | |
732e89f4 | 4222 | g_assert_not_reached(); |
29f5e925 RH |
4223 | } |
4224 | ||
40ae5c62 RH |
4225 | /* Make sure the temporary is in a register. If needed, allocate the register |
4226 | from DESIRED while avoiding ALLOCATED. */ | |
4227 | static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, | |
b722452a | 4228 | TCGRegSet allocated_regs, TCGRegSet preferred_regs) |
40ae5c62 RH |
4229 | { |
4230 | TCGReg reg; | |
4231 | ||
4232 | switch (ts->val_type) { | |
4233 | case TEMP_VAL_REG: | |
4234 | return; | |
4235 | case TEMP_VAL_CONST: | |
b016486e | 4236 | reg = tcg_reg_alloc(s, desired_regs, allocated_regs, |
b722452a | 4237 | preferred_regs, ts->indirect_base); |
0a6a8bc8 RH |
4238 | if (ts->type <= TCG_TYPE_I64) { |
4239 | tcg_out_movi(s, ts->type, reg, ts->val); | |
4240 | } else { | |
4e186175 RH |
4241 | uint64_t val = ts->val; |
4242 | MemOp vece = MO_64; | |
4243 | ||
4244 | /* | |
4245 | * Find the minimal vector element that matches the constant. | |
4246 | * The targets will, in general, have to do this search anyway, | |
4247 | * do this generically. | |
4248 | */ | |
4e186175 RH |
4249 | if (val == dup_const(MO_8, val)) { |
4250 | vece = MO_8; | |
4251 | } else if (val == dup_const(MO_16, val)) { | |
4252 | vece = MO_16; | |
0b4286dd | 4253 | } else if (val == dup_const(MO_32, val)) { |
4e186175 RH |
4254 | vece = MO_32; |
4255 | } | |
4256 | ||
4257 | tcg_out_dupi_vec(s, ts->type, vece, reg, ts->val); | |
0a6a8bc8 | 4258 | } |
40ae5c62 RH |
4259 | ts->mem_coherent = 0; |
4260 | break; | |
4261 | case TEMP_VAL_MEM: | |
b016486e | 4262 | reg = tcg_reg_alloc(s, desired_regs, allocated_regs, |
b722452a | 4263 | preferred_regs, ts->indirect_base); |
40ae5c62 RH |
4264 | tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); |
4265 | ts->mem_coherent = 1; | |
4266 | break; | |
4267 | case TEMP_VAL_DEAD: | |
4268 | default: | |
732e89f4 | 4269 | g_assert_not_reached(); |
40ae5c62 | 4270 | } |
098859f1 | 4271 | set_temp_val_reg(s, ts, reg); |
40ae5c62 RH |
4272 | } |
4273 | ||
59d7c14e RH |
4274 | /* Save a temporary to memory. 'allocated_regs' is used in case a |
4275 | temporary registers needs to be allocated to store a constant. */ | |
4276 | static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs) | |
1ad80729 | 4277 | { |
5a18407f RH |
4278 | /* The liveness analysis already ensures that globals are back |
4279 | in memory. Keep an tcg_debug_assert for safety. */ | |
e01fa97d | 4280 | tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || temp_readonly(ts)); |
1ad80729 AJ |
4281 | } |
4282 | ||
9814dd27 | 4283 | /* save globals to their canonical location and assume they can be |
e8996ee0 FB |
4284 | modified be the following code. 'allocated_regs' is used in case a |
4285 | temporary registers needs to be allocated to store a constant. */ | |
4286 | static void save_globals(TCGContext *s, TCGRegSet allocated_regs) | |
c896fe29 | 4287 | { |
ac3b8891 | 4288 | int i, n; |
c896fe29 | 4289 | |
ac3b8891 | 4290 | for (i = 0, n = s->nb_globals; i < n; i++) { |
b13eb728 | 4291 | temp_save(s, &s->temps[i], allocated_regs); |
c896fe29 | 4292 | } |
e5097dc8 FB |
4293 | } |
4294 | ||
3d5c5f87 AJ |
4295 | /* sync globals to their canonical location and assume they can be |
4296 | read by the following code. 'allocated_regs' is used in case a | |
4297 | temporary registers needs to be allocated to store a constant. */ | |
4298 | static void sync_globals(TCGContext *s, TCGRegSet allocated_regs) | |
4299 | { | |
ac3b8891 | 4300 | int i, n; |
3d5c5f87 | 4301 | |
ac3b8891 | 4302 | for (i = 0, n = s->nb_globals; i < n; i++) { |
12b9b11a | 4303 | TCGTemp *ts = &s->temps[i]; |
5a18407f | 4304 | tcg_debug_assert(ts->val_type != TEMP_VAL_REG |
ee17db83 | 4305 | || ts->kind == TEMP_FIXED |
5a18407f | 4306 | || ts->mem_coherent); |
3d5c5f87 AJ |
4307 | } |
4308 | } | |
4309 | ||
e5097dc8 | 4310 | /* at the end of a basic block, we assume all temporaries are dead and |
e8996ee0 FB |
4311 | all globals are stored at their canonical location. */ |
4312 | static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) | |
e5097dc8 | 4313 | { |
e5097dc8 FB |
4314 | int i; |
4315 | ||
b13eb728 RH |
4316 | for (i = s->nb_globals; i < s->nb_temps; i++) { |
4317 | TCGTemp *ts = &s->temps[i]; | |
c0522136 RH |
4318 | |
4319 | switch (ts->kind) { | |
f57c6915 | 4320 | case TEMP_TB: |
b13eb728 | 4321 | temp_save(s, ts, allocated_regs); |
c0522136 | 4322 | break; |
c7482438 | 4323 | case TEMP_EBB: |
5a18407f RH |
4324 | /* The liveness analysis already ensures that temps are dead. |
4325 | Keep an tcg_debug_assert for safety. */ | |
4326 | tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD); | |
c0522136 RH |
4327 | break; |
4328 | case TEMP_CONST: | |
4329 | /* Similarly, we should have freed any allocated register. */ | |
4330 | tcg_debug_assert(ts->val_type == TEMP_VAL_CONST); | |
4331 | break; | |
4332 | default: | |
4333 | g_assert_not_reached(); | |
c896fe29 FB |
4334 | } |
4335 | } | |
e8996ee0 FB |
4336 | |
4337 | save_globals(s, allocated_regs); | |
c896fe29 FB |
4338 | } |
4339 | ||
b4cb76e6 | 4340 | /* |
c7482438 RH |
4341 | * At a conditional branch, we assume all temporaries are dead unless |
4342 | * explicitly live-across-conditional-branch; all globals and local | |
4343 | * temps are synced to their location. | |
b4cb76e6 RH |
4344 | */ |
4345 | static void tcg_reg_alloc_cbranch(TCGContext *s, TCGRegSet allocated_regs) | |
4346 | { | |
4347 | sync_globals(s, allocated_regs); | |
4348 | ||
4349 | for (int i = s->nb_globals; i < s->nb_temps; i++) { | |
4350 | TCGTemp *ts = &s->temps[i]; | |
4351 | /* | |
4352 | * The liveness analysis already ensures that temps are dead. | |
4353 | * Keep tcg_debug_asserts for safety. | |
4354 | */ | |
c0522136 | 4355 | switch (ts->kind) { |
f57c6915 | 4356 | case TEMP_TB: |
b4cb76e6 | 4357 | tcg_debug_assert(ts->val_type != TEMP_VAL_REG || ts->mem_coherent); |
c0522136 | 4358 | break; |
c7482438 | 4359 | case TEMP_EBB: |
c0522136 RH |
4360 | case TEMP_CONST: |
4361 | break; | |
4362 | default: | |
4363 | g_assert_not_reached(); | |
b4cb76e6 RH |
4364 | } |
4365 | } | |
4366 | } | |
4367 | ||
bab1671f | 4368 | /* |
c58f4c97 | 4369 | * Specialized code generation for INDEX_op_mov_* with a constant. |
bab1671f | 4370 | */ |
0fe4fca4 | 4371 | static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, |
ba87719c RH |
4372 | tcg_target_ulong val, TCGLifeData arg_life, |
4373 | TCGRegSet preferred_regs) | |
e8996ee0 | 4374 | { |
d63e3b6e | 4375 | /* ENV should not be modified. */ |
e01fa97d | 4376 | tcg_debug_assert(!temp_readonly(ots)); |
59d7c14e RH |
4377 | |
4378 | /* The movi is not explicitly generated here. */ | |
098859f1 | 4379 | set_temp_val_nonreg(s, ots, TEMP_VAL_CONST); |
59d7c14e RH |
4380 | ots->val = val; |
4381 | ots->mem_coherent = 0; | |
4382 | if (NEED_SYNC_ARG(0)) { | |
ba87719c | 4383 | temp_sync(s, ots, s->reserved_regs, preferred_regs, IS_DEAD_ARG(0)); |
59d7c14e | 4384 | } else if (IS_DEAD_ARG(0)) { |
f8bf00f1 | 4385 | temp_dead(s, ots); |
4c4e1ab2 | 4386 | } |
e8996ee0 FB |
4387 | } |
4388 | ||
bab1671f RH |
4389 | /* |
4390 | * Specialized code generation for INDEX_op_mov_*. | |
4391 | */ | |
dd186292 | 4392 | static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) |
c896fe29 | 4393 | { |
dd186292 | 4394 | const TCGLifeData arg_life = op->life; |
69e3706d | 4395 | TCGRegSet allocated_regs, preferred_regs; |
c896fe29 | 4396 | TCGTemp *ts, *ots; |
450445d5 | 4397 | TCGType otype, itype; |
098859f1 | 4398 | TCGReg oreg, ireg; |
c896fe29 | 4399 | |
d21369f5 | 4400 | allocated_regs = s->reserved_regs; |
31fd884b | 4401 | preferred_regs = output_pref(op, 0); |
43439139 RH |
4402 | ots = arg_temp(op->args[0]); |
4403 | ts = arg_temp(op->args[1]); | |
450445d5 | 4404 | |
d63e3b6e | 4405 | /* ENV should not be modified. */ |
e01fa97d | 4406 | tcg_debug_assert(!temp_readonly(ots)); |
d63e3b6e | 4407 | |
450445d5 RH |
4408 | /* Note that otype != itype for no-op truncation. */ |
4409 | otype = ots->type; | |
4410 | itype = ts->type; | |
c29c1d7e | 4411 | |
0fe4fca4 PB |
4412 | if (ts->val_type == TEMP_VAL_CONST) { |
4413 | /* propagate constant or generate sti */ | |
4414 | tcg_target_ulong val = ts->val; | |
4415 | if (IS_DEAD_ARG(1)) { | |
4416 | temp_dead(s, ts); | |
4417 | } | |
69e3706d | 4418 | tcg_reg_alloc_do_movi(s, ots, val, arg_life, preferred_regs); |
0fe4fca4 PB |
4419 | return; |
4420 | } | |
4421 | ||
4422 | /* If the source value is in memory we're going to be forced | |
4423 | to have it in a register in order to perform the copy. Copy | |
4424 | the SOURCE value into its own register first, that way we | |
4425 | don't have to reload SOURCE the next time it is used. */ | |
4426 | if (ts->val_type == TEMP_VAL_MEM) { | |
69e3706d RH |
4427 | temp_load(s, ts, tcg_target_available_regs[itype], |
4428 | allocated_regs, preferred_regs); | |
c29c1d7e | 4429 | } |
0fe4fca4 | 4430 | tcg_debug_assert(ts->val_type == TEMP_VAL_REG); |
098859f1 RH |
4431 | ireg = ts->reg; |
4432 | ||
d63e3b6e | 4433 | if (IS_DEAD_ARG(0)) { |
c29c1d7e AJ |
4434 | /* mov to a non-saved dead register makes no sense (even with |
4435 | liveness analysis disabled). */ | |
eabb7b91 | 4436 | tcg_debug_assert(NEED_SYNC_ARG(0)); |
c29c1d7e | 4437 | if (!ots->mem_allocated) { |
2272e4a7 | 4438 | temp_allocate_frame(s, ots); |
c29c1d7e | 4439 | } |
098859f1 | 4440 | tcg_out_st(s, otype, ireg, ots->mem_base->reg, ots->mem_offset); |
c29c1d7e | 4441 | if (IS_DEAD_ARG(1)) { |
f8bf00f1 | 4442 | temp_dead(s, ts); |
c29c1d7e | 4443 | } |
f8bf00f1 | 4444 | temp_dead(s, ots); |
098859f1 RH |
4445 | return; |
4446 | } | |
4447 | ||
4448 | if (IS_DEAD_ARG(1) && ts->kind != TEMP_FIXED) { | |
4449 | /* | |
4450 | * The mov can be suppressed. Kill input first, so that it | |
4451 | * is unlinked from reg_to_temp, then set the output to the | |
4452 | * reg that we saved from the input. | |
4453 | */ | |
4454 | temp_dead(s, ts); | |
4455 | oreg = ireg; | |
c29c1d7e | 4456 | } else { |
098859f1 RH |
4457 | if (ots->val_type == TEMP_VAL_REG) { |
4458 | oreg = ots->reg; | |
c896fe29 | 4459 | } else { |
098859f1 RH |
4460 | /* Make sure to not spill the input register during allocation. */ |
4461 | oreg = tcg_reg_alloc(s, tcg_target_available_regs[otype], | |
4462 | allocated_regs | ((TCGRegSet)1 << ireg), | |
4463 | preferred_regs, ots->indirect_base); | |
c896fe29 | 4464 | } |
098859f1 RH |
4465 | if (!tcg_out_mov(s, otype, oreg, ireg)) { |
4466 | /* | |
4467 | * Cross register class move not supported. | |
4468 | * Store the source register into the destination slot | |
4469 | * and leave the destination temp as TEMP_VAL_MEM. | |
4470 | */ | |
4471 | assert(!temp_readonly(ots)); | |
4472 | if (!ts->mem_allocated) { | |
4473 | temp_allocate_frame(s, ots); | |
4474 | } | |
4475 | tcg_out_st(s, ts->type, ireg, ots->mem_base->reg, ots->mem_offset); | |
4476 | set_temp_val_nonreg(s, ts, TEMP_VAL_MEM); | |
4477 | ots->mem_coherent = 1; | |
4478 | return; | |
c896fe29 | 4479 | } |
ec7a869d | 4480 | } |
098859f1 RH |
4481 | set_temp_val_reg(s, ots, oreg); |
4482 | ots->mem_coherent = 0; | |
4483 | ||
4484 | if (NEED_SYNC_ARG(0)) { | |
4485 | temp_sync(s, ots, allocated_regs, 0, 0); | |
4486 | } | |
c896fe29 FB |
4487 | } |
4488 | ||
bab1671f RH |
4489 | /* |
4490 | * Specialized code generation for INDEX_op_dup_vec. | |
4491 | */ | |
4492 | static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) | |
4493 | { | |
4494 | const TCGLifeData arg_life = op->life; | |
4495 | TCGRegSet dup_out_regs, dup_in_regs; | |
4496 | TCGTemp *its, *ots; | |
4497 | TCGType itype, vtype; | |
4498 | unsigned vece; | |
31c96417 | 4499 | int lowpart_ofs; |
bab1671f RH |
4500 | bool ok; |
4501 | ||
4502 | ots = arg_temp(op->args[0]); | |
4503 | its = arg_temp(op->args[1]); | |
4504 | ||
4505 | /* ENV should not be modified. */ | |
e01fa97d | 4506 | tcg_debug_assert(!temp_readonly(ots)); |
bab1671f RH |
4507 | |
4508 | itype = its->type; | |
4509 | vece = TCGOP_VECE(op); | |
4510 | vtype = TCGOP_VECL(op) + TCG_TYPE_V64; | |
4511 | ||
4512 | if (its->val_type == TEMP_VAL_CONST) { | |
4513 | /* Propagate constant via movi -> dupi. */ | |
4514 | tcg_target_ulong val = its->val; | |
4515 | if (IS_DEAD_ARG(1)) { | |
4516 | temp_dead(s, its); | |
4517 | } | |
31fd884b | 4518 | tcg_reg_alloc_do_movi(s, ots, val, arg_life, output_pref(op, 0)); |
bab1671f RH |
4519 | return; |
4520 | } | |
4521 | ||
9be0d080 RH |
4522 | dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs; |
4523 | dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs; | |
bab1671f RH |
4524 | |
4525 | /* Allocate the output register now. */ | |
4526 | if (ots->val_type != TEMP_VAL_REG) { | |
4527 | TCGRegSet allocated_regs = s->reserved_regs; | |
098859f1 | 4528 | TCGReg oreg; |
bab1671f RH |
4529 | |
4530 | if (!IS_DEAD_ARG(1) && its->val_type == TEMP_VAL_REG) { | |
4531 | /* Make sure to not spill the input register. */ | |
4532 | tcg_regset_set_reg(allocated_regs, its->reg); | |
4533 | } | |
098859f1 | 4534 | oreg = tcg_reg_alloc(s, dup_out_regs, allocated_regs, |
31fd884b | 4535 | output_pref(op, 0), ots->indirect_base); |
098859f1 | 4536 | set_temp_val_reg(s, ots, oreg); |
bab1671f RH |
4537 | } |
4538 | ||
4539 | switch (its->val_type) { | |
4540 | case TEMP_VAL_REG: | |
4541 | /* | |
4542 | * The dup constriaints must be broad, covering all possible VECE. | |
4543 | * However, tcg_op_dup_vec() gets to see the VECE and we allow it | |
4544 | * to fail, indicating that extra moves are required for that case. | |
4545 | */ | |
4546 | if (tcg_regset_test_reg(dup_in_regs, its->reg)) { | |
4547 | if (tcg_out_dup_vec(s, vtype, vece, ots->reg, its->reg)) { | |
4548 | goto done; | |
4549 | } | |
4550 | /* Try again from memory or a vector input register. */ | |
4551 | } | |
4552 | if (!its->mem_coherent) { | |
4553 | /* | |
4554 | * The input register is not synced, and so an extra store | |
4555 | * would be required to use memory. Attempt an integer-vector | |
4556 | * register move first. We do not have a TCGRegSet for this. | |
4557 | */ | |
4558 | if (tcg_out_mov(s, itype, ots->reg, its->reg)) { | |
4559 | break; | |
4560 | } | |
4561 | /* Sync the temp back to its slot and load from there. */ | |
4562 | temp_sync(s, its, s->reserved_regs, 0, 0); | |
4563 | } | |
4564 | /* fall through */ | |
4565 | ||
4566 | case TEMP_VAL_MEM: | |
31c96417 RH |
4567 | lowpart_ofs = 0; |
4568 | if (HOST_BIG_ENDIAN) { | |
4569 | lowpart_ofs = tcg_type_size(itype) - (1 << vece); | |
4570 | } | |
d6ecb4a9 | 4571 | if (tcg_out_dupm_vec(s, vtype, vece, ots->reg, its->mem_base->reg, |
31c96417 | 4572 | its->mem_offset + lowpart_ofs)) { |
d6ecb4a9 RH |
4573 | goto done; |
4574 | } | |
098859f1 | 4575 | /* Load the input into the destination vector register. */ |
bab1671f RH |
4576 | tcg_out_ld(s, itype, ots->reg, its->mem_base->reg, its->mem_offset); |
4577 | break; | |
4578 | ||
4579 | default: | |
4580 | g_assert_not_reached(); | |
4581 | } | |
4582 | ||
4583 | /* We now have a vector input register, so dup must succeed. */ | |
4584 | ok = tcg_out_dup_vec(s, vtype, vece, ots->reg, ots->reg); | |
4585 | tcg_debug_assert(ok); | |
4586 | ||
4587 | done: | |
36f5539c | 4588 | ots->mem_coherent = 0; |
bab1671f RH |
4589 | if (IS_DEAD_ARG(1)) { |
4590 | temp_dead(s, its); | |
4591 | } | |
4592 | if (NEED_SYNC_ARG(0)) { | |
4593 | temp_sync(s, ots, s->reserved_regs, 0, 0); | |
4594 | } | |
4595 | if (IS_DEAD_ARG(0)) { | |
4596 | temp_dead(s, ots); | |
4597 | } | |
4598 | } | |
4599 | ||
dd186292 | 4600 | static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) |
c896fe29 | 4601 | { |
dd186292 RH |
4602 | const TCGLifeData arg_life = op->life; |
4603 | const TCGOpDef * const def = &tcg_op_defs[op->opc]; | |
82790a87 RH |
4604 | TCGRegSet i_allocated_regs; |
4605 | TCGRegSet o_allocated_regs; | |
b6638662 RH |
4606 | int i, k, nb_iargs, nb_oargs; |
4607 | TCGReg reg; | |
c896fe29 FB |
4608 | TCGArg arg; |
4609 | const TCGArgConstraint *arg_ct; | |
4610 | TCGTemp *ts; | |
4611 | TCGArg new_args[TCG_MAX_OP_ARGS]; | |
4612 | int const_args[TCG_MAX_OP_ARGS]; | |
4613 | ||
4614 | nb_oargs = def->nb_oargs; | |
4615 | nb_iargs = def->nb_iargs; | |
4616 | ||
4617 | /* copy constants */ | |
a813e36f | 4618 | memcpy(new_args + nb_oargs + nb_iargs, |
dd186292 | 4619 | op->args + nb_oargs + nb_iargs, |
c896fe29 FB |
4620 | sizeof(TCGArg) * def->nb_cargs); |
4621 | ||
d21369f5 RH |
4622 | i_allocated_regs = s->reserved_regs; |
4623 | o_allocated_regs = s->reserved_regs; | |
82790a87 | 4624 | |
a813e36f | 4625 | /* satisfy input constraints */ |
dd186292 | 4626 | for (k = 0; k < nb_iargs; k++) { |
29f5e925 RH |
4627 | TCGRegSet i_preferred_regs, i_required_regs; |
4628 | bool allocate_new_reg, copyto_new_reg; | |
4629 | TCGTemp *ts2; | |
4630 | int i1, i2; | |
d62816f2 | 4631 | |
66792f90 | 4632 | i = def->args_ct[nb_oargs + k].sort_index; |
dd186292 | 4633 | arg = op->args[i]; |
c896fe29 | 4634 | arg_ct = &def->args_ct[i]; |
43439139 | 4635 | ts = arg_temp(arg); |
40ae5c62 RH |
4636 | |
4637 | if (ts->val_type == TEMP_VAL_CONST | |
a4fbbd77 | 4638 | && tcg_target_const_match(ts->val, ts->type, arg_ct->ct)) { |
40ae5c62 RH |
4639 | /* constant is OK for instruction */ |
4640 | const_args[i] = 1; | |
4641 | new_args[i] = ts->val; | |
d62816f2 | 4642 | continue; |
c896fe29 | 4643 | } |
40ae5c62 | 4644 | |
1c1824dc RH |
4645 | reg = ts->reg; |
4646 | i_preferred_regs = 0; | |
29f5e925 | 4647 | i_required_regs = arg_ct->regs; |
1c1824dc | 4648 | allocate_new_reg = false; |
29f5e925 RH |
4649 | copyto_new_reg = false; |
4650 | ||
4651 | switch (arg_ct->pair) { | |
4652 | case 0: /* not paired */ | |
4653 | if (arg_ct->ialias) { | |
31fd884b | 4654 | i_preferred_regs = output_pref(op, arg_ct->alias_index); |
29f5e925 RH |
4655 | |
4656 | /* | |
4657 | * If the input is readonly, then it cannot also be an | |
4658 | * output and aliased to itself. If the input is not | |
4659 | * dead after the instruction, we must allocate a new | |
4660 | * register and move it. | |
4661 | */ | |
4662 | if (temp_readonly(ts) || !IS_DEAD_ARG(i)) { | |
4663 | allocate_new_reg = true; | |
4664 | } else if (ts->val_type == TEMP_VAL_REG) { | |
4665 | /* | |
4666 | * Check if the current register has already been | |
4667 | * allocated for another input. | |
4668 | */ | |
4669 | allocate_new_reg = | |
4670 | tcg_regset_test_reg(i_allocated_regs, reg); | |
4671 | } | |
4672 | } | |
4673 | if (!allocate_new_reg) { | |
4674 | temp_load(s, ts, i_required_regs, i_allocated_regs, | |
4675 | i_preferred_regs); | |
4676 | reg = ts->reg; | |
4677 | allocate_new_reg = !tcg_regset_test_reg(i_required_regs, reg); | |
4678 | } | |
4679 | if (allocate_new_reg) { | |
4680 | /* | |
4681 | * Allocate a new register matching the constraint | |
4682 | * and move the temporary register into it. | |
4683 | */ | |
4684 | temp_load(s, ts, tcg_target_available_regs[ts->type], | |
4685 | i_allocated_regs, 0); | |
4686 | reg = tcg_reg_alloc(s, i_required_regs, i_allocated_regs, | |
4687 | i_preferred_regs, ts->indirect_base); | |
4688 | copyto_new_reg = true; | |
4689 | } | |
4690 | break; | |
4691 | ||
4692 | case 1: | |
4693 | /* First of an input pair; if i1 == i2, the second is an output. */ | |
4694 | i1 = i; | |
4695 | i2 = arg_ct->pair_index; | |
4696 | ts2 = i1 != i2 ? arg_temp(op->args[i2]) : NULL; | |
4697 | ||
4698 | /* | |
4699 | * It is easier to default to allocating a new pair | |
4700 | * and to identify a few cases where it's not required. | |
4701 | */ | |
4702 | if (arg_ct->ialias) { | |
31fd884b | 4703 | i_preferred_regs = output_pref(op, arg_ct->alias_index); |
29f5e925 RH |
4704 | if (IS_DEAD_ARG(i1) && |
4705 | IS_DEAD_ARG(i2) && | |
4706 | !temp_readonly(ts) && | |
4707 | ts->val_type == TEMP_VAL_REG && | |
4708 | ts->reg < TCG_TARGET_NB_REGS - 1 && | |
4709 | tcg_regset_test_reg(i_required_regs, reg) && | |
4710 | !tcg_regset_test_reg(i_allocated_regs, reg) && | |
4711 | !tcg_regset_test_reg(i_allocated_regs, reg + 1) && | |
4712 | (ts2 | |
4713 | ? ts2->val_type == TEMP_VAL_REG && | |
4714 | ts2->reg == reg + 1 && | |
4715 | !temp_readonly(ts2) | |
4716 | : s->reg_to_temp[reg + 1] == NULL)) { | |
4717 | break; | |
4718 | } | |
4719 | } else { | |
4720 | /* Without aliasing, the pair must also be an input. */ | |
4721 | tcg_debug_assert(ts2); | |
4722 | if (ts->val_type == TEMP_VAL_REG && | |
4723 | ts2->val_type == TEMP_VAL_REG && | |
4724 | ts2->reg == reg + 1 && | |
4725 | tcg_regset_test_reg(i_required_regs, reg)) { | |
4726 | break; | |
4727 | } | |
4728 | } | |
4729 | reg = tcg_reg_alloc_pair(s, i_required_regs, i_allocated_regs, | |
4730 | 0, ts->indirect_base); | |
4731 | goto do_pair; | |
4732 | ||
4733 | case 2: /* pair second */ | |
4734 | reg = new_args[arg_ct->pair_index] + 1; | |
4735 | goto do_pair; | |
1c1824dc | 4736 | |
29f5e925 RH |
4737 | case 3: /* ialias with second output, no first input */ |
4738 | tcg_debug_assert(arg_ct->ialias); | |
31fd884b | 4739 | i_preferred_regs = output_pref(op, arg_ct->alias_index); |
d62816f2 | 4740 | |
29f5e925 RH |
4741 | if (IS_DEAD_ARG(i) && |
4742 | !temp_readonly(ts) && | |
4743 | ts->val_type == TEMP_VAL_REG && | |
4744 | reg > 0 && | |
4745 | s->reg_to_temp[reg - 1] == NULL && | |
4746 | tcg_regset_test_reg(i_required_regs, reg) && | |
4747 | !tcg_regset_test_reg(i_allocated_regs, reg) && | |
4748 | !tcg_regset_test_reg(i_allocated_regs, reg - 1)) { | |
4749 | tcg_regset_set_reg(i_allocated_regs, reg - 1); | |
4750 | break; | |
4751 | } | |
4752 | reg = tcg_reg_alloc_pair(s, i_required_regs >> 1, | |
4753 | i_allocated_regs, 0, | |
4754 | ts->indirect_base); | |
4755 | tcg_regset_set_reg(i_allocated_regs, reg); | |
4756 | reg += 1; | |
4757 | goto do_pair; | |
4758 | ||
4759 | do_pair: | |
c0522136 | 4760 | /* |
29f5e925 RH |
4761 | * If an aliased input is not dead after the instruction, |
4762 | * we must allocate a new register and move it. | |
c0522136 | 4763 | */ |
29f5e925 RH |
4764 | if (arg_ct->ialias && (!IS_DEAD_ARG(i) || temp_readonly(ts))) { |
4765 | TCGRegSet t_allocated_regs = i_allocated_regs; | |
4766 | ||
1c1824dc | 4767 | /* |
29f5e925 RH |
4768 | * Because of the alias, and the continued life, make sure |
4769 | * that the temp is somewhere *other* than the reg pair, | |
4770 | * and we get a copy in reg. | |
1c1824dc | 4771 | */ |
29f5e925 RH |
4772 | tcg_regset_set_reg(t_allocated_regs, reg); |
4773 | tcg_regset_set_reg(t_allocated_regs, reg + 1); | |
4774 | if (ts->val_type == TEMP_VAL_REG && ts->reg == reg) { | |
4775 | /* If ts was already in reg, copy it somewhere else. */ | |
4776 | TCGReg nr; | |
4777 | bool ok; | |
4778 | ||
4779 | tcg_debug_assert(ts->kind != TEMP_FIXED); | |
4780 | nr = tcg_reg_alloc(s, tcg_target_available_regs[ts->type], | |
4781 | t_allocated_regs, 0, ts->indirect_base); | |
4782 | ok = tcg_out_mov(s, ts->type, nr, reg); | |
4783 | tcg_debug_assert(ok); | |
4784 | ||
4785 | set_temp_val_reg(s, ts, nr); | |
4786 | } else { | |
4787 | temp_load(s, ts, tcg_target_available_regs[ts->type], | |
4788 | t_allocated_regs, 0); | |
4789 | copyto_new_reg = true; | |
4790 | } | |
4791 | } else { | |
4792 | /* Preferably allocate to reg, otherwise copy. */ | |
4793 | i_required_regs = (TCGRegSet)1 << reg; | |
4794 | temp_load(s, ts, i_required_regs, i_allocated_regs, | |
4795 | i_preferred_regs); | |
4796 | copyto_new_reg = ts->reg != reg; | |
5ff9d6a4 | 4797 | } |
29f5e925 | 4798 | break; |
d62816f2 | 4799 | |
29f5e925 RH |
4800 | default: |
4801 | g_assert_not_reached(); | |
1c1824dc | 4802 | } |
d62816f2 | 4803 | |
29f5e925 | 4804 | if (copyto_new_reg) { |
78113e83 | 4805 | if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { |
240c08d0 RH |
4806 | /* |
4807 | * Cross register class move not supported. Sync the | |
4808 | * temp back to its slot and load from there. | |
4809 | */ | |
4810 | temp_sync(s, ts, i_allocated_regs, 0, 0); | |
4811 | tcg_out_ld(s, ts->type, reg, | |
4812 | ts->mem_base->reg, ts->mem_offset); | |
78113e83 | 4813 | } |
c896fe29 | 4814 | } |
c896fe29 FB |
4815 | new_args[i] = reg; |
4816 | const_args[i] = 0; | |
82790a87 | 4817 | tcg_regset_set_reg(i_allocated_regs, reg); |
c896fe29 | 4818 | } |
a813e36f | 4819 | |
a52ad07e AJ |
4820 | /* mark dead temporaries and free the associated registers */ |
4821 | for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { | |
4822 | if (IS_DEAD_ARG(i)) { | |
43439139 | 4823 | temp_dead(s, arg_temp(op->args[i])); |
a52ad07e AJ |
4824 | } |
4825 | } | |
4826 | ||
b4cb76e6 RH |
4827 | if (def->flags & TCG_OPF_COND_BRANCH) { |
4828 | tcg_reg_alloc_cbranch(s, i_allocated_regs); | |
4829 | } else if (def->flags & TCG_OPF_BB_END) { | |
82790a87 | 4830 | tcg_reg_alloc_bb_end(s, i_allocated_regs); |
e8996ee0 | 4831 | } else { |
e8996ee0 | 4832 | if (def->flags & TCG_OPF_CALL_CLOBBER) { |
a813e36f | 4833 | /* XXX: permit generic clobber register list ? */ |
c8074023 RH |
4834 | for (i = 0; i < TCG_TARGET_NB_REGS; i++) { |
4835 | if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { | |
82790a87 | 4836 | tcg_reg_free(s, i, i_allocated_regs); |
e8996ee0 | 4837 | } |
c896fe29 | 4838 | } |
3d5c5f87 AJ |
4839 | } |
4840 | if (def->flags & TCG_OPF_SIDE_EFFECTS) { | |
4841 | /* sync globals if the op has side effects and might trigger | |
4842 | an exception. */ | |
82790a87 | 4843 | sync_globals(s, i_allocated_regs); |
c896fe29 | 4844 | } |
a813e36f | 4845 | |
e8996ee0 | 4846 | /* satisfy the output constraints */ |
e8996ee0 | 4847 | for(k = 0; k < nb_oargs; k++) { |
66792f90 | 4848 | i = def->args_ct[k].sort_index; |
dd186292 | 4849 | arg = op->args[i]; |
e8996ee0 | 4850 | arg_ct = &def->args_ct[i]; |
43439139 | 4851 | ts = arg_temp(arg); |
d63e3b6e RH |
4852 | |
4853 | /* ENV should not be modified. */ | |
e01fa97d | 4854 | tcg_debug_assert(!temp_readonly(ts)); |
d63e3b6e | 4855 | |
29f5e925 RH |
4856 | switch (arg_ct->pair) { |
4857 | case 0: /* not paired */ | |
4858 | if (arg_ct->oalias && !const_args[arg_ct->alias_index]) { | |
4859 | reg = new_args[arg_ct->alias_index]; | |
4860 | } else if (arg_ct->newreg) { | |
4861 | reg = tcg_reg_alloc(s, arg_ct->regs, | |
4862 | i_allocated_regs | o_allocated_regs, | |
31fd884b | 4863 | output_pref(op, k), ts->indirect_base); |
29f5e925 RH |
4864 | } else { |
4865 | reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs, | |
31fd884b | 4866 | output_pref(op, k), ts->indirect_base); |
29f5e925 RH |
4867 | } |
4868 | break; | |
4869 | ||
4870 | case 1: /* first of pair */ | |
4871 | tcg_debug_assert(!arg_ct->newreg); | |
4872 | if (arg_ct->oalias) { | |
4873 | reg = new_args[arg_ct->alias_index]; | |
4874 | break; | |
4875 | } | |
4876 | reg = tcg_reg_alloc_pair(s, arg_ct->regs, o_allocated_regs, | |
31fd884b | 4877 | output_pref(op, k), ts->indirect_base); |
29f5e925 RH |
4878 | break; |
4879 | ||
4880 | case 2: /* second of pair */ | |
4881 | tcg_debug_assert(!arg_ct->newreg); | |
4882 | if (arg_ct->oalias) { | |
4883 | reg = new_args[arg_ct->alias_index]; | |
4884 | } else { | |
4885 | reg = new_args[arg_ct->pair_index] + 1; | |
4886 | } | |
4887 | break; | |
4888 | ||
4889 | case 3: /* first of pair, aliasing with a second input */ | |
4890 | tcg_debug_assert(!arg_ct->newreg); | |
4891 | reg = new_args[arg_ct->pair_index] - 1; | |
4892 | break; | |
4893 | ||
4894 | default: | |
4895 | g_assert_not_reached(); | |
c896fe29 | 4896 | } |
82790a87 | 4897 | tcg_regset_set_reg(o_allocated_regs, reg); |
098859f1 | 4898 | set_temp_val_reg(s, ts, reg); |
d63e3b6e | 4899 | ts->mem_coherent = 0; |
e8996ee0 | 4900 | new_args[i] = reg; |
c896fe29 | 4901 | } |
c896fe29 FB |
4902 | } |
4903 | ||
c896fe29 | 4904 | /* emit instruction */ |
678155b2 RH |
4905 | switch (op->opc) { |
4906 | case INDEX_op_ext8s_i32: | |
4907 | tcg_out_ext8s(s, TCG_TYPE_I32, new_args[0], new_args[1]); | |
4908 | break; | |
4909 | case INDEX_op_ext8s_i64: | |
4910 | tcg_out_ext8s(s, TCG_TYPE_I64, new_args[0], new_args[1]); | |
4911 | break; | |
d0e66c89 RH |
4912 | case INDEX_op_ext8u_i32: |
4913 | case INDEX_op_ext8u_i64: | |
4914 | tcg_out_ext8u(s, new_args[0], new_args[1]); | |
4915 | break; | |
753e42ea RH |
4916 | case INDEX_op_ext16s_i32: |
4917 | tcg_out_ext16s(s, TCG_TYPE_I32, new_args[0], new_args[1]); | |
4918 | break; | |
4919 | case INDEX_op_ext16s_i64: | |
4920 | tcg_out_ext16s(s, TCG_TYPE_I64, new_args[0], new_args[1]); | |
4921 | break; | |
379afdff RH |
4922 | case INDEX_op_ext16u_i32: |
4923 | case INDEX_op_ext16u_i64: | |
4924 | tcg_out_ext16u(s, new_args[0], new_args[1]); | |
4925 | break; | |
52bf3398 RH |
4926 | case INDEX_op_ext32s_i64: |
4927 | tcg_out_ext32s(s, new_args[0], new_args[1]); | |
4928 | break; | |
9ecf5f61 RH |
4929 | case INDEX_op_ext32u_i64: |
4930 | tcg_out_ext32u(s, new_args[0], new_args[1]); | |
4931 | break; | |
9c6aa274 RH |
4932 | case INDEX_op_ext_i32_i64: |
4933 | tcg_out_exts_i32_i64(s, new_args[0], new_args[1]); | |
4934 | break; | |
b9bfe000 RH |
4935 | case INDEX_op_extu_i32_i64: |
4936 | tcg_out_extu_i32_i64(s, new_args[0], new_args[1]); | |
4937 | break; | |
b8b94ac6 RH |
4938 | case INDEX_op_extrl_i64_i32: |
4939 | tcg_out_extrl_i64_i32(s, new_args[0], new_args[1]); | |
4940 | break; | |
678155b2 RH |
4941 | default: |
4942 | if (def->flags & TCG_OPF_VECTOR) { | |
4943 | tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), | |
4944 | new_args, const_args); | |
4945 | } else { | |
4946 | tcg_out_op(s, op->opc, new_args, const_args); | |
4947 | } | |
4948 | break; | |
d2fd745f RH |
4949 | } |
4950 | ||
c896fe29 FB |
4951 | /* move the outputs in the correct register if needed */ |
4952 | for(i = 0; i < nb_oargs; i++) { | |
43439139 | 4953 | ts = arg_temp(op->args[i]); |
d63e3b6e RH |
4954 | |
4955 | /* ENV should not be modified. */ | |
e01fa97d | 4956 | tcg_debug_assert(!temp_readonly(ts)); |
d63e3b6e | 4957 | |
ec7a869d | 4958 | if (NEED_SYNC_ARG(i)) { |
98b4e186 | 4959 | temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i)); |
59d7c14e | 4960 | } else if (IS_DEAD_ARG(i)) { |
f8bf00f1 | 4961 | temp_dead(s, ts); |
ec7a869d | 4962 | } |
c896fe29 FB |
4963 | } |
4964 | } | |
4965 | ||
efe86b21 RH |
4966 | static bool tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op) |
4967 | { | |
4968 | const TCGLifeData arg_life = op->life; | |
4969 | TCGTemp *ots, *itsl, *itsh; | |
4970 | TCGType vtype = TCGOP_VECL(op) + TCG_TYPE_V64; | |
4971 | ||
4972 | /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */ | |
4973 | tcg_debug_assert(TCG_TARGET_REG_BITS == 32); | |
4974 | tcg_debug_assert(TCGOP_VECE(op) == MO_64); | |
4975 | ||
4976 | ots = arg_temp(op->args[0]); | |
4977 | itsl = arg_temp(op->args[1]); | |
4978 | itsh = arg_temp(op->args[2]); | |
4979 | ||
4980 | /* ENV should not be modified. */ | |
4981 | tcg_debug_assert(!temp_readonly(ots)); | |
4982 | ||
4983 | /* Allocate the output register now. */ | |
4984 | if (ots->val_type != TEMP_VAL_REG) { | |
4985 | TCGRegSet allocated_regs = s->reserved_regs; | |
4986 | TCGRegSet dup_out_regs = | |
4987 | tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs; | |
098859f1 | 4988 | TCGReg oreg; |
efe86b21 RH |
4989 | |
4990 | /* Make sure to not spill the input registers. */ | |
4991 | if (!IS_DEAD_ARG(1) && itsl->val_type == TEMP_VAL_REG) { | |
4992 | tcg_regset_set_reg(allocated_regs, itsl->reg); | |
4993 | } | |
4994 | if (!IS_DEAD_ARG(2) && itsh->val_type == TEMP_VAL_REG) { | |
4995 | tcg_regset_set_reg(allocated_regs, itsh->reg); | |
4996 | } | |
4997 | ||
098859f1 | 4998 | oreg = tcg_reg_alloc(s, dup_out_regs, allocated_regs, |
31fd884b | 4999 | output_pref(op, 0), ots->indirect_base); |
098859f1 | 5000 | set_temp_val_reg(s, ots, oreg); |
efe86b21 RH |
5001 | } |
5002 | ||
5003 | /* Promote dup2 of immediates to dupi_vec. */ | |
5004 | if (itsl->val_type == TEMP_VAL_CONST && itsh->val_type == TEMP_VAL_CONST) { | |
5005 | uint64_t val = deposit64(itsl->val, 32, 32, itsh->val); | |
5006 | MemOp vece = MO_64; | |
5007 | ||
5008 | if (val == dup_const(MO_8, val)) { | |
5009 | vece = MO_8; | |
5010 | } else if (val == dup_const(MO_16, val)) { | |
5011 | vece = MO_16; | |
5012 | } else if (val == dup_const(MO_32, val)) { | |
5013 | vece = MO_32; | |
5014 | } | |
5015 | ||
5016 | tcg_out_dupi_vec(s, vtype, vece, ots->reg, val); | |
5017 | goto done; | |
5018 | } | |
5019 | ||
5020 | /* If the two inputs form one 64-bit value, try dupm_vec. */ | |
aef85402 RH |
5021 | if (itsl->temp_subindex == HOST_BIG_ENDIAN && |
5022 | itsh->temp_subindex == !HOST_BIG_ENDIAN && | |
5023 | itsl == itsh + (HOST_BIG_ENDIAN ? 1 : -1)) { | |
5024 | TCGTemp *its = itsl - HOST_BIG_ENDIAN; | |
5025 | ||
5026 | temp_sync(s, its + 0, s->reserved_regs, 0, 0); | |
5027 | temp_sync(s, its + 1, s->reserved_regs, 0, 0); | |
5028 | ||
efe86b21 RH |
5029 | if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg, |
5030 | its->mem_base->reg, its->mem_offset)) { | |
5031 | goto done; | |
5032 | } | |
5033 | } | |
5034 | ||
5035 | /* Fall back to generic expansion. */ | |
5036 | return false; | |
5037 | ||
5038 | done: | |
36f5539c | 5039 | ots->mem_coherent = 0; |
efe86b21 RH |
5040 | if (IS_DEAD_ARG(1)) { |
5041 | temp_dead(s, itsl); | |
5042 | } | |
5043 | if (IS_DEAD_ARG(2)) { | |
5044 | temp_dead(s, itsh); | |
5045 | } | |
5046 | if (NEED_SYNC_ARG(0)) { | |
5047 | temp_sync(s, ots, s->reserved_regs, 0, IS_DEAD_ARG(0)); | |
5048 | } else if (IS_DEAD_ARG(0)) { | |
5049 | temp_dead(s, ots); | |
5050 | } | |
5051 | return true; | |
5052 | } | |
5053 | ||
39004a71 RH |
5054 | static void load_arg_reg(TCGContext *s, TCGReg reg, TCGTemp *ts, |
5055 | TCGRegSet allocated_regs) | |
c896fe29 | 5056 | { |
39004a71 RH |
5057 | if (ts->val_type == TEMP_VAL_REG) { |
5058 | if (ts->reg != reg) { | |
5059 | tcg_reg_free(s, reg, allocated_regs); | |
5060 | if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { | |
5061 | /* | |
5062 | * Cross register class move not supported. Sync the | |
5063 | * temp back to its slot and load from there. | |
5064 | */ | |
5065 | temp_sync(s, ts, allocated_regs, 0, 0); | |
5066 | tcg_out_ld(s, ts->type, reg, | |
5067 | ts->mem_base->reg, ts->mem_offset); | |
5068 | } | |
5069 | } | |
5070 | } else { | |
5071 | TCGRegSet arg_set = 0; | |
c896fe29 | 5072 | |
39004a71 RH |
5073 | tcg_reg_free(s, reg, allocated_regs); |
5074 | tcg_regset_set_reg(arg_set, reg); | |
5075 | temp_load(s, ts, arg_set, allocated_regs, 0); | |
b03cce8e | 5076 | } |
39004a71 | 5077 | } |
39cf05d3 | 5078 | |
d78e4a4f | 5079 | static void load_arg_stk(TCGContext *s, unsigned arg_slot, TCGTemp *ts, |
39004a71 RH |
5080 | TCGRegSet allocated_regs) |
5081 | { | |
5082 | /* | |
5083 | * When the destination is on the stack, load up the temp and store. | |
5084 | * If there are many call-saved registers, the temp might live to | |
5085 | * see another use; otherwise it'll be discarded. | |
5086 | */ | |
5087 | temp_load(s, ts, tcg_target_available_regs[ts->type], allocated_regs, 0); | |
5088 | tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, | |
d78e4a4f | 5089 | arg_slot_stk_ofs(arg_slot)); |
39004a71 | 5090 | } |
a813e36f | 5091 | |
39004a71 RH |
5092 | static void load_arg_normal(TCGContext *s, const TCGCallArgumentLoc *l, |
5093 | TCGTemp *ts, TCGRegSet *allocated_regs) | |
5094 | { | |
338b61e9 | 5095 | if (arg_slot_reg_p(l->arg_slot)) { |
39004a71 RH |
5096 | TCGReg reg = tcg_target_call_iarg_regs[l->arg_slot]; |
5097 | load_arg_reg(s, reg, ts, *allocated_regs); | |
5098 | tcg_regset_set_reg(*allocated_regs, reg); | |
5099 | } else { | |
d78e4a4f | 5100 | load_arg_stk(s, l->arg_slot, ts, *allocated_regs); |
39004a71 RH |
5101 | } |
5102 | } | |
40ae5c62 | 5103 | |
d78e4a4f | 5104 | static void load_arg_ref(TCGContext *s, unsigned arg_slot, TCGReg ref_base, |
313bdea8 RH |
5105 | intptr_t ref_off, TCGRegSet *allocated_regs) |
5106 | { | |
5107 | TCGReg reg; | |
313bdea8 | 5108 | |
d78e4a4f | 5109 | if (arg_slot_reg_p(arg_slot)) { |
313bdea8 RH |
5110 | reg = tcg_target_call_iarg_regs[arg_slot]; |
5111 | tcg_reg_free(s, reg, *allocated_regs); | |
5112 | tcg_out_addi_ptr(s, reg, ref_base, ref_off); | |
5113 | tcg_regset_set_reg(*allocated_regs, reg); | |
5114 | } else { | |
5115 | reg = tcg_reg_alloc(s, tcg_target_available_regs[TCG_TYPE_PTR], | |
5116 | *allocated_regs, 0, false); | |
5117 | tcg_out_addi_ptr(s, reg, ref_base, ref_off); | |
5118 | tcg_out_st(s, TCG_TYPE_PTR, reg, TCG_REG_CALL_STACK, | |
d78e4a4f | 5119 | arg_slot_stk_ofs(arg_slot)); |
313bdea8 RH |
5120 | } |
5121 | } | |
5122 | ||
39004a71 RH |
5123 | static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) |
5124 | { | |
5125 | const int nb_oargs = TCGOP_CALLO(op); | |
5126 | const int nb_iargs = TCGOP_CALLI(op); | |
5127 | const TCGLifeData arg_life = op->life; | |
5128 | const TCGHelperInfo *info = tcg_call_info(op); | |
5129 | TCGRegSet allocated_regs = s->reserved_regs; | |
5130 | int i; | |
40ae5c62 | 5131 | |
39004a71 RH |
5132 | /* |
5133 | * Move inputs into place in reverse order, | |
5134 | * so that we place stacked arguments first. | |
5135 | */ | |
5136 | for (i = nb_iargs - 1; i >= 0; --i) { | |
5137 | const TCGCallArgumentLoc *loc = &info->in[i]; | |
5138 | TCGTemp *ts = arg_temp(op->args[nb_oargs + i]); | |
40ae5c62 | 5139 | |
39004a71 RH |
5140 | switch (loc->kind) { |
5141 | case TCG_CALL_ARG_NORMAL: | |
5142 | case TCG_CALL_ARG_EXTEND_U: | |
5143 | case TCG_CALL_ARG_EXTEND_S: | |
5144 | load_arg_normal(s, loc, ts, &allocated_regs); | |
5145 | break; | |
313bdea8 RH |
5146 | case TCG_CALL_ARG_BY_REF: |
5147 | load_arg_stk(s, loc->ref_slot, ts, allocated_regs); | |
5148 | load_arg_ref(s, loc->arg_slot, TCG_REG_CALL_STACK, | |
d78e4a4f | 5149 | arg_slot_stk_ofs(loc->ref_slot), |
313bdea8 RH |
5150 | &allocated_regs); |
5151 | break; | |
5152 | case TCG_CALL_ARG_BY_REF_N: | |
5153 | load_arg_stk(s, loc->ref_slot, ts, allocated_regs); | |
5154 | break; | |
39004a71 RH |
5155 | default: |
5156 | g_assert_not_reached(); | |
c896fe29 | 5157 | } |
c896fe29 | 5158 | } |
a813e36f | 5159 | |
39004a71 | 5160 | /* Mark dead temporaries and free the associated registers. */ |
dd186292 | 5161 | for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { |
866cb6cb | 5162 | if (IS_DEAD_ARG(i)) { |
43439139 | 5163 | temp_dead(s, arg_temp(op->args[i])); |
c896fe29 FB |
5164 | } |
5165 | } | |
a813e36f | 5166 | |
39004a71 | 5167 | /* Clobber call registers. */ |
c8074023 RH |
5168 | for (i = 0; i < TCG_TARGET_NB_REGS; i++) { |
5169 | if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { | |
b3915dbb | 5170 | tcg_reg_free(s, i, allocated_regs); |
c896fe29 FB |
5171 | } |
5172 | } | |
78505279 | 5173 | |
39004a71 RH |
5174 | /* |
5175 | * Save globals if they might be written by the helper, | |
5176 | * sync them if they might be read. | |
5177 | */ | |
5178 | if (info->flags & TCG_CALL_NO_READ_GLOBALS) { | |
78505279 | 5179 | /* Nothing to do */ |
39004a71 | 5180 | } else if (info->flags & TCG_CALL_NO_WRITE_GLOBALS) { |
78505279 AJ |
5181 | sync_globals(s, allocated_regs); |
5182 | } else { | |
b9c18f56 AJ |
5183 | save_globals(s, allocated_regs); |
5184 | } | |
c896fe29 | 5185 | |
313bdea8 RH |
5186 | /* |
5187 | * If the ABI passes a pointer to the returned struct as the first | |
5188 | * argument, load that now. Pass a pointer to the output home slot. | |
5189 | */ | |
5190 | if (info->out_kind == TCG_CALL_RET_BY_REF) { | |
5191 | TCGTemp *ts = arg_temp(op->args[0]); | |
5192 | ||
5193 | if (!ts->mem_allocated) { | |
5194 | temp_allocate_frame(s, ts); | |
5195 | } | |
5196 | load_arg_ref(s, 0, ts->mem_base->reg, ts->mem_offset, &allocated_regs); | |
5197 | } | |
5198 | ||
cee44b03 | 5199 | tcg_out_call(s, tcg_call_func(op), info); |
c896fe29 | 5200 | |
39004a71 RH |
5201 | /* Assign output registers and emit moves if needed. */ |
5202 | switch (info->out_kind) { | |
5203 | case TCG_CALL_RET_NORMAL: | |
5204 | for (i = 0; i < nb_oargs; i++) { | |
5205 | TCGTemp *ts = arg_temp(op->args[i]); | |
5e3d0c19 | 5206 | TCGReg reg = tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, i); |
d63e3b6e | 5207 | |
39004a71 RH |
5208 | /* ENV should not be modified. */ |
5209 | tcg_debug_assert(!temp_readonly(ts)); | |
d63e3b6e | 5210 | |
39004a71 RH |
5211 | set_temp_val_reg(s, ts, reg); |
5212 | ts->mem_coherent = 0; | |
5213 | } | |
5214 | break; | |
313bdea8 | 5215 | |
c6556aa0 RH |
5216 | case TCG_CALL_RET_BY_VEC: |
5217 | { | |
5218 | TCGTemp *ts = arg_temp(op->args[0]); | |
5219 | ||
5220 | tcg_debug_assert(ts->base_type == TCG_TYPE_I128); | |
5221 | tcg_debug_assert(ts->temp_subindex == 0); | |
5222 | if (!ts->mem_allocated) { | |
5223 | temp_allocate_frame(s, ts); | |
5224 | } | |
5225 | tcg_out_st(s, TCG_TYPE_V128, | |
5226 | tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0), | |
5227 | ts->mem_base->reg, ts->mem_offset); | |
5228 | } | |
5229 | /* fall through to mark all parts in memory */ | |
5230 | ||
313bdea8 RH |
5231 | case TCG_CALL_RET_BY_REF: |
5232 | /* The callee has performed a write through the reference. */ | |
5233 | for (i = 0; i < nb_oargs; i++) { | |
5234 | TCGTemp *ts = arg_temp(op->args[i]); | |
5235 | ts->val_type = TEMP_VAL_MEM; | |
5236 | } | |
5237 | break; | |
5238 | ||
39004a71 RH |
5239 | default: |
5240 | g_assert_not_reached(); | |
5241 | } | |
5242 | ||
5243 | /* Flush or discard output registers as needed. */ | |
5244 | for (i = 0; i < nb_oargs; i++) { | |
5245 | TCGTemp *ts = arg_temp(op->args[i]); | |
d63e3b6e | 5246 | if (NEED_SYNC_ARG(i)) { |
39004a71 | 5247 | temp_sync(s, ts, s->reserved_regs, 0, IS_DEAD_ARG(i)); |
d63e3b6e RH |
5248 | } else if (IS_DEAD_ARG(i)) { |
5249 | temp_dead(s, ts); | |
c896fe29 FB |
5250 | } |
5251 | } | |
c896fe29 FB |
5252 | } |
5253 | ||
e63b8a29 RH |
5254 | /** |
5255 | * atom_and_align_for_opc: | |
5256 | * @s: tcg context | |
5257 | * @opc: memory operation code | |
5258 | * @host_atom: MO_ATOM_{IFALIGN,WITHIN16,SUBALIGN} for host operations | |
5259 | * @allow_two_ops: true if we are prepared to issue two operations | |
5260 | * | |
5261 | * Return the alignment and atomicity to use for the inline fast path | |
5262 | * for the given memory operation. The alignment may be larger than | |
5263 | * that specified in @opc, and the correct alignment will be diagnosed | |
5264 | * by the slow path helper. | |
5265 | * | |
5266 | * If @allow_two_ops, the host is prepared to test for 2x alignment, | |
5267 | * and issue two loads or stores for subalignment. | |
5268 | */ | |
5269 | static TCGAtomAlign atom_and_align_for_opc(TCGContext *s, MemOp opc, | |
5270 | MemOp host_atom, bool allow_two_ops) | |
5271 | { | |
5272 | MemOp align = get_alignment_bits(opc); | |
5273 | MemOp size = opc & MO_SIZE; | |
5274 | MemOp half = size ? size - 1 : 0; | |
5275 | MemOp atmax; | |
5276 | MemOp atom; | |
5277 | ||
5278 | /* When serialized, no further atomicity required. */ | |
5279 | if (s->gen_tb->cflags & CF_PARALLEL) { | |
5280 | atom = opc & MO_ATOM_MASK; | |
5281 | } else { | |
5282 | atom = MO_ATOM_NONE; | |
5283 | } | |
5284 | ||
5285 | switch (atom) { | |
5286 | case MO_ATOM_NONE: | |
5287 | /* The operation requires no specific atomicity. */ | |
5288 | atmax = MO_8; | |
5289 | break; | |
5290 | ||
5291 | case MO_ATOM_IFALIGN: | |
5292 | atmax = size; | |
5293 | break; | |
5294 | ||
5295 | case MO_ATOM_IFALIGN_PAIR: | |
5296 | atmax = half; | |
5297 | break; | |
5298 | ||
5299 | case MO_ATOM_WITHIN16: | |
5300 | atmax = size; | |
5301 | if (size == MO_128) { | |
5302 | /* Misalignment implies !within16, and therefore no atomicity. */ | |
5303 | } else if (host_atom != MO_ATOM_WITHIN16) { | |
5304 | /* The host does not implement within16, so require alignment. */ | |
5305 | align = MAX(align, size); | |
5306 | } | |
5307 | break; | |
5308 | ||
5309 | case MO_ATOM_WITHIN16_PAIR: | |
5310 | atmax = size; | |
5311 | /* | |
5312 | * Misalignment implies !within16, and therefore half atomicity. | |
5313 | * Any host prepared for two operations can implement this with | |
5314 | * half alignment. | |
5315 | */ | |
5316 | if (host_atom != MO_ATOM_WITHIN16 && allow_two_ops) { | |
5317 | align = MAX(align, half); | |
5318 | } | |
5319 | break; | |
5320 | ||
5321 | case MO_ATOM_SUBALIGN: | |
5322 | atmax = size; | |
5323 | if (host_atom != MO_ATOM_SUBALIGN) { | |
5324 | /* If unaligned but not odd, there are subobjects up to half. */ | |
5325 | if (allow_two_ops) { | |
5326 | align = MAX(align, half); | |
5327 | } else { | |
5328 | align = MAX(align, size); | |
5329 | } | |
5330 | } | |
5331 | break; | |
5332 | ||
5333 | default: | |
5334 | g_assert_not_reached(); | |
5335 | } | |
5336 | ||
5337 | return (TCGAtomAlign){ .atom = atmax, .align = align }; | |
5338 | } | |
5339 | ||
8429a1ca RH |
5340 | /* |
5341 | * Similarly for qemu_ld/st slow path helpers. | |
5342 | * We must re-implement tcg_gen_callN and tcg_reg_alloc_call simultaneously, | |
5343 | * using only the provided backend tcg_out_* functions. | |
5344 | */ | |
5345 | ||
5346 | static int tcg_out_helper_stk_ofs(TCGType type, unsigned slot) | |
5347 | { | |
5348 | int ofs = arg_slot_stk_ofs(slot); | |
5349 | ||
5350 | /* | |
5351 | * Each stack slot is TCG_TARGET_LONG_BITS. If the host does not | |
5352 | * require extension to uint64_t, adjust the address for uint32_t. | |
5353 | */ | |
5354 | if (HOST_BIG_ENDIAN && | |
5355 | TCG_TARGET_REG_BITS == 64 && | |
5356 | type == TCG_TYPE_I32) { | |
5357 | ofs += 4; | |
5358 | } | |
5359 | return ofs; | |
5360 | } | |
5361 | ||
8d314041 RH |
5362 | static void tcg_out_helper_load_slots(TCGContext *s, |
5363 | unsigned nmov, TCGMovExtend *mov, | |
5364 | const TCGLdstHelperParam *parm) | |
8429a1ca | 5365 | { |
8d314041 | 5366 | unsigned i; |
2462e30e RH |
5367 | TCGReg dst3; |
5368 | ||
8d314041 RH |
5369 | /* |
5370 | * Start from the end, storing to the stack first. | |
5371 | * This frees those registers, so we need not consider overlap. | |
5372 | */ | |
5373 | for (i = nmov; i-- > 0; ) { | |
5374 | unsigned slot = mov[i].dst; | |
5375 | ||
5376 | if (arg_slot_reg_p(slot)) { | |
5377 | goto found_reg; | |
5378 | } | |
5379 | ||
5380 | TCGReg src = mov[i].src; | |
5381 | TCGType dst_type = mov[i].dst_type; | |
5382 | MemOp dst_mo = dst_type == TCG_TYPE_I32 ? MO_32 : MO_64; | |
5383 | ||
5384 | /* The argument is going onto the stack; extend into scratch. */ | |
5385 | if ((mov[i].src_ext & MO_SIZE) != dst_mo) { | |
5386 | tcg_debug_assert(parm->ntmp != 0); | |
5387 | mov[i].dst = src = parm->tmp[0]; | |
5388 | tcg_out_movext1(s, &mov[i]); | |
5389 | } | |
5390 | ||
5391 | tcg_out_st(s, dst_type, src, TCG_REG_CALL_STACK, | |
5392 | tcg_out_helper_stk_ofs(dst_type, slot)); | |
5393 | } | |
5394 | return; | |
5395 | ||
5396 | found_reg: | |
5397 | /* | |
5398 | * The remaining arguments are in registers. | |
5399 | * Convert slot numbers to argument registers. | |
5400 | */ | |
5401 | nmov = i + 1; | |
5402 | for (i = 0; i < nmov; ++i) { | |
5403 | mov[i].dst = tcg_target_call_iarg_regs[mov[i].dst]; | |
5404 | } | |
5405 | ||
8429a1ca | 5406 | switch (nmov) { |
2462e30e | 5407 | case 4: |
8429a1ca | 5408 | /* The backend must have provided enough temps for the worst case. */ |
2462e30e | 5409 | tcg_debug_assert(parm->ntmp >= 2); |
8429a1ca | 5410 | |
2462e30e RH |
5411 | dst3 = mov[3].dst; |
5412 | for (unsigned j = 0; j < 3; ++j) { | |
5413 | if (dst3 == mov[j].src) { | |
5414 | /* | |
5415 | * Conflict. Copy the source to a temporary, perform the | |
5416 | * remaining moves, then the extension from our scratch | |
5417 | * on the way out. | |
5418 | */ | |
5419 | TCGReg scratch = parm->tmp[1]; | |
8429a1ca | 5420 | |
2462e30e RH |
5421 | tcg_out_mov(s, mov[3].src_type, scratch, mov[3].src); |
5422 | tcg_out_movext3(s, mov, mov + 1, mov + 2, parm->tmp[0]); | |
5423 | tcg_out_movext1_new_src(s, &mov[3], scratch); | |
5424 | break; | |
8429a1ca | 5425 | } |
8429a1ca | 5426 | } |
8429a1ca | 5427 | |
2462e30e RH |
5428 | /* No conflicts: perform this move and continue. */ |
5429 | tcg_out_movext1(s, &mov[3]); | |
5430 | /* fall through */ | |
5431 | ||
5432 | case 3: | |
5433 | tcg_out_movext3(s, mov, mov + 1, mov + 2, | |
5434 | parm->ntmp ? parm->tmp[0] : -1); | |
5435 | break; | |
8429a1ca | 5436 | case 2: |
2462e30e RH |
5437 | tcg_out_movext2(s, mov, mov + 1, |
5438 | parm->ntmp ? parm->tmp[0] : -1); | |
5439 | break; | |
8429a1ca RH |
5440 | case 1: |
5441 | tcg_out_movext1(s, mov); | |
2462e30e RH |
5442 | break; |
5443 | default: | |
8429a1ca RH |
5444 | g_assert_not_reached(); |
5445 | } | |
5446 | } | |
5447 | ||
8429a1ca RH |
5448 | static void tcg_out_helper_load_imm(TCGContext *s, unsigned slot, |
5449 | TCGType type, tcg_target_long imm, | |
5450 | const TCGLdstHelperParam *parm) | |
5451 | { | |
5452 | if (arg_slot_reg_p(slot)) { | |
5453 | tcg_out_movi(s, type, tcg_target_call_iarg_regs[slot], imm); | |
5454 | } else { | |
5455 | int ofs = tcg_out_helper_stk_ofs(type, slot); | |
5456 | if (!tcg_out_sti(s, type, imm, TCG_REG_CALL_STACK, ofs)) { | |
5457 | tcg_debug_assert(parm->ntmp != 0); | |
5458 | tcg_out_movi(s, type, parm->tmp[0], imm); | |
5459 | tcg_out_st(s, type, parm->tmp[0], TCG_REG_CALL_STACK, ofs); | |
5460 | } | |
5461 | } | |
5462 | } | |
5463 | ||
5464 | static void tcg_out_helper_load_common_args(TCGContext *s, | |
5465 | const TCGLabelQemuLdst *ldst, | |
5466 | const TCGLdstHelperParam *parm, | |
5467 | const TCGHelperInfo *info, | |
5468 | unsigned next_arg) | |
5469 | { | |
5470 | TCGMovExtend ptr_mov = { | |
5471 | .dst_type = TCG_TYPE_PTR, | |
5472 | .src_type = TCG_TYPE_PTR, | |
5473 | .src_ext = sizeof(void *) == 4 ? MO_32 : MO_64 | |
5474 | }; | |
5475 | const TCGCallArgumentLoc *loc = &info->in[0]; | |
5476 | TCGType type; | |
5477 | unsigned slot; | |
5478 | tcg_target_ulong imm; | |
5479 | ||
5480 | /* | |
5481 | * Handle env, which is always first. | |
5482 | */ | |
5483 | ptr_mov.dst = loc->arg_slot; | |
5484 | ptr_mov.src = TCG_AREG0; | |
5485 | tcg_out_helper_load_slots(s, 1, &ptr_mov, parm); | |
5486 | ||
5487 | /* | |
5488 | * Handle oi. | |
5489 | */ | |
5490 | imm = ldst->oi; | |
5491 | loc = &info->in[next_arg]; | |
5492 | type = TCG_TYPE_I32; | |
5493 | switch (loc->kind) { | |
5494 | case TCG_CALL_ARG_NORMAL: | |
5495 | break; | |
5496 | case TCG_CALL_ARG_EXTEND_U: | |
5497 | case TCG_CALL_ARG_EXTEND_S: | |
5498 | /* No extension required for MemOpIdx. */ | |
5499 | tcg_debug_assert(imm <= INT32_MAX); | |
5500 | type = TCG_TYPE_REG; | |
5501 | break; | |
5502 | default: | |
5503 | g_assert_not_reached(); | |
5504 | } | |
5505 | tcg_out_helper_load_imm(s, loc->arg_slot, type, imm, parm); | |
5506 | next_arg++; | |
5507 | ||
5508 | /* | |
5509 | * Handle ra. | |
5510 | */ | |
5511 | loc = &info->in[next_arg]; | |
5512 | slot = loc->arg_slot; | |
5513 | if (parm->ra_gen) { | |
5514 | int arg_reg = -1; | |
5515 | TCGReg ra_reg; | |
5516 | ||
5517 | if (arg_slot_reg_p(slot)) { | |
5518 | arg_reg = tcg_target_call_iarg_regs[slot]; | |
5519 | } | |
5520 | ra_reg = parm->ra_gen(s, ldst, arg_reg); | |
5521 | ||
5522 | ptr_mov.dst = slot; | |
5523 | ptr_mov.src = ra_reg; | |
5524 | tcg_out_helper_load_slots(s, 1, &ptr_mov, parm); | |
5525 | } else { | |
5526 | imm = (uintptr_t)ldst->raddr; | |
5527 | tcg_out_helper_load_imm(s, slot, TCG_TYPE_PTR, imm, parm); | |
5528 | } | |
5529 | } | |
5530 | ||
5531 | static unsigned tcg_out_helper_add_mov(TCGMovExtend *mov, | |
5532 | const TCGCallArgumentLoc *loc, | |
5533 | TCGType dst_type, TCGType src_type, | |
5534 | TCGReg lo, TCGReg hi) | |
5535 | { | |
ebebea53 RH |
5536 | MemOp reg_mo; |
5537 | ||
8429a1ca RH |
5538 | if (dst_type <= TCG_TYPE_REG) { |
5539 | MemOp src_ext; | |
5540 | ||
5541 | switch (loc->kind) { | |
5542 | case TCG_CALL_ARG_NORMAL: | |
5543 | src_ext = src_type == TCG_TYPE_I32 ? MO_32 : MO_64; | |
5544 | break; | |
5545 | case TCG_CALL_ARG_EXTEND_U: | |
5546 | dst_type = TCG_TYPE_REG; | |
5547 | src_ext = MO_UL; | |
5548 | break; | |
5549 | case TCG_CALL_ARG_EXTEND_S: | |
5550 | dst_type = TCG_TYPE_REG; | |
5551 | src_ext = MO_SL; | |
5552 | break; | |
5553 | default: | |
5554 | g_assert_not_reached(); | |
5555 | } | |
5556 | ||
5557 | mov[0].dst = loc->arg_slot; | |
5558 | mov[0].dst_type = dst_type; | |
5559 | mov[0].src = lo; | |
5560 | mov[0].src_type = src_type; | |
5561 | mov[0].src_ext = src_ext; | |
5562 | return 1; | |
5563 | } | |
5564 | ||
ebebea53 RH |
5565 | if (TCG_TARGET_REG_BITS == 32) { |
5566 | assert(dst_type == TCG_TYPE_I64); | |
5567 | reg_mo = MO_32; | |
5568 | } else { | |
5569 | assert(dst_type == TCG_TYPE_I128); | |
5570 | reg_mo = MO_64; | |
5571 | } | |
8429a1ca RH |
5572 | |
5573 | mov[0].dst = loc[HOST_BIG_ENDIAN].arg_slot; | |
5574 | mov[0].src = lo; | |
ebebea53 RH |
5575 | mov[0].dst_type = TCG_TYPE_REG; |
5576 | mov[0].src_type = TCG_TYPE_REG; | |
5577 | mov[0].src_ext = reg_mo; | |
8429a1ca RH |
5578 | |
5579 | mov[1].dst = loc[!HOST_BIG_ENDIAN].arg_slot; | |
5580 | mov[1].src = hi; | |
ebebea53 RH |
5581 | mov[1].dst_type = TCG_TYPE_REG; |
5582 | mov[1].src_type = TCG_TYPE_REG; | |
5583 | mov[1].src_ext = reg_mo; | |
8429a1ca RH |
5584 | |
5585 | return 2; | |
5586 | } | |
5587 | ||
5588 | static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst, | |
5589 | const TCGLdstHelperParam *parm) | |
5590 | { | |
5591 | const TCGHelperInfo *info; | |
5592 | const TCGCallArgumentLoc *loc; | |
5593 | TCGMovExtend mov[2]; | |
5594 | unsigned next_arg, nmov; | |
5595 | MemOp mop = get_memop(ldst->oi); | |
5596 | ||
5597 | switch (mop & MO_SIZE) { | |
5598 | case MO_8: | |
5599 | case MO_16: | |
5600 | case MO_32: | |
5601 | info = &info_helper_ld32_mmu; | |
5602 | break; | |
5603 | case MO_64: | |
5604 | info = &info_helper_ld64_mmu; | |
5605 | break; | |
ebebea53 RH |
5606 | case MO_128: |
5607 | info = &info_helper_ld128_mmu; | |
5608 | break; | |
8429a1ca RH |
5609 | default: |
5610 | g_assert_not_reached(); | |
5611 | } | |
5612 | ||
5613 | /* Defer env argument. */ | |
5614 | next_arg = 1; | |
5615 | ||
5616 | loc = &info->in[next_arg]; | |
c31e5fa4 | 5617 | if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I32) { |
24e46e6c RH |
5618 | /* |
5619 | * 32-bit host with 32-bit guest: zero-extend the guest address | |
5620 | * to 64-bits for the helper by storing the low part, then | |
5621 | * load a zero for the high part. | |
5622 | */ | |
5623 | tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN, | |
5624 | TCG_TYPE_I32, TCG_TYPE_I32, | |
5625 | ldst->addrlo_reg, -1); | |
5626 | tcg_out_helper_load_slots(s, 1, mov, parm); | |
8429a1ca | 5627 | |
24e46e6c RH |
5628 | tcg_out_helper_load_imm(s, loc[!HOST_BIG_ENDIAN].arg_slot, |
5629 | TCG_TYPE_I32, 0, parm); | |
5630 | next_arg += 2; | |
c31e5fa4 RH |
5631 | } else { |
5632 | nmov = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type, | |
5633 | ldst->addrlo_reg, ldst->addrhi_reg); | |
5634 | tcg_out_helper_load_slots(s, nmov, mov, parm); | |
5635 | next_arg += nmov; | |
24e46e6c | 5636 | } |
8429a1ca | 5637 | |
ebebea53 RH |
5638 | switch (info->out_kind) { |
5639 | case TCG_CALL_RET_NORMAL: | |
5640 | case TCG_CALL_RET_BY_VEC: | |
5641 | break; | |
5642 | case TCG_CALL_RET_BY_REF: | |
5643 | /* | |
5644 | * The return reference is in the first argument slot. | |
5645 | * We need memory in which to return: re-use the top of stack. | |
5646 | */ | |
5647 | { | |
5648 | int ofs_slot0 = TCG_TARGET_CALL_STACK_OFFSET; | |
5649 | ||
5650 | if (arg_slot_reg_p(0)) { | |
5651 | tcg_out_addi_ptr(s, tcg_target_call_iarg_regs[0], | |
5652 | TCG_REG_CALL_STACK, ofs_slot0); | |
5653 | } else { | |
5654 | tcg_debug_assert(parm->ntmp != 0); | |
5655 | tcg_out_addi_ptr(s, parm->tmp[0], | |
5656 | TCG_REG_CALL_STACK, ofs_slot0); | |
5657 | tcg_out_st(s, TCG_TYPE_PTR, parm->tmp[0], | |
5658 | TCG_REG_CALL_STACK, ofs_slot0); | |
5659 | } | |
5660 | } | |
5661 | break; | |
5662 | default: | |
5663 | g_assert_not_reached(); | |
5664 | } | |
8429a1ca RH |
5665 | |
5666 | tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); | |
5667 | } | |
5668 | ||
5669 | static void tcg_out_ld_helper_ret(TCGContext *s, const TCGLabelQemuLdst *ldst, | |
5670 | bool load_sign, | |
5671 | const TCGLdstHelperParam *parm) | |
5672 | { | |
ebebea53 | 5673 | MemOp mop = get_memop(ldst->oi); |
8429a1ca | 5674 | TCGMovExtend mov[2]; |
ebebea53 | 5675 | int ofs_slot0; |
8429a1ca | 5676 | |
ebebea53 RH |
5677 | switch (ldst->type) { |
5678 | case TCG_TYPE_I64: | |
5679 | if (TCG_TARGET_REG_BITS == 32) { | |
5680 | break; | |
5681 | } | |
5682 | /* fall through */ | |
8429a1ca | 5683 | |
ebebea53 | 5684 | case TCG_TYPE_I32: |
8429a1ca RH |
5685 | mov[0].dst = ldst->datalo_reg; |
5686 | mov[0].src = tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, 0); | |
5687 | mov[0].dst_type = ldst->type; | |
5688 | mov[0].src_type = TCG_TYPE_REG; | |
5689 | ||
5690 | /* | |
5691 | * If load_sign, then we allowed the helper to perform the | |
5692 | * appropriate sign extension to tcg_target_ulong, and all | |
5693 | * we need now is a plain move. | |
5694 | * | |
5695 | * If they do not, then we expect the relevant extension | |
5696 | * instruction to be no more expensive than a move, and | |
5697 | * we thus save the icache etc by only using one of two | |
5698 | * helper functions. | |
5699 | */ | |
5700 | if (load_sign || !(mop & MO_SIGN)) { | |
5701 | if (TCG_TARGET_REG_BITS == 32 || ldst->type == TCG_TYPE_I32) { | |
5702 | mov[0].src_ext = MO_32; | |
5703 | } else { | |
5704 | mov[0].src_ext = MO_64; | |
5705 | } | |
5706 | } else { | |
5707 | mov[0].src_ext = mop & MO_SSIZE; | |
5708 | } | |
5709 | tcg_out_movext1(s, mov); | |
ebebea53 | 5710 | return; |
8429a1ca | 5711 | |
ebebea53 RH |
5712 | case TCG_TYPE_I128: |
5713 | tcg_debug_assert(TCG_TARGET_REG_BITS == 64); | |
5714 | ofs_slot0 = TCG_TARGET_CALL_STACK_OFFSET; | |
5715 | switch (TCG_TARGET_CALL_RET_I128) { | |
5716 | case TCG_CALL_RET_NORMAL: | |
5717 | break; | |
5718 | case TCG_CALL_RET_BY_VEC: | |
5719 | tcg_out_st(s, TCG_TYPE_V128, | |
5720 | tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0), | |
5721 | TCG_REG_CALL_STACK, ofs_slot0); | |
5722 | /* fall through */ | |
5723 | case TCG_CALL_RET_BY_REF: | |
5724 | tcg_out_ld(s, TCG_TYPE_I64, ldst->datalo_reg, | |
5725 | TCG_REG_CALL_STACK, ofs_slot0 + 8 * HOST_BIG_ENDIAN); | |
5726 | tcg_out_ld(s, TCG_TYPE_I64, ldst->datahi_reg, | |
5727 | TCG_REG_CALL_STACK, ofs_slot0 + 8 * !HOST_BIG_ENDIAN); | |
5728 | return; | |
5729 | default: | |
5730 | g_assert_not_reached(); | |
5731 | } | |
5732 | break; | |
8429a1ca | 5733 | |
ebebea53 RH |
5734 | default: |
5735 | g_assert_not_reached(); | |
8429a1ca | 5736 | } |
ebebea53 RH |
5737 | |
5738 | mov[0].dst = ldst->datalo_reg; | |
5739 | mov[0].src = | |
5740 | tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, HOST_BIG_ENDIAN); | |
723d3a27 RH |
5741 | mov[0].dst_type = TCG_TYPE_REG; |
5742 | mov[0].src_type = TCG_TYPE_REG; | |
ebebea53 RH |
5743 | mov[0].src_ext = TCG_TARGET_REG_BITS == 32 ? MO_32 : MO_64; |
5744 | ||
5745 | mov[1].dst = ldst->datahi_reg; | |
5746 | mov[1].src = | |
5747 | tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, !HOST_BIG_ENDIAN); | |
5748 | mov[1].dst_type = TCG_TYPE_REG; | |
5749 | mov[1].src_type = TCG_TYPE_REG; | |
5750 | mov[1].src_ext = TCG_TARGET_REG_BITS == 32 ? MO_32 : MO_64; | |
5751 | ||
5752 | tcg_out_movext2(s, mov, mov + 1, parm->ntmp ? parm->tmp[0] : -1); | |
8429a1ca RH |
5753 | } |
5754 | ||
5755 | static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst, | |
5756 | const TCGLdstHelperParam *parm) | |
5757 | { | |
5758 | const TCGHelperInfo *info; | |
5759 | const TCGCallArgumentLoc *loc; | |
5760 | TCGMovExtend mov[4]; | |
5761 | TCGType data_type; | |
5762 | unsigned next_arg, nmov, n; | |
5763 | MemOp mop = get_memop(ldst->oi); | |
5764 | ||
5765 | switch (mop & MO_SIZE) { | |
5766 | case MO_8: | |
5767 | case MO_16: | |
5768 | case MO_32: | |
5769 | info = &info_helper_st32_mmu; | |
5770 | data_type = TCG_TYPE_I32; | |
5771 | break; | |
5772 | case MO_64: | |
5773 | info = &info_helper_st64_mmu; | |
5774 | data_type = TCG_TYPE_I64; | |
5775 | break; | |
ebebea53 RH |
5776 | case MO_128: |
5777 | info = &info_helper_st128_mmu; | |
5778 | data_type = TCG_TYPE_I128; | |
5779 | break; | |
8429a1ca RH |
5780 | default: |
5781 | g_assert_not_reached(); | |
5782 | } | |
5783 | ||
5784 | /* Defer env argument. */ | |
5785 | next_arg = 1; | |
5786 | nmov = 0; | |
5787 | ||
5788 | /* Handle addr argument. */ | |
5789 | loc = &info->in[next_arg]; | |
c31e5fa4 | 5790 | if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I32) { |
24e46e6c RH |
5791 | /* |
5792 | * 32-bit host with 32-bit guest: zero-extend the guest address | |
5793 | * to 64-bits for the helper by storing the low part. Later, | |
5794 | * after we have processed the register inputs, we will load a | |
5795 | * zero for the high part. | |
5796 | */ | |
5797 | tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN, | |
5798 | TCG_TYPE_I32, TCG_TYPE_I32, | |
5799 | ldst->addrlo_reg, -1); | |
5800 | next_arg += 2; | |
5801 | nmov += 1; | |
c31e5fa4 RH |
5802 | } else { |
5803 | n = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type, | |
5804 | ldst->addrlo_reg, ldst->addrhi_reg); | |
5805 | next_arg += n; | |
5806 | nmov += n; | |
24e46e6c | 5807 | } |
8429a1ca RH |
5808 | |
5809 | /* Handle data argument. */ | |
5810 | loc = &info->in[next_arg]; | |
ebebea53 RH |
5811 | switch (loc->kind) { |
5812 | case TCG_CALL_ARG_NORMAL: | |
5813 | case TCG_CALL_ARG_EXTEND_U: | |
5814 | case TCG_CALL_ARG_EXTEND_S: | |
5815 | n = tcg_out_helper_add_mov(mov + nmov, loc, data_type, ldst->type, | |
5816 | ldst->datalo_reg, ldst->datahi_reg); | |
5817 | next_arg += n; | |
5818 | nmov += n; | |
5819 | tcg_out_helper_load_slots(s, nmov, mov, parm); | |
5820 | break; | |
5821 | ||
5822 | case TCG_CALL_ARG_BY_REF: | |
5823 | tcg_debug_assert(TCG_TARGET_REG_BITS == 64); | |
5824 | tcg_debug_assert(data_type == TCG_TYPE_I128); | |
5825 | tcg_out_st(s, TCG_TYPE_I64, | |
5826 | HOST_BIG_ENDIAN ? ldst->datahi_reg : ldst->datalo_reg, | |
5827 | TCG_REG_CALL_STACK, arg_slot_stk_ofs(loc[0].ref_slot)); | |
5828 | tcg_out_st(s, TCG_TYPE_I64, | |
5829 | HOST_BIG_ENDIAN ? ldst->datalo_reg : ldst->datahi_reg, | |
5830 | TCG_REG_CALL_STACK, arg_slot_stk_ofs(loc[1].ref_slot)); | |
5831 | ||
5832 | tcg_out_helper_load_slots(s, nmov, mov, parm); | |
5833 | ||
5834 | if (arg_slot_reg_p(loc->arg_slot)) { | |
5835 | tcg_out_addi_ptr(s, tcg_target_call_iarg_regs[loc->arg_slot], | |
5836 | TCG_REG_CALL_STACK, | |
5837 | arg_slot_stk_ofs(loc->ref_slot)); | |
5838 | } else { | |
5839 | tcg_debug_assert(parm->ntmp != 0); | |
5840 | tcg_out_addi_ptr(s, parm->tmp[0], TCG_REG_CALL_STACK, | |
5841 | arg_slot_stk_ofs(loc->ref_slot)); | |
5842 | tcg_out_st(s, TCG_TYPE_PTR, parm->tmp[0], | |
5843 | TCG_REG_CALL_STACK, arg_slot_stk_ofs(loc->arg_slot)); | |
5844 | } | |
5845 | next_arg += 2; | |
5846 | break; | |
5847 | ||
5848 | default: | |
5849 | g_assert_not_reached(); | |
5850 | } | |
8429a1ca | 5851 | |
c31e5fa4 RH |
5852 | if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I32) { |
5853 | /* Zero extend the address by loading a zero for the high part. */ | |
24e46e6c RH |
5854 | loc = &info->in[1 + !HOST_BIG_ENDIAN]; |
5855 | tcg_out_helper_load_imm(s, loc->arg_slot, TCG_TYPE_I32, 0, parm); | |
5856 | } | |
5857 | ||
8429a1ca RH |
5858 | tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); |
5859 | } | |
5860 | ||
c896fe29 FB |
5861 | #ifdef CONFIG_PROFILER |
5862 | ||
c3fac113 EC |
5863 | /* avoid copy/paste errors */ |
5864 | #define PROF_ADD(to, from, field) \ | |
5865 | do { \ | |
d73415a3 | 5866 | (to)->field += qatomic_read(&((from)->field)); \ |
c3fac113 EC |
5867 | } while (0) |
5868 | ||
5869 | #define PROF_MAX(to, from, field) \ | |
5870 | do { \ | |
d73415a3 | 5871 | typeof((from)->field) val__ = qatomic_read(&((from)->field)); \ |
c3fac113 EC |
5872 | if (val__ > (to)->field) { \ |
5873 | (to)->field = val__; \ | |
5874 | } \ | |
5875 | } while (0) | |
5876 | ||
5877 | /* Pass in a zero'ed @prof */ | |
5878 | static inline | |
5879 | void tcg_profile_snapshot(TCGProfile *prof, bool counters, bool table) | |
5880 | { | |
0e2d61cf | 5881 | unsigned int n_ctxs = qatomic_read(&tcg_cur_ctxs); |
c3fac113 EC |
5882 | unsigned int i; |
5883 | ||
3468b59e | 5884 | for (i = 0; i < n_ctxs; i++) { |
d73415a3 | 5885 | TCGContext *s = qatomic_read(&tcg_ctxs[i]); |
3468b59e | 5886 | const TCGProfile *orig = &s->prof; |
c3fac113 EC |
5887 | |
5888 | if (counters) { | |
72fd2efb | 5889 | PROF_ADD(prof, orig, cpu_exec_time); |
c3fac113 EC |
5890 | PROF_ADD(prof, orig, tb_count1); |
5891 | PROF_ADD(prof, orig, tb_count); | |
5892 | PROF_ADD(prof, orig, op_count); | |
5893 | PROF_MAX(prof, orig, op_count_max); | |
5894 | PROF_ADD(prof, orig, temp_count); | |
5895 | PROF_MAX(prof, orig, temp_count_max); | |
5896 | PROF_ADD(prof, orig, del_op_count); | |
5897 | PROF_ADD(prof, orig, code_in_len); | |
5898 | PROF_ADD(prof, orig, code_out_len); | |
5899 | PROF_ADD(prof, orig, search_out_len); | |
5900 | PROF_ADD(prof, orig, interm_time); | |
5901 | PROF_ADD(prof, orig, code_time); | |
5902 | PROF_ADD(prof, orig, la_time); | |
5903 | PROF_ADD(prof, orig, opt_time); | |
5904 | PROF_ADD(prof, orig, restore_count); | |
5905 | PROF_ADD(prof, orig, restore_time); | |
5906 | } | |
5907 | if (table) { | |
5908 | int i; | |
5909 | ||
5910 | for (i = 0; i < NB_OPS; i++) { | |
5911 | PROF_ADD(prof, orig, table_op_count[i]); | |
5912 | } | |
5913 | } | |
5914 | } | |
5915 | } | |
5916 | ||
5917 | #undef PROF_ADD | |
5918 | #undef PROF_MAX | |
5919 | ||
5920 | static void tcg_profile_snapshot_counters(TCGProfile *prof) | |
5921 | { | |
5922 | tcg_profile_snapshot(prof, true, false); | |
5923 | } | |
5924 | ||
5925 | static void tcg_profile_snapshot_table(TCGProfile *prof) | |
5926 | { | |
5927 | tcg_profile_snapshot(prof, false, true); | |
5928 | } | |
c896fe29 | 5929 | |
b6a7f3e0 | 5930 | void tcg_dump_op_count(GString *buf) |
c896fe29 | 5931 | { |
c3fac113 | 5932 | TCGProfile prof = {}; |
c896fe29 | 5933 | int i; |
d70724ce | 5934 | |
c3fac113 | 5935 | tcg_profile_snapshot_table(&prof); |
15fc7daa | 5936 | for (i = 0; i < NB_OPS; i++) { |
b6a7f3e0 DB |
5937 | g_string_append_printf(buf, "%s %" PRId64 "\n", tcg_op_defs[i].name, |
5938 | prof.table_op_count[i]); | |
c896fe29 | 5939 | } |
c896fe29 | 5940 | } |
72fd2efb EC |
5941 | |
5942 | int64_t tcg_cpu_exec_time(void) | |
5943 | { | |
0e2d61cf | 5944 | unsigned int n_ctxs = qatomic_read(&tcg_cur_ctxs); |
72fd2efb EC |
5945 | unsigned int i; |
5946 | int64_t ret = 0; | |
5947 | ||
5948 | for (i = 0; i < n_ctxs; i++) { | |
d73415a3 | 5949 | const TCGContext *s = qatomic_read(&tcg_ctxs[i]); |
72fd2efb EC |
5950 | const TCGProfile *prof = &s->prof; |
5951 | ||
d73415a3 | 5952 | ret += qatomic_read(&prof->cpu_exec_time); |
72fd2efb EC |
5953 | } |
5954 | return ret; | |
5955 | } | |
246ae24d | 5956 | #else |
b6a7f3e0 | 5957 | void tcg_dump_op_count(GString *buf) |
246ae24d | 5958 | { |
b6a7f3e0 | 5959 | g_string_append_printf(buf, "[TCG profiler not compiled]\n"); |
246ae24d | 5960 | } |
72fd2efb EC |
5961 | |
5962 | int64_t tcg_cpu_exec_time(void) | |
5963 | { | |
5964 | error_report("%s: TCG profiler not compiled", __func__); | |
5965 | exit(EXIT_FAILURE); | |
5966 | } | |
c896fe29 FB |
5967 | #endif |
5968 | ||
5969 | ||
76cef4b2 | 5970 | int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start) |
c896fe29 | 5971 | { |
c3fac113 EC |
5972 | #ifdef CONFIG_PROFILER |
5973 | TCGProfile *prof = &s->prof; | |
5974 | #endif | |
15fa08f8 RH |
5975 | int i, num_insns; |
5976 | TCGOp *op; | |
c896fe29 | 5977 | |
04fe6400 RH |
5978 | #ifdef CONFIG_PROFILER |
5979 | { | |
c1f543b7 | 5980 | int n = 0; |
04fe6400 | 5981 | |
15fa08f8 RH |
5982 | QTAILQ_FOREACH(op, &s->ops, link) { |
5983 | n++; | |
5984 | } | |
d73415a3 | 5985 | qatomic_set(&prof->op_count, prof->op_count + n); |
c3fac113 | 5986 | if (n > prof->op_count_max) { |
d73415a3 | 5987 | qatomic_set(&prof->op_count_max, n); |
04fe6400 RH |
5988 | } |
5989 | ||
5990 | n = s->nb_temps; | |
d73415a3 | 5991 | qatomic_set(&prof->temp_count, prof->temp_count + n); |
c3fac113 | 5992 | if (n > prof->temp_count_max) { |
d73415a3 | 5993 | qatomic_set(&prof->temp_count_max, n); |
04fe6400 RH |
5994 | } |
5995 | } | |
5996 | #endif | |
5997 | ||
d977e1c2 | 5998 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) |
fbf59aad | 5999 | && qemu_log_in_addr_range(pc_start))) { |
c60f599b | 6000 | FILE *logfile = qemu_log_trylock(); |
78b54858 RH |
6001 | if (logfile) { |
6002 | fprintf(logfile, "OP:\n"); | |
b7a83ff8 | 6003 | tcg_dump_ops(s, logfile, false); |
78b54858 RH |
6004 | fprintf(logfile, "\n"); |
6005 | qemu_log_unlock(logfile); | |
6006 | } | |
c896fe29 | 6007 | } |
c896fe29 | 6008 | |
bef16ab4 RH |
6009 | #ifdef CONFIG_DEBUG_TCG |
6010 | /* Ensure all labels referenced have been emitted. */ | |
6011 | { | |
6012 | TCGLabel *l; | |
6013 | bool error = false; | |
6014 | ||
6015 | QSIMPLEQ_FOREACH(l, &s->labels, next) { | |
f85b1fc4 | 6016 | if (unlikely(!l->present) && !QSIMPLEQ_EMPTY(&l->branches)) { |
bef16ab4 RH |
6017 | qemu_log_mask(CPU_LOG_TB_OP, |
6018 | "$L%d referenced but not present.\n", l->id); | |
6019 | error = true; | |
6020 | } | |
6021 | } | |
6022 | assert(!error); | |
6023 | } | |
6024 | #endif | |
6025 | ||
c5cc28ff | 6026 | #ifdef CONFIG_PROFILER |
d73415a3 | 6027 | qatomic_set(&prof->opt_time, prof->opt_time - profile_getclock()); |
c5cc28ff AJ |
6028 | #endif |
6029 | ||
c45cb8bb | 6030 | tcg_optimize(s); |
8f2e8c07 | 6031 | |
a23a9ec6 | 6032 | #ifdef CONFIG_PROFILER |
d73415a3 SH |
6033 | qatomic_set(&prof->opt_time, prof->opt_time + profile_getclock()); |
6034 | qatomic_set(&prof->la_time, prof->la_time - profile_getclock()); | |
a23a9ec6 | 6035 | #endif |
c5cc28ff | 6036 | |
b4fc67c7 | 6037 | reachable_code_pass(s); |
874b8574 | 6038 | liveness_pass_0(s); |
b83eabea | 6039 | liveness_pass_1(s); |
5a18407f | 6040 | |
b83eabea | 6041 | if (s->nb_indirects > 0) { |
b83eabea | 6042 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) |
fbf59aad | 6043 | && qemu_log_in_addr_range(pc_start))) { |
c60f599b | 6044 | FILE *logfile = qemu_log_trylock(); |
78b54858 RH |
6045 | if (logfile) { |
6046 | fprintf(logfile, "OP before indirect lowering:\n"); | |
b7a83ff8 | 6047 | tcg_dump_ops(s, logfile, false); |
78b54858 RH |
6048 | fprintf(logfile, "\n"); |
6049 | qemu_log_unlock(logfile); | |
6050 | } | |
b83eabea | 6051 | } |
645e3a81 | 6052 | |
b83eabea RH |
6053 | /* Replace indirect temps with direct temps. */ |
6054 | if (liveness_pass_2(s)) { | |
6055 | /* If changes were made, re-run liveness. */ | |
6056 | liveness_pass_1(s); | |
5a18407f RH |
6057 | } |
6058 | } | |
c5cc28ff | 6059 | |
a23a9ec6 | 6060 | #ifdef CONFIG_PROFILER |
d73415a3 | 6061 | qatomic_set(&prof->la_time, prof->la_time + profile_getclock()); |
a23a9ec6 | 6062 | #endif |
c896fe29 | 6063 | |
d977e1c2 | 6064 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) |
fbf59aad | 6065 | && qemu_log_in_addr_range(pc_start))) { |
c60f599b | 6066 | FILE *logfile = qemu_log_trylock(); |
78b54858 RH |
6067 | if (logfile) { |
6068 | fprintf(logfile, "OP after optimization and liveness analysis:\n"); | |
b7a83ff8 | 6069 | tcg_dump_ops(s, logfile, true); |
78b54858 RH |
6070 | fprintf(logfile, "\n"); |
6071 | qemu_log_unlock(logfile); | |
6072 | } | |
c896fe29 | 6073 | } |
c896fe29 | 6074 | |
35abb009 | 6075 | /* Initialize goto_tb jump offsets. */ |
3a50f424 RH |
6076 | tb->jmp_reset_offset[0] = TB_JMP_OFFSET_INVALID; |
6077 | tb->jmp_reset_offset[1] = TB_JMP_OFFSET_INVALID; | |
9da6079b RH |
6078 | tb->jmp_insn_offset[0] = TB_JMP_OFFSET_INVALID; |
6079 | tb->jmp_insn_offset[1] = TB_JMP_OFFSET_INVALID; | |
35abb009 | 6080 | |
c896fe29 FB |
6081 | tcg_reg_alloc_start(s); |
6082 | ||
db0c51a3 RH |
6083 | /* |
6084 | * Reset the buffer pointers when restarting after overflow. | |
6085 | * TODO: Move this into translate-all.c with the rest of the | |
6086 | * buffer management. Having only this done here is confusing. | |
6087 | */ | |
6088 | s->code_buf = tcg_splitwx_to_rw(tb->tc.ptr); | |
6089 | s->code_ptr = s->code_buf; | |
c896fe29 | 6090 | |
659ef5cb | 6091 | #ifdef TCG_TARGET_NEED_LDST_LABELS |
6001f772 | 6092 | QSIMPLEQ_INIT(&s->ldst_labels); |
659ef5cb | 6093 | #endif |
57a26946 RH |
6094 | #ifdef TCG_TARGET_NEED_POOL_LABELS |
6095 | s->pool_labels = NULL; | |
6096 | #endif | |
9ecefc84 | 6097 | |
fca8a500 | 6098 | num_insns = -1; |
15fa08f8 | 6099 | QTAILQ_FOREACH(op, &s->ops, link) { |
c45cb8bb | 6100 | TCGOpcode opc = op->opc; |
b3db8758 | 6101 | |
c896fe29 | 6102 | #ifdef CONFIG_PROFILER |
d73415a3 | 6103 | qatomic_set(&prof->table_op_count[opc], prof->table_op_count[opc] + 1); |
c896fe29 | 6104 | #endif |
c45cb8bb RH |
6105 | |
6106 | switch (opc) { | |
c896fe29 | 6107 | case INDEX_op_mov_i32: |
c896fe29 | 6108 | case INDEX_op_mov_i64: |
d2fd745f | 6109 | case INDEX_op_mov_vec: |
dd186292 | 6110 | tcg_reg_alloc_mov(s, op); |
c896fe29 | 6111 | break; |
bab1671f RH |
6112 | case INDEX_op_dup_vec: |
6113 | tcg_reg_alloc_dup(s, op); | |
6114 | break; | |
765b842a | 6115 | case INDEX_op_insn_start: |
fca8a500 | 6116 | if (num_insns >= 0) { |
9f754620 RH |
6117 | size_t off = tcg_current_code_size(s); |
6118 | s->gen_insn_end_off[num_insns] = off; | |
6119 | /* Assert that we do not overflow our stored offset. */ | |
6120 | assert(s->gen_insn_end_off[num_insns] == off); | |
fca8a500 RH |
6121 | } |
6122 | num_insns++; | |
bad729e2 | 6123 | for (i = 0; i < TARGET_INSN_START_WORDS; ++i) { |
c9ad8d27 RH |
6124 | s->gen_insn_data[num_insns][i] = |
6125 | tcg_get_insn_start_param(op, i); | |
bad729e2 | 6126 | } |
c896fe29 | 6127 | break; |
5ff9d6a4 | 6128 | case INDEX_op_discard: |
43439139 | 6129 | temp_dead(s, arg_temp(op->args[0])); |
5ff9d6a4 | 6130 | break; |
c896fe29 | 6131 | case INDEX_op_set_label: |
e8996ee0 | 6132 | tcg_reg_alloc_bb_end(s, s->reserved_regs); |
92ab8e7d | 6133 | tcg_out_label(s, arg_label(op->args[0])); |
c896fe29 FB |
6134 | break; |
6135 | case INDEX_op_call: | |
dd186292 | 6136 | tcg_reg_alloc_call(s, op); |
c45cb8bb | 6137 | break; |
b55a8d9d RH |
6138 | case INDEX_op_exit_tb: |
6139 | tcg_out_exit_tb(s, op->args[0]); | |
6140 | break; | |
cf7d6b8e RH |
6141 | case INDEX_op_goto_tb: |
6142 | tcg_out_goto_tb(s, op->args[0]); | |
6143 | break; | |
efe86b21 RH |
6144 | case INDEX_op_dup2_vec: |
6145 | if (tcg_reg_alloc_dup2(s, op)) { | |
6146 | break; | |
6147 | } | |
6148 | /* fall through */ | |
c896fe29 | 6149 | default: |
25c4d9cc | 6150 | /* Sanity check that we've not introduced any unhandled opcodes. */ |
be0f34b5 | 6151 | tcg_debug_assert(tcg_op_supported(opc)); |
c896fe29 FB |
6152 | /* Note: in order to speed up the code, it would be much |
6153 | faster to have specialized register allocator functions for | |
6154 | some common argument patterns */ | |
dd186292 | 6155 | tcg_reg_alloc_op(s, op); |
c896fe29 FB |
6156 | break; |
6157 | } | |
b125f9dc RH |
6158 | /* Test for (pending) buffer overflow. The assumption is that any |
6159 | one operation beginning below the high water mark cannot overrun | |
6160 | the buffer completely. Thus we can test for overflow after | |
6161 | generating code without having to check during generation. */ | |
644da9b3 | 6162 | if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { |
b125f9dc RH |
6163 | return -1; |
6164 | } | |
6e6c4efe RH |
6165 | /* Test for TB overflow, as seen by gen_insn_end_off. */ |
6166 | if (unlikely(tcg_current_code_size(s) > UINT16_MAX)) { | |
6167 | return -2; | |
6168 | } | |
c896fe29 | 6169 | } |
fca8a500 RH |
6170 | tcg_debug_assert(num_insns >= 0); |
6171 | s->gen_insn_end_off[num_insns] = tcg_current_code_size(s); | |
c45cb8bb | 6172 | |
b76f0d8c | 6173 | /* Generate TB finalization at the end of block */ |
659ef5cb | 6174 | #ifdef TCG_TARGET_NEED_LDST_LABELS |
aeee05f5 RH |
6175 | i = tcg_out_ldst_finalize(s); |
6176 | if (i < 0) { | |
6177 | return i; | |
23dceda6 | 6178 | } |
659ef5cb | 6179 | #endif |
57a26946 | 6180 | #ifdef TCG_TARGET_NEED_POOL_LABELS |
1768987b RH |
6181 | i = tcg_out_pool_finalize(s); |
6182 | if (i < 0) { | |
6183 | return i; | |
57a26946 RH |
6184 | } |
6185 | #endif | |
7ecd02a0 RH |
6186 | if (!tcg_resolve_relocs(s)) { |
6187 | return -2; | |
6188 | } | |
c896fe29 | 6189 | |
df5d2b16 | 6190 | #ifndef CONFIG_TCG_INTERPRETER |
c896fe29 | 6191 | /* flush instruction cache */ |
db0c51a3 RH |
6192 | flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s->code_buf), |
6193 | (uintptr_t)s->code_buf, | |
1da8de39 | 6194 | tcg_ptr_byte_diff(s->code_ptr, s->code_buf)); |
df5d2b16 | 6195 | #endif |
2aeabc08 | 6196 | |
1813e175 | 6197 | return tcg_current_code_size(s); |
c896fe29 FB |
6198 | } |
6199 | ||
a23a9ec6 | 6200 | #ifdef CONFIG_PROFILER |
3a841ab5 | 6201 | void tcg_dump_info(GString *buf) |
a23a9ec6 | 6202 | { |
c3fac113 EC |
6203 | TCGProfile prof = {}; |
6204 | const TCGProfile *s; | |
6205 | int64_t tb_count; | |
6206 | int64_t tb_div_count; | |
6207 | int64_t tot; | |
6208 | ||
6209 | tcg_profile_snapshot_counters(&prof); | |
6210 | s = &prof; | |
6211 | tb_count = s->tb_count; | |
6212 | tb_div_count = tb_count ? tb_count : 1; | |
6213 | tot = s->interm_time + s->code_time; | |
a23a9ec6 | 6214 | |
3a841ab5 DB |
6215 | g_string_append_printf(buf, "JIT cycles %" PRId64 |
6216 | " (%0.3f s at 2.4 GHz)\n", | |
6217 | tot, tot / 2.4e9); | |
6218 | g_string_append_printf(buf, "translated TBs %" PRId64 | |
6219 | " (aborted=%" PRId64 " %0.1f%%)\n", | |
6220 | tb_count, s->tb_count1 - tb_count, | |
6221 | (double)(s->tb_count1 - s->tb_count) | |
6222 | / (s->tb_count1 ? s->tb_count1 : 1) * 100.0); | |
6223 | g_string_append_printf(buf, "avg ops/TB %0.1f max=%d\n", | |
6224 | (double)s->op_count / tb_div_count, s->op_count_max); | |
6225 | g_string_append_printf(buf, "deleted ops/TB %0.2f\n", | |
6226 | (double)s->del_op_count / tb_div_count); | |
6227 | g_string_append_printf(buf, "avg temps/TB %0.2f max=%d\n", | |
6228 | (double)s->temp_count / tb_div_count, | |
6229 | s->temp_count_max); | |
6230 | g_string_append_printf(buf, "avg host code/TB %0.1f\n", | |
6231 | (double)s->code_out_len / tb_div_count); | |
6232 | g_string_append_printf(buf, "avg search data/TB %0.1f\n", | |
6233 | (double)s->search_out_len / tb_div_count); | |
a813e36f | 6234 | |
3a841ab5 DB |
6235 | g_string_append_printf(buf, "cycles/op %0.1f\n", |
6236 | s->op_count ? (double)tot / s->op_count : 0); | |
6237 | g_string_append_printf(buf, "cycles/in byte %0.1f\n", | |
6238 | s->code_in_len ? (double)tot / s->code_in_len : 0); | |
6239 | g_string_append_printf(buf, "cycles/out byte %0.1f\n", | |
6240 | s->code_out_len ? (double)tot / s->code_out_len : 0); | |
6241 | g_string_append_printf(buf, "cycles/search byte %0.1f\n", | |
6242 | s->search_out_len ? | |
6243 | (double)tot / s->search_out_len : 0); | |
fca8a500 | 6244 | if (tot == 0) { |
a23a9ec6 | 6245 | tot = 1; |
fca8a500 | 6246 | } |
3a841ab5 DB |
6247 | g_string_append_printf(buf, " gen_interm time %0.1f%%\n", |
6248 | (double)s->interm_time / tot * 100.0); | |
6249 | g_string_append_printf(buf, " gen_code time %0.1f%%\n", | |
6250 | (double)s->code_time / tot * 100.0); | |
6251 | g_string_append_printf(buf, "optim./code time %0.1f%%\n", | |
6252 | (double)s->opt_time / (s->code_time ? | |
6253 | s->code_time : 1) | |
6254 | * 100.0); | |
6255 | g_string_append_printf(buf, "liveness/code time %0.1f%%\n", | |
6256 | (double)s->la_time / (s->code_time ? | |
6257 | s->code_time : 1) * 100.0); | |
6258 | g_string_append_printf(buf, "cpu_restore count %" PRId64 "\n", | |
6259 | s->restore_count); | |
6260 | g_string_append_printf(buf, " avg cycles %0.1f\n", | |
6261 | s->restore_count ? | |
6262 | (double)s->restore_time / s->restore_count : 0); | |
a23a9ec6 FB |
6263 | } |
6264 | #else | |
3a841ab5 | 6265 | void tcg_dump_info(GString *buf) |
a23a9ec6 | 6266 | { |
3a841ab5 | 6267 | g_string_append_printf(buf, "[TCG profiler not compiled]\n"); |
a23a9ec6 FB |
6268 | } |
6269 | #endif | |
813da627 RH |
6270 | |
6271 | #ifdef ELF_HOST_MACHINE | |
5872bbf2 RH |
6272 | /* In order to use this feature, the backend needs to do three things: |
6273 | ||
6274 | (1) Define ELF_HOST_MACHINE to indicate both what value to | |
6275 | put into the ELF image and to indicate support for the feature. | |
6276 | ||
6277 | (2) Define tcg_register_jit. This should create a buffer containing | |
6278 | the contents of a .debug_frame section that describes the post- | |
6279 | prologue unwind info for the tcg machine. | |
6280 | ||
6281 | (3) Call tcg_register_jit_int, with the constructed .debug_frame. | |
6282 | */ | |
813da627 RH |
6283 | |
6284 | /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */ | |
6285 | typedef enum { | |
6286 | JIT_NOACTION = 0, | |
6287 | JIT_REGISTER_FN, | |
6288 | JIT_UNREGISTER_FN | |
6289 | } jit_actions_t; | |
6290 | ||
6291 | struct jit_code_entry { | |
6292 | struct jit_code_entry *next_entry; | |
6293 | struct jit_code_entry *prev_entry; | |
6294 | const void *symfile_addr; | |
6295 | uint64_t symfile_size; | |
6296 | }; | |
6297 | ||
6298 | struct jit_descriptor { | |
6299 | uint32_t version; | |
6300 | uint32_t action_flag; | |
6301 | struct jit_code_entry *relevant_entry; | |
6302 | struct jit_code_entry *first_entry; | |
6303 | }; | |
6304 | ||
6305 | void __jit_debug_register_code(void) __attribute__((noinline)); | |
6306 | void __jit_debug_register_code(void) | |
6307 | { | |
6308 | asm(""); | |
6309 | } | |
6310 | ||
6311 | /* Must statically initialize the version, because GDB may check | |
6312 | the version before we can set it. */ | |
6313 | struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 }; | |
6314 | ||
6315 | /* End GDB interface. */ | |
6316 | ||
6317 | static int find_string(const char *strtab, const char *str) | |
6318 | { | |
6319 | const char *p = strtab + 1; | |
6320 | ||
6321 | while (1) { | |
6322 | if (strcmp(p, str) == 0) { | |
6323 | return p - strtab; | |
6324 | } | |
6325 | p += strlen(p) + 1; | |
6326 | } | |
6327 | } | |
6328 | ||
755bf9e5 | 6329 | static void tcg_register_jit_int(const void *buf_ptr, size_t buf_size, |
2c90784a RH |
6330 | const void *debug_frame, |
6331 | size_t debug_frame_size) | |
813da627 | 6332 | { |
5872bbf2 RH |
6333 | struct __attribute__((packed)) DebugInfo { |
6334 | uint32_t len; | |
6335 | uint16_t version; | |
6336 | uint32_t abbrev; | |
6337 | uint8_t ptr_size; | |
6338 | uint8_t cu_die; | |
6339 | uint16_t cu_lang; | |
6340 | uintptr_t cu_low_pc; | |
6341 | uintptr_t cu_high_pc; | |
6342 | uint8_t fn_die; | |
6343 | char fn_name[16]; | |
6344 | uintptr_t fn_low_pc; | |
6345 | uintptr_t fn_high_pc; | |
6346 | uint8_t cu_eoc; | |
6347 | }; | |
813da627 RH |
6348 | |
6349 | struct ElfImage { | |
6350 | ElfW(Ehdr) ehdr; | |
6351 | ElfW(Phdr) phdr; | |
5872bbf2 RH |
6352 | ElfW(Shdr) shdr[7]; |
6353 | ElfW(Sym) sym[2]; | |
6354 | struct DebugInfo di; | |
6355 | uint8_t da[24]; | |
6356 | char str[80]; | |
6357 | }; | |
6358 | ||
6359 | struct ElfImage *img; | |
6360 | ||
6361 | static const struct ElfImage img_template = { | |
6362 | .ehdr = { | |
6363 | .e_ident[EI_MAG0] = ELFMAG0, | |
6364 | .e_ident[EI_MAG1] = ELFMAG1, | |
6365 | .e_ident[EI_MAG2] = ELFMAG2, | |
6366 | .e_ident[EI_MAG3] = ELFMAG3, | |
6367 | .e_ident[EI_CLASS] = ELF_CLASS, | |
6368 | .e_ident[EI_DATA] = ELF_DATA, | |
6369 | .e_ident[EI_VERSION] = EV_CURRENT, | |
6370 | .e_type = ET_EXEC, | |
6371 | .e_machine = ELF_HOST_MACHINE, | |
6372 | .e_version = EV_CURRENT, | |
6373 | .e_phoff = offsetof(struct ElfImage, phdr), | |
6374 | .e_shoff = offsetof(struct ElfImage, shdr), | |
6375 | .e_ehsize = sizeof(ElfW(Shdr)), | |
6376 | .e_phentsize = sizeof(ElfW(Phdr)), | |
6377 | .e_phnum = 1, | |
6378 | .e_shentsize = sizeof(ElfW(Shdr)), | |
6379 | .e_shnum = ARRAY_SIZE(img->shdr), | |
6380 | .e_shstrndx = ARRAY_SIZE(img->shdr) - 1, | |
abbb3eae RH |
6381 | #ifdef ELF_HOST_FLAGS |
6382 | .e_flags = ELF_HOST_FLAGS, | |
6383 | #endif | |
6384 | #ifdef ELF_OSABI | |
6385 | .e_ident[EI_OSABI] = ELF_OSABI, | |
6386 | #endif | |
5872bbf2 RH |
6387 | }, |
6388 | .phdr = { | |
6389 | .p_type = PT_LOAD, | |
6390 | .p_flags = PF_X, | |
6391 | }, | |
6392 | .shdr = { | |
6393 | [0] = { .sh_type = SHT_NULL }, | |
6394 | /* Trick: The contents of code_gen_buffer are not present in | |
6395 | this fake ELF file; that got allocated elsewhere. Therefore | |
6396 | we mark .text as SHT_NOBITS (similar to .bss) so that readers | |
6397 | will not look for contents. We can record any address. */ | |
6398 | [1] = { /* .text */ | |
6399 | .sh_type = SHT_NOBITS, | |
6400 | .sh_flags = SHF_EXECINSTR | SHF_ALLOC, | |
6401 | }, | |
6402 | [2] = { /* .debug_info */ | |
6403 | .sh_type = SHT_PROGBITS, | |
6404 | .sh_offset = offsetof(struct ElfImage, di), | |
6405 | .sh_size = sizeof(struct DebugInfo), | |
6406 | }, | |
6407 | [3] = { /* .debug_abbrev */ | |
6408 | .sh_type = SHT_PROGBITS, | |
6409 | .sh_offset = offsetof(struct ElfImage, da), | |
6410 | .sh_size = sizeof(img->da), | |
6411 | }, | |
6412 | [4] = { /* .debug_frame */ | |
6413 | .sh_type = SHT_PROGBITS, | |
6414 | .sh_offset = sizeof(struct ElfImage), | |
6415 | }, | |
6416 | [5] = { /* .symtab */ | |
6417 | .sh_type = SHT_SYMTAB, | |
6418 | .sh_offset = offsetof(struct ElfImage, sym), | |
6419 | .sh_size = sizeof(img->sym), | |
6420 | .sh_info = 1, | |
6421 | .sh_link = ARRAY_SIZE(img->shdr) - 1, | |
6422 | .sh_entsize = sizeof(ElfW(Sym)), | |
6423 | }, | |
6424 | [6] = { /* .strtab */ | |
6425 | .sh_type = SHT_STRTAB, | |
6426 | .sh_offset = offsetof(struct ElfImage, str), | |
6427 | .sh_size = sizeof(img->str), | |
6428 | } | |
6429 | }, | |
6430 | .sym = { | |
6431 | [1] = { /* code_gen_buffer */ | |
6432 | .st_info = ELF_ST_INFO(STB_GLOBAL, STT_FUNC), | |
6433 | .st_shndx = 1, | |
6434 | } | |
6435 | }, | |
6436 | .di = { | |
6437 | .len = sizeof(struct DebugInfo) - 4, | |
6438 | .version = 2, | |
6439 | .ptr_size = sizeof(void *), | |
6440 | .cu_die = 1, | |
6441 | .cu_lang = 0x8001, /* DW_LANG_Mips_Assembler */ | |
6442 | .fn_die = 2, | |
6443 | .fn_name = "code_gen_buffer" | |
6444 | }, | |
6445 | .da = { | |
6446 | 1, /* abbrev number (the cu) */ | |
6447 | 0x11, 1, /* DW_TAG_compile_unit, has children */ | |
6448 | 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */ | |
6449 | 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ | |
6450 | 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ | |
6451 | 0, 0, /* end of abbrev */ | |
6452 | 2, /* abbrev number (the fn) */ | |
6453 | 0x2e, 0, /* DW_TAG_subprogram, no children */ | |
6454 | 0x3, 0x8, /* DW_AT_name, DW_FORM_string */ | |
6455 | 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ | |
6456 | 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ | |
6457 | 0, 0, /* end of abbrev */ | |
6458 | 0 /* no more abbrev */ | |
6459 | }, | |
6460 | .str = "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0" | |
6461 | ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer", | |
813da627 RH |
6462 | }; |
6463 | ||
6464 | /* We only need a single jit entry; statically allocate it. */ | |
6465 | static struct jit_code_entry one_entry; | |
6466 | ||
5872bbf2 | 6467 | uintptr_t buf = (uintptr_t)buf_ptr; |
813da627 | 6468 | size_t img_size = sizeof(struct ElfImage) + debug_frame_size; |
2c90784a | 6469 | DebugFrameHeader *dfh; |
813da627 | 6470 | |
5872bbf2 RH |
6471 | img = g_malloc(img_size); |
6472 | *img = img_template; | |
813da627 | 6473 | |
5872bbf2 RH |
6474 | img->phdr.p_vaddr = buf; |
6475 | img->phdr.p_paddr = buf; | |
6476 | img->phdr.p_memsz = buf_size; | |
813da627 | 6477 | |
813da627 | 6478 | img->shdr[1].sh_name = find_string(img->str, ".text"); |
5872bbf2 | 6479 | img->shdr[1].sh_addr = buf; |
813da627 RH |
6480 | img->shdr[1].sh_size = buf_size; |
6481 | ||
5872bbf2 RH |
6482 | img->shdr[2].sh_name = find_string(img->str, ".debug_info"); |
6483 | img->shdr[3].sh_name = find_string(img->str, ".debug_abbrev"); | |
6484 | ||
6485 | img->shdr[4].sh_name = find_string(img->str, ".debug_frame"); | |
6486 | img->shdr[4].sh_size = debug_frame_size; | |
6487 | ||
6488 | img->shdr[5].sh_name = find_string(img->str, ".symtab"); | |
6489 | img->shdr[6].sh_name = find_string(img->str, ".strtab"); | |
6490 | ||
6491 | img->sym[1].st_name = find_string(img->str, "code_gen_buffer"); | |
6492 | img->sym[1].st_value = buf; | |
6493 | img->sym[1].st_size = buf_size; | |
813da627 | 6494 | |
5872bbf2 | 6495 | img->di.cu_low_pc = buf; |
45aba097 | 6496 | img->di.cu_high_pc = buf + buf_size; |
5872bbf2 | 6497 | img->di.fn_low_pc = buf; |
45aba097 | 6498 | img->di.fn_high_pc = buf + buf_size; |
813da627 | 6499 | |
2c90784a RH |
6500 | dfh = (DebugFrameHeader *)(img + 1); |
6501 | memcpy(dfh, debug_frame, debug_frame_size); | |
6502 | dfh->fde.func_start = buf; | |
6503 | dfh->fde.func_len = buf_size; | |
6504 | ||
813da627 RH |
6505 | #ifdef DEBUG_JIT |
6506 | /* Enable this block to be able to debug the ELF image file creation. | |
6507 | One can use readelf, objdump, or other inspection utilities. */ | |
6508 | { | |
eb6b2edf BM |
6509 | g_autofree char *jit = g_strdup_printf("%s/qemu.jit", g_get_tmp_dir()); |
6510 | FILE *f = fopen(jit, "w+b"); | |
813da627 | 6511 | if (f) { |
5872bbf2 | 6512 | if (fwrite(img, img_size, 1, f) != img_size) { |
813da627 RH |
6513 | /* Avoid stupid unused return value warning for fwrite. */ |
6514 | } | |
6515 | fclose(f); | |
6516 | } | |
6517 | } | |
6518 | #endif | |
6519 | ||
6520 | one_entry.symfile_addr = img; | |
6521 | one_entry.symfile_size = img_size; | |
6522 | ||
6523 | __jit_debug_descriptor.action_flag = JIT_REGISTER_FN; | |
6524 | __jit_debug_descriptor.relevant_entry = &one_entry; | |
6525 | __jit_debug_descriptor.first_entry = &one_entry; | |
6526 | __jit_debug_register_code(); | |
6527 | } | |
6528 | #else | |
5872bbf2 RH |
6529 | /* No support for the feature. Provide the entry point expected by exec.c, |
6530 | and implement the internal function we declared earlier. */ | |
813da627 | 6531 | |
755bf9e5 | 6532 | static void tcg_register_jit_int(const void *buf, size_t size, |
2c90784a RH |
6533 | const void *debug_frame, |
6534 | size_t debug_frame_size) | |
813da627 RH |
6535 | { |
6536 | } | |
6537 | ||
755bf9e5 | 6538 | void tcg_register_jit(const void *buf, size_t buf_size) |
813da627 RH |
6539 | { |
6540 | } | |
6541 | #endif /* ELF_HOST_MACHINE */ | |
db432672 RH |
6542 | |
6543 | #if !TCG_TARGET_MAYBE_vec | |
6544 | void tcg_expand_vec_op(TCGOpcode o, TCGType t, unsigned e, TCGArg a0, ...) | |
6545 | { | |
6546 | g_assert_not_reached(); | |
6547 | } | |
6548 | #endif |