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tcg: Respect highwater in tcg_out_tb_finalize
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CommitLineData
c896fe29
FB
1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
c896fe29
FB
25/* define it to use liveness analysis (better code) */
26#define USE_LIVENESS_ANALYSIS
8f2e8c07 27#define USE_TCG_OPTIMIZATIONS
c896fe29 28
757e725b 29#include "qemu/osdep.h"
cca82982 30
813da627
RH
31/* Define to jump the ELF file used to communicate with GDB. */
32#undef DEBUG_JIT
33
a6c6f76c 34#if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
cca82982
AJ
35/* define it to suppress various consistency checks (faster) */
36#define NDEBUG
37#endif
38
ca10f867 39#include "qemu-common.h"
1de7afc9
PB
40#include "qemu/host-utils.h"
41#include "qemu/timer.h"
c896fe29 42
c5d3c498 43/* Note: the long term plan is to reduce the dependencies on the QEMU
c896fe29
FB
44 CPU definitions. Currently they are used for qemu_ld/st
45 instructions */
46#define NO_CPU_IO_DEFS
47#include "cpu.h"
c896fe29
FB
48
49#include "tcg-op.h"
813da627 50
edee2579 51#if UINTPTR_MAX == UINT32_MAX
813da627 52# define ELF_CLASS ELFCLASS32
edee2579
RH
53#else
54# define ELF_CLASS ELFCLASS64
813da627
RH
55#endif
56#ifdef HOST_WORDS_BIGENDIAN
57# define ELF_DATA ELFDATA2MSB
58#else
59# define ELF_DATA ELFDATA2LSB
60#endif
61
c896fe29 62#include "elf.h"
508127e2 63#include "exec/log.h"
c896fe29 64
c0ad3001 65/* Forward declarations for functions declared in tcg-target.c and used here. */
e4d58b41
RH
66static void tcg_target_init(TCGContext *s);
67static void tcg_target_qemu_prologue(TCGContext *s);
1813e175 68static void patch_reloc(tcg_insn_unit *code_ptr, int type,
2ba7fae2 69 intptr_t value, intptr_t addend);
c896fe29 70
497a22eb
RH
71/* The CIE and FDE header definitions will be common to all hosts. */
72typedef struct {
73 uint32_t len __attribute__((aligned((sizeof(void *)))));
74 uint32_t id;
75 uint8_t version;
76 char augmentation[1];
77 uint8_t code_align;
78 uint8_t data_align;
79 uint8_t return_column;
80} DebugFrameCIE;
81
82typedef struct QEMU_PACKED {
83 uint32_t len __attribute__((aligned((sizeof(void *)))));
84 uint32_t cie_offset;
edee2579
RH
85 uintptr_t func_start;
86 uintptr_t func_len;
497a22eb
RH
87} DebugFrameFDEHeader;
88
2c90784a
RH
89typedef struct QEMU_PACKED {
90 DebugFrameCIE cie;
91 DebugFrameFDEHeader fde;
92} DebugFrameHeader;
93
813da627 94static void tcg_register_jit_int(void *buf, size_t size,
2c90784a
RH
95 const void *debug_frame,
96 size_t debug_frame_size)
813da627
RH
97 __attribute__((unused));
98
c0ad3001
SW
99/* Forward declarations for functions declared and used in tcg-target.c. */
100static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str);
2a534aff 101static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
a05b5b9b 102 intptr_t arg2);
2a534aff 103static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
c0ad3001 104static void tcg_out_movi(TCGContext *s, TCGType type,
2a534aff 105 TCGReg ret, tcg_target_long arg);
c0ad3001
SW
106static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
107 const int *const_args);
2a534aff 108static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
a05b5b9b 109 intptr_t arg2);
cf066674 110static void tcg_out_call(TCGContext *s, tcg_insn_unit *target);
f6c6afc1 111static int tcg_target_const_match(tcg_target_long val, TCGType type,
c0ad3001 112 const TCGArgConstraint *arg_ct);
9ecefc84 113static void tcg_out_tb_init(TCGContext *s);
23dceda6 114static bool tcg_out_tb_finalize(TCGContext *s);
9ecefc84 115
c0ad3001 116
c896fe29 117
b1d8e52e
BS
118static TCGRegSet tcg_target_available_regs[2];
119static TCGRegSet tcg_target_call_clobber_regs;
c896fe29 120
1813e175 121#if TCG_TARGET_INSN_UNIT_SIZE == 1
4196dca6 122static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v)
c896fe29
FB
123{
124 *s->code_ptr++ = v;
125}
126
4196dca6
PM
127static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p,
128 uint8_t v)
5c53bb81 129{
1813e175 130 *p = v;
5c53bb81 131}
1813e175 132#endif
5c53bb81 133
1813e175 134#if TCG_TARGET_INSN_UNIT_SIZE <= 2
4196dca6 135static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v)
c896fe29 136{
1813e175
RH
137 if (TCG_TARGET_INSN_UNIT_SIZE == 2) {
138 *s->code_ptr++ = v;
139 } else {
140 tcg_insn_unit *p = s->code_ptr;
141 memcpy(p, &v, sizeof(v));
142 s->code_ptr = p + (2 / TCG_TARGET_INSN_UNIT_SIZE);
143 }
c896fe29
FB
144}
145
4196dca6
PM
146static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p,
147 uint16_t v)
5c53bb81 148{
1813e175
RH
149 if (TCG_TARGET_INSN_UNIT_SIZE == 2) {
150 *p = v;
151 } else {
152 memcpy(p, &v, sizeof(v));
153 }
5c53bb81 154}
1813e175 155#endif
5c53bb81 156
1813e175 157#if TCG_TARGET_INSN_UNIT_SIZE <= 4
4196dca6 158static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v)
c896fe29 159{
1813e175
RH
160 if (TCG_TARGET_INSN_UNIT_SIZE == 4) {
161 *s->code_ptr++ = v;
162 } else {
163 tcg_insn_unit *p = s->code_ptr;
164 memcpy(p, &v, sizeof(v));
165 s->code_ptr = p + (4 / TCG_TARGET_INSN_UNIT_SIZE);
166 }
c896fe29
FB
167}
168
4196dca6
PM
169static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p,
170 uint32_t v)
5c53bb81 171{
1813e175
RH
172 if (TCG_TARGET_INSN_UNIT_SIZE == 4) {
173 *p = v;
174 } else {
175 memcpy(p, &v, sizeof(v));
176 }
5c53bb81 177}
1813e175 178#endif
5c53bb81 179
1813e175 180#if TCG_TARGET_INSN_UNIT_SIZE <= 8
4196dca6 181static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v)
ac26eb69 182{
1813e175
RH
183 if (TCG_TARGET_INSN_UNIT_SIZE == 8) {
184 *s->code_ptr++ = v;
185 } else {
186 tcg_insn_unit *p = s->code_ptr;
187 memcpy(p, &v, sizeof(v));
188 s->code_ptr = p + (8 / TCG_TARGET_INSN_UNIT_SIZE);
189 }
ac26eb69
RH
190}
191
4196dca6
PM
192static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p,
193 uint64_t v)
5c53bb81 194{
1813e175
RH
195 if (TCG_TARGET_INSN_UNIT_SIZE == 8) {
196 *p = v;
197 } else {
198 memcpy(p, &v, sizeof(v));
199 }
5c53bb81 200}
1813e175 201#endif
5c53bb81 202
c896fe29
FB
203/* label relocation processing */
204
1813e175 205static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type,
bec16311 206 TCGLabel *l, intptr_t addend)
c896fe29 207{
c896fe29
FB
208 TCGRelocation *r;
209
c896fe29 210 if (l->has_value) {
623e265c
PB
211 /* FIXME: This may break relocations on RISC targets that
212 modify instruction fields in place. The caller may not have
213 written the initial value. */
f54b3f92 214 patch_reloc(code_ptr, type, l->u.value, addend);
c896fe29
FB
215 } else {
216 /* add a new relocation entry */
217 r = tcg_malloc(sizeof(TCGRelocation));
218 r->type = type;
219 r->ptr = code_ptr;
220 r->addend = addend;
221 r->next = l->u.first_reloc;
222 l->u.first_reloc = r;
223 }
224}
225
bec16311 226static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr)
c896fe29 227{
2ba7fae2 228 intptr_t value = (intptr_t)ptr;
1813e175 229 TCGRelocation *r;
c896fe29 230
1813e175
RH
231 assert(!l->has_value);
232
233 for (r = l->u.first_reloc; r != NULL; r = r->next) {
f54b3f92 234 patch_reloc(r->ptr, r->type, value, r->addend);
c896fe29 235 }
1813e175 236
c896fe29 237 l->has_value = 1;
1813e175 238 l->u.value_ptr = ptr;
c896fe29
FB
239}
240
42a268c2 241TCGLabel *gen_new_label(void)
c896fe29
FB
242{
243 TCGContext *s = &tcg_ctx;
51e3972c 244 TCGLabel *l = tcg_malloc(sizeof(TCGLabel));
c896fe29 245
51e3972c
RH
246 *l = (TCGLabel){
247 .id = s->nb_labels++
248 };
42a268c2
RH
249
250 return l;
c896fe29
FB
251}
252
253#include "tcg-target.c"
254
c896fe29
FB
255/* pool based memory allocation */
256void *tcg_malloc_internal(TCGContext *s, int size)
257{
258 TCGPool *p;
259 int pool_size;
260
261 if (size > TCG_POOL_CHUNK_SIZE) {
262 /* big malloc: insert a new pool (XXX: could optimize) */
7267c094 263 p = g_malloc(sizeof(TCGPool) + size);
c896fe29 264 p->size = size;
4055299e
KB
265 p->next = s->pool_first_large;
266 s->pool_first_large = p;
267 return p->data;
c896fe29
FB
268 } else {
269 p = s->pool_current;
270 if (!p) {
271 p = s->pool_first;
272 if (!p)
273 goto new_pool;
274 } else {
275 if (!p->next) {
276 new_pool:
277 pool_size = TCG_POOL_CHUNK_SIZE;
7267c094 278 p = g_malloc(sizeof(TCGPool) + pool_size);
c896fe29
FB
279 p->size = pool_size;
280 p->next = NULL;
281 if (s->pool_current)
282 s->pool_current->next = p;
283 else
284 s->pool_first = p;
285 } else {
286 p = p->next;
287 }
288 }
289 }
290 s->pool_current = p;
291 s->pool_cur = p->data + size;
292 s->pool_end = p->data + p->size;
293 return p->data;
294}
295
296void tcg_pool_reset(TCGContext *s)
297{
4055299e
KB
298 TCGPool *p, *t;
299 for (p = s->pool_first_large; p; p = t) {
300 t = p->next;
301 g_free(p);
302 }
303 s->pool_first_large = NULL;
c896fe29
FB
304 s->pool_cur = s->pool_end = NULL;
305 s->pool_current = NULL;
306}
307
100b5e01
RH
308typedef struct TCGHelperInfo {
309 void *func;
310 const char *name;
afb49896
RH
311 unsigned flags;
312 unsigned sizemask;
100b5e01
RH
313} TCGHelperInfo;
314
2ef6175a
RH
315#include "exec/helper-proto.h"
316
100b5e01 317static const TCGHelperInfo all_helpers[] = {
2ef6175a 318#include "exec/helper-tcg.h"
100b5e01
RH
319};
320
c896fe29
FB
321void tcg_context_init(TCGContext *s)
322{
100b5e01 323 int op, total_args, n, i;
c896fe29
FB
324 TCGOpDef *def;
325 TCGArgConstraint *args_ct;
326 int *sorted_args;
84fd9dd3 327 GHashTable *helper_table;
c896fe29
FB
328
329 memset(s, 0, sizeof(*s));
c896fe29
FB
330 s->nb_globals = 0;
331
332 /* Count total number of arguments and allocate the corresponding
333 space */
334 total_args = 0;
335 for(op = 0; op < NB_OPS; op++) {
336 def = &tcg_op_defs[op];
337 n = def->nb_iargs + def->nb_oargs;
338 total_args += n;
339 }
340
7267c094
AL
341 args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
342 sorted_args = g_malloc(sizeof(int) * total_args);
c896fe29
FB
343
344 for(op = 0; op < NB_OPS; op++) {
345 def = &tcg_op_defs[op];
346 def->args_ct = args_ct;
347 def->sorted_args = sorted_args;
348 n = def->nb_iargs + def->nb_oargs;
349 sorted_args += n;
350 args_ct += n;
351 }
5cd8f621
RH
352
353 /* Register helpers. */
84fd9dd3
RH
354 /* Use g_direct_hash/equal for direct pointer comparisons on func. */
355 s->helpers = helper_table = g_hash_table_new(NULL, NULL);
356
100b5e01 357 for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) {
84fd9dd3 358 g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func,
72866e82 359 (gpointer)&all_helpers[i]);
100b5e01 360 }
5cd8f621 361
c896fe29 362 tcg_target_init(s);
9002ec79 363}
b03cce8e 364
9002ec79
RH
365void tcg_prologue_init(TCGContext *s)
366{
8163b749
RH
367 size_t prologue_size, total_size;
368 void *buf0, *buf1;
369
370 /* Put the prologue at the beginning of code_gen_buffer. */
371 buf0 = s->code_gen_buffer;
372 s->code_ptr = buf0;
373 s->code_buf = buf0;
374 s->code_gen_prologue = buf0;
375
376 /* Generate the prologue. */
b03cce8e 377 tcg_target_qemu_prologue(s);
8163b749
RH
378 buf1 = s->code_ptr;
379 flush_icache_range((uintptr_t)buf0, (uintptr_t)buf1);
380
381 /* Deduct the prologue from the buffer. */
382 prologue_size = tcg_current_code_size(s);
383 s->code_gen_ptr = buf1;
384 s->code_gen_buffer = buf1;
385 s->code_buf = buf1;
386 total_size = s->code_gen_buffer_size - prologue_size;
387 s->code_gen_buffer_size = total_size;
388
b125f9dc
RH
389 /* Compute a high-water mark, at which we voluntarily flush the buffer
390 and start over. The size here is arbitrary, significantly larger
391 than we expect the code generation for any one opcode to require. */
23dceda6 392 s->code_gen_highwater = s->code_gen_buffer + (total_size - 1024);
8163b749
RH
393
394 tcg_register_jit(s->code_gen_buffer, total_size);
d6b64b2b
RH
395
396#ifdef DEBUG_DISAS
397 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) {
8163b749
RH
398 qemu_log("PROLOGUE: [size=%zu]\n", prologue_size);
399 log_disas(buf0, prologue_size);
d6b64b2b
RH
400 qemu_log("\n");
401 qemu_log_flush();
402 }
403#endif
c896fe29
FB
404}
405
e2c6d1b4 406void tcg_set_frame(TCGContext *s, int reg, intptr_t start, intptr_t size)
c896fe29
FB
407{
408 s->frame_start = start;
409 s->frame_end = start + size;
410 s->frame_reg = reg;
411}
412
c896fe29
FB
413void tcg_func_start(TCGContext *s)
414{
415 tcg_pool_reset(s);
416 s->nb_temps = s->nb_globals;
0ec9eabc
RH
417
418 /* No temps have been previously allocated for size or locality. */
419 memset(s->free_temps, 0, sizeof(s->free_temps));
420
c896fe29
FB
421 s->nb_labels = 0;
422 s->current_frame_offset = s->frame_start;
423
0a209d4b
RH
424#ifdef CONFIG_DEBUG_TCG
425 s->goto_tb_issue_mask = 0;
426#endif
427
c45cb8bb
RH
428 s->gen_first_op_idx = 0;
429 s->gen_last_op_idx = -1;
430 s->gen_next_op_idx = 0;
431 s->gen_next_parm_idx = 0;
b76f0d8c 432
9ecefc84 433 s->be = tcg_malloc(sizeof(TCGBackendData));
c896fe29
FB
434}
435
436static inline void tcg_temp_alloc(TCGContext *s, int n)
437{
438 if (n > TCG_MAX_TEMPS)
439 tcg_abort();
440}
441
a7812ae4
PB
442static inline int tcg_global_reg_new_internal(TCGType type, int reg,
443 const char *name)
c896fe29
FB
444{
445 TCGContext *s = &tcg_ctx;
446 TCGTemp *ts;
447 int idx;
448
449#if TCG_TARGET_REG_BITS == 32
450 if (type != TCG_TYPE_I32)
451 tcg_abort();
452#endif
453 if (tcg_regset_test_reg(s->reserved_regs, reg))
454 tcg_abort();
455 idx = s->nb_globals;
456 tcg_temp_alloc(s, s->nb_globals + 1);
457 ts = &s->temps[s->nb_globals];
458 ts->base_type = type;
459 ts->type = type;
460 ts->fixed_reg = 1;
461 ts->reg = reg;
c896fe29
FB
462 ts->name = name;
463 s->nb_globals++;
464 tcg_regset_set_reg(s->reserved_regs, reg);
a7812ae4
PB
465 return idx;
466}
467
468TCGv_i32 tcg_global_reg_new_i32(int reg, const char *name)
469{
470 int idx;
471
472 idx = tcg_global_reg_new_internal(TCG_TYPE_I32, reg, name);
473 return MAKE_TCGV_I32(idx);
474}
475
476TCGv_i64 tcg_global_reg_new_i64(int reg, const char *name)
477{
478 int idx;
479
480 idx = tcg_global_reg_new_internal(TCG_TYPE_I64, reg, name);
481 return MAKE_TCGV_I64(idx);
c896fe29
FB
482}
483
a7812ae4 484static inline int tcg_global_mem_new_internal(TCGType type, int reg,
2f2f244d 485 intptr_t offset,
a7812ae4 486 const char *name)
c896fe29
FB
487{
488 TCGContext *s = &tcg_ctx;
489 TCGTemp *ts;
490 int idx;
491
492 idx = s->nb_globals;
493#if TCG_TARGET_REG_BITS == 32
494 if (type == TCG_TYPE_I64) {
495 char buf[64];
c588979b 496 tcg_temp_alloc(s, s->nb_globals + 2);
c896fe29
FB
497 ts = &s->temps[s->nb_globals];
498 ts->base_type = type;
499 ts->type = TCG_TYPE_I32;
500 ts->fixed_reg = 0;
501 ts->mem_allocated = 1;
502 ts->mem_reg = reg;
02eb19d0 503#ifdef HOST_WORDS_BIGENDIAN
c896fe29
FB
504 ts->mem_offset = offset + 4;
505#else
506 ts->mem_offset = offset;
507#endif
c896fe29
FB
508 pstrcpy(buf, sizeof(buf), name);
509 pstrcat(buf, sizeof(buf), "_0");
510 ts->name = strdup(buf);
511 ts++;
512
513 ts->base_type = type;
514 ts->type = TCG_TYPE_I32;
515 ts->fixed_reg = 0;
516 ts->mem_allocated = 1;
517 ts->mem_reg = reg;
02eb19d0 518#ifdef HOST_WORDS_BIGENDIAN
c896fe29
FB
519 ts->mem_offset = offset;
520#else
521 ts->mem_offset = offset + 4;
522#endif
c896fe29
FB
523 pstrcpy(buf, sizeof(buf), name);
524 pstrcat(buf, sizeof(buf), "_1");
525 ts->name = strdup(buf);
526
527 s->nb_globals += 2;
528 } else
529#endif
530 {
531 tcg_temp_alloc(s, s->nb_globals + 1);
532 ts = &s->temps[s->nb_globals];
533 ts->base_type = type;
534 ts->type = type;
535 ts->fixed_reg = 0;
536 ts->mem_allocated = 1;
537 ts->mem_reg = reg;
538 ts->mem_offset = offset;
c896fe29
FB
539 ts->name = name;
540 s->nb_globals++;
541 }
a7812ae4
PB
542 return idx;
543}
544
2f2f244d 545TCGv_i32 tcg_global_mem_new_i32(int reg, intptr_t offset, const char *name)
a7812ae4 546{
2f2f244d 547 int idx = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
a7812ae4
PB
548 return MAKE_TCGV_I32(idx);
549}
550
2f2f244d 551TCGv_i64 tcg_global_mem_new_i64(int reg, intptr_t offset, const char *name)
a7812ae4 552{
2f2f244d 553 int idx = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
a7812ae4 554 return MAKE_TCGV_I64(idx);
c896fe29
FB
555}
556
a7812ae4 557static inline int tcg_temp_new_internal(TCGType type, int temp_local)
c896fe29
FB
558{
559 TCGContext *s = &tcg_ctx;
560 TCGTemp *ts;
641d5fbe 561 int idx, k;
c896fe29 562
0ec9eabc
RH
563 k = type + (temp_local ? TCG_TYPE_COUNT : 0);
564 idx = find_first_bit(s->free_temps[k].l, TCG_MAX_TEMPS);
565 if (idx < TCG_MAX_TEMPS) {
566 /* There is already an available temp with the right type. */
567 clear_bit(idx, s->free_temps[k].l);
568
e8996ee0 569 ts = &s->temps[idx];
e8996ee0 570 ts->temp_allocated = 1;
0ec9eabc 571 assert(ts->base_type == type);
641d5fbe 572 assert(ts->temp_local == temp_local);
e8996ee0
FB
573 } else {
574 idx = s->nb_temps;
c896fe29 575#if TCG_TARGET_REG_BITS == 32
e8996ee0 576 if (type == TCG_TYPE_I64) {
8df1ca4b 577 tcg_temp_alloc(s, s->nb_temps + 2);
e8996ee0
FB
578 ts = &s->temps[s->nb_temps];
579 ts->base_type = type;
580 ts->type = TCG_TYPE_I32;
581 ts->temp_allocated = 1;
641d5fbe 582 ts->temp_local = temp_local;
e8996ee0
FB
583 ts->name = NULL;
584 ts++;
f6aa2f7d 585 ts->base_type = type;
e8996ee0
FB
586 ts->type = TCG_TYPE_I32;
587 ts->temp_allocated = 1;
641d5fbe 588 ts->temp_local = temp_local;
e8996ee0
FB
589 ts->name = NULL;
590 s->nb_temps += 2;
591 } else
c896fe29 592#endif
e8996ee0
FB
593 {
594 tcg_temp_alloc(s, s->nb_temps + 1);
595 ts = &s->temps[s->nb_temps];
596 ts->base_type = type;
597 ts->type = type;
598 ts->temp_allocated = 1;
641d5fbe 599 ts->temp_local = temp_local;
e8996ee0
FB
600 ts->name = NULL;
601 s->nb_temps++;
602 }
c896fe29 603 }
27bfd83c
PM
604
605#if defined(CONFIG_DEBUG_TCG)
606 s->temps_in_use++;
607#endif
a7812ae4 608 return idx;
c896fe29
FB
609}
610
a7812ae4
PB
611TCGv_i32 tcg_temp_new_internal_i32(int temp_local)
612{
613 int idx;
614
615 idx = tcg_temp_new_internal(TCG_TYPE_I32, temp_local);
616 return MAKE_TCGV_I32(idx);
617}
618
619TCGv_i64 tcg_temp_new_internal_i64(int temp_local)
620{
621 int idx;
622
623 idx = tcg_temp_new_internal(TCG_TYPE_I64, temp_local);
624 return MAKE_TCGV_I64(idx);
625}
626
0ec9eabc 627static void tcg_temp_free_internal(int idx)
c896fe29
FB
628{
629 TCGContext *s = &tcg_ctx;
630 TCGTemp *ts;
641d5fbe 631 int k;
c896fe29 632
27bfd83c
PM
633#if defined(CONFIG_DEBUG_TCG)
634 s->temps_in_use--;
635 if (s->temps_in_use < 0) {
636 fprintf(stderr, "More temporaries freed than allocated!\n");
637 }
638#endif
639
e8996ee0 640 assert(idx >= s->nb_globals && idx < s->nb_temps);
c896fe29 641 ts = &s->temps[idx];
e8996ee0
FB
642 assert(ts->temp_allocated != 0);
643 ts->temp_allocated = 0;
0ec9eabc 644
18d13fa2 645 k = ts->base_type + (ts->temp_local ? TCG_TYPE_COUNT : 0);
0ec9eabc 646 set_bit(idx, s->free_temps[k].l);
c896fe29
FB
647}
648
a7812ae4
PB
649void tcg_temp_free_i32(TCGv_i32 arg)
650{
651 tcg_temp_free_internal(GET_TCGV_I32(arg));
652}
653
654void tcg_temp_free_i64(TCGv_i64 arg)
655{
656 tcg_temp_free_internal(GET_TCGV_I64(arg));
657}
e8996ee0 658
a7812ae4 659TCGv_i32 tcg_const_i32(int32_t val)
c896fe29 660{
a7812ae4
PB
661 TCGv_i32 t0;
662 t0 = tcg_temp_new_i32();
e8996ee0
FB
663 tcg_gen_movi_i32(t0, val);
664 return t0;
665}
c896fe29 666
a7812ae4 667TCGv_i64 tcg_const_i64(int64_t val)
e8996ee0 668{
a7812ae4
PB
669 TCGv_i64 t0;
670 t0 = tcg_temp_new_i64();
e8996ee0
FB
671 tcg_gen_movi_i64(t0, val);
672 return t0;
c896fe29
FB
673}
674
a7812ae4 675TCGv_i32 tcg_const_local_i32(int32_t val)
bdffd4a9 676{
a7812ae4
PB
677 TCGv_i32 t0;
678 t0 = tcg_temp_local_new_i32();
bdffd4a9
AJ
679 tcg_gen_movi_i32(t0, val);
680 return t0;
681}
682
a7812ae4 683TCGv_i64 tcg_const_local_i64(int64_t val)
bdffd4a9 684{
a7812ae4
PB
685 TCGv_i64 t0;
686 t0 = tcg_temp_local_new_i64();
bdffd4a9
AJ
687 tcg_gen_movi_i64(t0, val);
688 return t0;
689}
690
27bfd83c
PM
691#if defined(CONFIG_DEBUG_TCG)
692void tcg_clear_temp_count(void)
693{
694 TCGContext *s = &tcg_ctx;
695 s->temps_in_use = 0;
696}
697
698int tcg_check_temp_count(void)
699{
700 TCGContext *s = &tcg_ctx;
701 if (s->temps_in_use) {
702 /* Clear the count so that we don't give another
703 * warning immediately next time around.
704 */
705 s->temps_in_use = 0;
706 return 1;
707 }
708 return 0;
709}
710#endif
711
39cf05d3
FB
712/* Note: we convert the 64 bit args to 32 bit and do some alignment
713 and endian swap. Maybe it would be better to do the alignment
714 and endian swap in tcg_reg_alloc_call(). */
bbb8a1b4
RH
715void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
716 int nargs, TCGArg *args)
c896fe29 717{
c45cb8bb 718 int i, real_args, nb_rets, pi, pi_first;
bbb8a1b4 719 unsigned sizemask, flags;
afb49896
RH
720 TCGHelperInfo *info;
721
722 info = g_hash_table_lookup(s->helpers, (gpointer)func);
bbb8a1b4
RH
723 flags = info->flags;
724 sizemask = info->sizemask;
2bece2c8 725
34b1a49c
RH
726#if defined(__sparc__) && !defined(__arch64__) \
727 && !defined(CONFIG_TCG_INTERPRETER)
728 /* We have 64-bit values in one register, but need to pass as two
729 separate parameters. Split them. */
730 int orig_sizemask = sizemask;
731 int orig_nargs = nargs;
732 TCGv_i64 retl, reth;
733
734 TCGV_UNUSED_I64(retl);
735 TCGV_UNUSED_I64(reth);
736 if (sizemask != 0) {
737 TCGArg *split_args = __builtin_alloca(sizeof(TCGArg) * nargs * 2);
738 for (i = real_args = 0; i < nargs; ++i) {
739 int is_64bit = sizemask & (1 << (i+1)*2);
740 if (is_64bit) {
741 TCGv_i64 orig = MAKE_TCGV_I64(args[i]);
742 TCGv_i32 h = tcg_temp_new_i32();
743 TCGv_i32 l = tcg_temp_new_i32();
744 tcg_gen_extr_i64_i32(l, h, orig);
745 split_args[real_args++] = GET_TCGV_I32(h);
746 split_args[real_args++] = GET_TCGV_I32(l);
747 } else {
748 split_args[real_args++] = args[i];
749 }
750 }
751 nargs = real_args;
752 args = split_args;
753 sizemask = 0;
754 }
755#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
2bece2c8
RH
756 for (i = 0; i < nargs; ++i) {
757 int is_64bit = sizemask & (1 << (i+1)*2);
758 int is_signed = sizemask & (2 << (i+1)*2);
759 if (!is_64bit) {
760 TCGv_i64 temp = tcg_temp_new_i64();
761 TCGv_i64 orig = MAKE_TCGV_I64(args[i]);
762 if (is_signed) {
763 tcg_gen_ext32s_i64(temp, orig);
764 } else {
765 tcg_gen_ext32u_i64(temp, orig);
766 }
767 args[i] = GET_TCGV_I64(temp);
768 }
769 }
770#endif /* TCG_TARGET_EXTEND_ARGS */
771
c45cb8bb 772 pi_first = pi = s->gen_next_parm_idx;
a7812ae4 773 if (ret != TCG_CALL_DUMMY_ARG) {
34b1a49c
RH
774#if defined(__sparc__) && !defined(__arch64__) \
775 && !defined(CONFIG_TCG_INTERPRETER)
776 if (orig_sizemask & 1) {
777 /* The 32-bit ABI is going to return the 64-bit value in
778 the %o0/%o1 register pair. Prepare for this by using
779 two return temporaries, and reassemble below. */
780 retl = tcg_temp_new_i64();
781 reth = tcg_temp_new_i64();
c45cb8bb
RH
782 s->gen_opparam_buf[pi++] = GET_TCGV_I64(reth);
783 s->gen_opparam_buf[pi++] = GET_TCGV_I64(retl);
34b1a49c
RH
784 nb_rets = 2;
785 } else {
c45cb8bb 786 s->gen_opparam_buf[pi++] = ret;
34b1a49c
RH
787 nb_rets = 1;
788 }
789#else
790 if (TCG_TARGET_REG_BITS < 64 && (sizemask & 1)) {
02eb19d0 791#ifdef HOST_WORDS_BIGENDIAN
c45cb8bb
RH
792 s->gen_opparam_buf[pi++] = ret + 1;
793 s->gen_opparam_buf[pi++] = ret;
39cf05d3 794#else
c45cb8bb
RH
795 s->gen_opparam_buf[pi++] = ret;
796 s->gen_opparam_buf[pi++] = ret + 1;
39cf05d3 797#endif
a7812ae4 798 nb_rets = 2;
34b1a49c 799 } else {
c45cb8bb 800 s->gen_opparam_buf[pi++] = ret;
a7812ae4 801 nb_rets = 1;
c896fe29 802 }
34b1a49c 803#endif
a7812ae4
PB
804 } else {
805 nb_rets = 0;
c896fe29 806 }
a7812ae4
PB
807 real_args = 0;
808 for (i = 0; i < nargs; i++) {
2bece2c8 809 int is_64bit = sizemask & (1 << (i+1)*2);
bbb8a1b4 810 if (TCG_TARGET_REG_BITS < 64 && is_64bit) {
39cf05d3
FB
811#ifdef TCG_TARGET_CALL_ALIGN_ARGS
812 /* some targets want aligned 64 bit args */
ebd486d5 813 if (real_args & 1) {
c45cb8bb 814 s->gen_opparam_buf[pi++] = TCG_CALL_DUMMY_ARG;
ebd486d5 815 real_args++;
39cf05d3
FB
816 }
817#endif
3f90f252
RH
818 /* If stack grows up, then we will be placing successive
819 arguments at lower addresses, which means we need to
820 reverse the order compared to how we would normally
821 treat either big or little-endian. For those arguments
822 that will wind up in registers, this still works for
823 HPPA (the only current STACK_GROWSUP target) since the
824 argument registers are *also* allocated in decreasing
825 order. If another such target is added, this logic may
826 have to get more complicated to differentiate between
827 stack arguments and register arguments. */
02eb19d0 828#if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
c45cb8bb
RH
829 s->gen_opparam_buf[pi++] = args[i] + 1;
830 s->gen_opparam_buf[pi++] = args[i];
c896fe29 831#else
c45cb8bb
RH
832 s->gen_opparam_buf[pi++] = args[i];
833 s->gen_opparam_buf[pi++] = args[i] + 1;
c896fe29 834#endif
a7812ae4 835 real_args += 2;
2bece2c8 836 continue;
c896fe29 837 }
2bece2c8 838
c45cb8bb 839 s->gen_opparam_buf[pi++] = args[i];
2bece2c8 840 real_args++;
c896fe29 841 }
c45cb8bb
RH
842 s->gen_opparam_buf[pi++] = (uintptr_t)func;
843 s->gen_opparam_buf[pi++] = flags;
a7812ae4 844
c45cb8bb
RH
845 i = s->gen_next_op_idx;
846 tcg_debug_assert(i < OPC_BUF_SIZE);
847 tcg_debug_assert(pi <= OPPARAM_BUF_SIZE);
a7812ae4 848
c45cb8bb
RH
849 /* Set links for sequential allocation during translation. */
850 s->gen_op_buf[i] = (TCGOp){
851 .opc = INDEX_op_call,
852 .callo = nb_rets,
853 .calli = real_args,
854 .args = pi_first,
855 .prev = i - 1,
856 .next = i + 1
857 };
858
859 /* Make sure the calli field didn't overflow. */
860 tcg_debug_assert(s->gen_op_buf[i].calli == real_args);
861
862 s->gen_last_op_idx = i;
863 s->gen_next_op_idx = i + 1;
864 s->gen_next_parm_idx = pi;
2bece2c8 865
34b1a49c
RH
866#if defined(__sparc__) && !defined(__arch64__) \
867 && !defined(CONFIG_TCG_INTERPRETER)
868 /* Free all of the parts we allocated above. */
869 for (i = real_args = 0; i < orig_nargs; ++i) {
870 int is_64bit = orig_sizemask & (1 << (i+1)*2);
871 if (is_64bit) {
872 TCGv_i32 h = MAKE_TCGV_I32(args[real_args++]);
873 TCGv_i32 l = MAKE_TCGV_I32(args[real_args++]);
874 tcg_temp_free_i32(h);
875 tcg_temp_free_i32(l);
876 } else {
877 real_args++;
878 }
879 }
880 if (orig_sizemask & 1) {
881 /* The 32-bit ABI returned two 32-bit pieces. Re-assemble them.
882 Note that describing these as TCGv_i64 eliminates an unnecessary
883 zero-extension that tcg_gen_concat_i32_i64 would create. */
884 tcg_gen_concat32_i64(MAKE_TCGV_I64(ret), retl, reth);
885 tcg_temp_free_i64(retl);
886 tcg_temp_free_i64(reth);
887 }
888#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
2bece2c8
RH
889 for (i = 0; i < nargs; ++i) {
890 int is_64bit = sizemask & (1 << (i+1)*2);
891 if (!is_64bit) {
892 TCGv_i64 temp = MAKE_TCGV_I64(args[i]);
893 tcg_temp_free_i64(temp);
894 }
895 }
896#endif /* TCG_TARGET_EXTEND_ARGS */
c896fe29 897}
c896fe29 898
8fcd3692 899static void tcg_reg_alloc_start(TCGContext *s)
c896fe29
FB
900{
901 int i;
902 TCGTemp *ts;
903 for(i = 0; i < s->nb_globals; i++) {
904 ts = &s->temps[i];
905 if (ts->fixed_reg) {
906 ts->val_type = TEMP_VAL_REG;
907 } else {
908 ts->val_type = TEMP_VAL_MEM;
909 }
910 }
e8996ee0
FB
911 for(i = s->nb_globals; i < s->nb_temps; i++) {
912 ts = &s->temps[i];
7dfd8c6a
AJ
913 if (ts->temp_local) {
914 ts->val_type = TEMP_VAL_MEM;
915 } else {
916 ts->val_type = TEMP_VAL_DEAD;
917 }
e8996ee0
FB
918 ts->mem_allocated = 0;
919 ts->fixed_reg = 0;
920 }
c896fe29
FB
921 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
922 s->reg_to_temp[i] = -1;
923 }
924}
925
ac56dd48
PB
926static char *tcg_get_arg_str_idx(TCGContext *s, char *buf, int buf_size,
927 int idx)
c896fe29
FB
928{
929 TCGTemp *ts;
ac56dd48 930
7f6f0ae5 931 assert(idx >= 0 && idx < s->nb_temps);
ac56dd48
PB
932 ts = &s->temps[idx];
933 if (idx < s->nb_globals) {
934 pstrcpy(buf, buf_size, ts->name);
c896fe29 935 } else {
641d5fbe
FB
936 if (ts->temp_local)
937 snprintf(buf, buf_size, "loc%d", idx - s->nb_globals);
938 else
939 snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals);
c896fe29
FB
940 }
941 return buf;
942}
943
a7812ae4
PB
944char *tcg_get_arg_str_i32(TCGContext *s, char *buf, int buf_size, TCGv_i32 arg)
945{
946 return tcg_get_arg_str_idx(s, buf, buf_size, GET_TCGV_I32(arg));
947}
948
949char *tcg_get_arg_str_i64(TCGContext *s, char *buf, int buf_size, TCGv_i64 arg)
ac56dd48 950{
a810a2de 951 return tcg_get_arg_str_idx(s, buf, buf_size, GET_TCGV_I64(arg));
ac56dd48
PB
952}
953
6e085f72
RH
954/* Find helper name. */
955static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val)
4dc81f28 956{
6e085f72
RH
957 const char *ret = NULL;
958 if (s->helpers) {
72866e82
RH
959 TCGHelperInfo *info = g_hash_table_lookup(s->helpers, (gpointer)val);
960 if (info) {
961 ret = info->name;
962 }
4dc81f28 963 }
6e085f72 964 return ret;
4dc81f28
FB
965}
966
f48f3ede
BS
967static const char * const cond_name[] =
968{
0aed257f
RH
969 [TCG_COND_NEVER] = "never",
970 [TCG_COND_ALWAYS] = "always",
f48f3ede
BS
971 [TCG_COND_EQ] = "eq",
972 [TCG_COND_NE] = "ne",
973 [TCG_COND_LT] = "lt",
974 [TCG_COND_GE] = "ge",
975 [TCG_COND_LE] = "le",
976 [TCG_COND_GT] = "gt",
977 [TCG_COND_LTU] = "ltu",
978 [TCG_COND_GEU] = "geu",
979 [TCG_COND_LEU] = "leu",
980 [TCG_COND_GTU] = "gtu"
981};
982
f713d6ad
RH
983static const char * const ldst_name[] =
984{
985 [MO_UB] = "ub",
986 [MO_SB] = "sb",
987 [MO_LEUW] = "leuw",
988 [MO_LESW] = "lesw",
989 [MO_LEUL] = "leul",
990 [MO_LESL] = "lesl",
991 [MO_LEQ] = "leq",
992 [MO_BEUW] = "beuw",
993 [MO_BESW] = "besw",
994 [MO_BEUL] = "beul",
995 [MO_BESL] = "besl",
996 [MO_BEQ] = "beq",
997};
998
eeacee4d 999void tcg_dump_ops(TCGContext *s)
c896fe29 1000{
c896fe29 1001 char buf[128];
c45cb8bb
RH
1002 TCGOp *op;
1003 int oi;
1004
1005 for (oi = s->gen_first_op_idx; oi >= 0; oi = op->next) {
1006 int i, k, nb_oargs, nb_iargs, nb_cargs;
1007 const TCGOpDef *def;
1008 const TCGArg *args;
1009 TCGOpcode c;
c896fe29 1010
c45cb8bb
RH
1011 op = &s->gen_op_buf[oi];
1012 c = op->opc;
c896fe29 1013 def = &tcg_op_defs[c];
c45cb8bb
RH
1014 args = &s->gen_opparam_buf[op->args];
1015
765b842a 1016 if (c == INDEX_op_insn_start) {
9aef40ed
RH
1017 qemu_log("%s ----", oi != s->gen_first_op_idx ? "\n" : "");
1018
1019 for (i = 0; i < TARGET_INSN_START_WORDS; ++i) {
1020 target_ulong a;
7e4597d7 1021#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
9aef40ed 1022 a = ((target_ulong)args[i * 2 + 1] << 32) | args[i * 2];
7e4597d7 1023#else
9aef40ed 1024 a = args[i];
7e4597d7 1025#endif
9aef40ed 1026 qemu_log(" " TARGET_FMT_lx, a);
eeacee4d 1027 }
7e4597d7 1028 } else if (c == INDEX_op_call) {
c896fe29 1029 /* variable number of arguments */
c45cb8bb
RH
1030 nb_oargs = op->callo;
1031 nb_iargs = op->calli;
c896fe29 1032 nb_cargs = def->nb_cargs;
c896fe29 1033
cf066674
RH
1034 /* function name, flags, out args */
1035 qemu_log(" %s %s,$0x%" TCG_PRIlx ",$%d", def->name,
1036 tcg_find_helper(s, args[nb_oargs + nb_iargs]),
1037 args[nb_oargs + nb_iargs + 1], nb_oargs);
1038 for (i = 0; i < nb_oargs; i++) {
1039 qemu_log(",%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
eeacee4d 1040 args[i]));
b03cce8e 1041 }
cf066674
RH
1042 for (i = 0; i < nb_iargs; i++) {
1043 TCGArg arg = args[nb_oargs + i];
1044 const char *t = "<dummy>";
1045 if (arg != TCG_CALL_DUMMY_ARG) {
1046 t = tcg_get_arg_str_idx(s, buf, sizeof(buf), arg);
eeacee4d 1047 }
cf066674 1048 qemu_log(",%s", t);
e8996ee0 1049 }
b03cce8e 1050 } else {
eeacee4d 1051 qemu_log(" %s ", def->name);
c45cb8bb
RH
1052
1053 nb_oargs = def->nb_oargs;
1054 nb_iargs = def->nb_iargs;
1055 nb_cargs = def->nb_cargs;
1056
b03cce8e 1057 k = 0;
c45cb8bb 1058 for (i = 0; i < nb_oargs; i++) {
eeacee4d
BS
1059 if (k != 0) {
1060 qemu_log(",");
1061 }
1062 qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
1063 args[k++]));
b03cce8e 1064 }
c45cb8bb 1065 for (i = 0; i < nb_iargs; i++) {
eeacee4d
BS
1066 if (k != 0) {
1067 qemu_log(",");
1068 }
1069 qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
1070 args[k++]));
b03cce8e 1071 }
be210acb
RH
1072 switch (c) {
1073 case INDEX_op_brcond_i32:
be210acb 1074 case INDEX_op_setcond_i32:
ffc5ea09 1075 case INDEX_op_movcond_i32:
ffc5ea09 1076 case INDEX_op_brcond2_i32:
be210acb 1077 case INDEX_op_setcond2_i32:
ffc5ea09 1078 case INDEX_op_brcond_i64:
be210acb 1079 case INDEX_op_setcond_i64:
ffc5ea09 1080 case INDEX_op_movcond_i64:
eeacee4d
BS
1081 if (args[k] < ARRAY_SIZE(cond_name) && cond_name[args[k]]) {
1082 qemu_log(",%s", cond_name[args[k++]]);
1083 } else {
1084 qemu_log(",$0x%" TCG_PRIlx, args[k++]);
1085 }
f48f3ede 1086 i = 1;
be210acb 1087 break;
f713d6ad
RH
1088 case INDEX_op_qemu_ld_i32:
1089 case INDEX_op_qemu_st_i32:
1090 case INDEX_op_qemu_ld_i64:
1091 case INDEX_op_qemu_st_i64:
59227d5d
RH
1092 {
1093 TCGMemOpIdx oi = args[k++];
1094 TCGMemOp op = get_memop(oi);
1095 unsigned ix = get_mmuidx(oi);
1096
59c4b7e8 1097 if (op & ~(MO_AMASK | MO_BSWAP | MO_SSIZE)) {
59227d5d 1098 qemu_log(",$0x%x,%u", op, ix);
59c4b7e8
RH
1099 } else {
1100 const char *s_al = "", *s_op;
1101 if (op & MO_AMASK) {
1102 if ((op & MO_AMASK) == MO_ALIGN) {
1103 s_al = "al+";
1104 } else {
1105 s_al = "un+";
1106 }
1107 }
1108 s_op = ldst_name[op & (MO_BSWAP | MO_SSIZE)];
1109 qemu_log(",%s%s,%u", s_al, s_op, ix);
59227d5d
RH
1110 }
1111 i = 1;
f713d6ad 1112 }
f713d6ad 1113 break;
be210acb 1114 default:
f48f3ede 1115 i = 0;
be210acb
RH
1116 break;
1117 }
51e3972c
RH
1118 switch (c) {
1119 case INDEX_op_set_label:
1120 case INDEX_op_br:
1121 case INDEX_op_brcond_i32:
1122 case INDEX_op_brcond_i64:
1123 case INDEX_op_brcond2_i32:
1124 qemu_log("%s$L%d", k ? "," : "", arg_label(args[k])->id);
1125 i++, k++;
1126 break;
1127 default:
1128 break;
1129 }
1130 for (; i < nb_cargs; i++, k++) {
1131 qemu_log("%s$0x%" TCG_PRIlx, k ? "," : "", args[k]);
b03cce8e 1132 }
c896fe29 1133 }
eeacee4d 1134 qemu_log("\n");
c896fe29
FB
1135 }
1136}
1137
1138/* we give more priority to constraints with less registers */
1139static int get_constraint_priority(const TCGOpDef *def, int k)
1140{
1141 const TCGArgConstraint *arg_ct;
1142
1143 int i, n;
1144 arg_ct = &def->args_ct[k];
1145 if (arg_ct->ct & TCG_CT_ALIAS) {
1146 /* an alias is equivalent to a single register */
1147 n = 1;
1148 } else {
1149 if (!(arg_ct->ct & TCG_CT_REG))
1150 return 0;
1151 n = 0;
1152 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
1153 if (tcg_regset_test_reg(arg_ct->u.regs, i))
1154 n++;
1155 }
1156 }
1157 return TCG_TARGET_NB_REGS - n + 1;
1158}
1159
1160/* sort from highest priority to lowest */
1161static void sort_constraints(TCGOpDef *def, int start, int n)
1162{
1163 int i, j, p1, p2, tmp;
1164
1165 for(i = 0; i < n; i++)
1166 def->sorted_args[start + i] = start + i;
1167 if (n <= 1)
1168 return;
1169 for(i = 0; i < n - 1; i++) {
1170 for(j = i + 1; j < n; j++) {
1171 p1 = get_constraint_priority(def, def->sorted_args[start + i]);
1172 p2 = get_constraint_priority(def, def->sorted_args[start + j]);
1173 if (p1 < p2) {
1174 tmp = def->sorted_args[start + i];
1175 def->sorted_args[start + i] = def->sorted_args[start + j];
1176 def->sorted_args[start + j] = tmp;
1177 }
1178 }
1179 }
1180}
1181
1182void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs)
1183{
a9751609 1184 TCGOpcode op;
c896fe29
FB
1185 TCGOpDef *def;
1186 const char *ct_str;
1187 int i, nb_args;
1188
1189 for(;;) {
a9751609 1190 if (tdefs->op == (TCGOpcode)-1)
c896fe29
FB
1191 break;
1192 op = tdefs->op;
c3b08d0e 1193 assert((unsigned)op < NB_OPS);
c896fe29 1194 def = &tcg_op_defs[op];
c68aaa18
SW
1195#if defined(CONFIG_DEBUG_TCG)
1196 /* Duplicate entry in op definitions? */
1197 assert(!def->used);
1198 def->used = 1;
1199#endif
c896fe29
FB
1200 nb_args = def->nb_iargs + def->nb_oargs;
1201 for(i = 0; i < nb_args; i++) {
1202 ct_str = tdefs->args_ct_str[i];
c68aaa18
SW
1203 /* Incomplete TCGTargetOpDef entry? */
1204 assert(ct_str != NULL);
c896fe29
FB
1205 tcg_regset_clear(def->args_ct[i].u.regs);
1206 def->args_ct[i].ct = 0;
1207 if (ct_str[0] >= '0' && ct_str[0] <= '9') {
1208 int oarg;
1209 oarg = ct_str[0] - '0';
1210 assert(oarg < def->nb_oargs);
1211 assert(def->args_ct[oarg].ct & TCG_CT_REG);
1212 /* TCG_CT_ALIAS is for the output arguments. The input
5ff9d6a4 1213 argument is tagged with TCG_CT_IALIAS. */
c896fe29 1214 def->args_ct[i] = def->args_ct[oarg];
5ff9d6a4
FB
1215 def->args_ct[oarg].ct = TCG_CT_ALIAS;
1216 def->args_ct[oarg].alias_index = i;
c896fe29 1217 def->args_ct[i].ct |= TCG_CT_IALIAS;
5ff9d6a4 1218 def->args_ct[i].alias_index = oarg;
c896fe29
FB
1219 } else {
1220 for(;;) {
1221 if (*ct_str == '\0')
1222 break;
1223 switch(*ct_str) {
1224 case 'i':
1225 def->args_ct[i].ct |= TCG_CT_CONST;
1226 ct_str++;
1227 break;
1228 default:
1229 if (target_parse_constraint(&def->args_ct[i], &ct_str) < 0) {
1230 fprintf(stderr, "Invalid constraint '%s' for arg %d of operation '%s'\n",
1231 ct_str, i, def->name);
1232 exit(1);
1233 }
1234 }
1235 }
1236 }
1237 }
1238
c68aaa18
SW
1239 /* TCGTargetOpDef entry with too much information? */
1240 assert(i == TCG_MAX_OP_ARGS || tdefs->args_ct_str[i] == NULL);
1241
c896fe29
FB
1242 /* sort the constraints (XXX: this is just an heuristic) */
1243 sort_constraints(def, 0, def->nb_oargs);
1244 sort_constraints(def, def->nb_oargs, def->nb_iargs);
1245
1246#if 0
1247 {
1248 int i;
1249
1250 printf("%s: sorted=", def->name);
1251 for(i = 0; i < def->nb_oargs + def->nb_iargs; i++)
1252 printf(" %d", def->sorted_args[i]);
1253 printf("\n");
1254 }
1255#endif
1256 tdefs++;
1257 }
1258
c68aaa18 1259#if defined(CONFIG_DEBUG_TCG)
a9751609 1260 i = 0;
7d8f787d 1261 for (op = 0; op < tcg_op_defs_max; op++) {
f412c762 1262 const TCGOpDef *def = &tcg_op_defs[op];
c1a61f6c 1263 if (def->flags & TCG_OPF_NOT_PRESENT) {
c68aaa18 1264 /* Wrong entry in op definitions? */
f412c762
RH
1265 if (def->used) {
1266 fprintf(stderr, "Invalid op definition for %s\n", def->name);
a9751609
RH
1267 i = 1;
1268 }
c68aaa18
SW
1269 } else {
1270 /* Missing entry in op definitions? */
f412c762
RH
1271 if (!def->used) {
1272 fprintf(stderr, "Missing op definition for %s\n", def->name);
a9751609
RH
1273 i = 1;
1274 }
c68aaa18
SW
1275 }
1276 }
a9751609
RH
1277 if (i == 1) {
1278 tcg_abort();
1279 }
c68aaa18 1280#endif
c896fe29
FB
1281}
1282
0c627cdc
RH
1283void tcg_op_remove(TCGContext *s, TCGOp *op)
1284{
1285 int next = op->next;
1286 int prev = op->prev;
1287
1288 if (next >= 0) {
1289 s->gen_op_buf[next].prev = prev;
1290 } else {
1291 s->gen_last_op_idx = prev;
1292 }
1293 if (prev >= 0) {
1294 s->gen_op_buf[prev].next = next;
1295 } else {
1296 s->gen_first_op_idx = next;
1297 }
1298
15fc7daa 1299 memset(op, -1, sizeof(*op));
0c627cdc
RH
1300
1301#ifdef CONFIG_PROFILER
1302 s->del_op_count++;
1303#endif
1304}
1305
c896fe29 1306#ifdef USE_LIVENESS_ANALYSIS
9c43b68d
AJ
1307/* liveness analysis: end of function: all temps are dead, and globals
1308 should be in memory. */
1309static inline void tcg_la_func_end(TCGContext *s, uint8_t *dead_temps,
1310 uint8_t *mem_temps)
c896fe29 1311{
9c43b68d
AJ
1312 memset(dead_temps, 1, s->nb_temps);
1313 memset(mem_temps, 1, s->nb_globals);
1314 memset(mem_temps + s->nb_globals, 0, s->nb_temps - s->nb_globals);
c896fe29
FB
1315}
1316
9c43b68d
AJ
1317/* liveness analysis: end of basic block: all temps are dead, globals
1318 and local temps should be in memory. */
1319static inline void tcg_la_bb_end(TCGContext *s, uint8_t *dead_temps,
1320 uint8_t *mem_temps)
641d5fbe
FB
1321{
1322 int i;
641d5fbe 1323
9c43b68d
AJ
1324 memset(dead_temps, 1, s->nb_temps);
1325 memset(mem_temps, 1, s->nb_globals);
641d5fbe 1326 for(i = s->nb_globals; i < s->nb_temps; i++) {
9c43b68d 1327 mem_temps[i] = s->temps[i].temp_local;
641d5fbe
FB
1328 }
1329}
1330
866cb6cb 1331/* Liveness analysis : update the opc_dead_args array to tell if a
c896fe29
FB
1332 given input arguments is dead. Instructions updating dead
1333 temporaries are removed. */
8fcd3692 1334static void tcg_liveness_analysis(TCGContext *s)
c896fe29 1335{
9c43b68d 1336 uint8_t *dead_temps, *mem_temps;
c45cb8bb 1337 int oi, oi_prev, nb_ops;
c896fe29 1338
c45cb8bb 1339 nb_ops = s->gen_next_op_idx;
866cb6cb 1340 s->op_dead_args = tcg_malloc(nb_ops * sizeof(uint16_t));
ec7a869d 1341 s->op_sync_args = tcg_malloc(nb_ops * sizeof(uint8_t));
c896fe29
FB
1342
1343 dead_temps = tcg_malloc(s->nb_temps);
9c43b68d
AJ
1344 mem_temps = tcg_malloc(s->nb_temps);
1345 tcg_la_func_end(s, dead_temps, mem_temps);
c896fe29 1346
c45cb8bb
RH
1347 for (oi = s->gen_last_op_idx; oi >= 0; oi = oi_prev) {
1348 int i, nb_iargs, nb_oargs;
1349 TCGOpcode opc_new, opc_new2;
1350 bool have_opc_new2;
1351 uint16_t dead_args;
1352 uint8_t sync_args;
1353 TCGArg arg;
1354
1355 TCGOp * const op = &s->gen_op_buf[oi];
1356 TCGArg * const args = &s->gen_opparam_buf[op->args];
1357 TCGOpcode opc = op->opc;
1358 const TCGOpDef *def = &tcg_op_defs[opc];
1359
1360 oi_prev = op->prev;
1361
1362 switch (opc) {
c896fe29 1363 case INDEX_op_call:
c6e113f5
FB
1364 {
1365 int call_flags;
c896fe29 1366
c45cb8bb
RH
1367 nb_oargs = op->callo;
1368 nb_iargs = op->calli;
cf066674 1369 call_flags = args[nb_oargs + nb_iargs + 1];
c6e113f5 1370
c45cb8bb 1371 /* pure functions can be removed if their result is unused */
78505279 1372 if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) {
cf066674 1373 for (i = 0; i < nb_oargs; i++) {
c6e113f5 1374 arg = args[i];
9c43b68d 1375 if (!dead_temps[arg] || mem_temps[arg]) {
c6e113f5 1376 goto do_not_remove_call;
9c43b68d 1377 }
c6e113f5 1378 }
c45cb8bb 1379 goto do_remove;
c6e113f5
FB
1380 } else {
1381 do_not_remove_call:
c896fe29 1382
c6e113f5 1383 /* output args are dead */
6b64b624 1384 dead_args = 0;
ec7a869d 1385 sync_args = 0;
cf066674 1386 for (i = 0; i < nb_oargs; i++) {
c6e113f5 1387 arg = args[i];
6b64b624
AJ
1388 if (dead_temps[arg]) {
1389 dead_args |= (1 << i);
1390 }
9c43b68d
AJ
1391 if (mem_temps[arg]) {
1392 sync_args |= (1 << i);
1393 }
c6e113f5 1394 dead_temps[arg] = 1;
9c43b68d 1395 mem_temps[arg] = 0;
c6e113f5 1396 }
78505279
AJ
1397
1398 if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) {
1399 /* globals should be synced to memory */
1400 memset(mem_temps, 1, s->nb_globals);
1401 }
1402 if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS |
1403 TCG_CALL_NO_READ_GLOBALS))) {
9c43b68d
AJ
1404 /* globals should go back to memory */
1405 memset(dead_temps, 1, s->nb_globals);
b9c18f56
AJ
1406 }
1407
c19f47bf 1408 /* record arguments that die in this helper */
cf066674 1409 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
866cb6cb 1410 arg = args[i];
39cf05d3
FB
1411 if (arg != TCG_CALL_DUMMY_ARG) {
1412 if (dead_temps[arg]) {
866cb6cb 1413 dead_args |= (1 << i);
39cf05d3 1414 }
c6e113f5 1415 }
c6e113f5 1416 }
67cc32eb 1417 /* input arguments are live for preceding opcodes */
c19f47bf
AJ
1418 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
1419 arg = args[i];
1420 dead_temps[arg] = 0;
1421 }
c45cb8bb
RH
1422 s->op_dead_args[oi] = dead_args;
1423 s->op_sync_args[oi] = sync_args;
c896fe29 1424 }
c896fe29 1425 }
c896fe29 1426 break;
765b842a 1427 case INDEX_op_insn_start:
c896fe29 1428 break;
5ff9d6a4 1429 case INDEX_op_discard:
5ff9d6a4
FB
1430 /* mark the temporary as dead */
1431 dead_temps[args[0]] = 1;
9c43b68d 1432 mem_temps[args[0]] = 0;
5ff9d6a4 1433 break;
1305c451
RH
1434
1435 case INDEX_op_add2_i32:
c45cb8bb 1436 opc_new = INDEX_op_add_i32;
f1fae40c 1437 goto do_addsub2;
1305c451 1438 case INDEX_op_sub2_i32:
c45cb8bb 1439 opc_new = INDEX_op_sub_i32;
f1fae40c
RH
1440 goto do_addsub2;
1441 case INDEX_op_add2_i64:
c45cb8bb 1442 opc_new = INDEX_op_add_i64;
f1fae40c
RH
1443 goto do_addsub2;
1444 case INDEX_op_sub2_i64:
c45cb8bb 1445 opc_new = INDEX_op_sub_i64;
f1fae40c 1446 do_addsub2:
1305c451
RH
1447 nb_iargs = 4;
1448 nb_oargs = 2;
1449 /* Test if the high part of the operation is dead, but not
1450 the low part. The result can be optimized to a simple
1451 add or sub. This happens often for x86_64 guest when the
1452 cpu mode is set to 32 bit. */
3c5645fa
KB
1453 if (dead_temps[args[1]] && !mem_temps[args[1]]) {
1454 if (dead_temps[args[0]] && !mem_temps[args[0]]) {
1305c451
RH
1455 goto do_remove;
1456 }
c45cb8bb
RH
1457 /* Replace the opcode and adjust the args in place,
1458 leaving 3 unused args at the end. */
1459 op->opc = opc = opc_new;
1305c451
RH
1460 args[1] = args[2];
1461 args[2] = args[4];
1305c451
RH
1462 /* Fall through and mark the single-word operation live. */
1463 nb_iargs = 2;
1464 nb_oargs = 1;
1465 }
1466 goto do_not_remove;
1467
1414968a 1468 case INDEX_op_mulu2_i32:
c45cb8bb
RH
1469 opc_new = INDEX_op_mul_i32;
1470 opc_new2 = INDEX_op_muluh_i32;
1471 have_opc_new2 = TCG_TARGET_HAS_muluh_i32;
03271524 1472 goto do_mul2;
f1fae40c 1473 case INDEX_op_muls2_i32:
c45cb8bb
RH
1474 opc_new = INDEX_op_mul_i32;
1475 opc_new2 = INDEX_op_mulsh_i32;
1476 have_opc_new2 = TCG_TARGET_HAS_mulsh_i32;
f1fae40c
RH
1477 goto do_mul2;
1478 case INDEX_op_mulu2_i64:
c45cb8bb
RH
1479 opc_new = INDEX_op_mul_i64;
1480 opc_new2 = INDEX_op_muluh_i64;
1481 have_opc_new2 = TCG_TARGET_HAS_muluh_i64;
03271524 1482 goto do_mul2;
f1fae40c 1483 case INDEX_op_muls2_i64:
c45cb8bb
RH
1484 opc_new = INDEX_op_mul_i64;
1485 opc_new2 = INDEX_op_mulsh_i64;
1486 have_opc_new2 = TCG_TARGET_HAS_mulsh_i64;
03271524 1487 goto do_mul2;
f1fae40c 1488 do_mul2:
1414968a
RH
1489 nb_iargs = 2;
1490 nb_oargs = 2;
3c5645fa
KB
1491 if (dead_temps[args[1]] && !mem_temps[args[1]]) {
1492 if (dead_temps[args[0]] && !mem_temps[args[0]]) {
03271524 1493 /* Both parts of the operation are dead. */
1414968a
RH
1494 goto do_remove;
1495 }
03271524 1496 /* The high part of the operation is dead; generate the low. */
c45cb8bb 1497 op->opc = opc = opc_new;
1414968a
RH
1498 args[1] = args[2];
1499 args[2] = args[3];
c45cb8bb 1500 } else if (have_opc_new2 && dead_temps[args[0]]
03271524 1501 && !mem_temps[args[0]]) {
c45cb8bb
RH
1502 /* The low part of the operation is dead; generate the high. */
1503 op->opc = opc = opc_new2;
03271524
RH
1504 args[0] = args[1];
1505 args[1] = args[2];
1506 args[2] = args[3];
1507 } else {
1508 goto do_not_remove;
1414968a 1509 }
03271524
RH
1510 /* Mark the single-word operation live. */
1511 nb_oargs = 1;
1414968a
RH
1512 goto do_not_remove;
1513
c896fe29 1514 default:
1305c451 1515 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
49516bc0
AJ
1516 nb_iargs = def->nb_iargs;
1517 nb_oargs = def->nb_oargs;
c896fe29 1518
49516bc0
AJ
1519 /* Test if the operation can be removed because all
1520 its outputs are dead. We assume that nb_oargs == 0
1521 implies side effects */
1522 if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) {
c45cb8bb 1523 for (i = 0; i < nb_oargs; i++) {
49516bc0 1524 arg = args[i];
9c43b68d 1525 if (!dead_temps[arg] || mem_temps[arg]) {
49516bc0 1526 goto do_not_remove;
9c43b68d 1527 }
49516bc0 1528 }
1305c451 1529 do_remove:
0c627cdc 1530 tcg_op_remove(s, op);
49516bc0
AJ
1531 } else {
1532 do_not_remove:
49516bc0 1533 /* output args are dead */
6b64b624 1534 dead_args = 0;
ec7a869d 1535 sync_args = 0;
c45cb8bb 1536 for (i = 0; i < nb_oargs; i++) {
49516bc0 1537 arg = args[i];
6b64b624
AJ
1538 if (dead_temps[arg]) {
1539 dead_args |= (1 << i);
1540 }
9c43b68d
AJ
1541 if (mem_temps[arg]) {
1542 sync_args |= (1 << i);
1543 }
49516bc0 1544 dead_temps[arg] = 1;
9c43b68d 1545 mem_temps[arg] = 0;
49516bc0
AJ
1546 }
1547
1548 /* if end of basic block, update */
1549 if (def->flags & TCG_OPF_BB_END) {
9c43b68d 1550 tcg_la_bb_end(s, dead_temps, mem_temps);
3d5c5f87
AJ
1551 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) {
1552 /* globals should be synced to memory */
9c43b68d 1553 memset(mem_temps, 1, s->nb_globals);
49516bc0
AJ
1554 }
1555
c19f47bf 1556 /* record arguments that die in this opcode */
c45cb8bb 1557 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
866cb6cb 1558 arg = args[i];
49516bc0 1559 if (dead_temps[arg]) {
866cb6cb 1560 dead_args |= (1 << i);
c896fe29 1561 }
c19f47bf 1562 }
67cc32eb 1563 /* input arguments are live for preceding opcodes */
c19f47bf
AJ
1564 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
1565 arg = args[i];
49516bc0 1566 dead_temps[arg] = 0;
c896fe29 1567 }
c45cb8bb
RH
1568 s->op_dead_args[oi] = dead_args;
1569 s->op_sync_args[oi] = sync_args;
c896fe29
FB
1570 }
1571 break;
1572 }
1ff0a2c5 1573 }
c896fe29
FB
1574}
1575#else
1576/* dummy liveness analysis */
655feed5 1577static void tcg_liveness_analysis(TCGContext *s)
c896fe29
FB
1578{
1579 int nb_ops;
92414b31 1580 nb_ops = s->gen_opc_ptr - s->gen_opc_buf;
c896fe29 1581
866cb6cb
AJ
1582 s->op_dead_args = tcg_malloc(nb_ops * sizeof(uint16_t));
1583 memset(s->op_dead_args, 0, nb_ops * sizeof(uint16_t));
ec7a869d
AJ
1584 s->op_sync_args = tcg_malloc(nb_ops * sizeof(uint8_t));
1585 memset(s->op_sync_args, 0, nb_ops * sizeof(uint8_t));
c896fe29
FB
1586}
1587#endif
1588
1589#ifndef NDEBUG
1590static void dump_regs(TCGContext *s)
1591{
1592 TCGTemp *ts;
1593 int i;
1594 char buf[64];
1595
1596 for(i = 0; i < s->nb_temps; i++) {
1597 ts = &s->temps[i];
ac56dd48 1598 printf(" %10s: ", tcg_get_arg_str_idx(s, buf, sizeof(buf), i));
c896fe29
FB
1599 switch(ts->val_type) {
1600 case TEMP_VAL_REG:
1601 printf("%s", tcg_target_reg_names[ts->reg]);
1602 break;
1603 case TEMP_VAL_MEM:
1604 printf("%d(%s)", (int)ts->mem_offset, tcg_target_reg_names[ts->mem_reg]);
1605 break;
1606 case TEMP_VAL_CONST:
1607 printf("$0x%" TCG_PRIlx, ts->val);
1608 break;
1609 case TEMP_VAL_DEAD:
1610 printf("D");
1611 break;
1612 default:
1613 printf("???");
1614 break;
1615 }
1616 printf("\n");
1617 }
1618
1619 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
1620 if (s->reg_to_temp[i] >= 0) {
1621 printf("%s: %s\n",
1622 tcg_target_reg_names[i],
ac56dd48 1623 tcg_get_arg_str_idx(s, buf, sizeof(buf), s->reg_to_temp[i]));
c896fe29
FB
1624 }
1625 }
1626}
1627
1628static void check_regs(TCGContext *s)
1629{
1630 int reg, k;
1631 TCGTemp *ts;
1632 char buf[64];
1633
1634 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
1635 k = s->reg_to_temp[reg];
1636 if (k >= 0) {
1637 ts = &s->temps[k];
1638 if (ts->val_type != TEMP_VAL_REG ||
1639 ts->reg != reg) {
1640 printf("Inconsistency for register %s:\n",
1641 tcg_target_reg_names[reg]);
b03cce8e 1642 goto fail;
c896fe29
FB
1643 }
1644 }
1645 }
1646 for(k = 0; k < s->nb_temps; k++) {
1647 ts = &s->temps[k];
1648 if (ts->val_type == TEMP_VAL_REG &&
1649 !ts->fixed_reg &&
1650 s->reg_to_temp[ts->reg] != k) {
1651 printf("Inconsistency for temp %s:\n",
ac56dd48 1652 tcg_get_arg_str_idx(s, buf, sizeof(buf), k));
b03cce8e 1653 fail:
c896fe29
FB
1654 printf("reg state:\n");
1655 dump_regs(s);
1656 tcg_abort();
1657 }
1658 }
1659}
1660#endif
1661
1662static void temp_allocate_frame(TCGContext *s, int temp)
1663{
1664 TCGTemp *ts;
1665 ts = &s->temps[temp];
9b9c37c3
RH
1666#if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64)
1667 /* Sparc64 stack is accessed with offset of 2047 */
b591dc59
BS
1668 s->current_frame_offset = (s->current_frame_offset +
1669 (tcg_target_long)sizeof(tcg_target_long) - 1) &
1670 ~(sizeof(tcg_target_long) - 1);
f44c9960 1671#endif
b591dc59
BS
1672 if (s->current_frame_offset + (tcg_target_long)sizeof(tcg_target_long) >
1673 s->frame_end) {
5ff9d6a4 1674 tcg_abort();
b591dc59 1675 }
c896fe29
FB
1676 ts->mem_offset = s->current_frame_offset;
1677 ts->mem_reg = s->frame_reg;
1678 ts->mem_allocated = 1;
e2c6d1b4 1679 s->current_frame_offset += sizeof(tcg_target_long);
c896fe29
FB
1680}
1681
7f6ceedf
AJ
1682/* sync register 'reg' by saving it to the corresponding temporary */
1683static inline void tcg_reg_sync(TCGContext *s, int reg)
1684{
1685 TCGTemp *ts;
1686 int temp;
1687
1688 temp = s->reg_to_temp[reg];
1689 ts = &s->temps[temp];
1690 assert(ts->val_type == TEMP_VAL_REG);
1691 if (!ts->mem_coherent && !ts->fixed_reg) {
1692 if (!ts->mem_allocated) {
1693 temp_allocate_frame(s, temp);
1694 }
1695 tcg_out_st(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
1696 }
1697 ts->mem_coherent = 1;
1698}
1699
c896fe29
FB
1700/* free register 'reg' by spilling the corresponding temporary if necessary */
1701static void tcg_reg_free(TCGContext *s, int reg)
1702{
c896fe29
FB
1703 int temp;
1704
1705 temp = s->reg_to_temp[reg];
1706 if (temp != -1) {
7f6ceedf
AJ
1707 tcg_reg_sync(s, reg);
1708 s->temps[temp].val_type = TEMP_VAL_MEM;
c896fe29
FB
1709 s->reg_to_temp[reg] = -1;
1710 }
1711}
1712
1713/* Allocate a register belonging to reg1 & ~reg2 */
1714static int tcg_reg_alloc(TCGContext *s, TCGRegSet reg1, TCGRegSet reg2)
1715{
1716 int i, reg;
1717 TCGRegSet reg_ct;
1718
1719 tcg_regset_andnot(reg_ct, reg1, reg2);
1720
1721 /* first try free registers */
0954d0d9 1722 for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
c896fe29
FB
1723 reg = tcg_target_reg_alloc_order[i];
1724 if (tcg_regset_test_reg(reg_ct, reg) && s->reg_to_temp[reg] == -1)
1725 return reg;
1726 }
1727
1728 /* XXX: do better spill choice */
0954d0d9 1729 for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
c896fe29
FB
1730 reg = tcg_target_reg_alloc_order[i];
1731 if (tcg_regset_test_reg(reg_ct, reg)) {
1732 tcg_reg_free(s, reg);
1733 return reg;
1734 }
1735 }
1736
1737 tcg_abort();
1738}
1739
639368dd
AJ
1740/* mark a temporary as dead. */
1741static inline void temp_dead(TCGContext *s, int temp)
1742{
1743 TCGTemp *ts;
1744
1745 ts = &s->temps[temp];
1746 if (!ts->fixed_reg) {
1747 if (ts->val_type == TEMP_VAL_REG) {
1748 s->reg_to_temp[ts->reg] = -1;
1749 }
e5138db5 1750 if (temp < s->nb_globals || ts->temp_local) {
639368dd
AJ
1751 ts->val_type = TEMP_VAL_MEM;
1752 } else {
1753 ts->val_type = TEMP_VAL_DEAD;
1754 }
1755 }
1756}
1757
1ad80729 1758/* sync a temporary to memory. 'allocated_regs' is used in case a
641d5fbe 1759 temporary registers needs to be allocated to store a constant. */
1ad80729 1760static inline void temp_sync(TCGContext *s, int temp, TCGRegSet allocated_regs)
641d5fbe
FB
1761{
1762 TCGTemp *ts;
641d5fbe
FB
1763
1764 ts = &s->temps[temp];
1765 if (!ts->fixed_reg) {
1766 switch(ts->val_type) {
1ad80729
AJ
1767 case TEMP_VAL_CONST:
1768 ts->reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
1769 allocated_regs);
1770 ts->val_type = TEMP_VAL_REG;
1771 s->reg_to_temp[ts->reg] = temp;
1772 ts->mem_coherent = 0;
1773 tcg_out_movi(s, ts->type, ts->reg, ts->val);
1774 /* fallthrough*/
641d5fbe 1775 case TEMP_VAL_REG:
1ad80729 1776 tcg_reg_sync(s, ts->reg);
641d5fbe
FB
1777 break;
1778 case TEMP_VAL_DEAD:
641d5fbe
FB
1779 case TEMP_VAL_MEM:
1780 break;
1781 default:
1782 tcg_abort();
1783 }
1784 }
1785}
1786
1ad80729
AJ
1787/* save a temporary to memory. 'allocated_regs' is used in case a
1788 temporary registers needs to be allocated to store a constant. */
1789static inline void temp_save(TCGContext *s, int temp, TCGRegSet allocated_regs)
1790{
2c0366f0
AJ
1791#ifdef USE_LIVENESS_ANALYSIS
1792 /* The liveness analysis already ensures that globals are back
1793 in memory. Keep an assert for safety. */
1794 assert(s->temps[temp].val_type == TEMP_VAL_MEM || s->temps[temp].fixed_reg);
1795#else
1ad80729
AJ
1796 temp_sync(s, temp, allocated_regs);
1797 temp_dead(s, temp);
2c0366f0 1798#endif
1ad80729
AJ
1799}
1800
9814dd27 1801/* save globals to their canonical location and assume they can be
e8996ee0
FB
1802 modified be the following code. 'allocated_regs' is used in case a
1803 temporary registers needs to be allocated to store a constant. */
1804static void save_globals(TCGContext *s, TCGRegSet allocated_regs)
c896fe29 1805{
641d5fbe 1806 int i;
c896fe29
FB
1807
1808 for(i = 0; i < s->nb_globals; i++) {
641d5fbe 1809 temp_save(s, i, allocated_regs);
c896fe29 1810 }
e5097dc8
FB
1811}
1812
3d5c5f87
AJ
1813/* sync globals to their canonical location and assume they can be
1814 read by the following code. 'allocated_regs' is used in case a
1815 temporary registers needs to be allocated to store a constant. */
1816static void sync_globals(TCGContext *s, TCGRegSet allocated_regs)
1817{
1818 int i;
1819
1820 for (i = 0; i < s->nb_globals; i++) {
1821#ifdef USE_LIVENESS_ANALYSIS
1822 assert(s->temps[i].val_type != TEMP_VAL_REG || s->temps[i].fixed_reg ||
1823 s->temps[i].mem_coherent);
1824#else
1825 temp_sync(s, i, allocated_regs);
1826#endif
1827 }
1828}
1829
e5097dc8 1830/* at the end of a basic block, we assume all temporaries are dead and
e8996ee0
FB
1831 all globals are stored at their canonical location. */
1832static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs)
e5097dc8
FB
1833{
1834 TCGTemp *ts;
1835 int i;
1836
c896fe29
FB
1837 for(i = s->nb_globals; i < s->nb_temps; i++) {
1838 ts = &s->temps[i];
641d5fbe
FB
1839 if (ts->temp_local) {
1840 temp_save(s, i, allocated_regs);
1841 } else {
2c0366f0
AJ
1842#ifdef USE_LIVENESS_ANALYSIS
1843 /* The liveness analysis already ensures that temps are dead.
1844 Keep an assert for safety. */
1845 assert(ts->val_type == TEMP_VAL_DEAD);
1846#else
639368dd 1847 temp_dead(s, i);
2c0366f0 1848#endif
c896fe29
FB
1849 }
1850 }
e8996ee0
FB
1851
1852 save_globals(s, allocated_regs);
c896fe29
FB
1853}
1854
866cb6cb 1855#define IS_DEAD_ARG(n) ((dead_args >> (n)) & 1)
ec7a869d 1856#define NEED_SYNC_ARG(n) ((sync_args >> (n)) & 1)
c896fe29 1857
ec7a869d
AJ
1858static void tcg_reg_alloc_movi(TCGContext *s, const TCGArg *args,
1859 uint16_t dead_args, uint8_t sync_args)
e8996ee0
FB
1860{
1861 TCGTemp *ots;
1862 tcg_target_ulong val;
1863
1864 ots = &s->temps[args[0]];
1865 val = args[1];
1866
1867 if (ots->fixed_reg) {
1868 /* for fixed registers, we do not do any constant
1869 propagation */
1870 tcg_out_movi(s, ots->type, ots->reg, val);
1871 } else {
1235fc06 1872 /* The movi is not explicitly generated here */
e8996ee0
FB
1873 if (ots->val_type == TEMP_VAL_REG)
1874 s->reg_to_temp[ots->reg] = -1;
1875 ots->val_type = TEMP_VAL_CONST;
1876 ots->val = val;
1877 }
ec7a869d
AJ
1878 if (NEED_SYNC_ARG(0)) {
1879 temp_sync(s, args[0], s->reserved_regs);
1880 }
4c4e1ab2
AJ
1881 if (IS_DEAD_ARG(0)) {
1882 temp_dead(s, args[0]);
1883 }
e8996ee0
FB
1884}
1885
c896fe29 1886static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
ec7a869d
AJ
1887 const TCGArg *args, uint16_t dead_args,
1888 uint8_t sync_args)
c896fe29 1889{
c29c1d7e 1890 TCGRegSet allocated_regs;
c896fe29 1891 TCGTemp *ts, *ots;
450445d5 1892 TCGType otype, itype;
c896fe29 1893
c29c1d7e 1894 tcg_regset_set(allocated_regs, s->reserved_regs);
c896fe29
FB
1895 ots = &s->temps[args[0]];
1896 ts = &s->temps[args[1]];
450445d5
RH
1897
1898 /* Note that otype != itype for no-op truncation. */
1899 otype = ots->type;
1900 itype = ts->type;
c29c1d7e
AJ
1901
1902 /* If the source value is not in a register, and we're going to be
1903 forced to have it in a register in order to perform the copy,
1904 then copy the SOURCE value into its own register first. That way
1905 we don't have to reload SOURCE the next time it is used. */
1906 if (((NEED_SYNC_ARG(0) || ots->fixed_reg) && ts->val_type != TEMP_VAL_REG)
1907 || ts->val_type == TEMP_VAL_MEM) {
450445d5 1908 ts->reg = tcg_reg_alloc(s, tcg_target_available_regs[itype],
af3cbfbe 1909 allocated_regs);
c29c1d7e 1910 if (ts->val_type == TEMP_VAL_MEM) {
450445d5 1911 tcg_out_ld(s, itype, ts->reg, ts->mem_reg, ts->mem_offset);
c29c1d7e
AJ
1912 ts->mem_coherent = 1;
1913 } else if (ts->val_type == TEMP_VAL_CONST) {
450445d5 1914 tcg_out_movi(s, itype, ts->reg, ts->val);
bbeb8239 1915 ts->mem_coherent = 0;
c29c1d7e
AJ
1916 }
1917 s->reg_to_temp[ts->reg] = args[1];
1918 ts->val_type = TEMP_VAL_REG;
1919 }
c896fe29 1920
c29c1d7e
AJ
1921 if (IS_DEAD_ARG(0) && !ots->fixed_reg) {
1922 /* mov to a non-saved dead register makes no sense (even with
1923 liveness analysis disabled). */
1924 assert(NEED_SYNC_ARG(0));
1925 /* The code above should have moved the temp to a register. */
1926 assert(ts->val_type == TEMP_VAL_REG);
1927 if (!ots->mem_allocated) {
1928 temp_allocate_frame(s, args[0]);
1929 }
450445d5 1930 tcg_out_st(s, otype, ts->reg, ots->mem_reg, ots->mem_offset);
c29c1d7e
AJ
1931 if (IS_DEAD_ARG(1)) {
1932 temp_dead(s, args[1]);
1933 }
1934 temp_dead(s, args[0]);
1935 } else if (ts->val_type == TEMP_VAL_CONST) {
1936 /* propagate constant */
1937 if (ots->val_type == TEMP_VAL_REG) {
1938 s->reg_to_temp[ots->reg] = -1;
1939 }
1940 ots->val_type = TEMP_VAL_CONST;
1941 ots->val = ts->val;
7df69dea
AJ
1942 if (IS_DEAD_ARG(1)) {
1943 temp_dead(s, args[1]);
1944 }
c29c1d7e
AJ
1945 } else {
1946 /* The code in the first if block should have moved the
1947 temp to a register. */
1948 assert(ts->val_type == TEMP_VAL_REG);
866cb6cb 1949 if (IS_DEAD_ARG(1) && !ts->fixed_reg && !ots->fixed_reg) {
c896fe29 1950 /* the mov can be suppressed */
c29c1d7e 1951 if (ots->val_type == TEMP_VAL_REG) {
c896fe29 1952 s->reg_to_temp[ots->reg] = -1;
c29c1d7e
AJ
1953 }
1954 ots->reg = ts->reg;
639368dd 1955 temp_dead(s, args[1]);
c896fe29 1956 } else {
c29c1d7e
AJ
1957 if (ots->val_type != TEMP_VAL_REG) {
1958 /* When allocating a new register, make sure to not spill the
1959 input one. */
1960 tcg_regset_set_reg(allocated_regs, ts->reg);
450445d5 1961 ots->reg = tcg_reg_alloc(s, tcg_target_available_regs[otype],
af3cbfbe 1962 allocated_regs);
c896fe29 1963 }
450445d5 1964 tcg_out_mov(s, otype, ots->reg, ts->reg);
c896fe29 1965 }
c29c1d7e
AJ
1966 ots->val_type = TEMP_VAL_REG;
1967 ots->mem_coherent = 0;
1968 s->reg_to_temp[ots->reg] = args[0];
1969 if (NEED_SYNC_ARG(0)) {
1970 tcg_reg_sync(s, ots->reg);
c896fe29 1971 }
ec7a869d 1972 }
c896fe29
FB
1973}
1974
1975static void tcg_reg_alloc_op(TCGContext *s,
a9751609 1976 const TCGOpDef *def, TCGOpcode opc,
ec7a869d
AJ
1977 const TCGArg *args, uint16_t dead_args,
1978 uint8_t sync_args)
c896fe29
FB
1979{
1980 TCGRegSet allocated_regs;
1981 int i, k, nb_iargs, nb_oargs, reg;
1982 TCGArg arg;
1983 const TCGArgConstraint *arg_ct;
1984 TCGTemp *ts;
1985 TCGArg new_args[TCG_MAX_OP_ARGS];
1986 int const_args[TCG_MAX_OP_ARGS];
1987
1988 nb_oargs = def->nb_oargs;
1989 nb_iargs = def->nb_iargs;
1990
1991 /* copy constants */
1992 memcpy(new_args + nb_oargs + nb_iargs,
1993 args + nb_oargs + nb_iargs,
1994 sizeof(TCGArg) * def->nb_cargs);
1995
1996 /* satisfy input constraints */
1997 tcg_regset_set(allocated_regs, s->reserved_regs);
1998 for(k = 0; k < nb_iargs; k++) {
1999 i = def->sorted_args[nb_oargs + k];
2000 arg = args[i];
2001 arg_ct = &def->args_ct[i];
2002 ts = &s->temps[arg];
2003 if (ts->val_type == TEMP_VAL_MEM) {
2004 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
e4d5434c 2005 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
c896fe29
FB
2006 ts->val_type = TEMP_VAL_REG;
2007 ts->reg = reg;
2008 ts->mem_coherent = 1;
2009 s->reg_to_temp[reg] = arg;
2010 } else if (ts->val_type == TEMP_VAL_CONST) {
f6c6afc1 2011 if (tcg_target_const_match(ts->val, ts->type, arg_ct)) {
c896fe29
FB
2012 /* constant is OK for instruction */
2013 const_args[i] = 1;
2014 new_args[i] = ts->val;
2015 goto iarg_end;
2016 } else {
e8996ee0 2017 /* need to move to a register */
c896fe29
FB
2018 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
2019 tcg_out_movi(s, ts->type, reg, ts->val);
e8996ee0
FB
2020 ts->val_type = TEMP_VAL_REG;
2021 ts->reg = reg;
2022 ts->mem_coherent = 0;
2023 s->reg_to_temp[reg] = arg;
c896fe29
FB
2024 }
2025 }
2026 assert(ts->val_type == TEMP_VAL_REG);
5ff9d6a4
FB
2027 if (arg_ct->ct & TCG_CT_IALIAS) {
2028 if (ts->fixed_reg) {
2029 /* if fixed register, we must allocate a new register
2030 if the alias is not the same register */
2031 if (arg != args[arg_ct->alias_index])
2032 goto allocate_in_reg;
2033 } else {
2034 /* if the input is aliased to an output and if it is
2035 not dead after the instruction, we must allocate
2036 a new register and move it */
866cb6cb 2037 if (!IS_DEAD_ARG(i)) {
5ff9d6a4 2038 goto allocate_in_reg;
866cb6cb 2039 }
7e1df267
AJ
2040 /* check if the current register has already been allocated
2041 for another input aliased to an output */
2042 int k2, i2;
2043 for (k2 = 0 ; k2 < k ; k2++) {
2044 i2 = def->sorted_args[nb_oargs + k2];
2045 if ((def->args_ct[i2].ct & TCG_CT_IALIAS) &&
2046 (new_args[i2] == ts->reg)) {
2047 goto allocate_in_reg;
2048 }
2049 }
5ff9d6a4 2050 }
c896fe29
FB
2051 }
2052 reg = ts->reg;
2053 if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {
2054 /* nothing to do : the constraint is satisfied */
2055 } else {
2056 allocate_in_reg:
2057 /* allocate a new register matching the constraint
2058 and move the temporary register into it */
2059 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
3b6dac34 2060 tcg_out_mov(s, ts->type, reg, ts->reg);
c896fe29 2061 }
c896fe29
FB
2062 new_args[i] = reg;
2063 const_args[i] = 0;
2064 tcg_regset_set_reg(allocated_regs, reg);
2065 iarg_end: ;
2066 }
2067
a52ad07e
AJ
2068 /* mark dead temporaries and free the associated registers */
2069 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
2070 if (IS_DEAD_ARG(i)) {
2071 temp_dead(s, args[i]);
2072 }
2073 }
2074
e8996ee0
FB
2075 if (def->flags & TCG_OPF_BB_END) {
2076 tcg_reg_alloc_bb_end(s, allocated_regs);
2077 } else {
e8996ee0
FB
2078 if (def->flags & TCG_OPF_CALL_CLOBBER) {
2079 /* XXX: permit generic clobber register list ? */
2080 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
2081 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, reg)) {
2082 tcg_reg_free(s, reg);
2083 }
c896fe29 2084 }
3d5c5f87
AJ
2085 }
2086 if (def->flags & TCG_OPF_SIDE_EFFECTS) {
2087 /* sync globals if the op has side effects and might trigger
2088 an exception. */
2089 sync_globals(s, allocated_regs);
c896fe29 2090 }
e8996ee0
FB
2091
2092 /* satisfy the output constraints */
2093 tcg_regset_set(allocated_regs, s->reserved_regs);
2094 for(k = 0; k < nb_oargs; k++) {
2095 i = def->sorted_args[k];
2096 arg = args[i];
2097 arg_ct = &def->args_ct[i];
2098 ts = &s->temps[arg];
2099 if (arg_ct->ct & TCG_CT_ALIAS) {
2100 reg = new_args[arg_ct->alias_index];
2101 } else {
2102 /* if fixed register, we try to use it */
2103 reg = ts->reg;
2104 if (ts->fixed_reg &&
2105 tcg_regset_test_reg(arg_ct->u.regs, reg)) {
2106 goto oarg_end;
2107 }
2108 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
c896fe29 2109 }
e8996ee0
FB
2110 tcg_regset_set_reg(allocated_regs, reg);
2111 /* if a fixed register is used, then a move will be done afterwards */
2112 if (!ts->fixed_reg) {
ec7a869d
AJ
2113 if (ts->val_type == TEMP_VAL_REG) {
2114 s->reg_to_temp[ts->reg] = -1;
2115 }
2116 ts->val_type = TEMP_VAL_REG;
2117 ts->reg = reg;
2118 /* temp value is modified, so the value kept in memory is
2119 potentially not the same */
2120 ts->mem_coherent = 0;
2121 s->reg_to_temp[reg] = arg;
e8996ee0
FB
2122 }
2123 oarg_end:
2124 new_args[i] = reg;
c896fe29 2125 }
c896fe29
FB
2126 }
2127
c896fe29
FB
2128 /* emit instruction */
2129 tcg_out_op(s, opc, new_args, const_args);
2130
2131 /* move the outputs in the correct register if needed */
2132 for(i = 0; i < nb_oargs; i++) {
2133 ts = &s->temps[args[i]];
2134 reg = new_args[i];
2135 if (ts->fixed_reg && ts->reg != reg) {
3b6dac34 2136 tcg_out_mov(s, ts->type, ts->reg, reg);
c896fe29 2137 }
ec7a869d
AJ
2138 if (NEED_SYNC_ARG(i)) {
2139 tcg_reg_sync(s, reg);
2140 }
2141 if (IS_DEAD_ARG(i)) {
2142 temp_dead(s, args[i]);
2143 }
c896fe29
FB
2144 }
2145}
2146
b03cce8e
FB
2147#ifdef TCG_TARGET_STACK_GROWSUP
2148#define STACK_DIR(x) (-(x))
2149#else
2150#define STACK_DIR(x) (x)
2151#endif
2152
c45cb8bb
RH
2153static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
2154 const TCGArg * const args, uint16_t dead_args,
2155 uint8_t sync_args)
c896fe29 2156{
c45cb8bb 2157 int flags, nb_regs, i, reg;
cf066674 2158 TCGArg arg;
c896fe29 2159 TCGTemp *ts;
d3452f1f
RH
2160 intptr_t stack_offset;
2161 size_t call_stack_size;
cf066674
RH
2162 tcg_insn_unit *func_addr;
2163 int allocate_args;
c896fe29 2164 TCGRegSet allocated_regs;
c896fe29 2165
cf066674
RH
2166 func_addr = (tcg_insn_unit *)(intptr_t)args[nb_oargs + nb_iargs];
2167 flags = args[nb_oargs + nb_iargs + 1];
c896fe29 2168
6e17d0c5 2169 nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs);
c45cb8bb
RH
2170 if (nb_regs > nb_iargs) {
2171 nb_regs = nb_iargs;
cf066674 2172 }
c896fe29
FB
2173
2174 /* assign stack slots first */
c45cb8bb 2175 call_stack_size = (nb_iargs - nb_regs) * sizeof(tcg_target_long);
c896fe29
FB
2176 call_stack_size = (call_stack_size + TCG_TARGET_STACK_ALIGN - 1) &
2177 ~(TCG_TARGET_STACK_ALIGN - 1);
b03cce8e
FB
2178 allocate_args = (call_stack_size > TCG_STATIC_CALL_ARGS_SIZE);
2179 if (allocate_args) {
345649c0
BS
2180 /* XXX: if more than TCG_STATIC_CALL_ARGS_SIZE is needed,
2181 preallocate call stack */
2182 tcg_abort();
b03cce8e 2183 }
39cf05d3
FB
2184
2185 stack_offset = TCG_TARGET_CALL_STACK_OFFSET;
c45cb8bb 2186 for(i = nb_regs; i < nb_iargs; i++) {
c896fe29 2187 arg = args[nb_oargs + i];
39cf05d3
FB
2188#ifdef TCG_TARGET_STACK_GROWSUP
2189 stack_offset -= sizeof(tcg_target_long);
2190#endif
2191 if (arg != TCG_CALL_DUMMY_ARG) {
2192 ts = &s->temps[arg];
2193 if (ts->val_type == TEMP_VAL_REG) {
2194 tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_offset);
2195 } else if (ts->val_type == TEMP_VAL_MEM) {
2196 reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
2197 s->reserved_regs);
2198 /* XXX: not correct if reading values from the stack */
2199 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
2200 tcg_out_st(s, ts->type, reg, TCG_REG_CALL_STACK, stack_offset);
2201 } else if (ts->val_type == TEMP_VAL_CONST) {
2202 reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
2203 s->reserved_regs);
2204 /* XXX: sign extend may be needed on some targets */
2205 tcg_out_movi(s, ts->type, reg, ts->val);
2206 tcg_out_st(s, ts->type, reg, TCG_REG_CALL_STACK, stack_offset);
2207 } else {
2208 tcg_abort();
2209 }
c896fe29 2210 }
39cf05d3
FB
2211#ifndef TCG_TARGET_STACK_GROWSUP
2212 stack_offset += sizeof(tcg_target_long);
2213#endif
c896fe29
FB
2214 }
2215
2216 /* assign input registers */
2217 tcg_regset_set(allocated_regs, s->reserved_regs);
2218 for(i = 0; i < nb_regs; i++) {
2219 arg = args[nb_oargs + i];
39cf05d3
FB
2220 if (arg != TCG_CALL_DUMMY_ARG) {
2221 ts = &s->temps[arg];
2222 reg = tcg_target_call_iarg_regs[i];
2223 tcg_reg_free(s, reg);
2224 if (ts->val_type == TEMP_VAL_REG) {
2225 if (ts->reg != reg) {
3b6dac34 2226 tcg_out_mov(s, ts->type, reg, ts->reg);
39cf05d3
FB
2227 }
2228 } else if (ts->val_type == TEMP_VAL_MEM) {
2229 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
2230 } else if (ts->val_type == TEMP_VAL_CONST) {
2231 /* XXX: sign extend ? */
2232 tcg_out_movi(s, ts->type, reg, ts->val);
2233 } else {
2234 tcg_abort();
c896fe29 2235 }
39cf05d3 2236 tcg_regset_set_reg(allocated_regs, reg);
c896fe29 2237 }
c896fe29
FB
2238 }
2239
c896fe29 2240 /* mark dead temporaries and free the associated registers */
866cb6cb 2241 for(i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
866cb6cb 2242 if (IS_DEAD_ARG(i)) {
639368dd 2243 temp_dead(s, args[i]);
c896fe29
FB
2244 }
2245 }
2246
2247 /* clobber call registers */
2248 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
2249 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, reg)) {
2250 tcg_reg_free(s, reg);
2251 }
2252 }
78505279
AJ
2253
2254 /* Save globals if they might be written by the helper, sync them if
2255 they might be read. */
2256 if (flags & TCG_CALL_NO_READ_GLOBALS) {
2257 /* Nothing to do */
2258 } else if (flags & TCG_CALL_NO_WRITE_GLOBALS) {
2259 sync_globals(s, allocated_regs);
2260 } else {
b9c18f56
AJ
2261 save_globals(s, allocated_regs);
2262 }
c896fe29 2263
cf066674 2264 tcg_out_call(s, func_addr);
c896fe29
FB
2265
2266 /* assign output registers and emit moves if needed */
2267 for(i = 0; i < nb_oargs; i++) {
2268 arg = args[i];
2269 ts = &s->temps[arg];
2270 reg = tcg_target_call_oarg_regs[i];
e8996ee0 2271 assert(s->reg_to_temp[reg] == -1);
34b1a49c 2272
c896fe29
FB
2273 if (ts->fixed_reg) {
2274 if (ts->reg != reg) {
3b6dac34 2275 tcg_out_mov(s, ts->type, ts->reg, reg);
c896fe29
FB
2276 }
2277 } else {
ec7a869d
AJ
2278 if (ts->val_type == TEMP_VAL_REG) {
2279 s->reg_to_temp[ts->reg] = -1;
2280 }
2281 ts->val_type = TEMP_VAL_REG;
2282 ts->reg = reg;
2283 ts->mem_coherent = 0;
2284 s->reg_to_temp[reg] = arg;
2285 if (NEED_SYNC_ARG(i)) {
2286 tcg_reg_sync(s, reg);
2287 }
8c11ad25 2288 if (IS_DEAD_ARG(i)) {
639368dd 2289 temp_dead(s, args[i]);
8c11ad25 2290 }
c896fe29
FB
2291 }
2292 }
c896fe29
FB
2293}
2294
2295#ifdef CONFIG_PROFILER
2296
54604f74 2297static int64_t tcg_table_op_count[NB_OPS];
c896fe29 2298
246ae24d 2299void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf)
c896fe29
FB
2300{
2301 int i;
d70724ce 2302
15fc7daa 2303 for (i = 0; i < NB_OPS; i++) {
246ae24d
MF
2304 cpu_fprintf(f, "%s %" PRId64 "\n", tcg_op_defs[i].name,
2305 tcg_table_op_count[i]);
c896fe29 2306 }
c896fe29 2307}
246ae24d
MF
2308#else
2309void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf)
2310{
2311 cpu_fprintf(f, "[TCG profiler not compiled]\n");
2312}
c896fe29
FB
2313#endif
2314
2315
04fe6400 2316int tcg_gen_code(TCGContext *s, tcg_insn_unit *gen_code_buf)
c896fe29 2317{
fca8a500 2318 int i, oi, oi_next, num_insns;
c896fe29 2319
04fe6400
RH
2320#ifdef CONFIG_PROFILER
2321 {
2322 int n;
2323
2324 n = s->gen_last_op_idx + 1;
2325 s->op_count += n;
2326 if (n > s->op_count_max) {
2327 s->op_count_max = n;
2328 }
2329
2330 n = s->nb_temps;
2331 s->temp_count += n;
2332 if (n > s->temp_count_max) {
2333 s->temp_count_max = n;
2334 }
2335 }
2336#endif
2337
c896fe29 2338#ifdef DEBUG_DISAS
8fec2b8c 2339 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
93fcfe39 2340 qemu_log("OP:\n");
eeacee4d 2341 tcg_dump_ops(s);
93fcfe39 2342 qemu_log("\n");
c896fe29
FB
2343 }
2344#endif
2345
c5cc28ff
AJ
2346#ifdef CONFIG_PROFILER
2347 s->opt_time -= profile_getclock();
2348#endif
2349
8f2e8c07 2350#ifdef USE_TCG_OPTIMIZATIONS
c45cb8bb 2351 tcg_optimize(s);
8f2e8c07
KB
2352#endif
2353
a23a9ec6 2354#ifdef CONFIG_PROFILER
c5cc28ff 2355 s->opt_time += profile_getclock();
a23a9ec6
FB
2356 s->la_time -= profile_getclock();
2357#endif
c5cc28ff 2358
c896fe29 2359 tcg_liveness_analysis(s);
c5cc28ff 2360
a23a9ec6
FB
2361#ifdef CONFIG_PROFILER
2362 s->la_time += profile_getclock();
2363#endif
c896fe29
FB
2364
2365#ifdef DEBUG_DISAS
8fec2b8c 2366 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) {
c5cc28ff 2367 qemu_log("OP after optimization and liveness analysis:\n");
eeacee4d 2368 tcg_dump_ops(s);
93fcfe39 2369 qemu_log("\n");
c896fe29
FB
2370 }
2371#endif
2372
2373 tcg_reg_alloc_start(s);
2374
2375 s->code_buf = gen_code_buf;
2376 s->code_ptr = gen_code_buf;
2377
9ecefc84
RH
2378 tcg_out_tb_init(s);
2379
fca8a500 2380 num_insns = -1;
c45cb8bb
RH
2381 for (oi = s->gen_first_op_idx; oi >= 0; oi = oi_next) {
2382 TCGOp * const op = &s->gen_op_buf[oi];
2383 TCGArg * const args = &s->gen_opparam_buf[op->args];
2384 TCGOpcode opc = op->opc;
2385 const TCGOpDef *def = &tcg_op_defs[opc];
2386 uint16_t dead_args = s->op_dead_args[oi];
2387 uint8_t sync_args = s->op_sync_args[oi];
b3db8758 2388
c45cb8bb 2389 oi_next = op->next;
c896fe29 2390#ifdef CONFIG_PROFILER
54604f74 2391 tcg_table_op_count[opc]++;
c896fe29 2392#endif
c45cb8bb
RH
2393
2394 switch (opc) {
c896fe29 2395 case INDEX_op_mov_i32:
c896fe29 2396 case INDEX_op_mov_i64:
c45cb8bb 2397 tcg_reg_alloc_mov(s, def, args, dead_args, sync_args);
c896fe29 2398 break;
e8996ee0 2399 case INDEX_op_movi_i32:
e8996ee0 2400 case INDEX_op_movi_i64:
c45cb8bb 2401 tcg_reg_alloc_movi(s, args, dead_args, sync_args);
e8996ee0 2402 break;
765b842a 2403 case INDEX_op_insn_start:
fca8a500
RH
2404 if (num_insns >= 0) {
2405 s->gen_insn_end_off[num_insns] = tcg_current_code_size(s);
2406 }
2407 num_insns++;
bad729e2
RH
2408 for (i = 0; i < TARGET_INSN_START_WORDS; ++i) {
2409 target_ulong a;
2410#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
2411 a = ((target_ulong)args[i * 2 + 1] << 32) | args[i * 2];
2412#else
2413 a = args[i];
2414#endif
fca8a500 2415 s->gen_insn_data[num_insns][i] = a;
bad729e2 2416 }
c896fe29 2417 break;
5ff9d6a4 2418 case INDEX_op_discard:
639368dd 2419 temp_dead(s, args[0]);
5ff9d6a4 2420 break;
c896fe29 2421 case INDEX_op_set_label:
e8996ee0 2422 tcg_reg_alloc_bb_end(s, s->reserved_regs);
bec16311 2423 tcg_out_label(s, arg_label(args[0]), s->code_ptr);
c896fe29
FB
2424 break;
2425 case INDEX_op_call:
c45cb8bb
RH
2426 tcg_reg_alloc_call(s, op->callo, op->calli, args,
2427 dead_args, sync_args);
2428 break;
c896fe29 2429 default:
25c4d9cc
RH
2430 /* Sanity check that we've not introduced any unhandled opcodes. */
2431 if (def->flags & TCG_OPF_NOT_PRESENT) {
2432 tcg_abort();
2433 }
c896fe29
FB
2434 /* Note: in order to speed up the code, it would be much
2435 faster to have specialized register allocator functions for
2436 some common argument patterns */
c45cb8bb 2437 tcg_reg_alloc_op(s, def, opc, args, dead_args, sync_args);
c896fe29
FB
2438 break;
2439 }
c896fe29
FB
2440#ifndef NDEBUG
2441 check_regs(s);
2442#endif
b125f9dc
RH
2443 /* Test for (pending) buffer overflow. The assumption is that any
2444 one operation beginning below the high water mark cannot overrun
2445 the buffer completely. Thus we can test for overflow after
2446 generating code without having to check during generation. */
644da9b3 2447 if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) {
b125f9dc
RH
2448 return -1;
2449 }
c896fe29 2450 }
fca8a500
RH
2451 tcg_debug_assert(num_insns >= 0);
2452 s->gen_insn_end_off[num_insns] = tcg_current_code_size(s);
c45cb8bb 2453
b76f0d8c 2454 /* Generate TB finalization at the end of block */
23dceda6
RH
2455 if (!tcg_out_tb_finalize(s)) {
2456 return -1;
2457 }
c896fe29
FB
2458
2459 /* flush instruction cache */
1813e175 2460 flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);
2aeabc08 2461
1813e175 2462 return tcg_current_code_size(s);
c896fe29
FB
2463}
2464
a23a9ec6 2465#ifdef CONFIG_PROFILER
405cf9ff 2466void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
a23a9ec6
FB
2467{
2468 TCGContext *s = &tcg_ctx;
fca8a500
RH
2469 int64_t tb_count = s->tb_count;
2470 int64_t tb_div_count = tb_count ? tb_count : 1;
2471 int64_t tot = s->interm_time + s->code_time;
a23a9ec6 2472
a23a9ec6
FB
2473 cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n",
2474 tot, tot / 2.4e9);
2475 cpu_fprintf(f, "translated TBs %" PRId64 " (aborted=%" PRId64 " %0.1f%%)\n",
fca8a500
RH
2476 tb_count, s->tb_count1 - tb_count,
2477 (double)(s->tb_count1 - s->tb_count)
2478 / (s->tb_count1 ? s->tb_count1 : 1) * 100.0);
a23a9ec6 2479 cpu_fprintf(f, "avg ops/TB %0.1f max=%d\n",
fca8a500 2480 (double)s->op_count / tb_div_count, s->op_count_max);
a23a9ec6 2481 cpu_fprintf(f, "deleted ops/TB %0.2f\n",
fca8a500 2482 (double)s->del_op_count / tb_div_count);
a23a9ec6 2483 cpu_fprintf(f, "avg temps/TB %0.2f max=%d\n",
fca8a500
RH
2484 (double)s->temp_count / tb_div_count, s->temp_count_max);
2485 cpu_fprintf(f, "avg host code/TB %0.1f\n",
2486 (double)s->code_out_len / tb_div_count);
2487 cpu_fprintf(f, "avg search data/TB %0.1f\n",
2488 (double)s->search_out_len / tb_div_count);
a23a9ec6
FB
2489
2490 cpu_fprintf(f, "cycles/op %0.1f\n",
2491 s->op_count ? (double)tot / s->op_count : 0);
2492 cpu_fprintf(f, "cycles/in byte %0.1f\n",
2493 s->code_in_len ? (double)tot / s->code_in_len : 0);
2494 cpu_fprintf(f, "cycles/out byte %0.1f\n",
2495 s->code_out_len ? (double)tot / s->code_out_len : 0);
fca8a500
RH
2496 cpu_fprintf(f, "cycles/search byte %0.1f\n",
2497 s->search_out_len ? (double)tot / s->search_out_len : 0);
2498 if (tot == 0) {
a23a9ec6 2499 tot = 1;
fca8a500 2500 }
a23a9ec6
FB
2501 cpu_fprintf(f, " gen_interm time %0.1f%%\n",
2502 (double)s->interm_time / tot * 100.0);
2503 cpu_fprintf(f, " gen_code time %0.1f%%\n",
2504 (double)s->code_time / tot * 100.0);
c5cc28ff
AJ
2505 cpu_fprintf(f, "optim./code time %0.1f%%\n",
2506 (double)s->opt_time / (s->code_time ? s->code_time : 1)
2507 * 100.0);
a23a9ec6
FB
2508 cpu_fprintf(f, "liveness/code time %0.1f%%\n",
2509 (double)s->la_time / (s->code_time ? s->code_time : 1) * 100.0);
2510 cpu_fprintf(f, "cpu_restore count %" PRId64 "\n",
2511 s->restore_count);
2512 cpu_fprintf(f, " avg cycles %0.1f\n",
2513 s->restore_count ? (double)s->restore_time / s->restore_count : 0);
a23a9ec6
FB
2514}
2515#else
405cf9ff 2516void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
a23a9ec6 2517{
24bf7b3a 2518 cpu_fprintf(f, "[TCG profiler not compiled]\n");
a23a9ec6
FB
2519}
2520#endif
813da627
RH
2521
2522#ifdef ELF_HOST_MACHINE
5872bbf2
RH
2523/* In order to use this feature, the backend needs to do three things:
2524
2525 (1) Define ELF_HOST_MACHINE to indicate both what value to
2526 put into the ELF image and to indicate support for the feature.
2527
2528 (2) Define tcg_register_jit. This should create a buffer containing
2529 the contents of a .debug_frame section that describes the post-
2530 prologue unwind info for the tcg machine.
2531
2532 (3) Call tcg_register_jit_int, with the constructed .debug_frame.
2533*/
813da627
RH
2534
2535/* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */
2536typedef enum {
2537 JIT_NOACTION = 0,
2538 JIT_REGISTER_FN,
2539 JIT_UNREGISTER_FN
2540} jit_actions_t;
2541
2542struct jit_code_entry {
2543 struct jit_code_entry *next_entry;
2544 struct jit_code_entry *prev_entry;
2545 const void *symfile_addr;
2546 uint64_t symfile_size;
2547};
2548
2549struct jit_descriptor {
2550 uint32_t version;
2551 uint32_t action_flag;
2552 struct jit_code_entry *relevant_entry;
2553 struct jit_code_entry *first_entry;
2554};
2555
2556void __jit_debug_register_code(void) __attribute__((noinline));
2557void __jit_debug_register_code(void)
2558{
2559 asm("");
2560}
2561
2562/* Must statically initialize the version, because GDB may check
2563 the version before we can set it. */
2564struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 };
2565
2566/* End GDB interface. */
2567
2568static int find_string(const char *strtab, const char *str)
2569{
2570 const char *p = strtab + 1;
2571
2572 while (1) {
2573 if (strcmp(p, str) == 0) {
2574 return p - strtab;
2575 }
2576 p += strlen(p) + 1;
2577 }
2578}
2579
5872bbf2 2580static void tcg_register_jit_int(void *buf_ptr, size_t buf_size,
2c90784a
RH
2581 const void *debug_frame,
2582 size_t debug_frame_size)
813da627 2583{
5872bbf2
RH
2584 struct __attribute__((packed)) DebugInfo {
2585 uint32_t len;
2586 uint16_t version;
2587 uint32_t abbrev;
2588 uint8_t ptr_size;
2589 uint8_t cu_die;
2590 uint16_t cu_lang;
2591 uintptr_t cu_low_pc;
2592 uintptr_t cu_high_pc;
2593 uint8_t fn_die;
2594 char fn_name[16];
2595 uintptr_t fn_low_pc;
2596 uintptr_t fn_high_pc;
2597 uint8_t cu_eoc;
2598 };
813da627
RH
2599
2600 struct ElfImage {
2601 ElfW(Ehdr) ehdr;
2602 ElfW(Phdr) phdr;
5872bbf2
RH
2603 ElfW(Shdr) shdr[7];
2604 ElfW(Sym) sym[2];
2605 struct DebugInfo di;
2606 uint8_t da[24];
2607 char str[80];
2608 };
2609
2610 struct ElfImage *img;
2611
2612 static const struct ElfImage img_template = {
2613 .ehdr = {
2614 .e_ident[EI_MAG0] = ELFMAG0,
2615 .e_ident[EI_MAG1] = ELFMAG1,
2616 .e_ident[EI_MAG2] = ELFMAG2,
2617 .e_ident[EI_MAG3] = ELFMAG3,
2618 .e_ident[EI_CLASS] = ELF_CLASS,
2619 .e_ident[EI_DATA] = ELF_DATA,
2620 .e_ident[EI_VERSION] = EV_CURRENT,
2621 .e_type = ET_EXEC,
2622 .e_machine = ELF_HOST_MACHINE,
2623 .e_version = EV_CURRENT,
2624 .e_phoff = offsetof(struct ElfImage, phdr),
2625 .e_shoff = offsetof(struct ElfImage, shdr),
2626 .e_ehsize = sizeof(ElfW(Shdr)),
2627 .e_phentsize = sizeof(ElfW(Phdr)),
2628 .e_phnum = 1,
2629 .e_shentsize = sizeof(ElfW(Shdr)),
2630 .e_shnum = ARRAY_SIZE(img->shdr),
2631 .e_shstrndx = ARRAY_SIZE(img->shdr) - 1,
abbb3eae
RH
2632#ifdef ELF_HOST_FLAGS
2633 .e_flags = ELF_HOST_FLAGS,
2634#endif
2635#ifdef ELF_OSABI
2636 .e_ident[EI_OSABI] = ELF_OSABI,
2637#endif
5872bbf2
RH
2638 },
2639 .phdr = {
2640 .p_type = PT_LOAD,
2641 .p_flags = PF_X,
2642 },
2643 .shdr = {
2644 [0] = { .sh_type = SHT_NULL },
2645 /* Trick: The contents of code_gen_buffer are not present in
2646 this fake ELF file; that got allocated elsewhere. Therefore
2647 we mark .text as SHT_NOBITS (similar to .bss) so that readers
2648 will not look for contents. We can record any address. */
2649 [1] = { /* .text */
2650 .sh_type = SHT_NOBITS,
2651 .sh_flags = SHF_EXECINSTR | SHF_ALLOC,
2652 },
2653 [2] = { /* .debug_info */
2654 .sh_type = SHT_PROGBITS,
2655 .sh_offset = offsetof(struct ElfImage, di),
2656 .sh_size = sizeof(struct DebugInfo),
2657 },
2658 [3] = { /* .debug_abbrev */
2659 .sh_type = SHT_PROGBITS,
2660 .sh_offset = offsetof(struct ElfImage, da),
2661 .sh_size = sizeof(img->da),
2662 },
2663 [4] = { /* .debug_frame */
2664 .sh_type = SHT_PROGBITS,
2665 .sh_offset = sizeof(struct ElfImage),
2666 },
2667 [5] = { /* .symtab */
2668 .sh_type = SHT_SYMTAB,
2669 .sh_offset = offsetof(struct ElfImage, sym),
2670 .sh_size = sizeof(img->sym),
2671 .sh_info = 1,
2672 .sh_link = ARRAY_SIZE(img->shdr) - 1,
2673 .sh_entsize = sizeof(ElfW(Sym)),
2674 },
2675 [6] = { /* .strtab */
2676 .sh_type = SHT_STRTAB,
2677 .sh_offset = offsetof(struct ElfImage, str),
2678 .sh_size = sizeof(img->str),
2679 }
2680 },
2681 .sym = {
2682 [1] = { /* code_gen_buffer */
2683 .st_info = ELF_ST_INFO(STB_GLOBAL, STT_FUNC),
2684 .st_shndx = 1,
2685 }
2686 },
2687 .di = {
2688 .len = sizeof(struct DebugInfo) - 4,
2689 .version = 2,
2690 .ptr_size = sizeof(void *),
2691 .cu_die = 1,
2692 .cu_lang = 0x8001, /* DW_LANG_Mips_Assembler */
2693 .fn_die = 2,
2694 .fn_name = "code_gen_buffer"
2695 },
2696 .da = {
2697 1, /* abbrev number (the cu) */
2698 0x11, 1, /* DW_TAG_compile_unit, has children */
2699 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */
2700 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2701 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2702 0, 0, /* end of abbrev */
2703 2, /* abbrev number (the fn) */
2704 0x2e, 0, /* DW_TAG_subprogram, no children */
2705 0x3, 0x8, /* DW_AT_name, DW_FORM_string */
2706 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2707 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2708 0, 0, /* end of abbrev */
2709 0 /* no more abbrev */
2710 },
2711 .str = "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0"
2712 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer",
813da627
RH
2713 };
2714
2715 /* We only need a single jit entry; statically allocate it. */
2716 static struct jit_code_entry one_entry;
2717
5872bbf2 2718 uintptr_t buf = (uintptr_t)buf_ptr;
813da627 2719 size_t img_size = sizeof(struct ElfImage) + debug_frame_size;
2c90784a 2720 DebugFrameHeader *dfh;
813da627 2721
5872bbf2
RH
2722 img = g_malloc(img_size);
2723 *img = img_template;
813da627 2724
5872bbf2
RH
2725 img->phdr.p_vaddr = buf;
2726 img->phdr.p_paddr = buf;
2727 img->phdr.p_memsz = buf_size;
813da627 2728
813da627 2729 img->shdr[1].sh_name = find_string(img->str, ".text");
5872bbf2 2730 img->shdr[1].sh_addr = buf;
813da627
RH
2731 img->shdr[1].sh_size = buf_size;
2732
5872bbf2
RH
2733 img->shdr[2].sh_name = find_string(img->str, ".debug_info");
2734 img->shdr[3].sh_name = find_string(img->str, ".debug_abbrev");
2735
2736 img->shdr[4].sh_name = find_string(img->str, ".debug_frame");
2737 img->shdr[4].sh_size = debug_frame_size;
2738
2739 img->shdr[5].sh_name = find_string(img->str, ".symtab");
2740 img->shdr[6].sh_name = find_string(img->str, ".strtab");
2741
2742 img->sym[1].st_name = find_string(img->str, "code_gen_buffer");
2743 img->sym[1].st_value = buf;
2744 img->sym[1].st_size = buf_size;
813da627 2745
5872bbf2 2746 img->di.cu_low_pc = buf;
45aba097 2747 img->di.cu_high_pc = buf + buf_size;
5872bbf2 2748 img->di.fn_low_pc = buf;
45aba097 2749 img->di.fn_high_pc = buf + buf_size;
813da627 2750
2c90784a
RH
2751 dfh = (DebugFrameHeader *)(img + 1);
2752 memcpy(dfh, debug_frame, debug_frame_size);
2753 dfh->fde.func_start = buf;
2754 dfh->fde.func_len = buf_size;
2755
813da627
RH
2756#ifdef DEBUG_JIT
2757 /* Enable this block to be able to debug the ELF image file creation.
2758 One can use readelf, objdump, or other inspection utilities. */
2759 {
2760 FILE *f = fopen("/tmp/qemu.jit", "w+b");
2761 if (f) {
5872bbf2 2762 if (fwrite(img, img_size, 1, f) != img_size) {
813da627
RH
2763 /* Avoid stupid unused return value warning for fwrite. */
2764 }
2765 fclose(f);
2766 }
2767 }
2768#endif
2769
2770 one_entry.symfile_addr = img;
2771 one_entry.symfile_size = img_size;
2772
2773 __jit_debug_descriptor.action_flag = JIT_REGISTER_FN;
2774 __jit_debug_descriptor.relevant_entry = &one_entry;
2775 __jit_debug_descriptor.first_entry = &one_entry;
2776 __jit_debug_register_code();
2777}
2778#else
5872bbf2
RH
2779/* No support for the feature. Provide the entry point expected by exec.c,
2780 and implement the internal function we declared earlier. */
813da627
RH
2781
2782static void tcg_register_jit_int(void *buf, size_t size,
2c90784a
RH
2783 const void *debug_frame,
2784 size_t debug_frame_size)
813da627
RH
2785{
2786}
2787
2788void tcg_register_jit(void *buf, size_t buf_size)
2789{
2790}
2791#endif /* ELF_HOST_MACHINE */