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Commit | Line | Data |
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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
757e725b | 25 | #include "qemu/osdep.h" |
cca82982 | 26 | |
813da627 RH |
27 | /* Define to jump the ELF file used to communicate with GDB. */ |
28 | #undef DEBUG_JIT | |
29 | ||
72fd2efb | 30 | #include "qemu/error-report.h" |
f348b6d1 | 31 | #include "qemu/cutils.h" |
1de7afc9 | 32 | #include "qemu/host-utils.h" |
d4c51a0a | 33 | #include "qemu/qemu-print.h" |
084cfca1 | 34 | #include "qemu/cacheflush.h" |
ad768e6f | 35 | #include "qemu/cacheinfo.h" |
533206f0 | 36 | #include "qemu/timer.h" |
cac9b0fd | 37 | #include "exec/translation-block.h" |
d0a9bb5e | 38 | #include "exec/tlb-common.h" |
ad3d0e4d | 39 | #include "tcg/tcg-op-common.h" |
813da627 | 40 | |
edee2579 | 41 | #if UINTPTR_MAX == UINT32_MAX |
813da627 | 42 | # define ELF_CLASS ELFCLASS32 |
edee2579 RH |
43 | #else |
44 | # define ELF_CLASS ELFCLASS64 | |
813da627 | 45 | #endif |
e03b5686 | 46 | #if HOST_BIG_ENDIAN |
813da627 RH |
47 | # define ELF_DATA ELFDATA2MSB |
48 | #else | |
49 | # define ELF_DATA ELFDATA2LSB | |
50 | #endif | |
51 | ||
c896fe29 | 52 | #include "elf.h" |
508127e2 | 53 | #include "exec/log.h" |
d2ba8026 | 54 | #include "tcg/tcg-ldst.h" |
47f7313d | 55 | #include "tcg/tcg-temp-internal.h" |
5ff7258c | 56 | #include "tcg-internal.h" |
5584e2db | 57 | #include "accel/tcg/perf.h" |
7d478306 RH |
58 | #ifdef CONFIG_USER_ONLY |
59 | #include "exec/user/guest-base.h" | |
60 | #endif | |
c896fe29 | 61 | |
139c1837 | 62 | /* Forward declarations for functions declared in tcg-target.c.inc and |
ce151109 | 63 | used here. */ |
e4d58b41 RH |
64 | static void tcg_target_init(TCGContext *s); |
65 | static void tcg_target_qemu_prologue(TCGContext *s); | |
6ac17786 | 66 | static bool patch_reloc(tcg_insn_unit *code_ptr, int type, |
2ba7fae2 | 67 | intptr_t value, intptr_t addend); |
c896fe29 | 68 | |
497a22eb RH |
69 | /* The CIE and FDE header definitions will be common to all hosts. */ |
70 | typedef struct { | |
71 | uint32_t len __attribute__((aligned((sizeof(void *))))); | |
72 | uint32_t id; | |
73 | uint8_t version; | |
74 | char augmentation[1]; | |
75 | uint8_t code_align; | |
76 | uint8_t data_align; | |
77 | uint8_t return_column; | |
78 | } DebugFrameCIE; | |
79 | ||
80 | typedef struct QEMU_PACKED { | |
81 | uint32_t len __attribute__((aligned((sizeof(void *))))); | |
82 | uint32_t cie_offset; | |
edee2579 RH |
83 | uintptr_t func_start; |
84 | uintptr_t func_len; | |
497a22eb RH |
85 | } DebugFrameFDEHeader; |
86 | ||
2c90784a RH |
87 | typedef struct QEMU_PACKED { |
88 | DebugFrameCIE cie; | |
89 | DebugFrameFDEHeader fde; | |
90 | } DebugFrameHeader; | |
91 | ||
2528f771 RH |
92 | typedef struct TCGLabelQemuLdst { |
93 | bool is_ld; /* qemu_ld: true, qemu_st: false */ | |
94 | MemOpIdx oi; | |
95 | TCGType type; /* result type of a load */ | |
96 | TCGReg addrlo_reg; /* reg index for low word of guest virtual addr */ | |
97 | TCGReg addrhi_reg; /* reg index for high word of guest virtual addr */ | |
98 | TCGReg datalo_reg; /* reg index for low word to be loaded or stored */ | |
99 | TCGReg datahi_reg; /* reg index for high word to be loaded or stored */ | |
100 | const tcg_insn_unit *raddr; /* addr of the next IR of qemu_ld/st IR */ | |
101 | tcg_insn_unit *label_ptr[2]; /* label pointers to be updated */ | |
102 | QSIMPLEQ_ENTRY(TCGLabelQemuLdst) next; | |
103 | } TCGLabelQemuLdst; | |
104 | ||
755bf9e5 | 105 | static void tcg_register_jit_int(const void *buf, size_t size, |
2c90784a RH |
106 | const void *debug_frame, |
107 | size_t debug_frame_size) | |
813da627 RH |
108 | __attribute__((unused)); |
109 | ||
139c1837 | 110 | /* Forward declarations for functions declared and used in tcg-target.c.inc. */ |
9358fbbf | 111 | static void tcg_out_tb_start(TCGContext *s); |
2a534aff | 112 | static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, |
a05b5b9b | 113 | intptr_t arg2); |
78113e83 | 114 | static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); |
c0ad3001 | 115 | static void tcg_out_movi(TCGContext *s, TCGType type, |
2a534aff | 116 | TCGReg ret, tcg_target_long arg); |
678155b2 | 117 | static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); |
753e42ea | 118 | static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); |
d0e66c89 | 119 | static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg); |
379afdff | 120 | static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg); |
52bf3398 | 121 | static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg); |
9ecf5f61 | 122 | static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg); |
9c6aa274 | 123 | static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); |
b9bfe000 | 124 | static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg); |
b8b94ac6 | 125 | static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg); |
313bdea8 | 126 | static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long); |
129f1f9e | 127 | static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2); |
b55a8d9d | 128 | static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg); |
cf7d6b8e | 129 | static void tcg_out_goto_tb(TCGContext *s, int which); |
5e8892db MR |
130 | static void tcg_out_op(TCGContext *s, TCGOpcode opc, |
131 | const TCGArg args[TCG_MAX_OP_ARGS], | |
132 | const int const_args[TCG_MAX_OP_ARGS]); | |
d2fd745f | 133 | #if TCG_TARGET_MAYBE_vec |
e7632cfa RH |
134 | static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, |
135 | TCGReg dst, TCGReg src); | |
d6ecb4a9 RH |
136 | static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, |
137 | TCGReg dst, TCGReg base, intptr_t offset); | |
4e186175 RH |
138 | static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, |
139 | TCGReg dst, int64_t arg); | |
5e8892db MR |
140 | static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, |
141 | unsigned vecl, unsigned vece, | |
142 | const TCGArg args[TCG_MAX_OP_ARGS], | |
143 | const int const_args[TCG_MAX_OP_ARGS]); | |
d2fd745f | 144 | #else |
e7632cfa RH |
145 | static inline bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, |
146 | TCGReg dst, TCGReg src) | |
147 | { | |
148 | g_assert_not_reached(); | |
149 | } | |
d6ecb4a9 RH |
150 | static inline bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, |
151 | TCGReg dst, TCGReg base, intptr_t offset) | |
152 | { | |
153 | g_assert_not_reached(); | |
154 | } | |
4e186175 RH |
155 | static inline void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, |
156 | TCGReg dst, int64_t arg) | |
e7632cfa RH |
157 | { |
158 | g_assert_not_reached(); | |
159 | } | |
5e8892db MR |
160 | static inline void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, |
161 | unsigned vecl, unsigned vece, | |
162 | const TCGArg args[TCG_MAX_OP_ARGS], | |
163 | const int const_args[TCG_MAX_OP_ARGS]) | |
d2fd745f RH |
164 | { |
165 | g_assert_not_reached(); | |
166 | } | |
167 | #endif | |
2a534aff | 168 | static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1, |
a05b5b9b | 169 | intptr_t arg2); |
59d7c14e RH |
170 | static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, |
171 | TCGReg base, intptr_t ofs); | |
7b7d8b2d | 172 | static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, |
cee44b03 | 173 | const TCGHelperInfo *info); |
5e3d0c19 | 174 | static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot); |
ebe92db2 | 175 | static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece); |
659ef5cb | 176 | #ifdef TCG_TARGET_NEED_LDST_LABELS |
aeee05f5 | 177 | static int tcg_out_ldst_finalize(TCGContext *s); |
659ef5cb | 178 | #endif |
c896fe29 | 179 | |
8429a1ca RH |
180 | typedef struct TCGLdstHelperParam { |
181 | TCGReg (*ra_gen)(TCGContext *s, const TCGLabelQemuLdst *l, int arg_reg); | |
182 | unsigned ntmp; | |
183 | int tmp[3]; | |
184 | } TCGLdstHelperParam; | |
185 | ||
186 | static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *l, | |
187 | const TCGLdstHelperParam *p) | |
188 | __attribute__((unused)); | |
189 | static void tcg_out_ld_helper_ret(TCGContext *s, const TCGLabelQemuLdst *l, | |
190 | bool load_sign, const TCGLdstHelperParam *p) | |
191 | __attribute__((unused)); | |
192 | static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *l, | |
193 | const TCGLdstHelperParam *p) | |
194 | __attribute__((unused)); | |
195 | ||
de95016d | 196 | static void * const qemu_ld_helpers[MO_SSIZE + 1] __attribute__((unused)) = { |
0cadc1ed RH |
197 | [MO_UB] = helper_ldub_mmu, |
198 | [MO_SB] = helper_ldsb_mmu, | |
199 | [MO_UW] = helper_lduw_mmu, | |
200 | [MO_SW] = helper_ldsw_mmu, | |
201 | [MO_UL] = helper_ldul_mmu, | |
202 | [MO_UQ] = helper_ldq_mmu, | |
203 | #if TCG_TARGET_REG_BITS == 64 | |
204 | [MO_SL] = helper_ldsl_mmu, | |
ebebea53 | 205 | [MO_128] = helper_ld16_mmu, |
0cadc1ed RH |
206 | #endif |
207 | }; | |
208 | ||
de95016d | 209 | static void * const qemu_st_helpers[MO_SIZE + 1] __attribute__((unused)) = { |
0cadc1ed RH |
210 | [MO_8] = helper_stb_mmu, |
211 | [MO_16] = helper_stw_mmu, | |
212 | [MO_32] = helper_stl_mmu, | |
213 | [MO_64] = helper_stq_mmu, | |
ebebea53 RH |
214 | #if TCG_TARGET_REG_BITS == 64 |
215 | [MO_128] = helper_st16_mmu, | |
216 | #endif | |
0cadc1ed | 217 | }; |
0cadc1ed | 218 | |
e63b8a29 RH |
219 | typedef struct { |
220 | MemOp atom; /* lg2 bits of atomicity required */ | |
221 | MemOp align; /* lg2 bits of alignment to use */ | |
222 | } TCGAtomAlign; | |
223 | ||
224 | static TCGAtomAlign atom_and_align_for_opc(TCGContext *s, MemOp opc, | |
225 | MemOp host_atom, bool allow_two_ops) | |
226 | __attribute__((unused)); | |
227 | ||
42eb6dfc RH |
228 | TCGContext tcg_init_ctx; |
229 | __thread TCGContext *tcg_ctx; | |
230 | ||
5ff7258c | 231 | TCGContext **tcg_ctxs; |
0e2d61cf RH |
232 | unsigned int tcg_cur_ctxs; |
233 | unsigned int tcg_max_ctxs; | |
ad75a51e | 234 | TCGv_env tcg_env; |
c8bc1168 | 235 | const void *tcg_code_gen_epilogue; |
db0c51a3 | 236 | uintptr_t tcg_splitwx_diff; |
df2cce29 | 237 | |
b91ccb31 RH |
238 | #ifndef CONFIG_TCG_INTERPRETER |
239 | tcg_prologue_fn *tcg_qemu_tb_exec; | |
240 | #endif | |
241 | ||
d2fd745f | 242 | static TCGRegSet tcg_target_available_regs[TCG_TYPE_COUNT]; |
b1d8e52e | 243 | static TCGRegSet tcg_target_call_clobber_regs; |
c896fe29 | 244 | |
1813e175 | 245 | #if TCG_TARGET_INSN_UNIT_SIZE == 1 |
4196dca6 | 246 | static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v) |
c896fe29 FB |
247 | { |
248 | *s->code_ptr++ = v; | |
249 | } | |
250 | ||
4196dca6 PM |
251 | static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p, |
252 | uint8_t v) | |
5c53bb81 | 253 | { |
1813e175 | 254 | *p = v; |
5c53bb81 | 255 | } |
1813e175 | 256 | #endif |
5c53bb81 | 257 | |
1813e175 | 258 | #if TCG_TARGET_INSN_UNIT_SIZE <= 2 |
4196dca6 | 259 | static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v) |
c896fe29 | 260 | { |
1813e175 RH |
261 | if (TCG_TARGET_INSN_UNIT_SIZE == 2) { |
262 | *s->code_ptr++ = v; | |
263 | } else { | |
264 | tcg_insn_unit *p = s->code_ptr; | |
265 | memcpy(p, &v, sizeof(v)); | |
266 | s->code_ptr = p + (2 / TCG_TARGET_INSN_UNIT_SIZE); | |
267 | } | |
c896fe29 FB |
268 | } |
269 | ||
4196dca6 PM |
270 | static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p, |
271 | uint16_t v) | |
5c53bb81 | 272 | { |
1813e175 RH |
273 | if (TCG_TARGET_INSN_UNIT_SIZE == 2) { |
274 | *p = v; | |
275 | } else { | |
276 | memcpy(p, &v, sizeof(v)); | |
277 | } | |
5c53bb81 | 278 | } |
1813e175 | 279 | #endif |
5c53bb81 | 280 | |
1813e175 | 281 | #if TCG_TARGET_INSN_UNIT_SIZE <= 4 |
4196dca6 | 282 | static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v) |
c896fe29 | 283 | { |
1813e175 RH |
284 | if (TCG_TARGET_INSN_UNIT_SIZE == 4) { |
285 | *s->code_ptr++ = v; | |
286 | } else { | |
287 | tcg_insn_unit *p = s->code_ptr; | |
288 | memcpy(p, &v, sizeof(v)); | |
289 | s->code_ptr = p + (4 / TCG_TARGET_INSN_UNIT_SIZE); | |
290 | } | |
c896fe29 FB |
291 | } |
292 | ||
4196dca6 PM |
293 | static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p, |
294 | uint32_t v) | |
5c53bb81 | 295 | { |
1813e175 RH |
296 | if (TCG_TARGET_INSN_UNIT_SIZE == 4) { |
297 | *p = v; | |
298 | } else { | |
299 | memcpy(p, &v, sizeof(v)); | |
300 | } | |
5c53bb81 | 301 | } |
1813e175 | 302 | #endif |
5c53bb81 | 303 | |
1813e175 | 304 | #if TCG_TARGET_INSN_UNIT_SIZE <= 8 |
4196dca6 | 305 | static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v) |
ac26eb69 | 306 | { |
1813e175 RH |
307 | if (TCG_TARGET_INSN_UNIT_SIZE == 8) { |
308 | *s->code_ptr++ = v; | |
309 | } else { | |
310 | tcg_insn_unit *p = s->code_ptr; | |
311 | memcpy(p, &v, sizeof(v)); | |
312 | s->code_ptr = p + (8 / TCG_TARGET_INSN_UNIT_SIZE); | |
313 | } | |
ac26eb69 RH |
314 | } |
315 | ||
4196dca6 PM |
316 | static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p, |
317 | uint64_t v) | |
5c53bb81 | 318 | { |
1813e175 RH |
319 | if (TCG_TARGET_INSN_UNIT_SIZE == 8) { |
320 | *p = v; | |
321 | } else { | |
322 | memcpy(p, &v, sizeof(v)); | |
323 | } | |
5c53bb81 | 324 | } |
1813e175 | 325 | #endif |
5c53bb81 | 326 | |
c896fe29 FB |
327 | /* label relocation processing */ |
328 | ||
1813e175 | 329 | static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type, |
bec16311 | 330 | TCGLabel *l, intptr_t addend) |
c896fe29 | 331 | { |
7ecd02a0 | 332 | TCGRelocation *r = tcg_malloc(sizeof(TCGRelocation)); |
c896fe29 | 333 | |
7ecd02a0 RH |
334 | r->type = type; |
335 | r->ptr = code_ptr; | |
336 | r->addend = addend; | |
337 | QSIMPLEQ_INSERT_TAIL(&l->relocs, r, next); | |
c896fe29 FB |
338 | } |
339 | ||
92ab8e7d | 340 | static void tcg_out_label(TCGContext *s, TCGLabel *l) |
c896fe29 | 341 | { |
eabb7b91 | 342 | tcg_debug_assert(!l->has_value); |
c896fe29 | 343 | l->has_value = 1; |
92ab8e7d | 344 | l->u.value_ptr = tcg_splitwx_to_rx(s->code_ptr); |
c896fe29 FB |
345 | } |
346 | ||
42a268c2 | 347 | TCGLabel *gen_new_label(void) |
c896fe29 | 348 | { |
b1311c4a | 349 | TCGContext *s = tcg_ctx; |
51e3972c | 350 | TCGLabel *l = tcg_malloc(sizeof(TCGLabel)); |
c896fe29 | 351 | |
7ecd02a0 RH |
352 | memset(l, 0, sizeof(TCGLabel)); |
353 | l->id = s->nb_labels++; | |
f85b1fc4 | 354 | QSIMPLEQ_INIT(&l->branches); |
7ecd02a0 RH |
355 | QSIMPLEQ_INIT(&l->relocs); |
356 | ||
bef16ab4 | 357 | QSIMPLEQ_INSERT_TAIL(&s->labels, l, next); |
42a268c2 RH |
358 | |
359 | return l; | |
c896fe29 FB |
360 | } |
361 | ||
7ecd02a0 RH |
362 | static bool tcg_resolve_relocs(TCGContext *s) |
363 | { | |
364 | TCGLabel *l; | |
365 | ||
366 | QSIMPLEQ_FOREACH(l, &s->labels, next) { | |
367 | TCGRelocation *r; | |
368 | uintptr_t value = l->u.value; | |
369 | ||
370 | QSIMPLEQ_FOREACH(r, &l->relocs, next) { | |
371 | if (!patch_reloc(r->ptr, r->type, value, r->addend)) { | |
372 | return false; | |
373 | } | |
374 | } | |
375 | } | |
376 | return true; | |
377 | } | |
378 | ||
9f754620 RH |
379 | static void set_jmp_reset_offset(TCGContext *s, int which) |
380 | { | |
f14bed3f RH |
381 | /* |
382 | * We will check for overflow at the end of the opcode loop in | |
383 | * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX. | |
384 | */ | |
b7e4afbd | 385 | s->gen_tb->jmp_reset_offset[which] = tcg_current_code_size(s); |
9f754620 RH |
386 | } |
387 | ||
b52a2c03 RH |
388 | static void G_GNUC_UNUSED set_jmp_insn_offset(TCGContext *s, int which) |
389 | { | |
390 | /* | |
391 | * We will check for overflow at the end of the opcode loop in | |
392 | * tcg_gen_code, where we bound tcg_current_code_size to UINT16_MAX. | |
393 | */ | |
9da6079b | 394 | s->gen_tb->jmp_insn_offset[which] = tcg_current_code_size(s); |
b52a2c03 RH |
395 | } |
396 | ||
becc452a RH |
397 | static uintptr_t G_GNUC_UNUSED get_jmp_target_addr(TCGContext *s, int which) |
398 | { | |
399 | /* | |
400 | * Return the read-execute version of the pointer, for the benefit | |
401 | * of any pc-relative addressing mode. | |
402 | */ | |
9da6079b | 403 | return (uintptr_t)tcg_splitwx_to_rx(&s->gen_tb->jmp_target_addr[which]); |
becc452a RH |
404 | } |
405 | ||
d0a9bb5e RH |
406 | #if defined(CONFIG_SOFTMMU) && !defined(CONFIG_TCG_INTERPRETER) |
407 | static int tlb_mask_table_ofs(TCGContext *s, int which) | |
408 | { | |
7857ee11 RH |
409 | return (offsetof(CPUNegativeOffsetState, tlb.f[which]) - |
410 | sizeof(CPUNegativeOffsetState)); | |
d0a9bb5e RH |
411 | } |
412 | #endif | |
413 | ||
db6b7d0c | 414 | /* Signal overflow, starting over with fewer guest insns. */ |
8905770b MAL |
415 | static G_NORETURN |
416 | void tcg_raise_tb_overflow(TCGContext *s) | |
db6b7d0c RH |
417 | { |
418 | siglongjmp(s->jmp_trans, -2); | |
419 | } | |
420 | ||
8429a1ca RH |
421 | /* |
422 | * Used by tcg_out_movext{1,2} to hold the arguments for tcg_out_movext. | |
423 | * By the time we arrive at tcg_out_movext1, @dst is always a TCGReg. | |
424 | * | |
425 | * However, tcg_out_helper_load_slots reuses this field to hold an | |
426 | * argument slot number (which may designate a argument register or an | |
427 | * argument stack slot), converting to TCGReg once all arguments that | |
428 | * are destined for the stack are processed. | |
429 | */ | |
129f1f9e | 430 | typedef struct TCGMovExtend { |
8429a1ca | 431 | unsigned dst; |
129f1f9e RH |
432 | TCGReg src; |
433 | TCGType dst_type; | |
434 | TCGType src_type; | |
435 | MemOp src_ext; | |
436 | } TCGMovExtend; | |
437 | ||
b3dfd5fc RH |
438 | /** |
439 | * tcg_out_movext -- move and extend | |
440 | * @s: tcg context | |
441 | * @dst_type: integral type for destination | |
442 | * @dst: destination register | |
443 | * @src_type: integral type for source | |
444 | * @src_ext: extension to apply to source | |
445 | * @src: source register | |
446 | * | |
447 | * Move or extend @src into @dst, depending on @src_ext and the types. | |
448 | */ | |
129f1f9e RH |
449 | static void tcg_out_movext(TCGContext *s, TCGType dst_type, TCGReg dst, |
450 | TCGType src_type, MemOp src_ext, TCGReg src) | |
b3dfd5fc RH |
451 | { |
452 | switch (src_ext) { | |
453 | case MO_UB: | |
454 | tcg_out_ext8u(s, dst, src); | |
455 | break; | |
456 | case MO_SB: | |
457 | tcg_out_ext8s(s, dst_type, dst, src); | |
458 | break; | |
459 | case MO_UW: | |
460 | tcg_out_ext16u(s, dst, src); | |
461 | break; | |
462 | case MO_SW: | |
463 | tcg_out_ext16s(s, dst_type, dst, src); | |
464 | break; | |
465 | case MO_UL: | |
466 | case MO_SL: | |
467 | if (dst_type == TCG_TYPE_I32) { | |
468 | if (src_type == TCG_TYPE_I32) { | |
469 | tcg_out_mov(s, TCG_TYPE_I32, dst, src); | |
470 | } else { | |
471 | tcg_out_extrl_i64_i32(s, dst, src); | |
472 | } | |
473 | } else if (src_type == TCG_TYPE_I32) { | |
474 | if (src_ext & MO_SIGN) { | |
475 | tcg_out_exts_i32_i64(s, dst, src); | |
476 | } else { | |
477 | tcg_out_extu_i32_i64(s, dst, src); | |
478 | } | |
479 | } else { | |
480 | if (src_ext & MO_SIGN) { | |
481 | tcg_out_ext32s(s, dst, src); | |
482 | } else { | |
483 | tcg_out_ext32u(s, dst, src); | |
484 | } | |
485 | } | |
486 | break; | |
487 | case MO_UQ: | |
488 | tcg_debug_assert(TCG_TARGET_REG_BITS == 64); | |
489 | if (dst_type == TCG_TYPE_I32) { | |
490 | tcg_out_extrl_i64_i32(s, dst, src); | |
491 | } else { | |
492 | tcg_out_mov(s, TCG_TYPE_I64, dst, src); | |
493 | } | |
494 | break; | |
495 | default: | |
496 | g_assert_not_reached(); | |
497 | } | |
498 | } | |
499 | ||
129f1f9e RH |
500 | /* Minor variations on a theme, using a structure. */ |
501 | static void tcg_out_movext1_new_src(TCGContext *s, const TCGMovExtend *i, | |
502 | TCGReg src) | |
503 | { | |
504 | tcg_out_movext(s, i->dst_type, i->dst, i->src_type, i->src_ext, src); | |
505 | } | |
506 | ||
507 | static void tcg_out_movext1(TCGContext *s, const TCGMovExtend *i) | |
508 | { | |
509 | tcg_out_movext1_new_src(s, i, i->src); | |
510 | } | |
511 | ||
512 | /** | |
513 | * tcg_out_movext2 -- move and extend two pair | |
514 | * @s: tcg context | |
515 | * @i1: first move description | |
516 | * @i2: second move description | |
517 | * @scratch: temporary register, or -1 for none | |
518 | * | |
519 | * As tcg_out_movext, for both @i1 and @i2, caring for overlap | |
520 | * between the sources and destinations. | |
521 | */ | |
522 | ||
8429a1ca RH |
523 | static void tcg_out_movext2(TCGContext *s, const TCGMovExtend *i1, |
524 | const TCGMovExtend *i2, int scratch) | |
129f1f9e RH |
525 | { |
526 | TCGReg src1 = i1->src; | |
527 | TCGReg src2 = i2->src; | |
528 | ||
529 | if (i1->dst != src2) { | |
530 | tcg_out_movext1(s, i1); | |
531 | tcg_out_movext1(s, i2); | |
532 | return; | |
533 | } | |
534 | if (i2->dst == src1) { | |
535 | TCGType src1_type = i1->src_type; | |
536 | TCGType src2_type = i2->src_type; | |
537 | ||
538 | if (tcg_out_xchg(s, MAX(src1_type, src2_type), src1, src2)) { | |
539 | /* The data is now in the correct registers, now extend. */ | |
540 | src1 = i2->src; | |
541 | src2 = i1->src; | |
542 | } else { | |
543 | tcg_debug_assert(scratch >= 0); | |
544 | tcg_out_mov(s, src1_type, scratch, src1); | |
545 | src1 = scratch; | |
546 | } | |
547 | } | |
548 | tcg_out_movext1_new_src(s, i2, src2); | |
549 | tcg_out_movext1_new_src(s, i1, src1); | |
550 | } | |
551 | ||
2462e30e RH |
552 | /** |
553 | * tcg_out_movext3 -- move and extend three pair | |
554 | * @s: tcg context | |
555 | * @i1: first move description | |
556 | * @i2: second move description | |
557 | * @i3: third move description | |
558 | * @scratch: temporary register, or -1 for none | |
559 | * | |
560 | * As tcg_out_movext, for all of @i1, @i2 and @i3, caring for overlap | |
561 | * between the sources and destinations. | |
562 | */ | |
563 | ||
564 | static void tcg_out_movext3(TCGContext *s, const TCGMovExtend *i1, | |
565 | const TCGMovExtend *i2, const TCGMovExtend *i3, | |
566 | int scratch) | |
567 | { | |
568 | TCGReg src1 = i1->src; | |
569 | TCGReg src2 = i2->src; | |
570 | TCGReg src3 = i3->src; | |
571 | ||
572 | if (i1->dst != src2 && i1->dst != src3) { | |
573 | tcg_out_movext1(s, i1); | |
574 | tcg_out_movext2(s, i2, i3, scratch); | |
575 | return; | |
576 | } | |
577 | if (i2->dst != src1 && i2->dst != src3) { | |
578 | tcg_out_movext1(s, i2); | |
579 | tcg_out_movext2(s, i1, i3, scratch); | |
580 | return; | |
581 | } | |
582 | if (i3->dst != src1 && i3->dst != src2) { | |
583 | tcg_out_movext1(s, i3); | |
584 | tcg_out_movext2(s, i1, i2, scratch); | |
585 | return; | |
586 | } | |
587 | ||
588 | /* | |
589 | * There is a cycle. Since there are only 3 nodes, the cycle is | |
590 | * either "clockwise" or "anti-clockwise", and can be solved with | |
591 | * a single scratch or two xchg. | |
592 | */ | |
593 | if (i1->dst == src2 && i2->dst == src3 && i3->dst == src1) { | |
594 | /* "Clockwise" */ | |
595 | if (tcg_out_xchg(s, MAX(i1->src_type, i2->src_type), src1, src2)) { | |
596 | tcg_out_xchg(s, MAX(i2->src_type, i3->src_type), src2, src3); | |
597 | /* The data is now in the correct registers, now extend. */ | |
598 | tcg_out_movext1_new_src(s, i1, i1->dst); | |
599 | tcg_out_movext1_new_src(s, i2, i2->dst); | |
600 | tcg_out_movext1_new_src(s, i3, i3->dst); | |
601 | } else { | |
602 | tcg_debug_assert(scratch >= 0); | |
603 | tcg_out_mov(s, i1->src_type, scratch, src1); | |
604 | tcg_out_movext1(s, i3); | |
605 | tcg_out_movext1(s, i2); | |
606 | tcg_out_movext1_new_src(s, i1, scratch); | |
607 | } | |
608 | } else if (i1->dst == src3 && i2->dst == src1 && i3->dst == src2) { | |
609 | /* "Anti-clockwise" */ | |
610 | if (tcg_out_xchg(s, MAX(i2->src_type, i3->src_type), src2, src3)) { | |
611 | tcg_out_xchg(s, MAX(i1->src_type, i2->src_type), src1, src2); | |
612 | /* The data is now in the correct registers, now extend. */ | |
613 | tcg_out_movext1_new_src(s, i1, i1->dst); | |
614 | tcg_out_movext1_new_src(s, i2, i2->dst); | |
615 | tcg_out_movext1_new_src(s, i3, i3->dst); | |
616 | } else { | |
617 | tcg_debug_assert(scratch >= 0); | |
618 | tcg_out_mov(s, i1->src_type, scratch, src1); | |
619 | tcg_out_movext1(s, i2); | |
620 | tcg_out_movext1(s, i3); | |
621 | tcg_out_movext1_new_src(s, i1, scratch); | |
622 | } | |
623 | } else { | |
624 | g_assert_not_reached(); | |
625 | } | |
626 | } | |
627 | ||
4c22e840 RH |
628 | #define C_PFX1(P, A) P##A |
629 | #define C_PFX2(P, A, B) P##A##_##B | |
630 | #define C_PFX3(P, A, B, C) P##A##_##B##_##C | |
631 | #define C_PFX4(P, A, B, C, D) P##A##_##B##_##C##_##D | |
632 | #define C_PFX5(P, A, B, C, D, E) P##A##_##B##_##C##_##D##_##E | |
633 | #define C_PFX6(P, A, B, C, D, E, F) P##A##_##B##_##C##_##D##_##E##_##F | |
634 | ||
635 | /* Define an enumeration for the various combinations. */ | |
636 | ||
637 | #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1), | |
638 | #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2), | |
639 | #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3), | |
640 | #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4), | |
641 | ||
642 | #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1), | |
643 | #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2), | |
644 | #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3), | |
645 | #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4), | |
646 | ||
647 | #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2), | |
648 | ||
649 | #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1), | |
650 | #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2), | |
651 | #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3), | |
652 | #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4), | |
22d2e535 | 653 | #define C_N1_O1_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_n1_o1_i4_, O1, O2, I1, I2, I3, I4), |
4c22e840 RH |
654 | |
655 | typedef enum { | |
656 | #include "tcg-target-con-set.h" | |
657 | } TCGConstraintSetIndex; | |
658 | ||
659 | static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode); | |
660 | ||
661 | #undef C_O0_I1 | |
662 | #undef C_O0_I2 | |
663 | #undef C_O0_I3 | |
664 | #undef C_O0_I4 | |
665 | #undef C_O1_I1 | |
666 | #undef C_O1_I2 | |
667 | #undef C_O1_I3 | |
668 | #undef C_O1_I4 | |
669 | #undef C_N1_I2 | |
670 | #undef C_O2_I1 | |
671 | #undef C_O2_I2 | |
672 | #undef C_O2_I3 | |
673 | #undef C_O2_I4 | |
22d2e535 | 674 | #undef C_N1_O1_I4 |
4c22e840 RH |
675 | |
676 | /* Put all of the constraint sets into an array, indexed by the enum. */ | |
677 | ||
678 | #define C_O0_I1(I1) { .args_ct_str = { #I1 } }, | |
679 | #define C_O0_I2(I1, I2) { .args_ct_str = { #I1, #I2 } }, | |
680 | #define C_O0_I3(I1, I2, I3) { .args_ct_str = { #I1, #I2, #I3 } }, | |
681 | #define C_O0_I4(I1, I2, I3, I4) { .args_ct_str = { #I1, #I2, #I3, #I4 } }, | |
682 | ||
683 | #define C_O1_I1(O1, I1) { .args_ct_str = { #O1, #I1 } }, | |
684 | #define C_O1_I2(O1, I1, I2) { .args_ct_str = { #O1, #I1, #I2 } }, | |
685 | #define C_O1_I3(O1, I1, I2, I3) { .args_ct_str = { #O1, #I1, #I2, #I3 } }, | |
686 | #define C_O1_I4(O1, I1, I2, I3, I4) { .args_ct_str = { #O1, #I1, #I2, #I3, #I4 } }, | |
687 | ||
688 | #define C_N1_I2(O1, I1, I2) { .args_ct_str = { "&" #O1, #I1, #I2 } }, | |
689 | ||
690 | #define C_O2_I1(O1, O2, I1) { .args_ct_str = { #O1, #O2, #I1 } }, | |
691 | #define C_O2_I2(O1, O2, I1, I2) { .args_ct_str = { #O1, #O2, #I1, #I2 } }, | |
692 | #define C_O2_I3(O1, O2, I1, I2, I3) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3 } }, | |
693 | #define C_O2_I4(O1, O2, I1, I2, I3, I4) { .args_ct_str = { #O1, #O2, #I1, #I2, #I3, #I4 } }, | |
22d2e535 | 694 | #define C_N1_O1_I4(O1, O2, I1, I2, I3, I4) { .args_ct_str = { "&" #O1, #O2, #I1, #I2, #I3, #I4 } }, |
4c22e840 RH |
695 | |
696 | static const TCGTargetOpDef constraint_sets[] = { | |
697 | #include "tcg-target-con-set.h" | |
698 | }; | |
699 | ||
700 | ||
701 | #undef C_O0_I1 | |
702 | #undef C_O0_I2 | |
703 | #undef C_O0_I3 | |
704 | #undef C_O0_I4 | |
705 | #undef C_O1_I1 | |
706 | #undef C_O1_I2 | |
707 | #undef C_O1_I3 | |
708 | #undef C_O1_I4 | |
709 | #undef C_N1_I2 | |
710 | #undef C_O2_I1 | |
711 | #undef C_O2_I2 | |
712 | #undef C_O2_I3 | |
713 | #undef C_O2_I4 | |
22d2e535 | 714 | #undef C_N1_O1_I4 |
4c22e840 RH |
715 | |
716 | /* Expand the enumerator to be returned from tcg_target_op_def(). */ | |
717 | ||
718 | #define C_O0_I1(I1) C_PFX1(c_o0_i1_, I1) | |
719 | #define C_O0_I2(I1, I2) C_PFX2(c_o0_i2_, I1, I2) | |
720 | #define C_O0_I3(I1, I2, I3) C_PFX3(c_o0_i3_, I1, I2, I3) | |
721 | #define C_O0_I4(I1, I2, I3, I4) C_PFX4(c_o0_i4_, I1, I2, I3, I4) | |
722 | ||
723 | #define C_O1_I1(O1, I1) C_PFX2(c_o1_i1_, O1, I1) | |
724 | #define C_O1_I2(O1, I1, I2) C_PFX3(c_o1_i2_, O1, I1, I2) | |
725 | #define C_O1_I3(O1, I1, I2, I3) C_PFX4(c_o1_i3_, O1, I1, I2, I3) | |
726 | #define C_O1_I4(O1, I1, I2, I3, I4) C_PFX5(c_o1_i4_, O1, I1, I2, I3, I4) | |
727 | ||
728 | #define C_N1_I2(O1, I1, I2) C_PFX3(c_n1_i2_, O1, I1, I2) | |
729 | ||
730 | #define C_O2_I1(O1, O2, I1) C_PFX3(c_o2_i1_, O1, O2, I1) | |
731 | #define C_O2_I2(O1, O2, I1, I2) C_PFX4(c_o2_i2_, O1, O2, I1, I2) | |
732 | #define C_O2_I3(O1, O2, I1, I2, I3) C_PFX5(c_o2_i3_, O1, O2, I1, I2, I3) | |
733 | #define C_O2_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_o2_i4_, O1, O2, I1, I2, I3, I4) | |
22d2e535 | 734 | #define C_N1_O1_I4(O1, O2, I1, I2, I3, I4) C_PFX6(c_n1_o1_i4_, O1, O2, I1, I2, I3, I4) |
4c22e840 | 735 | |
139c1837 | 736 | #include "tcg-target.c.inc" |
c896fe29 | 737 | |
7857ee11 RH |
738 | #ifndef CONFIG_TCG_INTERPRETER |
739 | /* Validate CPUTLBDescFast placement. */ | |
740 | QEMU_BUILD_BUG_ON((int)(offsetof(CPUNegativeOffsetState, tlb.f[0]) - | |
741 | sizeof(CPUNegativeOffsetState)) | |
742 | < MIN_TLB_MASK_TABLE_OFS); | |
743 | #endif | |
744 | ||
38b47b19 EC |
745 | static void alloc_tcg_plugin_context(TCGContext *s) |
746 | { | |
747 | #ifdef CONFIG_PLUGIN | |
748 | s->plugin_tb = g_new0(struct qemu_plugin_tb, 1); | |
749 | s->plugin_tb->insns = | |
750 | g_ptr_array_new_with_free_func(qemu_plugin_insn_cleanup_fn); | |
751 | #endif | |
752 | } | |
753 | ||
3468b59e EC |
754 | /* |
755 | * All TCG threads except the parent (i.e. the one that called tcg_context_init | |
756 | * and registered the target's TCG globals) must register with this function | |
757 | * before initiating translation. | |
758 | * | |
759 | * In user-mode we just point tcg_ctx to tcg_init_ctx. See the documentation | |
760 | * of tcg_region_init() for the reasoning behind this. | |
761 | * | |
762 | * In softmmu each caller registers its context in tcg_ctxs[]. Note that in | |
763 | * softmmu tcg_ctxs[] does not track tcg_ctx_init, since the initial context | |
764 | * is not used anymore for translation once this function is called. | |
765 | * | |
766 | * Not tracking tcg_init_ctx in tcg_ctxs[] in softmmu keeps code that iterates | |
767 | * over the array (e.g. tcg_code_size() the same for both softmmu and user-mode. | |
768 | */ | |
769 | #ifdef CONFIG_USER_ONLY | |
770 | void tcg_register_thread(void) | |
771 | { | |
772 | tcg_ctx = &tcg_init_ctx; | |
773 | } | |
774 | #else | |
775 | void tcg_register_thread(void) | |
776 | { | |
777 | TCGContext *s = g_malloc(sizeof(*s)); | |
778 | unsigned int i, n; | |
3468b59e EC |
779 | |
780 | *s = tcg_init_ctx; | |
781 | ||
782 | /* Relink mem_base. */ | |
783 | for (i = 0, n = tcg_init_ctx.nb_globals; i < n; ++i) { | |
784 | if (tcg_init_ctx.temps[i].mem_base) { | |
785 | ptrdiff_t b = tcg_init_ctx.temps[i].mem_base - tcg_init_ctx.temps; | |
786 | tcg_debug_assert(b >= 0 && b < n); | |
787 | s->temps[i].mem_base = &s->temps[b]; | |
788 | } | |
789 | } | |
790 | ||
791 | /* Claim an entry in tcg_ctxs */ | |
0e2d61cf RH |
792 | n = qatomic_fetch_inc(&tcg_cur_ctxs); |
793 | g_assert(n < tcg_max_ctxs); | |
d73415a3 | 794 | qatomic_set(&tcg_ctxs[n], s); |
3468b59e | 795 | |
38b47b19 EC |
796 | if (n > 0) { |
797 | alloc_tcg_plugin_context(s); | |
bf042e8e | 798 | tcg_region_initial_alloc(s); |
38b47b19 EC |
799 | } |
800 | ||
3468b59e | 801 | tcg_ctx = s; |
e8feb96f | 802 | } |
3468b59e | 803 | #endif /* !CONFIG_USER_ONLY */ |
e8feb96f | 804 | |
c896fe29 FB |
805 | /* pool based memory allocation */ |
806 | void *tcg_malloc_internal(TCGContext *s, int size) | |
807 | { | |
808 | TCGPool *p; | |
809 | int pool_size; | |
a813e36f | 810 | |
c896fe29 FB |
811 | if (size > TCG_POOL_CHUNK_SIZE) { |
812 | /* big malloc: insert a new pool (XXX: could optimize) */ | |
7267c094 | 813 | p = g_malloc(sizeof(TCGPool) + size); |
c896fe29 | 814 | p->size = size; |
4055299e KB |
815 | p->next = s->pool_first_large; |
816 | s->pool_first_large = p; | |
817 | return p->data; | |
c896fe29 FB |
818 | } else { |
819 | p = s->pool_current; | |
820 | if (!p) { | |
821 | p = s->pool_first; | |
822 | if (!p) | |
823 | goto new_pool; | |
824 | } else { | |
825 | if (!p->next) { | |
826 | new_pool: | |
827 | pool_size = TCG_POOL_CHUNK_SIZE; | |
7267c094 | 828 | p = g_malloc(sizeof(TCGPool) + pool_size); |
c896fe29 FB |
829 | p->size = pool_size; |
830 | p->next = NULL; | |
a813e36f | 831 | if (s->pool_current) { |
c896fe29 | 832 | s->pool_current->next = p; |
a813e36f | 833 | } else { |
c896fe29 | 834 | s->pool_first = p; |
a813e36f | 835 | } |
c896fe29 FB |
836 | } else { |
837 | p = p->next; | |
838 | } | |
839 | } | |
840 | } | |
841 | s->pool_current = p; | |
842 | s->pool_cur = p->data + size; | |
843 | s->pool_end = p->data + p->size; | |
844 | return p->data; | |
845 | } | |
846 | ||
847 | void tcg_pool_reset(TCGContext *s) | |
848 | { | |
4055299e KB |
849 | TCGPool *p, *t; |
850 | for (p = s->pool_first_large; p; p = t) { | |
851 | t = p->next; | |
852 | g_free(p); | |
853 | } | |
854 | s->pool_first_large = NULL; | |
c896fe29 FB |
855 | s->pool_cur = s->pool_end = NULL; |
856 | s->pool_current = NULL; | |
857 | } | |
858 | ||
8429a1ca RH |
859 | /* |
860 | * Create TCGHelperInfo structures for "tcg/tcg-ldst.h" functions, | |
861 | * akin to what "exec/helper-tcg.h" does with DEF_HELPER_FLAGS_N. | |
862 | * We only use these for layout in tcg_out_ld_helper_ret and | |
863 | * tcg_out_st_helper_args, and share them between several of | |
864 | * the helpers, with the end result that it's easier to build manually. | |
865 | */ | |
866 | ||
867 | #if TCG_TARGET_REG_BITS == 32 | |
868 | # define dh_typecode_ttl dh_typecode_i32 | |
869 | #else | |
870 | # define dh_typecode_ttl dh_typecode_i64 | |
871 | #endif | |
872 | ||
873 | static TCGHelperInfo info_helper_ld32_mmu = { | |
874 | .flags = TCG_CALL_NO_WG, | |
875 | .typemask = dh_typemask(ttl, 0) /* return tcg_target_ulong */ | |
876 | | dh_typemask(env, 1) | |
24e46e6c | 877 | | dh_typemask(i64, 2) /* uint64_t addr */ |
8429a1ca RH |
878 | | dh_typemask(i32, 3) /* unsigned oi */ |
879 | | dh_typemask(ptr, 4) /* uintptr_t ra */ | |
880 | }; | |
881 | ||
882 | static TCGHelperInfo info_helper_ld64_mmu = { | |
883 | .flags = TCG_CALL_NO_WG, | |
884 | .typemask = dh_typemask(i64, 0) /* return uint64_t */ | |
885 | | dh_typemask(env, 1) | |
24e46e6c | 886 | | dh_typemask(i64, 2) /* uint64_t addr */ |
8429a1ca RH |
887 | | dh_typemask(i32, 3) /* unsigned oi */ |
888 | | dh_typemask(ptr, 4) /* uintptr_t ra */ | |
889 | }; | |
890 | ||
ebebea53 RH |
891 | static TCGHelperInfo info_helper_ld128_mmu = { |
892 | .flags = TCG_CALL_NO_WG, | |
893 | .typemask = dh_typemask(i128, 0) /* return Int128 */ | |
894 | | dh_typemask(env, 1) | |
24e46e6c | 895 | | dh_typemask(i64, 2) /* uint64_t addr */ |
ebebea53 RH |
896 | | dh_typemask(i32, 3) /* unsigned oi */ |
897 | | dh_typemask(ptr, 4) /* uintptr_t ra */ | |
898 | }; | |
899 | ||
8429a1ca RH |
900 | static TCGHelperInfo info_helper_st32_mmu = { |
901 | .flags = TCG_CALL_NO_WG, | |
902 | .typemask = dh_typemask(void, 0) | |
903 | | dh_typemask(env, 1) | |
24e46e6c | 904 | | dh_typemask(i64, 2) /* uint64_t addr */ |
8429a1ca RH |
905 | | dh_typemask(i32, 3) /* uint32_t data */ |
906 | | dh_typemask(i32, 4) /* unsigned oi */ | |
907 | | dh_typemask(ptr, 5) /* uintptr_t ra */ | |
908 | }; | |
909 | ||
910 | static TCGHelperInfo info_helper_st64_mmu = { | |
911 | .flags = TCG_CALL_NO_WG, | |
912 | .typemask = dh_typemask(void, 0) | |
913 | | dh_typemask(env, 1) | |
24e46e6c | 914 | | dh_typemask(i64, 2) /* uint64_t addr */ |
8429a1ca RH |
915 | | dh_typemask(i64, 3) /* uint64_t data */ |
916 | | dh_typemask(i32, 4) /* unsigned oi */ | |
917 | | dh_typemask(ptr, 5) /* uintptr_t ra */ | |
918 | }; | |
919 | ||
ebebea53 RH |
920 | static TCGHelperInfo info_helper_st128_mmu = { |
921 | .flags = TCG_CALL_NO_WG, | |
922 | .typemask = dh_typemask(void, 0) | |
923 | | dh_typemask(env, 1) | |
24e46e6c | 924 | | dh_typemask(i64, 2) /* uint64_t addr */ |
ebebea53 RH |
925 | | dh_typemask(i128, 3) /* Int128 data */ |
926 | | dh_typemask(i32, 4) /* unsigned oi */ | |
927 | | dh_typemask(ptr, 5) /* uintptr_t ra */ | |
928 | }; | |
929 | ||
22f15579 | 930 | #ifdef CONFIG_TCG_INTERPRETER |
c6ef8c7b PMD |
931 | static ffi_type *typecode_to_ffi(int argmask) |
932 | { | |
e9709e17 RH |
933 | /* |
934 | * libffi does not support __int128_t, so we have forced Int128 | |
935 | * to use the structure definition instead of the builtin type. | |
936 | */ | |
937 | static ffi_type *ffi_type_i128_elements[3] = { | |
938 | &ffi_type_uint64, | |
939 | &ffi_type_uint64, | |
940 | NULL | |
941 | }; | |
942 | static ffi_type ffi_type_i128 = { | |
943 | .size = 16, | |
944 | .alignment = __alignof__(Int128), | |
945 | .type = FFI_TYPE_STRUCT, | |
946 | .elements = ffi_type_i128_elements, | |
947 | }; | |
948 | ||
c6ef8c7b PMD |
949 | switch (argmask) { |
950 | case dh_typecode_void: | |
951 | return &ffi_type_void; | |
952 | case dh_typecode_i32: | |
953 | return &ffi_type_uint32; | |
954 | case dh_typecode_s32: | |
955 | return &ffi_type_sint32; | |
956 | case dh_typecode_i64: | |
957 | return &ffi_type_uint64; | |
958 | case dh_typecode_s64: | |
959 | return &ffi_type_sint64; | |
960 | case dh_typecode_ptr: | |
961 | return &ffi_type_pointer; | |
e9709e17 RH |
962 | case dh_typecode_i128: |
963 | return &ffi_type_i128; | |
c6ef8c7b PMD |
964 | } |
965 | g_assert_not_reached(); | |
966 | } | |
0c22e176 | 967 | |
d53106c9 | 968 | static ffi_cif *init_ffi_layout(TCGHelperInfo *info) |
0c22e176 | 969 | { |
d53106c9 RH |
970 | unsigned typemask = info->typemask; |
971 | struct { | |
972 | ffi_cif cif; | |
973 | ffi_type *args[]; | |
974 | } *ca; | |
975 | ffi_status status; | |
976 | int nargs; | |
977 | ||
978 | /* Ignoring the return type, find the last non-zero field. */ | |
979 | nargs = 32 - clz32(typemask >> 3); | |
980 | nargs = DIV_ROUND_UP(nargs, 3); | |
981 | assert(nargs <= MAX_CALL_IARGS); | |
982 | ||
983 | ca = g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *)); | |
984 | ca->cif.rtype = typecode_to_ffi(typemask & 7); | |
985 | ca->cif.nargs = nargs; | |
986 | ||
987 | if (nargs != 0) { | |
988 | ca->cif.arg_types = ca->args; | |
989 | for (int j = 0; j < nargs; ++j) { | |
990 | int typecode = extract32(typemask, (j + 1) * 3, 3); | |
991 | ca->args[j] = typecode_to_ffi(typecode); | |
0c22e176 | 992 | } |
0c22e176 | 993 | } |
f9c4bb80 | 994 | |
d53106c9 RH |
995 | status = ffi_prep_cif(&ca->cif, FFI_DEFAULT_ABI, nargs, |
996 | ca->cif.rtype, ca->cif.arg_types); | |
997 | assert(status == FFI_OK); | |
998 | ||
999 | return &ca->cif; | |
0c22e176 | 1000 | } |
d53106c9 RH |
1001 | |
1002 | #define HELPER_INFO_INIT(I) (&(I)->cif) | |
1003 | #define HELPER_INFO_INIT_VAL(I) init_ffi_layout(I) | |
1004 | #else | |
1005 | #define HELPER_INFO_INIT(I) (&(I)->init) | |
1006 | #define HELPER_INFO_INIT_VAL(I) 1 | |
0c22e176 | 1007 | #endif /* CONFIG_TCG_INTERPRETER */ |
22f15579 | 1008 | |
338b61e9 RH |
1009 | static inline bool arg_slot_reg_p(unsigned arg_slot) |
1010 | { | |
1011 | /* | |
1012 | * Split the sizeof away from the comparison to avoid Werror from | |
1013 | * "unsigned < 0 is always false", when iarg_regs is empty. | |
1014 | */ | |
1015 | unsigned nreg = ARRAY_SIZE(tcg_target_call_iarg_regs); | |
1016 | return arg_slot < nreg; | |
1017 | } | |
1018 | ||
d78e4a4f RH |
1019 | static inline int arg_slot_stk_ofs(unsigned arg_slot) |
1020 | { | |
1021 | unsigned max = TCG_STATIC_CALL_ARGS_SIZE / sizeof(tcg_target_long); | |
1022 | unsigned stk_slot = arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs); | |
1023 | ||
1024 | tcg_debug_assert(stk_slot < max); | |
1025 | return TCG_TARGET_CALL_STACK_OFFSET + stk_slot * sizeof(tcg_target_long); | |
1026 | } | |
1027 | ||
39004a71 RH |
1028 | typedef struct TCGCumulativeArgs { |
1029 | int arg_idx; /* tcg_gen_callN args[] */ | |
1030 | int info_in_idx; /* TCGHelperInfo in[] */ | |
1031 | int arg_slot; /* regs+stack slot */ | |
1032 | int ref_slot; /* stack slots for references */ | |
1033 | } TCGCumulativeArgs; | |
1034 | ||
1035 | static void layout_arg_even(TCGCumulativeArgs *cum) | |
1036 | { | |
1037 | cum->arg_slot += cum->arg_slot & 1; | |
1038 | } | |
1039 | ||
1040 | static void layout_arg_1(TCGCumulativeArgs *cum, TCGHelperInfo *info, | |
1041 | TCGCallArgumentKind kind) | |
1042 | { | |
1043 | TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; | |
1044 | ||
1045 | *loc = (TCGCallArgumentLoc){ | |
1046 | .kind = kind, | |
1047 | .arg_idx = cum->arg_idx, | |
1048 | .arg_slot = cum->arg_slot, | |
1049 | }; | |
1050 | cum->info_in_idx++; | |
1051 | cum->arg_slot++; | |
1052 | } | |
1053 | ||
1054 | static void layout_arg_normal_n(TCGCumulativeArgs *cum, | |
1055 | TCGHelperInfo *info, int n) | |
1056 | { | |
1057 | TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; | |
1058 | ||
1059 | for (int i = 0; i < n; ++i) { | |
1060 | /* Layout all using the same arg_idx, adjusting the subindex. */ | |
1061 | loc[i] = (TCGCallArgumentLoc){ | |
1062 | .kind = TCG_CALL_ARG_NORMAL, | |
1063 | .arg_idx = cum->arg_idx, | |
1064 | .tmp_subindex = i, | |
1065 | .arg_slot = cum->arg_slot + i, | |
1066 | }; | |
1067 | } | |
1068 | cum->info_in_idx += n; | |
1069 | cum->arg_slot += n; | |
1070 | } | |
1071 | ||
313bdea8 RH |
1072 | static void layout_arg_by_ref(TCGCumulativeArgs *cum, TCGHelperInfo *info) |
1073 | { | |
1074 | TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; | |
1075 | int n = 128 / TCG_TARGET_REG_BITS; | |
1076 | ||
1077 | /* The first subindex carries the pointer. */ | |
1078 | layout_arg_1(cum, info, TCG_CALL_ARG_BY_REF); | |
1079 | ||
1080 | /* | |
1081 | * The callee is allowed to clobber memory associated with | |
1082 | * structure pass by-reference. Therefore we must make copies. | |
1083 | * Allocate space from "ref_slot", which will be adjusted to | |
1084 | * follow the parameters on the stack. | |
1085 | */ | |
1086 | loc[0].ref_slot = cum->ref_slot; | |
1087 | ||
1088 | /* | |
1089 | * Subsequent words also go into the reference slot, but | |
1090 | * do not accumulate into the regular arguments. | |
1091 | */ | |
1092 | for (int i = 1; i < n; ++i) { | |
1093 | loc[i] = (TCGCallArgumentLoc){ | |
1094 | .kind = TCG_CALL_ARG_BY_REF_N, | |
1095 | .arg_idx = cum->arg_idx, | |
1096 | .tmp_subindex = i, | |
1097 | .ref_slot = cum->ref_slot + i, | |
1098 | }; | |
1099 | } | |
e18ed26c | 1100 | cum->info_in_idx += n - 1; /* i=0 accounted for in layout_arg_1 */ |
313bdea8 RH |
1101 | cum->ref_slot += n; |
1102 | } | |
1103 | ||
39004a71 RH |
1104 | static void init_call_layout(TCGHelperInfo *info) |
1105 | { | |
1106 | int max_reg_slots = ARRAY_SIZE(tcg_target_call_iarg_regs); | |
1107 | int max_stk_slots = TCG_STATIC_CALL_ARGS_SIZE / sizeof(tcg_target_long); | |
1108 | unsigned typemask = info->typemask; | |
1109 | unsigned typecode; | |
1110 | TCGCumulativeArgs cum = { }; | |
1111 | ||
1112 | /* | |
1113 | * Parse and place any function return value. | |
1114 | */ | |
1115 | typecode = typemask & 7; | |
1116 | switch (typecode) { | |
1117 | case dh_typecode_void: | |
1118 | info->nr_out = 0; | |
1119 | break; | |
1120 | case dh_typecode_i32: | |
1121 | case dh_typecode_s32: | |
1122 | case dh_typecode_ptr: | |
1123 | info->nr_out = 1; | |
1124 | info->out_kind = TCG_CALL_RET_NORMAL; | |
1125 | break; | |
1126 | case dh_typecode_i64: | |
1127 | case dh_typecode_s64: | |
1128 | info->nr_out = 64 / TCG_TARGET_REG_BITS; | |
1129 | info->out_kind = TCG_CALL_RET_NORMAL; | |
5e3d0c19 RH |
1130 | /* Query the last register now to trigger any assert early. */ |
1131 | tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); | |
466d3759 RH |
1132 | break; |
1133 | case dh_typecode_i128: | |
1134 | info->nr_out = 128 / TCG_TARGET_REG_BITS; | |
5427a9a7 RH |
1135 | info->out_kind = TCG_TARGET_CALL_RET_I128; |
1136 | switch (TCG_TARGET_CALL_RET_I128) { | |
466d3759 | 1137 | case TCG_CALL_RET_NORMAL: |
5e3d0c19 RH |
1138 | /* Query the last register now to trigger any assert early. */ |
1139 | tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); | |
466d3759 | 1140 | break; |
c6556aa0 RH |
1141 | case TCG_CALL_RET_BY_VEC: |
1142 | /* Query the single register now to trigger any assert early. */ | |
1143 | tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0); | |
1144 | break; | |
313bdea8 RH |
1145 | case TCG_CALL_RET_BY_REF: |
1146 | /* | |
1147 | * Allocate the first argument to the output. | |
1148 | * We don't need to store this anywhere, just make it | |
1149 | * unavailable for use in the input loop below. | |
1150 | */ | |
1151 | cum.arg_slot = 1; | |
1152 | break; | |
466d3759 RH |
1153 | default: |
1154 | qemu_build_not_reached(); | |
1155 | } | |
39004a71 RH |
1156 | break; |
1157 | default: | |
1158 | g_assert_not_reached(); | |
1159 | } | |
39004a71 RH |
1160 | |
1161 | /* | |
1162 | * Parse and place function arguments. | |
1163 | */ | |
1164 | for (typemask >>= 3; typemask; typemask >>= 3, cum.arg_idx++) { | |
1165 | TCGCallArgumentKind kind; | |
1166 | TCGType type; | |
1167 | ||
1168 | typecode = typemask & 7; | |
1169 | switch (typecode) { | |
1170 | case dh_typecode_i32: | |
1171 | case dh_typecode_s32: | |
1172 | type = TCG_TYPE_I32; | |
1173 | break; | |
1174 | case dh_typecode_i64: | |
1175 | case dh_typecode_s64: | |
1176 | type = TCG_TYPE_I64; | |
1177 | break; | |
1178 | case dh_typecode_ptr: | |
1179 | type = TCG_TYPE_PTR; | |
1180 | break; | |
466d3759 RH |
1181 | case dh_typecode_i128: |
1182 | type = TCG_TYPE_I128; | |
1183 | break; | |
39004a71 RH |
1184 | default: |
1185 | g_assert_not_reached(); | |
1186 | } | |
1187 | ||
1188 | switch (type) { | |
1189 | case TCG_TYPE_I32: | |
1190 | switch (TCG_TARGET_CALL_ARG_I32) { | |
1191 | case TCG_CALL_ARG_EVEN: | |
1192 | layout_arg_even(&cum); | |
1193 | /* fall through */ | |
1194 | case TCG_CALL_ARG_NORMAL: | |
1195 | layout_arg_1(&cum, info, TCG_CALL_ARG_NORMAL); | |
1196 | break; | |
1197 | case TCG_CALL_ARG_EXTEND: | |
1198 | kind = TCG_CALL_ARG_EXTEND_U + (typecode & 1); | |
1199 | layout_arg_1(&cum, info, kind); | |
1200 | break; | |
1201 | default: | |
1202 | qemu_build_not_reached(); | |
1203 | } | |
1204 | break; | |
1205 | ||
1206 | case TCG_TYPE_I64: | |
1207 | switch (TCG_TARGET_CALL_ARG_I64) { | |
1208 | case TCG_CALL_ARG_EVEN: | |
1209 | layout_arg_even(&cum); | |
1210 | /* fall through */ | |
1211 | case TCG_CALL_ARG_NORMAL: | |
1212 | if (TCG_TARGET_REG_BITS == 32) { | |
1213 | layout_arg_normal_n(&cum, info, 2); | |
1214 | } else { | |
1215 | layout_arg_1(&cum, info, TCG_CALL_ARG_NORMAL); | |
1216 | } | |
1217 | break; | |
1218 | default: | |
1219 | qemu_build_not_reached(); | |
1220 | } | |
1221 | break; | |
1222 | ||
466d3759 | 1223 | case TCG_TYPE_I128: |
5427a9a7 | 1224 | switch (TCG_TARGET_CALL_ARG_I128) { |
466d3759 RH |
1225 | case TCG_CALL_ARG_EVEN: |
1226 | layout_arg_even(&cum); | |
1227 | /* fall through */ | |
1228 | case TCG_CALL_ARG_NORMAL: | |
1229 | layout_arg_normal_n(&cum, info, 128 / TCG_TARGET_REG_BITS); | |
1230 | break; | |
313bdea8 RH |
1231 | case TCG_CALL_ARG_BY_REF: |
1232 | layout_arg_by_ref(&cum, info); | |
1233 | break; | |
466d3759 RH |
1234 | default: |
1235 | qemu_build_not_reached(); | |
1236 | } | |
1237 | break; | |
1238 | ||
39004a71 RH |
1239 | default: |
1240 | g_assert_not_reached(); | |
1241 | } | |
1242 | } | |
1243 | info->nr_in = cum.info_in_idx; | |
1244 | ||
1245 | /* Validate that we didn't overrun the input array. */ | |
1246 | assert(cum.info_in_idx <= ARRAY_SIZE(info->in)); | |
1247 | /* Validate the backend has enough argument space. */ | |
1248 | assert(cum.arg_slot <= max_reg_slots + max_stk_slots); | |
313bdea8 RH |
1249 | |
1250 | /* | |
1251 | * Relocate the "ref_slot" area to the end of the parameters. | |
1252 | * Minimizing this stack offset helps code size for x86, | |
1253 | * which has a signed 8-bit offset encoding. | |
1254 | */ | |
1255 | if (cum.ref_slot != 0) { | |
1256 | int ref_base = 0; | |
1257 | ||
1258 | if (cum.arg_slot > max_reg_slots) { | |
1259 | int align = __alignof(Int128) / sizeof(tcg_target_long); | |
1260 | ||
1261 | ref_base = cum.arg_slot - max_reg_slots; | |
1262 | if (align > 1) { | |
1263 | ref_base = ROUND_UP(ref_base, align); | |
1264 | } | |
1265 | } | |
1266 | assert(ref_base + cum.ref_slot <= max_stk_slots); | |
d78e4a4f | 1267 | ref_base += max_reg_slots; |
313bdea8 RH |
1268 | |
1269 | if (ref_base != 0) { | |
1270 | for (int i = cum.info_in_idx - 1; i >= 0; --i) { | |
1271 | TCGCallArgumentLoc *loc = &info->in[i]; | |
1272 | switch (loc->kind) { | |
1273 | case TCG_CALL_ARG_BY_REF: | |
1274 | case TCG_CALL_ARG_BY_REF_N: | |
1275 | loc->ref_slot += ref_base; | |
1276 | break; | |
1277 | default: | |
1278 | break; | |
1279 | } | |
1280 | } | |
1281 | } | |
1282 | } | |
39004a71 RH |
1283 | } |
1284 | ||
91478cef | 1285 | static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)]; |
f69d277e | 1286 | static void process_op_defs(TCGContext *s); |
1c2adb95 RH |
1287 | static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, |
1288 | TCGReg reg, const char *name); | |
91478cef | 1289 | |
43b972b7 | 1290 | static void tcg_context_init(unsigned max_cpus) |
c896fe29 | 1291 | { |
a76aabd3 | 1292 | TCGContext *s = &tcg_init_ctx; |
100b5e01 | 1293 | int op, total_args, n, i; |
c896fe29 FB |
1294 | TCGOpDef *def; |
1295 | TCGArgConstraint *args_ct; | |
1c2adb95 | 1296 | TCGTemp *ts; |
c896fe29 FB |
1297 | |
1298 | memset(s, 0, sizeof(*s)); | |
c896fe29 | 1299 | s->nb_globals = 0; |
c70fbf0a | 1300 | |
c896fe29 FB |
1301 | /* Count total number of arguments and allocate the corresponding |
1302 | space */ | |
1303 | total_args = 0; | |
1304 | for(op = 0; op < NB_OPS; op++) { | |
1305 | def = &tcg_op_defs[op]; | |
1306 | n = def->nb_iargs + def->nb_oargs; | |
1307 | total_args += n; | |
1308 | } | |
1309 | ||
bc2b17e6 | 1310 | args_ct = g_new0(TCGArgConstraint, total_args); |
c896fe29 FB |
1311 | |
1312 | for(op = 0; op < NB_OPS; op++) { | |
1313 | def = &tcg_op_defs[op]; | |
1314 | def->args_ct = args_ct; | |
c896fe29 | 1315 | n = def->nb_iargs + def->nb_oargs; |
c896fe29 FB |
1316 | args_ct += n; |
1317 | } | |
5cd8f621 | 1318 | |
8429a1ca RH |
1319 | init_call_layout(&info_helper_ld32_mmu); |
1320 | init_call_layout(&info_helper_ld64_mmu); | |
ebebea53 | 1321 | init_call_layout(&info_helper_ld128_mmu); |
8429a1ca RH |
1322 | init_call_layout(&info_helper_st32_mmu); |
1323 | init_call_layout(&info_helper_st64_mmu); | |
ebebea53 | 1324 | init_call_layout(&info_helper_st128_mmu); |
8429a1ca | 1325 | |
c896fe29 | 1326 | tcg_target_init(s); |
f69d277e | 1327 | process_op_defs(s); |
91478cef RH |
1328 | |
1329 | /* Reverse the order of the saved registers, assuming they're all at | |
1330 | the start of tcg_target_reg_alloc_order. */ | |
1331 | for (n = 0; n < ARRAY_SIZE(tcg_target_reg_alloc_order); ++n) { | |
1332 | int r = tcg_target_reg_alloc_order[n]; | |
1333 | if (tcg_regset_test_reg(tcg_target_call_clobber_regs, r)) { | |
1334 | break; | |
1335 | } | |
1336 | } | |
1337 | for (i = 0; i < n; ++i) { | |
1338 | indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[n - 1 - i]; | |
1339 | } | |
1340 | for (; i < ARRAY_SIZE(tcg_target_reg_alloc_order); ++i) { | |
1341 | indirect_reg_alloc_order[i] = tcg_target_reg_alloc_order[i]; | |
1342 | } | |
b1311c4a | 1343 | |
38b47b19 EC |
1344 | alloc_tcg_plugin_context(s); |
1345 | ||
b1311c4a | 1346 | tcg_ctx = s; |
3468b59e EC |
1347 | /* |
1348 | * In user-mode we simply share the init context among threads, since we | |
1349 | * use a single region. See the documentation tcg_region_init() for the | |
1350 | * reasoning behind this. | |
1351 | * In softmmu we will have at most max_cpus TCG threads. | |
1352 | */ | |
1353 | #ifdef CONFIG_USER_ONLY | |
df2cce29 | 1354 | tcg_ctxs = &tcg_ctx; |
0e2d61cf RH |
1355 | tcg_cur_ctxs = 1; |
1356 | tcg_max_ctxs = 1; | |
3468b59e | 1357 | #else |
0e2d61cf RH |
1358 | tcg_max_ctxs = max_cpus; |
1359 | tcg_ctxs = g_new0(TCGContext *, max_cpus); | |
3468b59e | 1360 | #endif |
1c2adb95 RH |
1361 | |
1362 | tcg_debug_assert(!tcg_regset_test_reg(s->reserved_regs, TCG_AREG0)); | |
1363 | ts = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, TCG_AREG0, "env"); | |
ad75a51e | 1364 | tcg_env = temp_tcgv_ptr(ts); |
9002ec79 | 1365 | } |
b03cce8e | 1366 | |
43b972b7 | 1367 | void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus) |
a76aabd3 | 1368 | { |
43b972b7 RH |
1369 | tcg_context_init(max_cpus); |
1370 | tcg_region_init(tb_size, splitwx, max_cpus); | |
a76aabd3 RH |
1371 | } |
1372 | ||
6e3b2bfd EC |
1373 | /* |
1374 | * Allocate TBs right before their corresponding translated code, making | |
1375 | * sure that TBs and code are on different cache lines. | |
1376 | */ | |
1377 | TranslationBlock *tcg_tb_alloc(TCGContext *s) | |
1378 | { | |
1379 | uintptr_t align = qemu_icache_linesize; | |
1380 | TranslationBlock *tb; | |
1381 | void *next; | |
1382 | ||
e8feb96f | 1383 | retry: |
6e3b2bfd EC |
1384 | tb = (void *)ROUND_UP((uintptr_t)s->code_gen_ptr, align); |
1385 | next = (void *)ROUND_UP((uintptr_t)(tb + 1), align); | |
1386 | ||
1387 | if (unlikely(next > s->code_gen_highwater)) { | |
e8feb96f EC |
1388 | if (tcg_region_alloc(s)) { |
1389 | return NULL; | |
1390 | } | |
1391 | goto retry; | |
6e3b2bfd | 1392 | } |
d73415a3 | 1393 | qatomic_set(&s->code_gen_ptr, next); |
57a26946 | 1394 | s->data_gen_ptr = NULL; |
6e3b2bfd EC |
1395 | return tb; |
1396 | } | |
1397 | ||
9002ec79 RH |
1398 | void tcg_prologue_init(TCGContext *s) |
1399 | { | |
b0a0794a | 1400 | size_t prologue_size; |
8163b749 | 1401 | |
b0a0794a RH |
1402 | s->code_ptr = s->code_gen_ptr; |
1403 | s->code_buf = s->code_gen_ptr; | |
5b38ee31 | 1404 | s->data_gen_ptr = NULL; |
b91ccb31 RH |
1405 | |
1406 | #ifndef CONFIG_TCG_INTERPRETER | |
b0a0794a | 1407 | tcg_qemu_tb_exec = (tcg_prologue_fn *)tcg_splitwx_to_rx(s->code_ptr); |
b91ccb31 | 1408 | #endif |
8163b749 | 1409 | |
5b38ee31 RH |
1410 | #ifdef TCG_TARGET_NEED_POOL_LABELS |
1411 | s->pool_labels = NULL; | |
1412 | #endif | |
1413 | ||
653b87eb | 1414 | qemu_thread_jit_write(); |
8163b749 | 1415 | /* Generate the prologue. */ |
b03cce8e | 1416 | tcg_target_qemu_prologue(s); |
5b38ee31 RH |
1417 | |
1418 | #ifdef TCG_TARGET_NEED_POOL_LABELS | |
1419 | /* Allow the prologue to put e.g. guest_base into a pool entry. */ | |
1420 | { | |
1768987b RH |
1421 | int result = tcg_out_pool_finalize(s); |
1422 | tcg_debug_assert(result == 0); | |
5b38ee31 RH |
1423 | } |
1424 | #endif | |
1425 | ||
b0a0794a | 1426 | prologue_size = tcg_current_code_size(s); |
5584e2db | 1427 | perf_report_prologue(s->code_gen_ptr, prologue_size); |
b0a0794a | 1428 | |
df5d2b16 | 1429 | #ifndef CONFIG_TCG_INTERPRETER |
b0a0794a RH |
1430 | flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s->code_buf), |
1431 | (uintptr_t)s->code_buf, prologue_size); | |
df5d2b16 | 1432 | #endif |
8163b749 | 1433 | |
d6b64b2b | 1434 | if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) { |
c60f599b | 1435 | FILE *logfile = qemu_log_trylock(); |
78b54858 RH |
1436 | if (logfile) { |
1437 | fprintf(logfile, "PROLOGUE: [size=%zu]\n", prologue_size); | |
1438 | if (s->data_gen_ptr) { | |
1439 | size_t code_size = s->data_gen_ptr - s->code_gen_ptr; | |
1440 | size_t data_size = prologue_size - code_size; | |
1441 | size_t i; | |
1442 | ||
1443 | disas(logfile, s->code_gen_ptr, code_size); | |
1444 | ||
1445 | for (i = 0; i < data_size; i += sizeof(tcg_target_ulong)) { | |
1446 | if (sizeof(tcg_target_ulong) == 8) { | |
1447 | fprintf(logfile, | |
1448 | "0x%08" PRIxPTR ": .quad 0x%016" PRIx64 "\n", | |
1449 | (uintptr_t)s->data_gen_ptr + i, | |
1450 | *(uint64_t *)(s->data_gen_ptr + i)); | |
1451 | } else { | |
1452 | fprintf(logfile, | |
1453 | "0x%08" PRIxPTR ": .long 0x%08x\n", | |
1454 | (uintptr_t)s->data_gen_ptr + i, | |
1455 | *(uint32_t *)(s->data_gen_ptr + i)); | |
1456 | } | |
5b38ee31 | 1457 | } |
78b54858 RH |
1458 | } else { |
1459 | disas(logfile, s->code_gen_ptr, prologue_size); | |
5b38ee31 | 1460 | } |
78b54858 | 1461 | fprintf(logfile, "\n"); |
78b54858 | 1462 | qemu_log_unlock(logfile); |
5b38ee31 | 1463 | } |
d6b64b2b | 1464 | } |
cedbcb01 | 1465 | |
6eea0434 RH |
1466 | #ifndef CONFIG_TCG_INTERPRETER |
1467 | /* | |
1468 | * Assert that goto_ptr is implemented completely, setting an epilogue. | |
1469 | * For tci, we use NULL as the signal to return from the interpreter, | |
1470 | * so skip this check. | |
1471 | */ | |
f4e01e30 | 1472 | tcg_debug_assert(tcg_code_gen_epilogue != NULL); |
6eea0434 | 1473 | #endif |
d1c74ab3 RH |
1474 | |
1475 | tcg_region_prologue_set(s); | |
c896fe29 FB |
1476 | } |
1477 | ||
c896fe29 FB |
1478 | void tcg_func_start(TCGContext *s) |
1479 | { | |
1480 | tcg_pool_reset(s); | |
1481 | s->nb_temps = s->nb_globals; | |
0ec9eabc RH |
1482 | |
1483 | /* No temps have been previously allocated for size or locality. */ | |
1484 | memset(s->free_temps, 0, sizeof(s->free_temps)); | |
1485 | ||
c0522136 RH |
1486 | /* No constant temps have been previously allocated. */ |
1487 | for (int i = 0; i < TCG_TYPE_COUNT; ++i) { | |
1488 | if (s->const_table[i]) { | |
1489 | g_hash_table_remove_all(s->const_table[i]); | |
1490 | } | |
1491 | } | |
1492 | ||
abebf925 | 1493 | s->nb_ops = 0; |
c896fe29 FB |
1494 | s->nb_labels = 0; |
1495 | s->current_frame_offset = s->frame_start; | |
1496 | ||
0a209d4b RH |
1497 | #ifdef CONFIG_DEBUG_TCG |
1498 | s->goto_tb_issue_mask = 0; | |
1499 | #endif | |
1500 | ||
15fa08f8 RH |
1501 | QTAILQ_INIT(&s->ops); |
1502 | QTAILQ_INIT(&s->free_ops); | |
bef16ab4 | 1503 | QSIMPLEQ_INIT(&s->labels); |
4baf3978 RH |
1504 | |
1505 | tcg_debug_assert(s->addr_type == TCG_TYPE_I32 || | |
1506 | s->addr_type == TCG_TYPE_I64); | |
d0a9bb5e | 1507 | |
747bd69d | 1508 | tcg_debug_assert(s->insn_start_words > 0); |
c896fe29 FB |
1509 | } |
1510 | ||
ae30e866 | 1511 | static TCGTemp *tcg_temp_alloc(TCGContext *s) |
7ca4b752 RH |
1512 | { |
1513 | int n = s->nb_temps++; | |
ae30e866 RH |
1514 | |
1515 | if (n >= TCG_MAX_TEMPS) { | |
db6b7d0c | 1516 | tcg_raise_tb_overflow(s); |
ae30e866 | 1517 | } |
7ca4b752 RH |
1518 | return memset(&s->temps[n], 0, sizeof(TCGTemp)); |
1519 | } | |
1520 | ||
ae30e866 | 1521 | static TCGTemp *tcg_global_alloc(TCGContext *s) |
7ca4b752 | 1522 | { |
fa477d25 RH |
1523 | TCGTemp *ts; |
1524 | ||
7ca4b752 | 1525 | tcg_debug_assert(s->nb_globals == s->nb_temps); |
ae30e866 | 1526 | tcg_debug_assert(s->nb_globals < TCG_MAX_TEMPS); |
7ca4b752 | 1527 | s->nb_globals++; |
fa477d25 | 1528 | ts = tcg_temp_alloc(s); |
ee17db83 | 1529 | ts->kind = TEMP_GLOBAL; |
fa477d25 RH |
1530 | |
1531 | return ts; | |
c896fe29 FB |
1532 | } |
1533 | ||
085272b3 RH |
1534 | static TCGTemp *tcg_global_reg_new_internal(TCGContext *s, TCGType type, |
1535 | TCGReg reg, const char *name) | |
c896fe29 | 1536 | { |
c896fe29 | 1537 | TCGTemp *ts; |
c896fe29 | 1538 | |
1a057554 | 1539 | tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); |
7ca4b752 RH |
1540 | |
1541 | ts = tcg_global_alloc(s); | |
c896fe29 FB |
1542 | ts->base_type = type; |
1543 | ts->type = type; | |
ee17db83 | 1544 | ts->kind = TEMP_FIXED; |
c896fe29 | 1545 | ts->reg = reg; |
c896fe29 | 1546 | ts->name = name; |
c896fe29 | 1547 | tcg_regset_set_reg(s->reserved_regs, reg); |
7ca4b752 | 1548 | |
085272b3 | 1549 | return ts; |
a7812ae4 PB |
1550 | } |
1551 | ||
b6638662 | 1552 | void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size) |
b3a62939 | 1553 | { |
b3a62939 RH |
1554 | s->frame_start = start; |
1555 | s->frame_end = start + size; | |
085272b3 RH |
1556 | s->frame_temp |
1557 | = tcg_global_reg_new_internal(s, TCG_TYPE_PTR, reg, "_frame"); | |
b3a62939 RH |
1558 | } |
1559 | ||
085272b3 RH |
1560 | TCGTemp *tcg_global_mem_new_internal(TCGType type, TCGv_ptr base, |
1561 | intptr_t offset, const char *name) | |
c896fe29 | 1562 | { |
b1311c4a | 1563 | TCGContext *s = tcg_ctx; |
dc41aa7d | 1564 | TCGTemp *base_ts = tcgv_ptr_temp(base); |
7ca4b752 | 1565 | TCGTemp *ts = tcg_global_alloc(s); |
aef85402 | 1566 | int indirect_reg = 0; |
c896fe29 | 1567 | |
c0522136 RH |
1568 | switch (base_ts->kind) { |
1569 | case TEMP_FIXED: | |
1570 | break; | |
1571 | case TEMP_GLOBAL: | |
5a18407f RH |
1572 | /* We do not support double-indirect registers. */ |
1573 | tcg_debug_assert(!base_ts->indirect_reg); | |
b3915dbb | 1574 | base_ts->indirect_base = 1; |
5a18407f RH |
1575 | s->nb_indirects += (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64 |
1576 | ? 2 : 1); | |
1577 | indirect_reg = 1; | |
c0522136 RH |
1578 | break; |
1579 | default: | |
1580 | g_assert_not_reached(); | |
b3915dbb RH |
1581 | } |
1582 | ||
7ca4b752 RH |
1583 | if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { |
1584 | TCGTemp *ts2 = tcg_global_alloc(s); | |
c896fe29 | 1585 | char buf[64]; |
7ca4b752 RH |
1586 | |
1587 | ts->base_type = TCG_TYPE_I64; | |
c896fe29 | 1588 | ts->type = TCG_TYPE_I32; |
b3915dbb | 1589 | ts->indirect_reg = indirect_reg; |
c896fe29 | 1590 | ts->mem_allocated = 1; |
b3a62939 | 1591 | ts->mem_base = base_ts; |
aef85402 | 1592 | ts->mem_offset = offset; |
c896fe29 FB |
1593 | pstrcpy(buf, sizeof(buf), name); |
1594 | pstrcat(buf, sizeof(buf), "_0"); | |
1595 | ts->name = strdup(buf); | |
c896fe29 | 1596 | |
7ca4b752 RH |
1597 | tcg_debug_assert(ts2 == ts + 1); |
1598 | ts2->base_type = TCG_TYPE_I64; | |
1599 | ts2->type = TCG_TYPE_I32; | |
b3915dbb | 1600 | ts2->indirect_reg = indirect_reg; |
7ca4b752 RH |
1601 | ts2->mem_allocated = 1; |
1602 | ts2->mem_base = base_ts; | |
aef85402 | 1603 | ts2->mem_offset = offset + 4; |
fac87bd2 | 1604 | ts2->temp_subindex = 1; |
c896fe29 FB |
1605 | pstrcpy(buf, sizeof(buf), name); |
1606 | pstrcat(buf, sizeof(buf), "_1"); | |
120c1084 | 1607 | ts2->name = strdup(buf); |
7ca4b752 | 1608 | } else { |
c896fe29 FB |
1609 | ts->base_type = type; |
1610 | ts->type = type; | |
b3915dbb | 1611 | ts->indirect_reg = indirect_reg; |
c896fe29 | 1612 | ts->mem_allocated = 1; |
b3a62939 | 1613 | ts->mem_base = base_ts; |
c896fe29 | 1614 | ts->mem_offset = offset; |
c896fe29 | 1615 | ts->name = name; |
c896fe29 | 1616 | } |
085272b3 | 1617 | return ts; |
a7812ae4 PB |
1618 | } |
1619 | ||
bbf989bf | 1620 | TCGTemp *tcg_temp_new_internal(TCGType type, TCGTempKind kind) |
c896fe29 | 1621 | { |
b1311c4a | 1622 | TCGContext *s = tcg_ctx; |
c896fe29 | 1623 | TCGTemp *ts; |
e1c08b00 | 1624 | int n; |
7ca4b752 | 1625 | |
e1c08b00 RH |
1626 | if (kind == TEMP_EBB) { |
1627 | int idx = find_first_bit(s->free_temps[type].l, TCG_MAX_TEMPS); | |
1628 | ||
1629 | if (idx < TCG_MAX_TEMPS) { | |
1630 | /* There is already an available temp with the right type. */ | |
1631 | clear_bit(idx, s->free_temps[type].l); | |
1632 | ||
1633 | ts = &s->temps[idx]; | |
1634 | ts->temp_allocated = 1; | |
1635 | tcg_debug_assert(ts->base_type == type); | |
1636 | tcg_debug_assert(ts->kind == kind); | |
2f2e911d | 1637 | return ts; |
43eef72f | 1638 | } |
e1c08b00 RH |
1639 | } else { |
1640 | tcg_debug_assert(kind == TEMP_TB); | |
1641 | } | |
7ca4b752 | 1642 | |
e1c08b00 RH |
1643 | switch (type) { |
1644 | case TCG_TYPE_I32: | |
1645 | case TCG_TYPE_V64: | |
1646 | case TCG_TYPE_V128: | |
1647 | case TCG_TYPE_V256: | |
1648 | n = 1; | |
1649 | break; | |
1650 | case TCG_TYPE_I64: | |
1651 | n = 64 / TCG_TARGET_REG_BITS; | |
1652 | break; | |
1653 | case TCG_TYPE_I128: | |
1654 | n = 128 / TCG_TARGET_REG_BITS; | |
1655 | break; | |
1656 | default: | |
1657 | g_assert_not_reached(); | |
1658 | } | |
43eef72f | 1659 | |
e1c08b00 RH |
1660 | ts = tcg_temp_alloc(s); |
1661 | ts->base_type = type; | |
1662 | ts->temp_allocated = 1; | |
1663 | ts->kind = kind; | |
1664 | ||
1665 | if (n == 1) { | |
1666 | ts->type = type; | |
1667 | } else { | |
1668 | ts->type = TCG_TYPE_REG; | |
43eef72f | 1669 | |
e1c08b00 RH |
1670 | for (int i = 1; i < n; ++i) { |
1671 | TCGTemp *ts2 = tcg_temp_alloc(s); | |
43eef72f | 1672 | |
e1c08b00 RH |
1673 | tcg_debug_assert(ts2 == ts + i); |
1674 | ts2->base_type = type; | |
1675 | ts2->type = TCG_TYPE_REG; | |
1676 | ts2->temp_allocated = 1; | |
1677 | ts2->temp_subindex = i; | |
1678 | ts2->kind = kind; | |
e8996ee0 | 1679 | } |
c896fe29 | 1680 | } |
085272b3 | 1681 | return ts; |
c896fe29 FB |
1682 | } |
1683 | ||
d2fd745f RH |
1684 | TCGv_vec tcg_temp_new_vec(TCGType type) |
1685 | { | |
1686 | TCGTemp *t; | |
1687 | ||
1688 | #ifdef CONFIG_DEBUG_TCG | |
1689 | switch (type) { | |
1690 | case TCG_TYPE_V64: | |
1691 | assert(TCG_TARGET_HAS_v64); | |
1692 | break; | |
1693 | case TCG_TYPE_V128: | |
1694 | assert(TCG_TARGET_HAS_v128); | |
1695 | break; | |
1696 | case TCG_TYPE_V256: | |
1697 | assert(TCG_TARGET_HAS_v256); | |
1698 | break; | |
1699 | default: | |
1700 | g_assert_not_reached(); | |
1701 | } | |
1702 | #endif | |
1703 | ||
bbf989bf | 1704 | t = tcg_temp_new_internal(type, TEMP_EBB); |
d2fd745f RH |
1705 | return temp_tcgv_vec(t); |
1706 | } | |
1707 | ||
1708 | /* Create a new temp of the same type as an existing temp. */ | |
1709 | TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match) | |
1710 | { | |
1711 | TCGTemp *t = tcgv_vec_temp(match); | |
1712 | ||
1713 | tcg_debug_assert(t->temp_allocated != 0); | |
1714 | ||
bbf989bf | 1715 | t = tcg_temp_new_internal(t->base_type, TEMP_EBB); |
d2fd745f RH |
1716 | return temp_tcgv_vec(t); |
1717 | } | |
1718 | ||
5bfa8034 | 1719 | void tcg_temp_free_internal(TCGTemp *ts) |
c896fe29 | 1720 | { |
b1311c4a | 1721 | TCGContext *s = tcg_ctx; |
c896fe29 | 1722 | |
c7482438 RH |
1723 | switch (ts->kind) { |
1724 | case TEMP_CONST: | |
f57c6915 | 1725 | case TEMP_TB: |
2f2e911d RH |
1726 | /* Silently ignore free. */ |
1727 | break; | |
1728 | case TEMP_EBB: | |
1729 | tcg_debug_assert(ts->temp_allocated != 0); | |
1730 | ts->temp_allocated = 0; | |
1731 | set_bit(temp_idx(ts), s->free_temps[ts->base_type].l); | |
c7482438 RH |
1732 | break; |
1733 | default: | |
2f2e911d | 1734 | /* It never made sense to free TEMP_FIXED or TEMP_GLOBAL. */ |
c7482438 | 1735 | g_assert_not_reached(); |
c0522136 | 1736 | } |
c896fe29 FB |
1737 | } |
1738 | ||
c0522136 RH |
1739 | TCGTemp *tcg_constant_internal(TCGType type, int64_t val) |
1740 | { | |
1741 | TCGContext *s = tcg_ctx; | |
1742 | GHashTable *h = s->const_table[type]; | |
1743 | TCGTemp *ts; | |
1744 | ||
1745 | if (h == NULL) { | |
1746 | h = g_hash_table_new(g_int64_hash, g_int64_equal); | |
1747 | s->const_table[type] = h; | |
1748 | } | |
1749 | ||
1750 | ts = g_hash_table_lookup(h, &val); | |
1751 | if (ts == NULL) { | |
aef85402 RH |
1752 | int64_t *val_ptr; |
1753 | ||
c0522136 RH |
1754 | ts = tcg_temp_alloc(s); |
1755 | ||
1756 | if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { | |
1757 | TCGTemp *ts2 = tcg_temp_alloc(s); | |
1758 | ||
aef85402 RH |
1759 | tcg_debug_assert(ts2 == ts + 1); |
1760 | ||
c0522136 RH |
1761 | ts->base_type = TCG_TYPE_I64; |
1762 | ts->type = TCG_TYPE_I32; | |
1763 | ts->kind = TEMP_CONST; | |
1764 | ts->temp_allocated = 1; | |
c0522136 | 1765 | |
c0522136 RH |
1766 | ts2->base_type = TCG_TYPE_I64; |
1767 | ts2->type = TCG_TYPE_I32; | |
1768 | ts2->kind = TEMP_CONST; | |
1769 | ts2->temp_allocated = 1; | |
fac87bd2 | 1770 | ts2->temp_subindex = 1; |
aef85402 RH |
1771 | |
1772 | /* | |
1773 | * Retain the full value of the 64-bit constant in the low | |
1774 | * part, so that the hash table works. Actual uses will | |
1775 | * truncate the value to the low part. | |
1776 | */ | |
1777 | ts[HOST_BIG_ENDIAN].val = val; | |
1778 | ts[!HOST_BIG_ENDIAN].val = val >> 32; | |
1779 | val_ptr = &ts[HOST_BIG_ENDIAN].val; | |
c0522136 RH |
1780 | } else { |
1781 | ts->base_type = type; | |
1782 | ts->type = type; | |
1783 | ts->kind = TEMP_CONST; | |
1784 | ts->temp_allocated = 1; | |
1785 | ts->val = val; | |
aef85402 | 1786 | val_ptr = &ts->val; |
c0522136 | 1787 | } |
aef85402 | 1788 | g_hash_table_insert(h, val_ptr, ts); |
c0522136 RH |
1789 | } |
1790 | ||
1791 | return ts; | |
1792 | } | |
1793 | ||
1794 | TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val) | |
1795 | { | |
1796 | val = dup_const(vece, val); | |
1797 | return temp_tcgv_vec(tcg_constant_internal(type, val)); | |
1798 | } | |
1799 | ||
88d4005b RH |
1800 | TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val) |
1801 | { | |
1802 | TCGTemp *t = tcgv_vec_temp(match); | |
1803 | ||
1804 | tcg_debug_assert(t->temp_allocated != 0); | |
1805 | return tcg_constant_vec(t->base_type, vece, val); | |
1806 | } | |
1807 | ||
177f648f RH |
1808 | #ifdef CONFIG_DEBUG_TCG |
1809 | size_t temp_idx(TCGTemp *ts) | |
1810 | { | |
1811 | ptrdiff_t n = ts - tcg_ctx->temps; | |
1812 | assert(n >= 0 && n < tcg_ctx->nb_temps); | |
1813 | return n; | |
1814 | } | |
1815 | ||
1816 | TCGTemp *tcgv_i32_temp(TCGv_i32 v) | |
1817 | { | |
1818 | uintptr_t o = (uintptr_t)v - offsetof(TCGContext, temps); | |
1819 | ||
1820 | assert(o < sizeof(TCGTemp) * tcg_ctx->nb_temps); | |
1821 | assert(o % sizeof(TCGTemp) == 0); | |
1822 | ||
1823 | return (void *)tcg_ctx + (uintptr_t)v; | |
1824 | } | |
1825 | #endif /* CONFIG_DEBUG_TCG */ | |
1826 | ||
be0f34b5 RH |
1827 | /* Return true if OP may appear in the opcode stream. |
1828 | Test the runtime variable that controls each opcode. */ | |
1829 | bool tcg_op_supported(TCGOpcode op) | |
1830 | { | |
d2fd745f RH |
1831 | const bool have_vec |
1832 | = TCG_TARGET_HAS_v64 | TCG_TARGET_HAS_v128 | TCG_TARGET_HAS_v256; | |
1833 | ||
be0f34b5 RH |
1834 | switch (op) { |
1835 | case INDEX_op_discard: | |
1836 | case INDEX_op_set_label: | |
1837 | case INDEX_op_call: | |
1838 | case INDEX_op_br: | |
1839 | case INDEX_op_mb: | |
1840 | case INDEX_op_insn_start: | |
1841 | case INDEX_op_exit_tb: | |
1842 | case INDEX_op_goto_tb: | |
f4e01e30 | 1843 | case INDEX_op_goto_ptr: |
fecccfcc RH |
1844 | case INDEX_op_qemu_ld_a32_i32: |
1845 | case INDEX_op_qemu_ld_a64_i32: | |
1846 | case INDEX_op_qemu_st_a32_i32: | |
1847 | case INDEX_op_qemu_st_a64_i32: | |
1848 | case INDEX_op_qemu_ld_a32_i64: | |
1849 | case INDEX_op_qemu_ld_a64_i64: | |
1850 | case INDEX_op_qemu_st_a32_i64: | |
1851 | case INDEX_op_qemu_st_a64_i64: | |
be0f34b5 RH |
1852 | return true; |
1853 | ||
fecccfcc RH |
1854 | case INDEX_op_qemu_st8_a32_i32: |
1855 | case INDEX_op_qemu_st8_a64_i32: | |
07ce0b05 RH |
1856 | return TCG_TARGET_HAS_qemu_st8_i32; |
1857 | ||
fecccfcc RH |
1858 | case INDEX_op_qemu_ld_a32_i128: |
1859 | case INDEX_op_qemu_ld_a64_i128: | |
1860 | case INDEX_op_qemu_st_a32_i128: | |
1861 | case INDEX_op_qemu_st_a64_i128: | |
12fde9bc RH |
1862 | return TCG_TARGET_HAS_qemu_ldst_i128; |
1863 | ||
be0f34b5 | 1864 | case INDEX_op_mov_i32: |
be0f34b5 RH |
1865 | case INDEX_op_setcond_i32: |
1866 | case INDEX_op_brcond_i32: | |
1867 | case INDEX_op_ld8u_i32: | |
1868 | case INDEX_op_ld8s_i32: | |
1869 | case INDEX_op_ld16u_i32: | |
1870 | case INDEX_op_ld16s_i32: | |
1871 | case INDEX_op_ld_i32: | |
1872 | case INDEX_op_st8_i32: | |
1873 | case INDEX_op_st16_i32: | |
1874 | case INDEX_op_st_i32: | |
1875 | case INDEX_op_add_i32: | |
1876 | case INDEX_op_sub_i32: | |
1877 | case INDEX_op_mul_i32: | |
1878 | case INDEX_op_and_i32: | |
1879 | case INDEX_op_or_i32: | |
1880 | case INDEX_op_xor_i32: | |
1881 | case INDEX_op_shl_i32: | |
1882 | case INDEX_op_shr_i32: | |
1883 | case INDEX_op_sar_i32: | |
1884 | return true; | |
1885 | ||
3635502d RH |
1886 | case INDEX_op_negsetcond_i32: |
1887 | return TCG_TARGET_HAS_negsetcond_i32; | |
be0f34b5 RH |
1888 | case INDEX_op_movcond_i32: |
1889 | return TCG_TARGET_HAS_movcond_i32; | |
1890 | case INDEX_op_div_i32: | |
1891 | case INDEX_op_divu_i32: | |
1892 | return TCG_TARGET_HAS_div_i32; | |
1893 | case INDEX_op_rem_i32: | |
1894 | case INDEX_op_remu_i32: | |
1895 | return TCG_TARGET_HAS_rem_i32; | |
1896 | case INDEX_op_div2_i32: | |
1897 | case INDEX_op_divu2_i32: | |
1898 | return TCG_TARGET_HAS_div2_i32; | |
1899 | case INDEX_op_rotl_i32: | |
1900 | case INDEX_op_rotr_i32: | |
1901 | return TCG_TARGET_HAS_rot_i32; | |
1902 | case INDEX_op_deposit_i32: | |
1903 | return TCG_TARGET_HAS_deposit_i32; | |
1904 | case INDEX_op_extract_i32: | |
1905 | return TCG_TARGET_HAS_extract_i32; | |
1906 | case INDEX_op_sextract_i32: | |
1907 | return TCG_TARGET_HAS_sextract_i32; | |
fce1296f RH |
1908 | case INDEX_op_extract2_i32: |
1909 | return TCG_TARGET_HAS_extract2_i32; | |
be0f34b5 RH |
1910 | case INDEX_op_add2_i32: |
1911 | return TCG_TARGET_HAS_add2_i32; | |
1912 | case INDEX_op_sub2_i32: | |
1913 | return TCG_TARGET_HAS_sub2_i32; | |
1914 | case INDEX_op_mulu2_i32: | |
1915 | return TCG_TARGET_HAS_mulu2_i32; | |
1916 | case INDEX_op_muls2_i32: | |
1917 | return TCG_TARGET_HAS_muls2_i32; | |
1918 | case INDEX_op_muluh_i32: | |
1919 | return TCG_TARGET_HAS_muluh_i32; | |
1920 | case INDEX_op_mulsh_i32: | |
1921 | return TCG_TARGET_HAS_mulsh_i32; | |
1922 | case INDEX_op_ext8s_i32: | |
1923 | return TCG_TARGET_HAS_ext8s_i32; | |
1924 | case INDEX_op_ext16s_i32: | |
1925 | return TCG_TARGET_HAS_ext16s_i32; | |
1926 | case INDEX_op_ext8u_i32: | |
1927 | return TCG_TARGET_HAS_ext8u_i32; | |
1928 | case INDEX_op_ext16u_i32: | |
1929 | return TCG_TARGET_HAS_ext16u_i32; | |
1930 | case INDEX_op_bswap16_i32: | |
1931 | return TCG_TARGET_HAS_bswap16_i32; | |
1932 | case INDEX_op_bswap32_i32: | |
1933 | return TCG_TARGET_HAS_bswap32_i32; | |
1934 | case INDEX_op_not_i32: | |
1935 | return TCG_TARGET_HAS_not_i32; | |
1936 | case INDEX_op_neg_i32: | |
1937 | return TCG_TARGET_HAS_neg_i32; | |
1938 | case INDEX_op_andc_i32: | |
1939 | return TCG_TARGET_HAS_andc_i32; | |
1940 | case INDEX_op_orc_i32: | |
1941 | return TCG_TARGET_HAS_orc_i32; | |
1942 | case INDEX_op_eqv_i32: | |
1943 | return TCG_TARGET_HAS_eqv_i32; | |
1944 | case INDEX_op_nand_i32: | |
1945 | return TCG_TARGET_HAS_nand_i32; | |
1946 | case INDEX_op_nor_i32: | |
1947 | return TCG_TARGET_HAS_nor_i32; | |
1948 | case INDEX_op_clz_i32: | |
1949 | return TCG_TARGET_HAS_clz_i32; | |
1950 | case INDEX_op_ctz_i32: | |
1951 | return TCG_TARGET_HAS_ctz_i32; | |
1952 | case INDEX_op_ctpop_i32: | |
1953 | return TCG_TARGET_HAS_ctpop_i32; | |
1954 | ||
1955 | case INDEX_op_brcond2_i32: | |
1956 | case INDEX_op_setcond2_i32: | |
1957 | return TCG_TARGET_REG_BITS == 32; | |
1958 | ||
1959 | case INDEX_op_mov_i64: | |
be0f34b5 RH |
1960 | case INDEX_op_setcond_i64: |
1961 | case INDEX_op_brcond_i64: | |
1962 | case INDEX_op_ld8u_i64: | |
1963 | case INDEX_op_ld8s_i64: | |
1964 | case INDEX_op_ld16u_i64: | |
1965 | case INDEX_op_ld16s_i64: | |
1966 | case INDEX_op_ld32u_i64: | |
1967 | case INDEX_op_ld32s_i64: | |
1968 | case INDEX_op_ld_i64: | |
1969 | case INDEX_op_st8_i64: | |
1970 | case INDEX_op_st16_i64: | |
1971 | case INDEX_op_st32_i64: | |
1972 | case INDEX_op_st_i64: | |
1973 | case INDEX_op_add_i64: | |
1974 | case INDEX_op_sub_i64: | |
1975 | case INDEX_op_mul_i64: | |
1976 | case INDEX_op_and_i64: | |
1977 | case INDEX_op_or_i64: | |
1978 | case INDEX_op_xor_i64: | |
1979 | case INDEX_op_shl_i64: | |
1980 | case INDEX_op_shr_i64: | |
1981 | case INDEX_op_sar_i64: | |
1982 | case INDEX_op_ext_i32_i64: | |
1983 | case INDEX_op_extu_i32_i64: | |
1984 | return TCG_TARGET_REG_BITS == 64; | |
1985 | ||
3635502d RH |
1986 | case INDEX_op_negsetcond_i64: |
1987 | return TCG_TARGET_HAS_negsetcond_i64; | |
be0f34b5 RH |
1988 | case INDEX_op_movcond_i64: |
1989 | return TCG_TARGET_HAS_movcond_i64; | |
1990 | case INDEX_op_div_i64: | |
1991 | case INDEX_op_divu_i64: | |
1992 | return TCG_TARGET_HAS_div_i64; | |
1993 | case INDEX_op_rem_i64: | |
1994 | case INDEX_op_remu_i64: | |
1995 | return TCG_TARGET_HAS_rem_i64; | |
1996 | case INDEX_op_div2_i64: | |
1997 | case INDEX_op_divu2_i64: | |
1998 | return TCG_TARGET_HAS_div2_i64; | |
1999 | case INDEX_op_rotl_i64: | |
2000 | case INDEX_op_rotr_i64: | |
2001 | return TCG_TARGET_HAS_rot_i64; | |
2002 | case INDEX_op_deposit_i64: | |
2003 | return TCG_TARGET_HAS_deposit_i64; | |
2004 | case INDEX_op_extract_i64: | |
2005 | return TCG_TARGET_HAS_extract_i64; | |
2006 | case INDEX_op_sextract_i64: | |
2007 | return TCG_TARGET_HAS_sextract_i64; | |
fce1296f RH |
2008 | case INDEX_op_extract2_i64: |
2009 | return TCG_TARGET_HAS_extract2_i64; | |
be0f34b5 | 2010 | case INDEX_op_extrl_i64_i32: |
be0f34b5 | 2011 | case INDEX_op_extrh_i64_i32: |
13d885b0 | 2012 | return TCG_TARGET_HAS_extr_i64_i32; |
be0f34b5 RH |
2013 | case INDEX_op_ext8s_i64: |
2014 | return TCG_TARGET_HAS_ext8s_i64; | |
2015 | case INDEX_op_ext16s_i64: | |
2016 | return TCG_TARGET_HAS_ext16s_i64; | |
2017 | case INDEX_op_ext32s_i64: | |
2018 | return TCG_TARGET_HAS_ext32s_i64; | |
2019 | case INDEX_op_ext8u_i64: | |
2020 | return TCG_TARGET_HAS_ext8u_i64; | |
2021 | case INDEX_op_ext16u_i64: | |
2022 | return TCG_TARGET_HAS_ext16u_i64; | |
2023 | case INDEX_op_ext32u_i64: | |
2024 | return TCG_TARGET_HAS_ext32u_i64; | |
2025 | case INDEX_op_bswap16_i64: | |
2026 | return TCG_TARGET_HAS_bswap16_i64; | |
2027 | case INDEX_op_bswap32_i64: | |
2028 | return TCG_TARGET_HAS_bswap32_i64; | |
2029 | case INDEX_op_bswap64_i64: | |
2030 | return TCG_TARGET_HAS_bswap64_i64; | |
2031 | case INDEX_op_not_i64: | |
2032 | return TCG_TARGET_HAS_not_i64; | |
2033 | case INDEX_op_neg_i64: | |
2034 | return TCG_TARGET_HAS_neg_i64; | |
2035 | case INDEX_op_andc_i64: | |
2036 | return TCG_TARGET_HAS_andc_i64; | |
2037 | case INDEX_op_orc_i64: | |
2038 | return TCG_TARGET_HAS_orc_i64; | |
2039 | case INDEX_op_eqv_i64: | |
2040 | return TCG_TARGET_HAS_eqv_i64; | |
2041 | case INDEX_op_nand_i64: | |
2042 | return TCG_TARGET_HAS_nand_i64; | |
2043 | case INDEX_op_nor_i64: | |
2044 | return TCG_TARGET_HAS_nor_i64; | |
2045 | case INDEX_op_clz_i64: | |
2046 | return TCG_TARGET_HAS_clz_i64; | |
2047 | case INDEX_op_ctz_i64: | |
2048 | return TCG_TARGET_HAS_ctz_i64; | |
2049 | case INDEX_op_ctpop_i64: | |
2050 | return TCG_TARGET_HAS_ctpop_i64; | |
2051 | case INDEX_op_add2_i64: | |
2052 | return TCG_TARGET_HAS_add2_i64; | |
2053 | case INDEX_op_sub2_i64: | |
2054 | return TCG_TARGET_HAS_sub2_i64; | |
2055 | case INDEX_op_mulu2_i64: | |
2056 | return TCG_TARGET_HAS_mulu2_i64; | |
2057 | case INDEX_op_muls2_i64: | |
2058 | return TCG_TARGET_HAS_muls2_i64; | |
2059 | case INDEX_op_muluh_i64: | |
2060 | return TCG_TARGET_HAS_muluh_i64; | |
2061 | case INDEX_op_mulsh_i64: | |
2062 | return TCG_TARGET_HAS_mulsh_i64; | |
2063 | ||
d2fd745f RH |
2064 | case INDEX_op_mov_vec: |
2065 | case INDEX_op_dup_vec: | |
37ee55a0 | 2066 | case INDEX_op_dupm_vec: |
d2fd745f RH |
2067 | case INDEX_op_ld_vec: |
2068 | case INDEX_op_st_vec: | |
2069 | case INDEX_op_add_vec: | |
2070 | case INDEX_op_sub_vec: | |
2071 | case INDEX_op_and_vec: | |
2072 | case INDEX_op_or_vec: | |
2073 | case INDEX_op_xor_vec: | |
212be173 | 2074 | case INDEX_op_cmp_vec: |
d2fd745f RH |
2075 | return have_vec; |
2076 | case INDEX_op_dup2_vec: | |
2077 | return have_vec && TCG_TARGET_REG_BITS == 32; | |
2078 | case INDEX_op_not_vec: | |
2079 | return have_vec && TCG_TARGET_HAS_not_vec; | |
2080 | case INDEX_op_neg_vec: | |
2081 | return have_vec && TCG_TARGET_HAS_neg_vec; | |
bcefc902 RH |
2082 | case INDEX_op_abs_vec: |
2083 | return have_vec && TCG_TARGET_HAS_abs_vec; | |
d2fd745f RH |
2084 | case INDEX_op_andc_vec: |
2085 | return have_vec && TCG_TARGET_HAS_andc_vec; | |
2086 | case INDEX_op_orc_vec: | |
2087 | return have_vec && TCG_TARGET_HAS_orc_vec; | |
ed523473 RH |
2088 | case INDEX_op_nand_vec: |
2089 | return have_vec && TCG_TARGET_HAS_nand_vec; | |
2090 | case INDEX_op_nor_vec: | |
2091 | return have_vec && TCG_TARGET_HAS_nor_vec; | |
2092 | case INDEX_op_eqv_vec: | |
2093 | return have_vec && TCG_TARGET_HAS_eqv_vec; | |
3774030a RH |
2094 | case INDEX_op_mul_vec: |
2095 | return have_vec && TCG_TARGET_HAS_mul_vec; | |
d0ec9796 RH |
2096 | case INDEX_op_shli_vec: |
2097 | case INDEX_op_shri_vec: | |
2098 | case INDEX_op_sari_vec: | |
2099 | return have_vec && TCG_TARGET_HAS_shi_vec; | |
2100 | case INDEX_op_shls_vec: | |
2101 | case INDEX_op_shrs_vec: | |
2102 | case INDEX_op_sars_vec: | |
2103 | return have_vec && TCG_TARGET_HAS_shs_vec; | |
2104 | case INDEX_op_shlv_vec: | |
2105 | case INDEX_op_shrv_vec: | |
2106 | case INDEX_op_sarv_vec: | |
2107 | return have_vec && TCG_TARGET_HAS_shv_vec; | |
b0f7e744 RH |
2108 | case INDEX_op_rotli_vec: |
2109 | return have_vec && TCG_TARGET_HAS_roti_vec; | |
23850a74 RH |
2110 | case INDEX_op_rotls_vec: |
2111 | return have_vec && TCG_TARGET_HAS_rots_vec; | |
5d0ceda9 RH |
2112 | case INDEX_op_rotlv_vec: |
2113 | case INDEX_op_rotrv_vec: | |
2114 | return have_vec && TCG_TARGET_HAS_rotv_vec; | |
8afaf050 RH |
2115 | case INDEX_op_ssadd_vec: |
2116 | case INDEX_op_usadd_vec: | |
2117 | case INDEX_op_sssub_vec: | |
2118 | case INDEX_op_ussub_vec: | |
2119 | return have_vec && TCG_TARGET_HAS_sat_vec; | |
dd0a0fcd RH |
2120 | case INDEX_op_smin_vec: |
2121 | case INDEX_op_umin_vec: | |
2122 | case INDEX_op_smax_vec: | |
2123 | case INDEX_op_umax_vec: | |
2124 | return have_vec && TCG_TARGET_HAS_minmax_vec; | |
38dc1294 RH |
2125 | case INDEX_op_bitsel_vec: |
2126 | return have_vec && TCG_TARGET_HAS_bitsel_vec; | |
f75da298 RH |
2127 | case INDEX_op_cmpsel_vec: |
2128 | return have_vec && TCG_TARGET_HAS_cmpsel_vec; | |
d2fd745f | 2129 | |
db432672 RH |
2130 | default: |
2131 | tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS); | |
2132 | return true; | |
be0f34b5 | 2133 | } |
be0f34b5 RH |
2134 | } |
2135 | ||
39004a71 RH |
2136 | static TCGOp *tcg_op_alloc(TCGOpcode opc, unsigned nargs); |
2137 | ||
a3a692b8 | 2138 | static void tcg_gen_callN(TCGHelperInfo *info, TCGTemp *ret, TCGTemp **args) |
c896fe29 | 2139 | { |
39004a71 RH |
2140 | TCGv_i64 extend_free[MAX_CALL_IARGS]; |
2141 | int n_extend = 0; | |
75e8b9b7 | 2142 | TCGOp *op; |
39004a71 | 2143 | int i, n, pi = 0, total_args; |
afb49896 | 2144 | |
d53106c9 RH |
2145 | if (unlikely(g_once_init_enter(HELPER_INFO_INIT(info)))) { |
2146 | init_call_layout(info); | |
2147 | g_once_init_leave(HELPER_INFO_INIT(info), HELPER_INFO_INIT_VAL(info)); | |
2148 | } | |
2149 | ||
39004a71 RH |
2150 | total_args = info->nr_out + info->nr_in + 2; |
2151 | op = tcg_op_alloc(INDEX_op_call, total_args); | |
2bece2c8 | 2152 | |
38b47b19 | 2153 | #ifdef CONFIG_PLUGIN |
17083f6f EC |
2154 | /* Flag helpers that may affect guest state */ |
2155 | if (tcg_ctx->plugin_insn && | |
2156 | !(info->flags & TCG_CALL_PLUGIN) && | |
2157 | !(info->flags & TCG_CALL_NO_SIDE_EFFECTS)) { | |
38b47b19 EC |
2158 | tcg_ctx->plugin_insn->calls_helpers = true; |
2159 | } | |
2160 | #endif | |
2161 | ||
39004a71 RH |
2162 | TCGOP_CALLO(op) = n = info->nr_out; |
2163 | switch (n) { | |
2164 | case 0: | |
2165 | tcg_debug_assert(ret == NULL); | |
2166 | break; | |
2167 | case 1: | |
2168 | tcg_debug_assert(ret != NULL); | |
2169 | op->args[pi++] = temp_arg(ret); | |
2170 | break; | |
2171 | case 2: | |
466d3759 | 2172 | case 4: |
39004a71 | 2173 | tcg_debug_assert(ret != NULL); |
466d3759 | 2174 | tcg_debug_assert(ret->base_type == ret->type + ctz32(n)); |
39004a71 | 2175 | tcg_debug_assert(ret->temp_subindex == 0); |
466d3759 RH |
2176 | for (i = 0; i < n; ++i) { |
2177 | op->args[pi++] = temp_arg(ret + i); | |
2178 | } | |
39004a71 RH |
2179 | break; |
2180 | default: | |
2181 | g_assert_not_reached(); | |
2182 | } | |
2183 | ||
2184 | TCGOP_CALLI(op) = n = info->nr_in; | |
2185 | for (i = 0; i < n; i++) { | |
2186 | const TCGCallArgumentLoc *loc = &info->in[i]; | |
2187 | TCGTemp *ts = args[loc->arg_idx] + loc->tmp_subindex; | |
2188 | ||
2189 | switch (loc->kind) { | |
2190 | case TCG_CALL_ARG_NORMAL: | |
313bdea8 RH |
2191 | case TCG_CALL_ARG_BY_REF: |
2192 | case TCG_CALL_ARG_BY_REF_N: | |
39004a71 RH |
2193 | op->args[pi++] = temp_arg(ts); |
2194 | break; | |
eb8b0224 | 2195 | |
39004a71 RH |
2196 | case TCG_CALL_ARG_EXTEND_U: |
2197 | case TCG_CALL_ARG_EXTEND_S: | |
2198 | { | |
5dd48602 | 2199 | TCGv_i64 temp = tcg_temp_ebb_new_i64(); |
39004a71 RH |
2200 | TCGv_i32 orig = temp_tcgv_i32(ts); |
2201 | ||
2202 | if (loc->kind == TCG_CALL_ARG_EXTEND_S) { | |
eb8b0224 RH |
2203 | tcg_gen_ext_i32_i64(temp, orig); |
2204 | } else { | |
2205 | tcg_gen_extu_i32_i64(temp, orig); | |
2206 | } | |
39004a71 RH |
2207 | op->args[pi++] = tcgv_i64_arg(temp); |
2208 | extend_free[n_extend++] = temp; | |
2bece2c8 | 2209 | } |
e2a9dd6b | 2210 | break; |
7b7d8b2d | 2211 | |
e2a9dd6b RH |
2212 | default: |
2213 | g_assert_not_reached(); | |
c896fe29 FB |
2214 | } |
2215 | } | |
d53106c9 | 2216 | op->args[pi++] = (uintptr_t)info->func; |
3e92aa34 | 2217 | op->args[pi++] = (uintptr_t)info; |
39004a71 | 2218 | tcg_debug_assert(pi == total_args); |
a7812ae4 | 2219 | |
39004a71 | 2220 | QTAILQ_INSERT_TAIL(&tcg_ctx->ops, op, link); |
7319d83a | 2221 | |
39004a71 RH |
2222 | tcg_debug_assert(n_extend < ARRAY_SIZE(extend_free)); |
2223 | for (i = 0; i < n_extend; ++i) { | |
2224 | tcg_temp_free_i64(extend_free[i]); | |
2bece2c8 | 2225 | } |
c896fe29 | 2226 | } |
c896fe29 | 2227 | |
a3a692b8 RH |
2228 | void tcg_gen_call0(TCGHelperInfo *info, TCGTemp *ret) |
2229 | { | |
2230 | tcg_gen_callN(info, ret, NULL); | |
2231 | } | |
2232 | ||
2233 | void tcg_gen_call1(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1) | |
2234 | { | |
2235 | tcg_gen_callN(info, ret, &t1); | |
2236 | } | |
2237 | ||
2238 | void tcg_gen_call2(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, TCGTemp *t2) | |
2239 | { | |
2240 | TCGTemp *args[2] = { t1, t2 }; | |
2241 | tcg_gen_callN(info, ret, args); | |
2242 | } | |
2243 | ||
2244 | void tcg_gen_call3(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, | |
2245 | TCGTemp *t2, TCGTemp *t3) | |
2246 | { | |
2247 | TCGTemp *args[3] = { t1, t2, t3 }; | |
2248 | tcg_gen_callN(info, ret, args); | |
2249 | } | |
2250 | ||
2251 | void tcg_gen_call4(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, | |
2252 | TCGTemp *t2, TCGTemp *t3, TCGTemp *t4) | |
2253 | { | |
2254 | TCGTemp *args[4] = { t1, t2, t3, t4 }; | |
2255 | tcg_gen_callN(info, ret, args); | |
2256 | } | |
2257 | ||
2258 | void tcg_gen_call5(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, | |
2259 | TCGTemp *t2, TCGTemp *t3, TCGTemp *t4, TCGTemp *t5) | |
2260 | { | |
2261 | TCGTemp *args[5] = { t1, t2, t3, t4, t5 }; | |
2262 | tcg_gen_callN(info, ret, args); | |
2263 | } | |
2264 | ||
2265 | void tcg_gen_call6(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, TCGTemp *t2, | |
2266 | TCGTemp *t3, TCGTemp *t4, TCGTemp *t5, TCGTemp *t6) | |
2267 | { | |
2268 | TCGTemp *args[6] = { t1, t2, t3, t4, t5, t6 }; | |
2269 | tcg_gen_callN(info, ret, args); | |
2270 | } | |
2271 | ||
2272 | void tcg_gen_call7(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, | |
2273 | TCGTemp *t2, TCGTemp *t3, TCGTemp *t4, | |
2274 | TCGTemp *t5, TCGTemp *t6, TCGTemp *t7) | |
2275 | { | |
2276 | TCGTemp *args[7] = { t1, t2, t3, t4, t5, t6, t7 }; | |
2277 | tcg_gen_callN(info, ret, args); | |
2278 | } | |
2279 | ||
8fcd3692 | 2280 | static void tcg_reg_alloc_start(TCGContext *s) |
c896fe29 | 2281 | { |
ac3b8891 | 2282 | int i, n; |
ac3b8891 | 2283 | |
ee17db83 RH |
2284 | for (i = 0, n = s->nb_temps; i < n; i++) { |
2285 | TCGTemp *ts = &s->temps[i]; | |
2286 | TCGTempVal val = TEMP_VAL_MEM; | |
2287 | ||
2288 | switch (ts->kind) { | |
c0522136 RH |
2289 | case TEMP_CONST: |
2290 | val = TEMP_VAL_CONST; | |
2291 | break; | |
ee17db83 RH |
2292 | case TEMP_FIXED: |
2293 | val = TEMP_VAL_REG; | |
2294 | break; | |
2295 | case TEMP_GLOBAL: | |
2296 | break; | |
c7482438 | 2297 | case TEMP_EBB: |
ee17db83 RH |
2298 | val = TEMP_VAL_DEAD; |
2299 | /* fall through */ | |
f57c6915 | 2300 | case TEMP_TB: |
ee17db83 RH |
2301 | ts->mem_allocated = 0; |
2302 | break; | |
2303 | default: | |
2304 | g_assert_not_reached(); | |
2305 | } | |
2306 | ts->val_type = val; | |
e8996ee0 | 2307 | } |
f8b2f202 RH |
2308 | |
2309 | memset(s->reg_to_temp, 0, sizeof(s->reg_to_temp)); | |
c896fe29 FB |
2310 | } |
2311 | ||
f8b2f202 RH |
2312 | static char *tcg_get_arg_str_ptr(TCGContext *s, char *buf, int buf_size, |
2313 | TCGTemp *ts) | |
c896fe29 | 2314 | { |
1807f4c4 | 2315 | int idx = temp_idx(ts); |
ac56dd48 | 2316 | |
ee17db83 RH |
2317 | switch (ts->kind) { |
2318 | case TEMP_FIXED: | |
2319 | case TEMP_GLOBAL: | |
ac56dd48 | 2320 | pstrcpy(buf, buf_size, ts->name); |
ee17db83 | 2321 | break; |
f57c6915 | 2322 | case TEMP_TB: |
f8b2f202 | 2323 | snprintf(buf, buf_size, "loc%d", idx - s->nb_globals); |
ee17db83 | 2324 | break; |
c7482438 | 2325 | case TEMP_EBB: |
f8b2f202 | 2326 | snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals); |
ee17db83 | 2327 | break; |
c0522136 RH |
2328 | case TEMP_CONST: |
2329 | switch (ts->type) { | |
2330 | case TCG_TYPE_I32: | |
2331 | snprintf(buf, buf_size, "$0x%x", (int32_t)ts->val); | |
2332 | break; | |
2333 | #if TCG_TARGET_REG_BITS > 32 | |
2334 | case TCG_TYPE_I64: | |
2335 | snprintf(buf, buf_size, "$0x%" PRIx64, ts->val); | |
2336 | break; | |
2337 | #endif | |
2338 | case TCG_TYPE_V64: | |
2339 | case TCG_TYPE_V128: | |
2340 | case TCG_TYPE_V256: | |
2341 | snprintf(buf, buf_size, "v%d$0x%" PRIx64, | |
2342 | 64 << (ts->type - TCG_TYPE_V64), ts->val); | |
2343 | break; | |
2344 | default: | |
2345 | g_assert_not_reached(); | |
2346 | } | |
2347 | break; | |
c896fe29 FB |
2348 | } |
2349 | return buf; | |
2350 | } | |
2351 | ||
43439139 RH |
2352 | static char *tcg_get_arg_str(TCGContext *s, char *buf, |
2353 | int buf_size, TCGArg arg) | |
f8b2f202 | 2354 | { |
43439139 | 2355 | return tcg_get_arg_str_ptr(s, buf, buf_size, arg_temp(arg)); |
f8b2f202 RH |
2356 | } |
2357 | ||
f48f3ede BS |
2358 | static const char * const cond_name[] = |
2359 | { | |
0aed257f RH |
2360 | [TCG_COND_NEVER] = "never", |
2361 | [TCG_COND_ALWAYS] = "always", | |
f48f3ede BS |
2362 | [TCG_COND_EQ] = "eq", |
2363 | [TCG_COND_NE] = "ne", | |
2364 | [TCG_COND_LT] = "lt", | |
2365 | [TCG_COND_GE] = "ge", | |
2366 | [TCG_COND_LE] = "le", | |
2367 | [TCG_COND_GT] = "gt", | |
2368 | [TCG_COND_LTU] = "ltu", | |
2369 | [TCG_COND_GEU] = "geu", | |
2370 | [TCG_COND_LEU] = "leu", | |
2371 | [TCG_COND_GTU] = "gtu" | |
2372 | }; | |
2373 | ||
12fde9bc | 2374 | static const char * const ldst_name[(MO_BSWAP | MO_SSIZE) + 1] = |
f713d6ad RH |
2375 | { |
2376 | [MO_UB] = "ub", | |
2377 | [MO_SB] = "sb", | |
2378 | [MO_LEUW] = "leuw", | |
2379 | [MO_LESW] = "lesw", | |
2380 | [MO_LEUL] = "leul", | |
2381 | [MO_LESL] = "lesl", | |
fc313c64 | 2382 | [MO_LEUQ] = "leq", |
f713d6ad RH |
2383 | [MO_BEUW] = "beuw", |
2384 | [MO_BESW] = "besw", | |
2385 | [MO_BEUL] = "beul", | |
2386 | [MO_BESL] = "besl", | |
fc313c64 | 2387 | [MO_BEUQ] = "beq", |
12fde9bc RH |
2388 | [MO_128 + MO_BE] = "beo", |
2389 | [MO_128 + MO_LE] = "leo", | |
f713d6ad RH |
2390 | }; |
2391 | ||
1f00b27f | 2392 | static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = { |
1f00b27f | 2393 | [MO_UNALN >> MO_ASHIFT] = "un+", |
1f00b27f | 2394 | [MO_ALIGN >> MO_ASHIFT] = "al+", |
1f00b27f SS |
2395 | [MO_ALIGN_2 >> MO_ASHIFT] = "al2+", |
2396 | [MO_ALIGN_4 >> MO_ASHIFT] = "al4+", | |
2397 | [MO_ALIGN_8 >> MO_ASHIFT] = "al8+", | |
2398 | [MO_ALIGN_16 >> MO_ASHIFT] = "al16+", | |
2399 | [MO_ALIGN_32 >> MO_ASHIFT] = "al32+", | |
2400 | [MO_ALIGN_64 >> MO_ASHIFT] = "al64+", | |
2401 | }; | |
2402 | ||
37031fef RH |
2403 | static const char * const atom_name[(MO_ATOM_MASK >> MO_ATOM_SHIFT) + 1] = { |
2404 | [MO_ATOM_IFALIGN >> MO_ATOM_SHIFT] = "", | |
2405 | [MO_ATOM_IFALIGN_PAIR >> MO_ATOM_SHIFT] = "pair+", | |
2406 | [MO_ATOM_WITHIN16 >> MO_ATOM_SHIFT] = "w16+", | |
2407 | [MO_ATOM_WITHIN16_PAIR >> MO_ATOM_SHIFT] = "w16p+", | |
2408 | [MO_ATOM_SUBALIGN >> MO_ATOM_SHIFT] = "sub+", | |
2409 | [MO_ATOM_NONE >> MO_ATOM_SHIFT] = "noat+", | |
2410 | }; | |
2411 | ||
587195bd RH |
2412 | static const char bswap_flag_name[][6] = { |
2413 | [TCG_BSWAP_IZ] = "iz", | |
2414 | [TCG_BSWAP_OZ] = "oz", | |
2415 | [TCG_BSWAP_OS] = "os", | |
2416 | [TCG_BSWAP_IZ | TCG_BSWAP_OZ] = "iz,oz", | |
2417 | [TCG_BSWAP_IZ | TCG_BSWAP_OS] = "iz,os", | |
2418 | }; | |
2419 | ||
b016486e RH |
2420 | static inline bool tcg_regset_single(TCGRegSet d) |
2421 | { | |
2422 | return (d & (d - 1)) == 0; | |
2423 | } | |
2424 | ||
2425 | static inline TCGReg tcg_regset_first(TCGRegSet d) | |
2426 | { | |
2427 | if (TCG_TARGET_NB_REGS <= 32) { | |
2428 | return ctz32(d); | |
2429 | } else { | |
2430 | return ctz64(d); | |
2431 | } | |
2432 | } | |
2433 | ||
b7a83ff8 RH |
2434 | /* Return only the number of characters output -- no error return. */ |
2435 | #define ne_fprintf(...) \ | |
2436 | ({ int ret_ = fprintf(__VA_ARGS__); ret_ >= 0 ? ret_ : 0; }) | |
2437 | ||
2438 | static void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs) | |
c896fe29 | 2439 | { |
c896fe29 | 2440 | char buf[128]; |
c45cb8bb | 2441 | TCGOp *op; |
c45cb8bb | 2442 | |
15fa08f8 | 2443 | QTAILQ_FOREACH(op, &s->ops, link) { |
c45cb8bb RH |
2444 | int i, k, nb_oargs, nb_iargs, nb_cargs; |
2445 | const TCGOpDef *def; | |
c45cb8bb | 2446 | TCGOpcode c; |
bdfb460e | 2447 | int col = 0; |
c896fe29 | 2448 | |
c45cb8bb | 2449 | c = op->opc; |
c896fe29 | 2450 | def = &tcg_op_defs[c]; |
c45cb8bb | 2451 | |
765b842a | 2452 | if (c == INDEX_op_insn_start) { |
b016486e | 2453 | nb_oargs = 0; |
b7a83ff8 | 2454 | col += ne_fprintf(f, "\n ----"); |
9aef40ed | 2455 | |
747bd69d | 2456 | for (i = 0, k = s->insn_start_words; i < k; ++i) { |
c9ad8d27 RH |
2457 | col += ne_fprintf(f, " %016" PRIx64, |
2458 | tcg_get_insn_start_param(op, i)); | |
eeacee4d | 2459 | } |
7e4597d7 | 2460 | } else if (c == INDEX_op_call) { |
3e92aa34 | 2461 | const TCGHelperInfo *info = tcg_call_info(op); |
fa52e660 | 2462 | void *func = tcg_call_func(op); |
3e92aa34 | 2463 | |
c896fe29 | 2464 | /* variable number of arguments */ |
cd9090aa RH |
2465 | nb_oargs = TCGOP_CALLO(op); |
2466 | nb_iargs = TCGOP_CALLI(op); | |
c896fe29 | 2467 | nb_cargs = def->nb_cargs; |
c896fe29 | 2468 | |
b7a83ff8 | 2469 | col += ne_fprintf(f, " %s ", def->name); |
3e92aa34 RH |
2470 | |
2471 | /* | |
2472 | * Print the function name from TCGHelperInfo, if available. | |
2473 | * Note that plugins have a template function for the info, | |
2474 | * but the actual function pointer comes from the plugin. | |
2475 | */ | |
3e92aa34 | 2476 | if (func == info->func) { |
b7a83ff8 | 2477 | col += ne_fprintf(f, "%s", info->name); |
3e92aa34 | 2478 | } else { |
b7a83ff8 | 2479 | col += ne_fprintf(f, "plugin(%p)", func); |
3e92aa34 RH |
2480 | } |
2481 | ||
b7a83ff8 | 2482 | col += ne_fprintf(f, ",$0x%x,$%d", info->flags, nb_oargs); |
cf066674 | 2483 | for (i = 0; i < nb_oargs; i++) { |
b7a83ff8 RH |
2484 | col += ne_fprintf(f, ",%s", tcg_get_arg_str(s, buf, sizeof(buf), |
2485 | op->args[i])); | |
b03cce8e | 2486 | } |
cf066674 | 2487 | for (i = 0; i < nb_iargs; i++) { |
efee3746 | 2488 | TCGArg arg = op->args[nb_oargs + i]; |
39004a71 | 2489 | const char *t = tcg_get_arg_str(s, buf, sizeof(buf), arg); |
b7a83ff8 | 2490 | col += ne_fprintf(f, ",%s", t); |
e8996ee0 | 2491 | } |
b03cce8e | 2492 | } else { |
b7a83ff8 | 2493 | col += ne_fprintf(f, " %s ", def->name); |
c45cb8bb RH |
2494 | |
2495 | nb_oargs = def->nb_oargs; | |
2496 | nb_iargs = def->nb_iargs; | |
2497 | nb_cargs = def->nb_cargs; | |
2498 | ||
d2fd745f | 2499 | if (def->flags & TCG_OPF_VECTOR) { |
b7a83ff8 RH |
2500 | col += ne_fprintf(f, "v%d,e%d,", 64 << TCGOP_VECL(op), |
2501 | 8 << TCGOP_VECE(op)); | |
d2fd745f RH |
2502 | } |
2503 | ||
b03cce8e | 2504 | k = 0; |
c45cb8bb | 2505 | for (i = 0; i < nb_oargs; i++) { |
b7a83ff8 RH |
2506 | const char *sep = k ? "," : ""; |
2507 | col += ne_fprintf(f, "%s%s", sep, | |
2508 | tcg_get_arg_str(s, buf, sizeof(buf), | |
2509 | op->args[k++])); | |
b03cce8e | 2510 | } |
c45cb8bb | 2511 | for (i = 0; i < nb_iargs; i++) { |
b7a83ff8 RH |
2512 | const char *sep = k ? "," : ""; |
2513 | col += ne_fprintf(f, "%s%s", sep, | |
2514 | tcg_get_arg_str(s, buf, sizeof(buf), | |
2515 | op->args[k++])); | |
b03cce8e | 2516 | } |
be210acb RH |
2517 | switch (c) { |
2518 | case INDEX_op_brcond_i32: | |
be210acb | 2519 | case INDEX_op_setcond_i32: |
3635502d | 2520 | case INDEX_op_negsetcond_i32: |
ffc5ea09 | 2521 | case INDEX_op_movcond_i32: |
ffc5ea09 | 2522 | case INDEX_op_brcond2_i32: |
be210acb | 2523 | case INDEX_op_setcond2_i32: |
ffc5ea09 | 2524 | case INDEX_op_brcond_i64: |
be210acb | 2525 | case INDEX_op_setcond_i64: |
3635502d | 2526 | case INDEX_op_negsetcond_i64: |
ffc5ea09 | 2527 | case INDEX_op_movcond_i64: |
212be173 | 2528 | case INDEX_op_cmp_vec: |
f75da298 | 2529 | case INDEX_op_cmpsel_vec: |
efee3746 RH |
2530 | if (op->args[k] < ARRAY_SIZE(cond_name) |
2531 | && cond_name[op->args[k]]) { | |
b7a83ff8 | 2532 | col += ne_fprintf(f, ",%s", cond_name[op->args[k++]]); |
eeacee4d | 2533 | } else { |
b7a83ff8 | 2534 | col += ne_fprintf(f, ",$0x%" TCG_PRIlx, op->args[k++]); |
eeacee4d | 2535 | } |
f48f3ede | 2536 | i = 1; |
be210acb | 2537 | break; |
fecccfcc RH |
2538 | case INDEX_op_qemu_ld_a32_i32: |
2539 | case INDEX_op_qemu_ld_a64_i32: | |
2540 | case INDEX_op_qemu_st_a32_i32: | |
2541 | case INDEX_op_qemu_st_a64_i32: | |
2542 | case INDEX_op_qemu_st8_a32_i32: | |
2543 | case INDEX_op_qemu_st8_a64_i32: | |
2544 | case INDEX_op_qemu_ld_a32_i64: | |
2545 | case INDEX_op_qemu_ld_a64_i64: | |
2546 | case INDEX_op_qemu_st_a32_i64: | |
2547 | case INDEX_op_qemu_st_a64_i64: | |
2548 | case INDEX_op_qemu_ld_a32_i128: | |
2549 | case INDEX_op_qemu_ld_a64_i128: | |
2550 | case INDEX_op_qemu_st_a32_i128: | |
2551 | case INDEX_op_qemu_st_a64_i128: | |
59227d5d | 2552 | { |
37031fef | 2553 | const char *s_al, *s_op, *s_at; |
9002ffcb | 2554 | MemOpIdx oi = op->args[k++]; |
9a239c6e | 2555 | MemOp mop = get_memop(oi); |
59227d5d RH |
2556 | unsigned ix = get_mmuidx(oi); |
2557 | ||
9a239c6e PMD |
2558 | s_al = alignment_name[(mop & MO_AMASK) >> MO_ASHIFT]; |
2559 | s_op = ldst_name[mop & (MO_BSWAP | MO_SSIZE)]; | |
2560 | s_at = atom_name[(mop & MO_ATOM_MASK) >> MO_ATOM_SHIFT]; | |
2561 | mop &= ~(MO_AMASK | MO_BSWAP | MO_SSIZE | MO_ATOM_MASK); | |
37031fef RH |
2562 | |
2563 | /* If all fields are accounted for, print symbolically. */ | |
9a239c6e | 2564 | if (!mop && s_al && s_op && s_at) { |
37031fef RH |
2565 | col += ne_fprintf(f, ",%s%s%s,%u", |
2566 | s_at, s_al, s_op, ix); | |
59c4b7e8 | 2567 | } else { |
9a239c6e PMD |
2568 | mop = get_memop(oi); |
2569 | col += ne_fprintf(f, ",$0x%x,%u", mop, ix); | |
59227d5d RH |
2570 | } |
2571 | i = 1; | |
f713d6ad | 2572 | } |
f713d6ad | 2573 | break; |
587195bd RH |
2574 | case INDEX_op_bswap16_i32: |
2575 | case INDEX_op_bswap16_i64: | |
2576 | case INDEX_op_bswap32_i32: | |
2577 | case INDEX_op_bswap32_i64: | |
2578 | case INDEX_op_bswap64_i64: | |
2579 | { | |
2580 | TCGArg flags = op->args[k]; | |
2581 | const char *name = NULL; | |
2582 | ||
2583 | if (flags < ARRAY_SIZE(bswap_flag_name)) { | |
2584 | name = bswap_flag_name[flags]; | |
2585 | } | |
2586 | if (name) { | |
b7a83ff8 | 2587 | col += ne_fprintf(f, ",%s", name); |
587195bd | 2588 | } else { |
b7a83ff8 | 2589 | col += ne_fprintf(f, ",$0x%" TCG_PRIlx, flags); |
587195bd RH |
2590 | } |
2591 | i = k = 1; | |
2592 | } | |
2593 | break; | |
be210acb | 2594 | default: |
f48f3ede | 2595 | i = 0; |
be210acb RH |
2596 | break; |
2597 | } | |
51e3972c RH |
2598 | switch (c) { |
2599 | case INDEX_op_set_label: | |
2600 | case INDEX_op_br: | |
2601 | case INDEX_op_brcond_i32: | |
2602 | case INDEX_op_brcond_i64: | |
2603 | case INDEX_op_brcond2_i32: | |
b7a83ff8 RH |
2604 | col += ne_fprintf(f, "%s$L%d", k ? "," : "", |
2605 | arg_label(op->args[k])->id); | |
51e3972c RH |
2606 | i++, k++; |
2607 | break; | |
3470867b RH |
2608 | case INDEX_op_mb: |
2609 | { | |
2610 | TCGBar membar = op->args[k]; | |
2611 | const char *b_op, *m_op; | |
2612 | ||
2613 | switch (membar & TCG_BAR_SC) { | |
2614 | case 0: | |
2615 | b_op = "none"; | |
2616 | break; | |
2617 | case TCG_BAR_LDAQ: | |
2618 | b_op = "acq"; | |
2619 | break; | |
2620 | case TCG_BAR_STRL: | |
2621 | b_op = "rel"; | |
2622 | break; | |
2623 | case TCG_BAR_SC: | |
2624 | b_op = "seq"; | |
2625 | break; | |
2626 | default: | |
2627 | g_assert_not_reached(); | |
2628 | } | |
2629 | ||
2630 | switch (membar & TCG_MO_ALL) { | |
2631 | case 0: | |
2632 | m_op = "none"; | |
2633 | break; | |
2634 | case TCG_MO_LD_LD: | |
2635 | m_op = "rr"; | |
2636 | break; | |
2637 | case TCG_MO_LD_ST: | |
2638 | m_op = "rw"; | |
2639 | break; | |
2640 | case TCG_MO_ST_LD: | |
2641 | m_op = "wr"; | |
2642 | break; | |
2643 | case TCG_MO_ST_ST: | |
2644 | m_op = "ww"; | |
2645 | break; | |
2646 | case TCG_MO_LD_LD | TCG_MO_LD_ST: | |
2647 | m_op = "rr+rw"; | |
2648 | break; | |
2649 | case TCG_MO_LD_LD | TCG_MO_ST_LD: | |
2650 | m_op = "rr+wr"; | |
2651 | break; | |
2652 | case TCG_MO_LD_LD | TCG_MO_ST_ST: | |
2653 | m_op = "rr+ww"; | |
2654 | break; | |
2655 | case TCG_MO_LD_ST | TCG_MO_ST_LD: | |
2656 | m_op = "rw+wr"; | |
2657 | break; | |
2658 | case TCG_MO_LD_ST | TCG_MO_ST_ST: | |
2659 | m_op = "rw+ww"; | |
2660 | break; | |
2661 | case TCG_MO_ST_LD | TCG_MO_ST_ST: | |
2662 | m_op = "wr+ww"; | |
2663 | break; | |
2664 | case TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_LD: | |
2665 | m_op = "rr+rw+wr"; | |
2666 | break; | |
2667 | case TCG_MO_LD_LD | TCG_MO_LD_ST | TCG_MO_ST_ST: | |
2668 | m_op = "rr+rw+ww"; | |
2669 | break; | |
2670 | case TCG_MO_LD_LD | TCG_MO_ST_LD | TCG_MO_ST_ST: | |
2671 | m_op = "rr+wr+ww"; | |
2672 | break; | |
2673 | case TCG_MO_LD_ST | TCG_MO_ST_LD | TCG_MO_ST_ST: | |
2674 | m_op = "rw+wr+ww"; | |
2675 | break; | |
2676 | case TCG_MO_ALL: | |
2677 | m_op = "all"; | |
2678 | break; | |
2679 | default: | |
2680 | g_assert_not_reached(); | |
2681 | } | |
2682 | ||
2683 | col += ne_fprintf(f, "%s%s:%s", (k ? "," : ""), b_op, m_op); | |
2684 | i++, k++; | |
2685 | } | |
2686 | break; | |
51e3972c RH |
2687 | default: |
2688 | break; | |
2689 | } | |
2690 | for (; i < nb_cargs; i++, k++) { | |
b7a83ff8 RH |
2691 | col += ne_fprintf(f, "%s$0x%" TCG_PRIlx, k ? "," : "", |
2692 | op->args[k]); | |
bdfb460e RH |
2693 | } |
2694 | } | |
bdfb460e | 2695 | |
1894f69a | 2696 | if (have_prefs || op->life) { |
b7a83ff8 RH |
2697 | for (; col < 40; ++col) { |
2698 | putc(' ', f); | |
bdfb460e | 2699 | } |
1894f69a RH |
2700 | } |
2701 | ||
2702 | if (op->life) { | |
2703 | unsigned life = op->life; | |
bdfb460e RH |
2704 | |
2705 | if (life & (SYNC_ARG * 3)) { | |
b7a83ff8 | 2706 | ne_fprintf(f, " sync:"); |
bdfb460e RH |
2707 | for (i = 0; i < 2; ++i) { |
2708 | if (life & (SYNC_ARG << i)) { | |
b7a83ff8 | 2709 | ne_fprintf(f, " %d", i); |
bdfb460e RH |
2710 | } |
2711 | } | |
2712 | } | |
2713 | life /= DEAD_ARG; | |
2714 | if (life) { | |
b7a83ff8 | 2715 | ne_fprintf(f, " dead:"); |
bdfb460e RH |
2716 | for (i = 0; life; ++i, life >>= 1) { |
2717 | if (life & 1) { | |
b7a83ff8 | 2718 | ne_fprintf(f, " %d", i); |
bdfb460e RH |
2719 | } |
2720 | } | |
b03cce8e | 2721 | } |
c896fe29 | 2722 | } |
1894f69a RH |
2723 | |
2724 | if (have_prefs) { | |
2725 | for (i = 0; i < nb_oargs; ++i) { | |
31fd884b | 2726 | TCGRegSet set = output_pref(op, i); |
1894f69a RH |
2727 | |
2728 | if (i == 0) { | |
b7a83ff8 | 2729 | ne_fprintf(f, " pref="); |
1894f69a | 2730 | } else { |
b7a83ff8 | 2731 | ne_fprintf(f, ","); |
1894f69a RH |
2732 | } |
2733 | if (set == 0) { | |
b7a83ff8 | 2734 | ne_fprintf(f, "none"); |
1894f69a | 2735 | } else if (set == MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS)) { |
b7a83ff8 | 2736 | ne_fprintf(f, "all"); |
1894f69a RH |
2737 | #ifdef CONFIG_DEBUG_TCG |
2738 | } else if (tcg_regset_single(set)) { | |
2739 | TCGReg reg = tcg_regset_first(set); | |
b7a83ff8 | 2740 | ne_fprintf(f, "%s", tcg_target_reg_names[reg]); |
1894f69a RH |
2741 | #endif |
2742 | } else if (TCG_TARGET_NB_REGS <= 32) { | |
b7a83ff8 | 2743 | ne_fprintf(f, "0x%x", (uint32_t)set); |
1894f69a | 2744 | } else { |
b7a83ff8 | 2745 | ne_fprintf(f, "0x%" PRIx64, (uint64_t)set); |
1894f69a RH |
2746 | } |
2747 | } | |
2748 | } | |
2749 | ||
b7a83ff8 | 2750 | putc('\n', f); |
c896fe29 FB |
2751 | } |
2752 | } | |
2753 | ||
2754 | /* we give more priority to constraints with less registers */ | |
2755 | static int get_constraint_priority(const TCGOpDef *def, int k) | |
2756 | { | |
74a11790 | 2757 | const TCGArgConstraint *arg_ct = &def->args_ct[k]; |
29f5e925 | 2758 | int n = ctpop64(arg_ct->regs); |
c896fe29 | 2759 | |
29f5e925 RH |
2760 | /* |
2761 | * Sort constraints of a single register first, which includes output | |
2762 | * aliases (which must exactly match the input already allocated). | |
2763 | */ | |
2764 | if (n == 1 || arg_ct->oalias) { | |
2765 | return INT_MAX; | |
2766 | } | |
2767 | ||
2768 | /* | |
2769 | * Sort register pairs next, first then second immediately after. | |
2770 | * Arbitrarily sort multiple pairs by the index of the first reg; | |
2771 | * there shouldn't be many pairs. | |
2772 | */ | |
2773 | switch (arg_ct->pair) { | |
2774 | case 1: | |
2775 | case 3: | |
2776 | return (k + 1) * 2; | |
2777 | case 2: | |
2778 | return (arg_ct->pair_index + 1) * 2 - 1; | |
c896fe29 | 2779 | } |
29f5e925 RH |
2780 | |
2781 | /* Finally, sort by decreasing register count. */ | |
2782 | assert(n > 1); | |
2783 | return -n; | |
c896fe29 FB |
2784 | } |
2785 | ||
2786 | /* sort from highest priority to lowest */ | |
2787 | static void sort_constraints(TCGOpDef *def, int start, int n) | |
2788 | { | |
66792f90 RH |
2789 | int i, j; |
2790 | TCGArgConstraint *a = def->args_ct; | |
c896fe29 | 2791 | |
66792f90 RH |
2792 | for (i = 0; i < n; i++) { |
2793 | a[start + i].sort_index = start + i; | |
2794 | } | |
2795 | if (n <= 1) { | |
c896fe29 | 2796 | return; |
66792f90 RH |
2797 | } |
2798 | for (i = 0; i < n - 1; i++) { | |
2799 | for (j = i + 1; j < n; j++) { | |
2800 | int p1 = get_constraint_priority(def, a[start + i].sort_index); | |
2801 | int p2 = get_constraint_priority(def, a[start + j].sort_index); | |
c896fe29 | 2802 | if (p1 < p2) { |
66792f90 RH |
2803 | int tmp = a[start + i].sort_index; |
2804 | a[start + i].sort_index = a[start + j].sort_index; | |
2805 | a[start + j].sort_index = tmp; | |
c896fe29 FB |
2806 | } |
2807 | } | |
2808 | } | |
2809 | } | |
2810 | ||
f69d277e | 2811 | static void process_op_defs(TCGContext *s) |
c896fe29 | 2812 | { |
a9751609 | 2813 | TCGOpcode op; |
c896fe29 | 2814 | |
f69d277e RH |
2815 | for (op = 0; op < NB_OPS; op++) { |
2816 | TCGOpDef *def = &tcg_op_defs[op]; | |
2817 | const TCGTargetOpDef *tdefs; | |
29f5e925 RH |
2818 | bool saw_alias_pair = false; |
2819 | int i, o, i2, o2, nb_args; | |
f69d277e RH |
2820 | |
2821 | if (def->flags & TCG_OPF_NOT_PRESENT) { | |
2822 | continue; | |
2823 | } | |
2824 | ||
c896fe29 | 2825 | nb_args = def->nb_iargs + def->nb_oargs; |
f69d277e RH |
2826 | if (nb_args == 0) { |
2827 | continue; | |
2828 | } | |
2829 | ||
4c22e840 RH |
2830 | /* |
2831 | * Macro magic should make it impossible, but double-check that | |
2832 | * the array index is in range. Since the signness of an enum | |
2833 | * is implementation defined, force the result to unsigned. | |
2834 | */ | |
2835 | unsigned con_set = tcg_target_op_def(op); | |
2836 | tcg_debug_assert(con_set < ARRAY_SIZE(constraint_sets)); | |
2837 | tdefs = &constraint_sets[con_set]; | |
f69d277e RH |
2838 | |
2839 | for (i = 0; i < nb_args; i++) { | |
2840 | const char *ct_str = tdefs->args_ct_str[i]; | |
8940ea0d PMD |
2841 | bool input_p = i >= def->nb_oargs; |
2842 | ||
f69d277e | 2843 | /* Incomplete TCGTargetOpDef entry. */ |
eabb7b91 | 2844 | tcg_debug_assert(ct_str != NULL); |
f69d277e | 2845 | |
8940ea0d PMD |
2846 | switch (*ct_str) { |
2847 | case '0' ... '9': | |
2848 | o = *ct_str - '0'; | |
2849 | tcg_debug_assert(input_p); | |
2850 | tcg_debug_assert(o < def->nb_oargs); | |
2851 | tcg_debug_assert(def->args_ct[o].regs != 0); | |
2852 | tcg_debug_assert(!def->args_ct[o].oalias); | |
2853 | def->args_ct[i] = def->args_ct[o]; | |
2854 | /* The output sets oalias. */ | |
2855 | def->args_ct[o].oalias = 1; | |
2856 | def->args_ct[o].alias_index = i; | |
2857 | /* The input sets ialias. */ | |
2858 | def->args_ct[i].ialias = 1; | |
2859 | def->args_ct[i].alias_index = o; | |
29f5e925 RH |
2860 | if (def->args_ct[i].pair) { |
2861 | saw_alias_pair = true; | |
2862 | } | |
8940ea0d PMD |
2863 | tcg_debug_assert(ct_str[1] == '\0'); |
2864 | continue; | |
2865 | ||
2866 | case '&': | |
2867 | tcg_debug_assert(!input_p); | |
2868 | def->args_ct[i].newreg = true; | |
2869 | ct_str++; | |
2870 | break; | |
29f5e925 RH |
2871 | |
2872 | case 'p': /* plus */ | |
2873 | /* Allocate to the register after the previous. */ | |
2874 | tcg_debug_assert(i > (input_p ? def->nb_oargs : 0)); | |
2875 | o = i - 1; | |
2876 | tcg_debug_assert(!def->args_ct[o].pair); | |
2877 | tcg_debug_assert(!def->args_ct[o].ct); | |
2878 | def->args_ct[i] = (TCGArgConstraint){ | |
2879 | .pair = 2, | |
2880 | .pair_index = o, | |
2881 | .regs = def->args_ct[o].regs << 1, | |
2882 | }; | |
2883 | def->args_ct[o].pair = 1; | |
2884 | def->args_ct[o].pair_index = i; | |
2885 | tcg_debug_assert(ct_str[1] == '\0'); | |
2886 | continue; | |
2887 | ||
2888 | case 'm': /* minus */ | |
2889 | /* Allocate to the register before the previous. */ | |
2890 | tcg_debug_assert(i > (input_p ? def->nb_oargs : 0)); | |
2891 | o = i - 1; | |
2892 | tcg_debug_assert(!def->args_ct[o].pair); | |
2893 | tcg_debug_assert(!def->args_ct[o].ct); | |
2894 | def->args_ct[i] = (TCGArgConstraint){ | |
2895 | .pair = 1, | |
2896 | .pair_index = o, | |
2897 | .regs = def->args_ct[o].regs >> 1, | |
2898 | }; | |
2899 | def->args_ct[o].pair = 2; | |
2900 | def->args_ct[o].pair_index = i; | |
2901 | tcg_debug_assert(ct_str[1] == '\0'); | |
2902 | continue; | |
8940ea0d PMD |
2903 | } |
2904 | ||
2905 | do { | |
2906 | switch (*ct_str) { | |
17280ff4 RH |
2907 | case 'i': |
2908 | def->args_ct[i].ct |= TCG_CT_CONST; | |
17280ff4 | 2909 | break; |
358b4923 | 2910 | |
358b4923 RH |
2911 | /* Include all of the target-specific constraints. */ |
2912 | ||
2913 | #undef CONST | |
2914 | #define CONST(CASE, MASK) \ | |
8940ea0d | 2915 | case CASE: def->args_ct[i].ct |= MASK; break; |
358b4923 | 2916 | #define REGS(CASE, MASK) \ |
8940ea0d | 2917 | case CASE: def->args_ct[i].regs |= MASK; break; |
358b4923 RH |
2918 | |
2919 | #include "tcg-target-con-str.h" | |
2920 | ||
2921 | #undef REGS | |
2922 | #undef CONST | |
17280ff4 | 2923 | default: |
8940ea0d PMD |
2924 | case '0' ... '9': |
2925 | case '&': | |
29f5e925 RH |
2926 | case 'p': |
2927 | case 'm': | |
17280ff4 | 2928 | /* Typo in TCGTargetOpDef constraint. */ |
358b4923 | 2929 | g_assert_not_reached(); |
c896fe29 | 2930 | } |
8940ea0d | 2931 | } while (*++ct_str != '\0'); |
c896fe29 FB |
2932 | } |
2933 | ||
c68aaa18 | 2934 | /* TCGTargetOpDef entry with too much information? */ |
eabb7b91 | 2935 | tcg_debug_assert(i == TCG_MAX_OP_ARGS || tdefs->args_ct_str[i] == NULL); |
c68aaa18 | 2936 | |
29f5e925 RH |
2937 | /* |
2938 | * Fix up output pairs that are aliased with inputs. | |
2939 | * When we created the alias, we copied pair from the output. | |
2940 | * There are three cases: | |
2941 | * (1a) Pairs of inputs alias pairs of outputs. | |
2942 | * (1b) One input aliases the first of a pair of outputs. | |
2943 | * (2) One input aliases the second of a pair of outputs. | |
2944 | * | |
2945 | * Case 1a is handled by making sure that the pair_index'es are | |
2946 | * properly updated so that they appear the same as a pair of inputs. | |
2947 | * | |
2948 | * Case 1b is handled by setting the pair_index of the input to | |
2949 | * itself, simply so it doesn't point to an unrelated argument. | |
2950 | * Since we don't encounter the "second" during the input allocation | |
2951 | * phase, nothing happens with the second half of the input pair. | |
2952 | * | |
2953 | * Case 2 is handled by setting the second input to pair=3, the | |
2954 | * first output to pair=3, and the pair_index'es to match. | |
2955 | */ | |
2956 | if (saw_alias_pair) { | |
2957 | for (i = def->nb_oargs; i < nb_args; i++) { | |
2958 | /* | |
2959 | * Since [0-9pm] must be alone in the constraint string, | |
2960 | * the only way they can both be set is if the pair comes | |
2961 | * from the output alias. | |
2962 | */ | |
2963 | if (!def->args_ct[i].ialias) { | |
2964 | continue; | |
2965 | } | |
2966 | switch (def->args_ct[i].pair) { | |
2967 | case 0: | |
2968 | break; | |
2969 | case 1: | |
2970 | o = def->args_ct[i].alias_index; | |
2971 | o2 = def->args_ct[o].pair_index; | |
2972 | tcg_debug_assert(def->args_ct[o].pair == 1); | |
2973 | tcg_debug_assert(def->args_ct[o2].pair == 2); | |
2974 | if (def->args_ct[o2].oalias) { | |
2975 | /* Case 1a */ | |
2976 | i2 = def->args_ct[o2].alias_index; | |
2977 | tcg_debug_assert(def->args_ct[i2].pair == 2); | |
2978 | def->args_ct[i2].pair_index = i; | |
2979 | def->args_ct[i].pair_index = i2; | |
2980 | } else { | |
2981 | /* Case 1b */ | |
2982 | def->args_ct[i].pair_index = i; | |
2983 | } | |
2984 | break; | |
2985 | case 2: | |
2986 | o = def->args_ct[i].alias_index; | |
2987 | o2 = def->args_ct[o].pair_index; | |
2988 | tcg_debug_assert(def->args_ct[o].pair == 2); | |
2989 | tcg_debug_assert(def->args_ct[o2].pair == 1); | |
2990 | if (def->args_ct[o2].oalias) { | |
2991 | /* Case 1a */ | |
2992 | i2 = def->args_ct[o2].alias_index; | |
2993 | tcg_debug_assert(def->args_ct[i2].pair == 1); | |
2994 | def->args_ct[i2].pair_index = i; | |
2995 | def->args_ct[i].pair_index = i2; | |
2996 | } else { | |
2997 | /* Case 2 */ | |
2998 | def->args_ct[i].pair = 3; | |
2999 | def->args_ct[o2].pair = 3; | |
3000 | def->args_ct[i].pair_index = o2; | |
3001 | def->args_ct[o2].pair_index = i; | |
3002 | } | |
3003 | break; | |
3004 | default: | |
3005 | g_assert_not_reached(); | |
3006 | } | |
3007 | } | |
3008 | } | |
3009 | ||
c896fe29 FB |
3010 | /* sort the constraints (XXX: this is just an heuristic) */ |
3011 | sort_constraints(def, 0, def->nb_oargs); | |
3012 | sort_constraints(def, def->nb_oargs, def->nb_iargs); | |
a9751609 | 3013 | } |
c896fe29 FB |
3014 | } |
3015 | ||
f85b1fc4 | 3016 | static void remove_label_use(TCGOp *op, int idx) |
0c627cdc | 3017 | { |
f85b1fc4 RH |
3018 | TCGLabel *label = arg_label(op->args[idx]); |
3019 | TCGLabelUse *use; | |
d88a117e | 3020 | |
f85b1fc4 RH |
3021 | QSIMPLEQ_FOREACH(use, &label->branches, next) { |
3022 | if (use->op == op) { | |
3023 | QSIMPLEQ_REMOVE(&label->branches, use, TCGLabelUse, next); | |
3024 | return; | |
3025 | } | |
3026 | } | |
3027 | g_assert_not_reached(); | |
3028 | } | |
3029 | ||
3030 | void tcg_op_remove(TCGContext *s, TCGOp *op) | |
3031 | { | |
d88a117e RH |
3032 | switch (op->opc) { |
3033 | case INDEX_op_br: | |
f85b1fc4 | 3034 | remove_label_use(op, 0); |
d88a117e RH |
3035 | break; |
3036 | case INDEX_op_brcond_i32: | |
3037 | case INDEX_op_brcond_i64: | |
f85b1fc4 | 3038 | remove_label_use(op, 3); |
d88a117e RH |
3039 | break; |
3040 | case INDEX_op_brcond2_i32: | |
f85b1fc4 | 3041 | remove_label_use(op, 5); |
d88a117e RH |
3042 | break; |
3043 | default: | |
3044 | break; | |
3045 | } | |
3046 | ||
15fa08f8 RH |
3047 | QTAILQ_REMOVE(&s->ops, op, link); |
3048 | QTAILQ_INSERT_TAIL(&s->free_ops, op, link); | |
abebf925 | 3049 | s->nb_ops--; |
0c627cdc RH |
3050 | } |
3051 | ||
a80cdd31 RH |
3052 | void tcg_remove_ops_after(TCGOp *op) |
3053 | { | |
3054 | TCGContext *s = tcg_ctx; | |
3055 | ||
3056 | while (true) { | |
3057 | TCGOp *last = tcg_last_op(); | |
3058 | if (last == op) { | |
3059 | return; | |
3060 | } | |
3061 | tcg_op_remove(s, last); | |
3062 | } | |
3063 | } | |
3064 | ||
d4478943 | 3065 | static TCGOp *tcg_op_alloc(TCGOpcode opc, unsigned nargs) |
5a18407f | 3066 | { |
15fa08f8 | 3067 | TCGContext *s = tcg_ctx; |
cb10bc63 RH |
3068 | TCGOp *op = NULL; |
3069 | ||
3070 | if (unlikely(!QTAILQ_EMPTY(&s->free_ops))) { | |
3071 | QTAILQ_FOREACH(op, &s->free_ops, link) { | |
3072 | if (nargs <= op->nargs) { | |
3073 | QTAILQ_REMOVE(&s->free_ops, op, link); | |
3074 | nargs = op->nargs; | |
3075 | goto found; | |
3076 | } | |
3077 | } | |
15fa08f8 | 3078 | } |
cb10bc63 RH |
3079 | |
3080 | /* Most opcodes have 3 or 4 operands: reduce fragmentation. */ | |
3081 | nargs = MAX(4, nargs); | |
3082 | op = tcg_malloc(sizeof(TCGOp) + sizeof(TCGArg) * nargs); | |
3083 | ||
3084 | found: | |
15fa08f8 RH |
3085 | memset(op, 0, offsetof(TCGOp, link)); |
3086 | op->opc = opc; | |
cb10bc63 RH |
3087 | op->nargs = nargs; |
3088 | ||
3089 | /* Check for bitfield overflow. */ | |
3090 | tcg_debug_assert(op->nargs == nargs); | |
5a18407f | 3091 | |
cb10bc63 | 3092 | s->nb_ops++; |
15fa08f8 RH |
3093 | return op; |
3094 | } | |
3095 | ||
d4478943 | 3096 | TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs) |
15fa08f8 | 3097 | { |
d4478943 | 3098 | TCGOp *op = tcg_op_alloc(opc, nargs); |
15fa08f8 RH |
3099 | QTAILQ_INSERT_TAIL(&tcg_ctx->ops, op, link); |
3100 | return op; | |
3101 | } | |
5a18407f | 3102 | |
d4478943 PMD |
3103 | TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *old_op, |
3104 | TCGOpcode opc, unsigned nargs) | |
15fa08f8 | 3105 | { |
d4478943 | 3106 | TCGOp *new_op = tcg_op_alloc(opc, nargs); |
15fa08f8 | 3107 | QTAILQ_INSERT_BEFORE(old_op, new_op, link); |
5a18407f RH |
3108 | return new_op; |
3109 | } | |
3110 | ||
d4478943 PMD |
3111 | TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op, |
3112 | TCGOpcode opc, unsigned nargs) | |
5a18407f | 3113 | { |
d4478943 | 3114 | TCGOp *new_op = tcg_op_alloc(opc, nargs); |
15fa08f8 | 3115 | QTAILQ_INSERT_AFTER(&s->ops, old_op, new_op, link); |
5a18407f RH |
3116 | return new_op; |
3117 | } | |
3118 | ||
968f305e RH |
3119 | static void move_label_uses(TCGLabel *to, TCGLabel *from) |
3120 | { | |
3121 | TCGLabelUse *u; | |
3122 | ||
3123 | QSIMPLEQ_FOREACH(u, &from->branches, next) { | |
3124 | TCGOp *op = u->op; | |
3125 | switch (op->opc) { | |
3126 | case INDEX_op_br: | |
3127 | op->args[0] = label_arg(to); | |
3128 | break; | |
3129 | case INDEX_op_brcond_i32: | |
3130 | case INDEX_op_brcond_i64: | |
3131 | op->args[3] = label_arg(to); | |
3132 | break; | |
3133 | case INDEX_op_brcond2_i32: | |
3134 | op->args[5] = label_arg(to); | |
3135 | break; | |
3136 | default: | |
3137 | g_assert_not_reached(); | |
3138 | } | |
3139 | } | |
3140 | ||
3141 | QSIMPLEQ_CONCAT(&to->branches, &from->branches); | |
3142 | } | |
3143 | ||
b4fc67c7 | 3144 | /* Reachable analysis : remove unreachable code. */ |
9bbee4c0 RH |
3145 | static void __attribute__((noinline)) |
3146 | reachable_code_pass(TCGContext *s) | |
b4fc67c7 | 3147 | { |
4d89d0bb | 3148 | TCGOp *op, *op_next, *op_prev; |
b4fc67c7 RH |
3149 | bool dead = false; |
3150 | ||
3151 | QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { | |
3152 | bool remove = dead; | |
3153 | TCGLabel *label; | |
b4fc67c7 RH |
3154 | |
3155 | switch (op->opc) { | |
3156 | case INDEX_op_set_label: | |
3157 | label = arg_label(op->args[0]); | |
4d89d0bb | 3158 | |
968f305e RH |
3159 | /* |
3160 | * Note that the first op in the TB is always a load, | |
3161 | * so there is always something before a label. | |
3162 | */ | |
3163 | op_prev = QTAILQ_PREV(op, link); | |
3164 | ||
3165 | /* | |
3166 | * If we find two sequential labels, move all branches to | |
3167 | * reference the second label and remove the first label. | |
3168 | * Do this before branch to next optimization, so that the | |
3169 | * middle label is out of the way. | |
3170 | */ | |
3171 | if (op_prev->opc == INDEX_op_set_label) { | |
3172 | move_label_uses(label, arg_label(op_prev->args[0])); | |
3173 | tcg_op_remove(s, op_prev); | |
3174 | op_prev = QTAILQ_PREV(op, link); | |
3175 | } | |
3176 | ||
4d89d0bb RH |
3177 | /* |
3178 | * Optimization can fold conditional branches to unconditional. | |
3179 | * If we find a label which is preceded by an unconditional | |
3180 | * branch to next, remove the branch. We couldn't do this when | |
3181 | * processing the branch because any dead code between the branch | |
3182 | * and label had not yet been removed. | |
3183 | */ | |
4d89d0bb RH |
3184 | if (op_prev->opc == INDEX_op_br && |
3185 | label == arg_label(op_prev->args[0])) { | |
3186 | tcg_op_remove(s, op_prev); | |
3187 | /* Fall through means insns become live again. */ | |
3188 | dead = false; | |
3189 | } | |
3190 | ||
f85b1fc4 | 3191 | if (QSIMPLEQ_EMPTY(&label->branches)) { |
b4fc67c7 RH |
3192 | /* |
3193 | * While there is an occasional backward branch, virtually | |
3194 | * all branches generated by the translators are forward. | |
3195 | * Which means that generally we will have already removed | |
3196 | * all references to the label that will be, and there is | |
3197 | * little to be gained by iterating. | |
3198 | */ | |
3199 | remove = true; | |
3200 | } else { | |
3201 | /* Once we see a label, insns become live again. */ | |
3202 | dead = false; | |
3203 | remove = false; | |
b4fc67c7 RH |
3204 | } |
3205 | break; | |
3206 | ||
3207 | case INDEX_op_br: | |
3208 | case INDEX_op_exit_tb: | |
3209 | case INDEX_op_goto_ptr: | |
3210 | /* Unconditional branches; everything following is dead. */ | |
3211 | dead = true; | |
3212 | break; | |
3213 | ||
3214 | case INDEX_op_call: | |
3215 | /* Notice noreturn helper calls, raising exceptions. */ | |
90163900 | 3216 | if (tcg_call_flags(op) & TCG_CALL_NO_RETURN) { |
b4fc67c7 RH |
3217 | dead = true; |
3218 | } | |
3219 | break; | |
3220 | ||
3221 | case INDEX_op_insn_start: | |
3222 | /* Never remove -- we need to keep these for unwind. */ | |
3223 | remove = false; | |
3224 | break; | |
3225 | ||
3226 | default: | |
3227 | break; | |
3228 | } | |
3229 | ||
3230 | if (remove) { | |
3231 | tcg_op_remove(s, op); | |
3232 | } | |
3233 | } | |
3234 | } | |
3235 | ||
c70fbf0a RH |
3236 | #define TS_DEAD 1 |
3237 | #define TS_MEM 2 | |
3238 | ||
5a18407f RH |
3239 | #define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n))) |
3240 | #define NEED_SYNC_ARG(n) (arg_life & (SYNC_ARG << (n))) | |
3241 | ||
25f49c5f RH |
3242 | /* For liveness_pass_1, the register preferences for a given temp. */ |
3243 | static inline TCGRegSet *la_temp_pref(TCGTemp *ts) | |
3244 | { | |
3245 | return ts->state_ptr; | |
3246 | } | |
3247 | ||
3248 | /* For liveness_pass_1, reset the preferences for a given temp to the | |
3249 | * maximal regset for its type. | |
3250 | */ | |
3251 | static inline void la_reset_pref(TCGTemp *ts) | |
3252 | { | |
3253 | *la_temp_pref(ts) | |
3254 | = (ts->state == TS_DEAD ? 0 : tcg_target_available_regs[ts->type]); | |
3255 | } | |
3256 | ||
9c43b68d AJ |
3257 | /* liveness analysis: end of function: all temps are dead, and globals |
3258 | should be in memory. */ | |
2616c808 | 3259 | static void la_func_end(TCGContext *s, int ng, int nt) |
c896fe29 | 3260 | { |
b83eabea RH |
3261 | int i; |
3262 | ||
3263 | for (i = 0; i < ng; ++i) { | |
3264 | s->temps[i].state = TS_DEAD | TS_MEM; | |
25f49c5f | 3265 | la_reset_pref(&s->temps[i]); |
b83eabea RH |
3266 | } |
3267 | for (i = ng; i < nt; ++i) { | |
3268 | s->temps[i].state = TS_DEAD; | |
25f49c5f | 3269 | la_reset_pref(&s->temps[i]); |
b83eabea | 3270 | } |
c896fe29 FB |
3271 | } |
3272 | ||
9c43b68d AJ |
3273 | /* liveness analysis: end of basic block: all temps are dead, globals |
3274 | and local temps should be in memory. */ | |
2616c808 | 3275 | static void la_bb_end(TCGContext *s, int ng, int nt) |
641d5fbe | 3276 | { |
b83eabea | 3277 | int i; |
641d5fbe | 3278 | |
ee17db83 RH |
3279 | for (i = 0; i < nt; ++i) { |
3280 | TCGTemp *ts = &s->temps[i]; | |
3281 | int state; | |
3282 | ||
3283 | switch (ts->kind) { | |
3284 | case TEMP_FIXED: | |
3285 | case TEMP_GLOBAL: | |
f57c6915 | 3286 | case TEMP_TB: |
ee17db83 RH |
3287 | state = TS_DEAD | TS_MEM; |
3288 | break; | |
c7482438 | 3289 | case TEMP_EBB: |
c0522136 | 3290 | case TEMP_CONST: |
ee17db83 RH |
3291 | state = TS_DEAD; |
3292 | break; | |
3293 | default: | |
3294 | g_assert_not_reached(); | |
3295 | } | |
3296 | ts->state = state; | |
3297 | la_reset_pref(ts); | |
641d5fbe FB |
3298 | } |
3299 | } | |
3300 | ||
f65a061c RH |
3301 | /* liveness analysis: sync globals back to memory. */ |
3302 | static void la_global_sync(TCGContext *s, int ng) | |
3303 | { | |
3304 | int i; | |
3305 | ||
3306 | for (i = 0; i < ng; ++i) { | |
25f49c5f RH |
3307 | int state = s->temps[i].state; |
3308 | s->temps[i].state = state | TS_MEM; | |
3309 | if (state == TS_DEAD) { | |
3310 | /* If the global was previously dead, reset prefs. */ | |
3311 | la_reset_pref(&s->temps[i]); | |
3312 | } | |
f65a061c RH |
3313 | } |
3314 | } | |
3315 | ||
b4cb76e6 | 3316 | /* |
c7482438 RH |
3317 | * liveness analysis: conditional branch: all temps are dead unless |
3318 | * explicitly live-across-conditional-branch, globals and local temps | |
3319 | * should be synced. | |
b4cb76e6 RH |
3320 | */ |
3321 | static void la_bb_sync(TCGContext *s, int ng, int nt) | |
3322 | { | |
3323 | la_global_sync(s, ng); | |
3324 | ||
3325 | for (int i = ng; i < nt; ++i) { | |
c0522136 RH |
3326 | TCGTemp *ts = &s->temps[i]; |
3327 | int state; | |
3328 | ||
3329 | switch (ts->kind) { | |
f57c6915 | 3330 | case TEMP_TB: |
c0522136 RH |
3331 | state = ts->state; |
3332 | ts->state = state | TS_MEM; | |
b4cb76e6 RH |
3333 | if (state != TS_DEAD) { |
3334 | continue; | |
3335 | } | |
c0522136 | 3336 | break; |
c7482438 | 3337 | case TEMP_EBB: |
c0522136 RH |
3338 | case TEMP_CONST: |
3339 | continue; | |
3340 | default: | |
3341 | g_assert_not_reached(); | |
b4cb76e6 RH |
3342 | } |
3343 | la_reset_pref(&s->temps[i]); | |
3344 | } | |
3345 | } | |
3346 | ||
f65a061c RH |
3347 | /* liveness analysis: sync globals back to memory and kill. */ |
3348 | static void la_global_kill(TCGContext *s, int ng) | |
3349 | { | |
3350 | int i; | |
3351 | ||
3352 | for (i = 0; i < ng; i++) { | |
3353 | s->temps[i].state = TS_DEAD | TS_MEM; | |
25f49c5f RH |
3354 | la_reset_pref(&s->temps[i]); |
3355 | } | |
3356 | } | |
3357 | ||
3358 | /* liveness analysis: note live globals crossing calls. */ | |
3359 | static void la_cross_call(TCGContext *s, int nt) | |
3360 | { | |
3361 | TCGRegSet mask = ~tcg_target_call_clobber_regs; | |
3362 | int i; | |
3363 | ||
3364 | for (i = 0; i < nt; i++) { | |
3365 | TCGTemp *ts = &s->temps[i]; | |
3366 | if (!(ts->state & TS_DEAD)) { | |
3367 | TCGRegSet *pset = la_temp_pref(ts); | |
3368 | TCGRegSet set = *pset; | |
3369 | ||
3370 | set &= mask; | |
3371 | /* If the combination is not possible, restart. */ | |
3372 | if (set == 0) { | |
3373 | set = tcg_target_available_regs[ts->type] & mask; | |
3374 | } | |
3375 | *pset = set; | |
3376 | } | |
f65a061c RH |
3377 | } |
3378 | } | |
3379 | ||
874b8574 RH |
3380 | /* |
3381 | * Liveness analysis: Verify the lifetime of TEMP_TB, and reduce | |
3382 | * to TEMP_EBB, if possible. | |
3383 | */ | |
3384 | static void __attribute__((noinline)) | |
3385 | liveness_pass_0(TCGContext *s) | |
3386 | { | |
3387 | void * const multiple_ebb = (void *)(uintptr_t)-1; | |
3388 | int nb_temps = s->nb_temps; | |
3389 | TCGOp *op, *ebb; | |
3390 | ||
3391 | for (int i = s->nb_globals; i < nb_temps; ++i) { | |
3392 | s->temps[i].state_ptr = NULL; | |
3393 | } | |
3394 | ||
3395 | /* | |
3396 | * Represent each EBB by the op at which it begins. In the case of | |
3397 | * the first EBB, this is the first op, otherwise it is a label. | |
3398 | * Collect the uses of each TEMP_TB: NULL for unused, EBB for use | |
3399 | * within a single EBB, else MULTIPLE_EBB. | |
3400 | */ | |
3401 | ebb = QTAILQ_FIRST(&s->ops); | |
3402 | QTAILQ_FOREACH(op, &s->ops, link) { | |
3403 | const TCGOpDef *def; | |
3404 | int nb_oargs, nb_iargs; | |
3405 | ||
3406 | switch (op->opc) { | |
3407 | case INDEX_op_set_label: | |
3408 | ebb = op; | |
3409 | continue; | |
3410 | case INDEX_op_discard: | |
3411 | continue; | |
3412 | case INDEX_op_call: | |
3413 | nb_oargs = TCGOP_CALLO(op); | |
3414 | nb_iargs = TCGOP_CALLI(op); | |
3415 | break; | |
3416 | default: | |
3417 | def = &tcg_op_defs[op->opc]; | |
3418 | nb_oargs = def->nb_oargs; | |
3419 | nb_iargs = def->nb_iargs; | |
3420 | break; | |
3421 | } | |
3422 | ||
3423 | for (int i = 0; i < nb_oargs + nb_iargs; ++i) { | |
3424 | TCGTemp *ts = arg_temp(op->args[i]); | |
3425 | ||
3426 | if (ts->kind != TEMP_TB) { | |
3427 | continue; | |
3428 | } | |
3429 | if (ts->state_ptr == NULL) { | |
3430 | ts->state_ptr = ebb; | |
3431 | } else if (ts->state_ptr != ebb) { | |
3432 | ts->state_ptr = multiple_ebb; | |
3433 | } | |
3434 | } | |
3435 | } | |
3436 | ||
3437 | /* | |
3438 | * For TEMP_TB that turned out not to be used beyond one EBB, | |
3439 | * reduce the liveness to TEMP_EBB. | |
3440 | */ | |
3441 | for (int i = s->nb_globals; i < nb_temps; ++i) { | |
3442 | TCGTemp *ts = &s->temps[i]; | |
3443 | if (ts->kind == TEMP_TB && ts->state_ptr != multiple_ebb) { | |
3444 | ts->kind = TEMP_EBB; | |
3445 | } | |
3446 | } | |
3447 | } | |
3448 | ||
a1b3c48d | 3449 | /* Liveness analysis : update the opc_arg_life array to tell if a |
c896fe29 FB |
3450 | given input arguments is dead. Instructions updating dead |
3451 | temporaries are removed. */ | |
9bbee4c0 RH |
3452 | static void __attribute__((noinline)) |
3453 | liveness_pass_1(TCGContext *s) | |
c896fe29 | 3454 | { |
c70fbf0a | 3455 | int nb_globals = s->nb_globals; |
2616c808 | 3456 | int nb_temps = s->nb_temps; |
15fa08f8 | 3457 | TCGOp *op, *op_prev; |
25f49c5f RH |
3458 | TCGRegSet *prefs; |
3459 | int i; | |
3460 | ||
3461 | prefs = tcg_malloc(sizeof(TCGRegSet) * nb_temps); | |
3462 | for (i = 0; i < nb_temps; ++i) { | |
3463 | s->temps[i].state_ptr = prefs + i; | |
3464 | } | |
a1b3c48d | 3465 | |
ae36a246 | 3466 | /* ??? Should be redundant with the exit_tb that ends the TB. */ |
2616c808 | 3467 | la_func_end(s, nb_globals, nb_temps); |
c896fe29 | 3468 | |
eae3eb3e | 3469 | QTAILQ_FOREACH_REVERSE_SAFE(op, &s->ops, link, op_prev) { |
25f49c5f | 3470 | int nb_iargs, nb_oargs; |
c45cb8bb RH |
3471 | TCGOpcode opc_new, opc_new2; |
3472 | bool have_opc_new2; | |
a1b3c48d | 3473 | TCGLifeData arg_life = 0; |
25f49c5f | 3474 | TCGTemp *ts; |
c45cb8bb RH |
3475 | TCGOpcode opc = op->opc; |
3476 | const TCGOpDef *def = &tcg_op_defs[opc]; | |
3477 | ||
c45cb8bb | 3478 | switch (opc) { |
c896fe29 | 3479 | case INDEX_op_call: |
c6e113f5 | 3480 | { |
39004a71 RH |
3481 | const TCGHelperInfo *info = tcg_call_info(op); |
3482 | int call_flags = tcg_call_flags(op); | |
c896fe29 | 3483 | |
cd9090aa RH |
3484 | nb_oargs = TCGOP_CALLO(op); |
3485 | nb_iargs = TCGOP_CALLI(op); | |
c6e113f5 | 3486 | |
c45cb8bb | 3487 | /* pure functions can be removed if their result is unused */ |
78505279 | 3488 | if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) { |
cf066674 | 3489 | for (i = 0; i < nb_oargs; i++) { |
25f49c5f RH |
3490 | ts = arg_temp(op->args[i]); |
3491 | if (ts->state != TS_DEAD) { | |
c6e113f5 | 3492 | goto do_not_remove_call; |
9c43b68d | 3493 | } |
c6e113f5 | 3494 | } |
c45cb8bb | 3495 | goto do_remove; |
152c35aa RH |
3496 | } |
3497 | do_not_remove_call: | |
c896fe29 | 3498 | |
25f49c5f | 3499 | /* Output args are dead. */ |
152c35aa | 3500 | for (i = 0; i < nb_oargs; i++) { |
25f49c5f RH |
3501 | ts = arg_temp(op->args[i]); |
3502 | if (ts->state & TS_DEAD) { | |
152c35aa RH |
3503 | arg_life |= DEAD_ARG << i; |
3504 | } | |
25f49c5f | 3505 | if (ts->state & TS_MEM) { |
152c35aa | 3506 | arg_life |= SYNC_ARG << i; |
c6e113f5 | 3507 | } |
25f49c5f RH |
3508 | ts->state = TS_DEAD; |
3509 | la_reset_pref(ts); | |
152c35aa | 3510 | } |
78505279 | 3511 | |
31fd884b RH |
3512 | /* Not used -- it will be tcg_target_call_oarg_reg(). */ |
3513 | memset(op->output_pref, 0, sizeof(op->output_pref)); | |
3514 | ||
152c35aa RH |
3515 | if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS | |
3516 | TCG_CALL_NO_READ_GLOBALS))) { | |
f65a061c | 3517 | la_global_kill(s, nb_globals); |
152c35aa | 3518 | } else if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) { |
f65a061c | 3519 | la_global_sync(s, nb_globals); |
152c35aa | 3520 | } |
b9c18f56 | 3521 | |
25f49c5f | 3522 | /* Record arguments that die in this helper. */ |
152c35aa | 3523 | for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { |
25f49c5f | 3524 | ts = arg_temp(op->args[i]); |
39004a71 | 3525 | if (ts->state & TS_DEAD) { |
152c35aa | 3526 | arg_life |= DEAD_ARG << i; |
c6e113f5 | 3527 | } |
152c35aa | 3528 | } |
25f49c5f RH |
3529 | |
3530 | /* For all live registers, remove call-clobbered prefs. */ | |
3531 | la_cross_call(s, nb_temps); | |
3532 | ||
39004a71 RH |
3533 | /* |
3534 | * Input arguments are live for preceding opcodes. | |
3535 | * | |
3536 | * For those arguments that die, and will be allocated in | |
3537 | * registers, clear the register set for that arg, to be | |
3538 | * filled in below. For args that will be on the stack, | |
3539 | * reset to any available reg. Process arguments in reverse | |
3540 | * order so that if a temp is used more than once, the stack | |
3541 | * reset to max happens before the register reset to 0. | |
3542 | */ | |
3543 | for (i = nb_iargs - 1; i >= 0; i--) { | |
3544 | const TCGCallArgumentLoc *loc = &info->in[i]; | |
3545 | ts = arg_temp(op->args[nb_oargs + i]); | |
25f49c5f | 3546 | |
39004a71 RH |
3547 | if (ts->state & TS_DEAD) { |
3548 | switch (loc->kind) { | |
3549 | case TCG_CALL_ARG_NORMAL: | |
3550 | case TCG_CALL_ARG_EXTEND_U: | |
3551 | case TCG_CALL_ARG_EXTEND_S: | |
338b61e9 | 3552 | if (arg_slot_reg_p(loc->arg_slot)) { |
39004a71 RH |
3553 | *la_temp_pref(ts) = 0; |
3554 | break; | |
3555 | } | |
3556 | /* fall through */ | |
3557 | default: | |
3558 | *la_temp_pref(ts) = | |
3559 | tcg_target_available_regs[ts->type]; | |
3560 | break; | |
3561 | } | |
25f49c5f RH |
3562 | ts->state &= ~TS_DEAD; |
3563 | } | |
3564 | } | |
3565 | ||
39004a71 RH |
3566 | /* |
3567 | * For each input argument, add its input register to prefs. | |
3568 | * If a temp is used once, this produces a single set bit; | |
3569 | * if a temp is used multiple times, this produces a set. | |
3570 | */ | |
3571 | for (i = 0; i < nb_iargs; i++) { | |
3572 | const TCGCallArgumentLoc *loc = &info->in[i]; | |
3573 | ts = arg_temp(op->args[nb_oargs + i]); | |
3574 | ||
3575 | switch (loc->kind) { | |
3576 | case TCG_CALL_ARG_NORMAL: | |
3577 | case TCG_CALL_ARG_EXTEND_U: | |
3578 | case TCG_CALL_ARG_EXTEND_S: | |
338b61e9 | 3579 | if (arg_slot_reg_p(loc->arg_slot)) { |
39004a71 RH |
3580 | tcg_regset_set_reg(*la_temp_pref(ts), |
3581 | tcg_target_call_iarg_regs[loc->arg_slot]); | |
3582 | } | |
3583 | break; | |
3584 | default: | |
3585 | break; | |
c19f47bf | 3586 | } |
c896fe29 | 3587 | } |
c896fe29 | 3588 | } |
c896fe29 | 3589 | break; |
765b842a | 3590 | case INDEX_op_insn_start: |
c896fe29 | 3591 | break; |
5ff9d6a4 | 3592 | case INDEX_op_discard: |
5ff9d6a4 | 3593 | /* mark the temporary as dead */ |
25f49c5f RH |
3594 | ts = arg_temp(op->args[0]); |
3595 | ts->state = TS_DEAD; | |
3596 | la_reset_pref(ts); | |
5ff9d6a4 | 3597 | break; |
1305c451 RH |
3598 | |
3599 | case INDEX_op_add2_i32: | |
c45cb8bb | 3600 | opc_new = INDEX_op_add_i32; |
f1fae40c | 3601 | goto do_addsub2; |
1305c451 | 3602 | case INDEX_op_sub2_i32: |
c45cb8bb | 3603 | opc_new = INDEX_op_sub_i32; |
f1fae40c RH |
3604 | goto do_addsub2; |
3605 | case INDEX_op_add2_i64: | |
c45cb8bb | 3606 | opc_new = INDEX_op_add_i64; |
f1fae40c RH |
3607 | goto do_addsub2; |
3608 | case INDEX_op_sub2_i64: | |
c45cb8bb | 3609 | opc_new = INDEX_op_sub_i64; |
f1fae40c | 3610 | do_addsub2: |
1305c451 RH |
3611 | nb_iargs = 4; |
3612 | nb_oargs = 2; | |
3613 | /* Test if the high part of the operation is dead, but not | |
3614 | the low part. The result can be optimized to a simple | |
3615 | add or sub. This happens often for x86_64 guest when the | |
3616 | cpu mode is set to 32 bit. */ | |
b83eabea RH |
3617 | if (arg_temp(op->args[1])->state == TS_DEAD) { |
3618 | if (arg_temp(op->args[0])->state == TS_DEAD) { | |
1305c451 RH |
3619 | goto do_remove; |
3620 | } | |
c45cb8bb RH |
3621 | /* Replace the opcode and adjust the args in place, |
3622 | leaving 3 unused args at the end. */ | |
3623 | op->opc = opc = opc_new; | |
efee3746 RH |
3624 | op->args[1] = op->args[2]; |
3625 | op->args[2] = op->args[4]; | |
1305c451 RH |
3626 | /* Fall through and mark the single-word operation live. */ |
3627 | nb_iargs = 2; | |
3628 | nb_oargs = 1; | |
3629 | } | |
3630 | goto do_not_remove; | |
3631 | ||
1414968a | 3632 | case INDEX_op_mulu2_i32: |
c45cb8bb RH |
3633 | opc_new = INDEX_op_mul_i32; |
3634 | opc_new2 = INDEX_op_muluh_i32; | |
3635 | have_opc_new2 = TCG_TARGET_HAS_muluh_i32; | |
03271524 | 3636 | goto do_mul2; |
f1fae40c | 3637 | case INDEX_op_muls2_i32: |
c45cb8bb RH |
3638 | opc_new = INDEX_op_mul_i32; |
3639 | opc_new2 = INDEX_op_mulsh_i32; | |
3640 | have_opc_new2 = TCG_TARGET_HAS_mulsh_i32; | |
f1fae40c RH |
3641 | goto do_mul2; |
3642 | case INDEX_op_mulu2_i64: | |
c45cb8bb RH |
3643 | opc_new = INDEX_op_mul_i64; |
3644 | opc_new2 = INDEX_op_muluh_i64; | |
3645 | have_opc_new2 = TCG_TARGET_HAS_muluh_i64; | |
03271524 | 3646 | goto do_mul2; |
f1fae40c | 3647 | case INDEX_op_muls2_i64: |
c45cb8bb RH |
3648 | opc_new = INDEX_op_mul_i64; |
3649 | opc_new2 = INDEX_op_mulsh_i64; | |
3650 | have_opc_new2 = TCG_TARGET_HAS_mulsh_i64; | |
03271524 | 3651 | goto do_mul2; |
f1fae40c | 3652 | do_mul2: |
1414968a RH |
3653 | nb_iargs = 2; |
3654 | nb_oargs = 2; | |
b83eabea RH |
3655 | if (arg_temp(op->args[1])->state == TS_DEAD) { |
3656 | if (arg_temp(op->args[0])->state == TS_DEAD) { | |
03271524 | 3657 | /* Both parts of the operation are dead. */ |
1414968a RH |
3658 | goto do_remove; |
3659 | } | |
03271524 | 3660 | /* The high part of the operation is dead; generate the low. */ |
c45cb8bb | 3661 | op->opc = opc = opc_new; |
efee3746 RH |
3662 | op->args[1] = op->args[2]; |
3663 | op->args[2] = op->args[3]; | |
b83eabea | 3664 | } else if (arg_temp(op->args[0])->state == TS_DEAD && have_opc_new2) { |
c45cb8bb RH |
3665 | /* The low part of the operation is dead; generate the high. */ |
3666 | op->opc = opc = opc_new2; | |
efee3746 RH |
3667 | op->args[0] = op->args[1]; |
3668 | op->args[1] = op->args[2]; | |
3669 | op->args[2] = op->args[3]; | |
03271524 RH |
3670 | } else { |
3671 | goto do_not_remove; | |
1414968a | 3672 | } |
03271524 RH |
3673 | /* Mark the single-word operation live. */ |
3674 | nb_oargs = 1; | |
1414968a RH |
3675 | goto do_not_remove; |
3676 | ||
c896fe29 | 3677 | default: |
1305c451 | 3678 | /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */ |
49516bc0 AJ |
3679 | nb_iargs = def->nb_iargs; |
3680 | nb_oargs = def->nb_oargs; | |
c896fe29 | 3681 | |
49516bc0 AJ |
3682 | /* Test if the operation can be removed because all |
3683 | its outputs are dead. We assume that nb_oargs == 0 | |
3684 | implies side effects */ | |
3685 | if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) { | |
c45cb8bb | 3686 | for (i = 0; i < nb_oargs; i++) { |
b83eabea | 3687 | if (arg_temp(op->args[i])->state != TS_DEAD) { |
49516bc0 | 3688 | goto do_not_remove; |
9c43b68d | 3689 | } |
49516bc0 | 3690 | } |
152c35aa RH |
3691 | goto do_remove; |
3692 | } | |
3693 | goto do_not_remove; | |
49516bc0 | 3694 | |
152c35aa RH |
3695 | do_remove: |
3696 | tcg_op_remove(s, op); | |
3697 | break; | |
3698 | ||
3699 | do_not_remove: | |
152c35aa | 3700 | for (i = 0; i < nb_oargs; i++) { |
25f49c5f RH |
3701 | ts = arg_temp(op->args[i]); |
3702 | ||
3703 | /* Remember the preference of the uses that followed. */ | |
31fd884b RH |
3704 | if (i < ARRAY_SIZE(op->output_pref)) { |
3705 | op->output_pref[i] = *la_temp_pref(ts); | |
3706 | } | |
25f49c5f RH |
3707 | |
3708 | /* Output args are dead. */ | |
3709 | if (ts->state & TS_DEAD) { | |
152c35aa | 3710 | arg_life |= DEAD_ARG << i; |
49516bc0 | 3711 | } |
25f49c5f | 3712 | if (ts->state & TS_MEM) { |
152c35aa RH |
3713 | arg_life |= SYNC_ARG << i; |
3714 | } | |
25f49c5f RH |
3715 | ts->state = TS_DEAD; |
3716 | la_reset_pref(ts); | |
152c35aa | 3717 | } |
49516bc0 | 3718 | |
25f49c5f | 3719 | /* If end of basic block, update. */ |
ae36a246 RH |
3720 | if (def->flags & TCG_OPF_BB_EXIT) { |
3721 | la_func_end(s, nb_globals, nb_temps); | |
b4cb76e6 RH |
3722 | } else if (def->flags & TCG_OPF_COND_BRANCH) { |
3723 | la_bb_sync(s, nb_globals, nb_temps); | |
ae36a246 | 3724 | } else if (def->flags & TCG_OPF_BB_END) { |
2616c808 | 3725 | la_bb_end(s, nb_globals, nb_temps); |
152c35aa | 3726 | } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { |
f65a061c | 3727 | la_global_sync(s, nb_globals); |
25f49c5f RH |
3728 | if (def->flags & TCG_OPF_CALL_CLOBBER) { |
3729 | la_cross_call(s, nb_temps); | |
3730 | } | |
152c35aa RH |
3731 | } |
3732 | ||
25f49c5f | 3733 | /* Record arguments that die in this opcode. */ |
152c35aa | 3734 | for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { |
25f49c5f RH |
3735 | ts = arg_temp(op->args[i]); |
3736 | if (ts->state & TS_DEAD) { | |
152c35aa | 3737 | arg_life |= DEAD_ARG << i; |
c896fe29 | 3738 | } |
c896fe29 | 3739 | } |
25f49c5f RH |
3740 | |
3741 | /* Input arguments are live for preceding opcodes. */ | |
152c35aa | 3742 | for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { |
25f49c5f RH |
3743 | ts = arg_temp(op->args[i]); |
3744 | if (ts->state & TS_DEAD) { | |
3745 | /* For operands that were dead, initially allow | |
3746 | all regs for the type. */ | |
3747 | *la_temp_pref(ts) = tcg_target_available_regs[ts->type]; | |
3748 | ts->state &= ~TS_DEAD; | |
3749 | } | |
3750 | } | |
3751 | ||
3752 | /* Incorporate constraints for this operand. */ | |
3753 | switch (opc) { | |
3754 | case INDEX_op_mov_i32: | |
3755 | case INDEX_op_mov_i64: | |
3756 | /* Note that these are TCG_OPF_NOT_PRESENT and do not | |
3757 | have proper constraints. That said, special case | |
3758 | moves to propagate preferences backward. */ | |
3759 | if (IS_DEAD_ARG(1)) { | |
3760 | *la_temp_pref(arg_temp(op->args[0])) | |
3761 | = *la_temp_pref(arg_temp(op->args[1])); | |
3762 | } | |
3763 | break; | |
3764 | ||
3765 | default: | |
3766 | for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { | |
3767 | const TCGArgConstraint *ct = &def->args_ct[i]; | |
3768 | TCGRegSet set, *pset; | |
3769 | ||
3770 | ts = arg_temp(op->args[i]); | |
3771 | pset = la_temp_pref(ts); | |
3772 | set = *pset; | |
3773 | ||
9be0d080 | 3774 | set &= ct->regs; |
bc2b17e6 | 3775 | if (ct->ialias) { |
31fd884b | 3776 | set &= output_pref(op, ct->alias_index); |
25f49c5f RH |
3777 | } |
3778 | /* If the combination is not possible, restart. */ | |
3779 | if (set == 0) { | |
9be0d080 | 3780 | set = ct->regs; |
25f49c5f RH |
3781 | } |
3782 | *pset = set; | |
3783 | } | |
3784 | break; | |
152c35aa | 3785 | } |
c896fe29 FB |
3786 | break; |
3787 | } | |
bee158cb | 3788 | op->life = arg_life; |
1ff0a2c5 | 3789 | } |
c896fe29 | 3790 | } |
c896fe29 | 3791 | |
5a18407f | 3792 | /* Liveness analysis: Convert indirect regs to direct temporaries. */ |
9bbee4c0 RH |
3793 | static bool __attribute__((noinline)) |
3794 | liveness_pass_2(TCGContext *s) | |
5a18407f RH |
3795 | { |
3796 | int nb_globals = s->nb_globals; | |
15fa08f8 | 3797 | int nb_temps, i; |
5a18407f | 3798 | bool changes = false; |
15fa08f8 | 3799 | TCGOp *op, *op_next; |
5a18407f | 3800 | |
5a18407f RH |
3801 | /* Create a temporary for each indirect global. */ |
3802 | for (i = 0; i < nb_globals; ++i) { | |
3803 | TCGTemp *its = &s->temps[i]; | |
3804 | if (its->indirect_reg) { | |
3805 | TCGTemp *dts = tcg_temp_alloc(s); | |
3806 | dts->type = its->type; | |
3807 | dts->base_type = its->base_type; | |
e1e64652 | 3808 | dts->temp_subindex = its->temp_subindex; |
c7482438 | 3809 | dts->kind = TEMP_EBB; |
b83eabea RH |
3810 | its->state_ptr = dts; |
3811 | } else { | |
3812 | its->state_ptr = NULL; | |
5a18407f | 3813 | } |
b83eabea RH |
3814 | /* All globals begin dead. */ |
3815 | its->state = TS_DEAD; | |
3816 | } | |
3817 | for (nb_temps = s->nb_temps; i < nb_temps; ++i) { | |
3818 | TCGTemp *its = &s->temps[i]; | |
3819 | its->state_ptr = NULL; | |
3820 | its->state = TS_DEAD; | |
5a18407f | 3821 | } |
5a18407f | 3822 | |
15fa08f8 | 3823 | QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { |
5a18407f RH |
3824 | TCGOpcode opc = op->opc; |
3825 | const TCGOpDef *def = &tcg_op_defs[opc]; | |
3826 | TCGLifeData arg_life = op->life; | |
3827 | int nb_iargs, nb_oargs, call_flags; | |
b83eabea | 3828 | TCGTemp *arg_ts, *dir_ts; |
5a18407f | 3829 | |
5a18407f | 3830 | if (opc == INDEX_op_call) { |
cd9090aa RH |
3831 | nb_oargs = TCGOP_CALLO(op); |
3832 | nb_iargs = TCGOP_CALLI(op); | |
90163900 | 3833 | call_flags = tcg_call_flags(op); |
5a18407f RH |
3834 | } else { |
3835 | nb_iargs = def->nb_iargs; | |
3836 | nb_oargs = def->nb_oargs; | |
3837 | ||
3838 | /* Set flags similar to how calls require. */ | |
b4cb76e6 RH |
3839 | if (def->flags & TCG_OPF_COND_BRANCH) { |
3840 | /* Like reading globals: sync_globals */ | |
3841 | call_flags = TCG_CALL_NO_WRITE_GLOBALS; | |
3842 | } else if (def->flags & TCG_OPF_BB_END) { | |
5a18407f RH |
3843 | /* Like writing globals: save_globals */ |
3844 | call_flags = 0; | |
3845 | } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { | |
3846 | /* Like reading globals: sync_globals */ | |
3847 | call_flags = TCG_CALL_NO_WRITE_GLOBALS; | |
3848 | } else { | |
3849 | /* No effect on globals. */ | |
3850 | call_flags = (TCG_CALL_NO_READ_GLOBALS | | |
3851 | TCG_CALL_NO_WRITE_GLOBALS); | |
3852 | } | |
3853 | } | |
3854 | ||
3855 | /* Make sure that input arguments are available. */ | |
3856 | for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { | |
b83eabea | 3857 | arg_ts = arg_temp(op->args[i]); |
39004a71 RH |
3858 | dir_ts = arg_ts->state_ptr; |
3859 | if (dir_ts && arg_ts->state == TS_DEAD) { | |
3860 | TCGOpcode lopc = (arg_ts->type == TCG_TYPE_I32 | |
3861 | ? INDEX_op_ld_i32 | |
3862 | : INDEX_op_ld_i64); | |
3863 | TCGOp *lop = tcg_op_insert_before(s, op, lopc, 3); | |
3864 | ||
3865 | lop->args[0] = temp_arg(dir_ts); | |
3866 | lop->args[1] = temp_arg(arg_ts->mem_base); | |
3867 | lop->args[2] = arg_ts->mem_offset; | |
3868 | ||
3869 | /* Loaded, but synced with memory. */ | |
3870 | arg_ts->state = TS_MEM; | |
5a18407f RH |
3871 | } |
3872 | } | |
3873 | ||
3874 | /* Perform input replacement, and mark inputs that became dead. | |
3875 | No action is required except keeping temp_state up to date | |
3876 | so that we reload when needed. */ | |
3877 | for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { | |
b83eabea | 3878 | arg_ts = arg_temp(op->args[i]); |
39004a71 RH |
3879 | dir_ts = arg_ts->state_ptr; |
3880 | if (dir_ts) { | |
3881 | op->args[i] = temp_arg(dir_ts); | |
3882 | changes = true; | |
3883 | if (IS_DEAD_ARG(i)) { | |
3884 | arg_ts->state = TS_DEAD; | |
5a18407f RH |
3885 | } |
3886 | } | |
3887 | } | |
3888 | ||
3889 | /* Liveness analysis should ensure that the following are | |
3890 | all correct, for call sites and basic block end points. */ | |
3891 | if (call_flags & TCG_CALL_NO_READ_GLOBALS) { | |
3892 | /* Nothing to do */ | |
3893 | } else if (call_flags & TCG_CALL_NO_WRITE_GLOBALS) { | |
3894 | for (i = 0; i < nb_globals; ++i) { | |
3895 | /* Liveness should see that globals are synced back, | |
3896 | that is, either TS_DEAD or TS_MEM. */ | |
b83eabea RH |
3897 | arg_ts = &s->temps[i]; |
3898 | tcg_debug_assert(arg_ts->state_ptr == 0 | |
3899 | || arg_ts->state != 0); | |
5a18407f RH |
3900 | } |
3901 | } else { | |
3902 | for (i = 0; i < nb_globals; ++i) { | |
3903 | /* Liveness should see that globals are saved back, | |
3904 | that is, TS_DEAD, waiting to be reloaded. */ | |
b83eabea RH |
3905 | arg_ts = &s->temps[i]; |
3906 | tcg_debug_assert(arg_ts->state_ptr == 0 | |
3907 | || arg_ts->state == TS_DEAD); | |
5a18407f RH |
3908 | } |
3909 | } | |
3910 | ||
3911 | /* Outputs become available. */ | |
61f15c48 RH |
3912 | if (opc == INDEX_op_mov_i32 || opc == INDEX_op_mov_i64) { |
3913 | arg_ts = arg_temp(op->args[0]); | |
b83eabea | 3914 | dir_ts = arg_ts->state_ptr; |
61f15c48 RH |
3915 | if (dir_ts) { |
3916 | op->args[0] = temp_arg(dir_ts); | |
3917 | changes = true; | |
3918 | ||
3919 | /* The output is now live and modified. */ | |
3920 | arg_ts->state = 0; | |
3921 | ||
3922 | if (NEED_SYNC_ARG(0)) { | |
3923 | TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 | |
3924 | ? INDEX_op_st_i32 | |
3925 | : INDEX_op_st_i64); | |
d4478943 | 3926 | TCGOp *sop = tcg_op_insert_after(s, op, sopc, 3); |
61f15c48 RH |
3927 | TCGTemp *out_ts = dir_ts; |
3928 | ||
3929 | if (IS_DEAD_ARG(0)) { | |
3930 | out_ts = arg_temp(op->args[1]); | |
3931 | arg_ts->state = TS_DEAD; | |
3932 | tcg_op_remove(s, op); | |
3933 | } else { | |
3934 | arg_ts->state = TS_MEM; | |
3935 | } | |
3936 | ||
3937 | sop->args[0] = temp_arg(out_ts); | |
3938 | sop->args[1] = temp_arg(arg_ts->mem_base); | |
3939 | sop->args[2] = arg_ts->mem_offset; | |
3940 | } else { | |
3941 | tcg_debug_assert(!IS_DEAD_ARG(0)); | |
3942 | } | |
5a18407f | 3943 | } |
61f15c48 RH |
3944 | } else { |
3945 | for (i = 0; i < nb_oargs; i++) { | |
3946 | arg_ts = arg_temp(op->args[i]); | |
3947 | dir_ts = arg_ts->state_ptr; | |
3948 | if (!dir_ts) { | |
3949 | continue; | |
3950 | } | |
3951 | op->args[i] = temp_arg(dir_ts); | |
3952 | changes = true; | |
5a18407f | 3953 | |
61f15c48 RH |
3954 | /* The output is now live and modified. */ |
3955 | arg_ts->state = 0; | |
5a18407f | 3956 | |
61f15c48 RH |
3957 | /* Sync outputs upon their last write. */ |
3958 | if (NEED_SYNC_ARG(i)) { | |
3959 | TCGOpcode sopc = (arg_ts->type == TCG_TYPE_I32 | |
3960 | ? INDEX_op_st_i32 | |
3961 | : INDEX_op_st_i64); | |
d4478943 | 3962 | TCGOp *sop = tcg_op_insert_after(s, op, sopc, 3); |
5a18407f | 3963 | |
61f15c48 RH |
3964 | sop->args[0] = temp_arg(dir_ts); |
3965 | sop->args[1] = temp_arg(arg_ts->mem_base); | |
3966 | sop->args[2] = arg_ts->mem_offset; | |
5a18407f | 3967 | |
61f15c48 RH |
3968 | arg_ts->state = TS_MEM; |
3969 | } | |
3970 | /* Drop outputs that are dead. */ | |
3971 | if (IS_DEAD_ARG(i)) { | |
3972 | arg_ts->state = TS_DEAD; | |
3973 | } | |
5a18407f RH |
3974 | } |
3975 | } | |
3976 | } | |
3977 | ||
3978 | return changes; | |
3979 | } | |
3980 | ||
2272e4a7 | 3981 | static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) |
c896fe29 | 3982 | { |
31c96417 | 3983 | intptr_t off; |
273eb50c | 3984 | int size, align; |
c1c09194 | 3985 | |
273eb50c RH |
3986 | /* When allocating an object, look at the full type. */ |
3987 | size = tcg_type_size(ts->base_type); | |
3988 | switch (ts->base_type) { | |
c1c09194 | 3989 | case TCG_TYPE_I32: |
31c96417 | 3990 | align = 4; |
c1c09194 RH |
3991 | break; |
3992 | case TCG_TYPE_I64: | |
3993 | case TCG_TYPE_V64: | |
31c96417 | 3994 | align = 8; |
c1c09194 | 3995 | break; |
43eef72f | 3996 | case TCG_TYPE_I128: |
c1c09194 | 3997 | case TCG_TYPE_V128: |
c1c09194 | 3998 | case TCG_TYPE_V256: |
43eef72f RH |
3999 | /* |
4000 | * Note that we do not require aligned storage for V256, | |
4001 | * and that we provide alignment for I128 to match V128, | |
4002 | * even if that's above what the host ABI requires. | |
4003 | */ | |
31c96417 | 4004 | align = 16; |
c1c09194 RH |
4005 | break; |
4006 | default: | |
4007 | g_assert_not_reached(); | |
b591dc59 | 4008 | } |
c1c09194 | 4009 | |
b9537d59 RH |
4010 | /* |
4011 | * Assume the stack is sufficiently aligned. | |
4012 | * This affects e.g. ARM NEON, where we have 8 byte stack alignment | |
4013 | * and do not require 16 byte vector alignment. This seems slightly | |
4014 | * easier than fully parameterizing the above switch statement. | |
4015 | */ | |
4016 | align = MIN(TCG_TARGET_STACK_ALIGN, align); | |
c1c09194 | 4017 | off = ROUND_UP(s->current_frame_offset, align); |
732d5897 RH |
4018 | |
4019 | /* If we've exhausted the stack frame, restart with a smaller TB. */ | |
4020 | if (off + size > s->frame_end) { | |
4021 | tcg_raise_tb_overflow(s); | |
4022 | } | |
c1c09194 | 4023 | s->current_frame_offset = off + size; |
9defd1bd | 4024 | #if defined(__sparc__) |
273eb50c | 4025 | off += TCG_TARGET_STACK_BIAS; |
9defd1bd | 4026 | #endif |
273eb50c RH |
4027 | |
4028 | /* If the object was subdivided, assign memory to all the parts. */ | |
4029 | if (ts->base_type != ts->type) { | |
4030 | int part_size = tcg_type_size(ts->type); | |
4031 | int part_count = size / part_size; | |
4032 | ||
4033 | /* | |
4034 | * Each part is allocated sequentially in tcg_temp_new_internal. | |
4035 | * Jump back to the first part by subtracting the current index. | |
4036 | */ | |
4037 | ts -= ts->temp_subindex; | |
4038 | for (int i = 0; i < part_count; ++i) { | |
4039 | ts[i].mem_offset = off + i * part_size; | |
4040 | ts[i].mem_base = s->frame_temp; | |
4041 | ts[i].mem_allocated = 1; | |
4042 | } | |
4043 | } else { | |
4044 | ts->mem_offset = off; | |
4045 | ts->mem_base = s->frame_temp; | |
4046 | ts->mem_allocated = 1; | |
4047 | } | |
c896fe29 FB |
4048 | } |
4049 | ||
098859f1 RH |
4050 | /* Assign @reg to @ts, and update reg_to_temp[]. */ |
4051 | static void set_temp_val_reg(TCGContext *s, TCGTemp *ts, TCGReg reg) | |
4052 | { | |
4053 | if (ts->val_type == TEMP_VAL_REG) { | |
4054 | TCGReg old = ts->reg; | |
4055 | tcg_debug_assert(s->reg_to_temp[old] == ts); | |
4056 | if (old == reg) { | |
4057 | return; | |
4058 | } | |
4059 | s->reg_to_temp[old] = NULL; | |
4060 | } | |
4061 | tcg_debug_assert(s->reg_to_temp[reg] == NULL); | |
4062 | s->reg_to_temp[reg] = ts; | |
4063 | ts->val_type = TEMP_VAL_REG; | |
4064 | ts->reg = reg; | |
4065 | } | |
4066 | ||
4067 | /* Assign a non-register value type to @ts, and update reg_to_temp[]. */ | |
4068 | static void set_temp_val_nonreg(TCGContext *s, TCGTemp *ts, TCGTempVal type) | |
4069 | { | |
4070 | tcg_debug_assert(type != TEMP_VAL_REG); | |
4071 | if (ts->val_type == TEMP_VAL_REG) { | |
4072 | TCGReg reg = ts->reg; | |
4073 | tcg_debug_assert(s->reg_to_temp[reg] == ts); | |
4074 | s->reg_to_temp[reg] = NULL; | |
4075 | } | |
4076 | ts->val_type = type; | |
4077 | } | |
4078 | ||
b722452a | 4079 | static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); |
b3915dbb | 4080 | |
59d7c14e RH |
4081 | /* Mark a temporary as free or dead. If 'free_or_dead' is negative, |
4082 | mark it free; otherwise mark it dead. */ | |
4083 | static void temp_free_or_dead(TCGContext *s, TCGTemp *ts, int free_or_dead) | |
7f6ceedf | 4084 | { |
c0522136 RH |
4085 | TCGTempVal new_type; |
4086 | ||
4087 | switch (ts->kind) { | |
4088 | case TEMP_FIXED: | |
59d7c14e | 4089 | return; |
c0522136 | 4090 | case TEMP_GLOBAL: |
f57c6915 | 4091 | case TEMP_TB: |
c0522136 RH |
4092 | new_type = TEMP_VAL_MEM; |
4093 | break; | |
c7482438 | 4094 | case TEMP_EBB: |
c0522136 RH |
4095 | new_type = free_or_dead < 0 ? TEMP_VAL_MEM : TEMP_VAL_DEAD; |
4096 | break; | |
4097 | case TEMP_CONST: | |
4098 | new_type = TEMP_VAL_CONST; | |
4099 | break; | |
4100 | default: | |
4101 | g_assert_not_reached(); | |
59d7c14e | 4102 | } |
098859f1 | 4103 | set_temp_val_nonreg(s, ts, new_type); |
59d7c14e | 4104 | } |
7f6ceedf | 4105 | |
59d7c14e RH |
4106 | /* Mark a temporary as dead. */ |
4107 | static inline void temp_dead(TCGContext *s, TCGTemp *ts) | |
4108 | { | |
4109 | temp_free_or_dead(s, ts, 1); | |
4110 | } | |
4111 | ||
4112 | /* Sync a temporary to memory. 'allocated_regs' is used in case a temporary | |
4113 | registers needs to be allocated to store a constant. If 'free_or_dead' | |
4114 | is non-zero, subsequently release the temporary; if it is positive, the | |
4115 | temp is dead; if it is negative, the temp is free. */ | |
98b4e186 RH |
4116 | static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, |
4117 | TCGRegSet preferred_regs, int free_or_dead) | |
59d7c14e | 4118 | { |
c0522136 | 4119 | if (!temp_readonly(ts) && !ts->mem_coherent) { |
7f6ceedf | 4120 | if (!ts->mem_allocated) { |
2272e4a7 | 4121 | temp_allocate_frame(s, ts); |
59d7c14e | 4122 | } |
59d7c14e RH |
4123 | switch (ts->val_type) { |
4124 | case TEMP_VAL_CONST: | |
4125 | /* If we're going to free the temp immediately, then we won't | |
4126 | require it later in a register, so attempt to store the | |
4127 | constant to memory directly. */ | |
4128 | if (free_or_dead | |
4129 | && tcg_out_sti(s, ts->type, ts->val, | |
4130 | ts->mem_base->reg, ts->mem_offset)) { | |
4131 | break; | |
4132 | } | |
4133 | temp_load(s, ts, tcg_target_available_regs[ts->type], | |
98b4e186 | 4134 | allocated_regs, preferred_regs); |
59d7c14e RH |
4135 | /* fallthrough */ |
4136 | ||
4137 | case TEMP_VAL_REG: | |
4138 | tcg_out_st(s, ts->type, ts->reg, | |
4139 | ts->mem_base->reg, ts->mem_offset); | |
4140 | break; | |
4141 | ||
4142 | case TEMP_VAL_MEM: | |
4143 | break; | |
4144 | ||
4145 | case TEMP_VAL_DEAD: | |
4146 | default: | |
732e89f4 | 4147 | g_assert_not_reached(); |
59d7c14e RH |
4148 | } |
4149 | ts->mem_coherent = 1; | |
4150 | } | |
4151 | if (free_or_dead) { | |
4152 | temp_free_or_dead(s, ts, free_or_dead); | |
7f6ceedf | 4153 | } |
7f6ceedf AJ |
4154 | } |
4155 | ||
c896fe29 | 4156 | /* free register 'reg' by spilling the corresponding temporary if necessary */ |
b3915dbb | 4157 | static void tcg_reg_free(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs) |
c896fe29 | 4158 | { |
f8b2f202 | 4159 | TCGTemp *ts = s->reg_to_temp[reg]; |
f8b2f202 | 4160 | if (ts != NULL) { |
98b4e186 | 4161 | temp_sync(s, ts, allocated_regs, 0, -1); |
c896fe29 FB |
4162 | } |
4163 | } | |
4164 | ||
b016486e RH |
4165 | /** |
4166 | * tcg_reg_alloc: | |
4167 | * @required_regs: Set of registers in which we must allocate. | |
4168 | * @allocated_regs: Set of registers which must be avoided. | |
4169 | * @preferred_regs: Set of registers we should prefer. | |
4170 | * @rev: True if we search the registers in "indirect" order. | |
4171 | * | |
4172 | * The allocated register must be in @required_regs & ~@allocated_regs, | |
4173 | * but if we can put it in @preferred_regs we may save a move later. | |
4174 | */ | |
4175 | static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet required_regs, | |
4176 | TCGRegSet allocated_regs, | |
4177 | TCGRegSet preferred_regs, bool rev) | |
c896fe29 | 4178 | { |
b016486e RH |
4179 | int i, j, f, n = ARRAY_SIZE(tcg_target_reg_alloc_order); |
4180 | TCGRegSet reg_ct[2]; | |
91478cef | 4181 | const int *order; |
c896fe29 | 4182 | |
b016486e RH |
4183 | reg_ct[1] = required_regs & ~allocated_regs; |
4184 | tcg_debug_assert(reg_ct[1] != 0); | |
4185 | reg_ct[0] = reg_ct[1] & preferred_regs; | |
4186 | ||
4187 | /* Skip the preferred_regs option if it cannot be satisfied, | |
4188 | or if the preference made no difference. */ | |
4189 | f = reg_ct[0] == 0 || reg_ct[0] == reg_ct[1]; | |
4190 | ||
91478cef | 4191 | order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; |
c896fe29 | 4192 | |
b016486e RH |
4193 | /* Try free registers, preferences first. */ |
4194 | for (j = f; j < 2; j++) { | |
4195 | TCGRegSet set = reg_ct[j]; | |
4196 | ||
4197 | if (tcg_regset_single(set)) { | |
4198 | /* One register in the set. */ | |
4199 | TCGReg reg = tcg_regset_first(set); | |
4200 | if (s->reg_to_temp[reg] == NULL) { | |
4201 | return reg; | |
4202 | } | |
4203 | } else { | |
4204 | for (i = 0; i < n; i++) { | |
4205 | TCGReg reg = order[i]; | |
4206 | if (s->reg_to_temp[reg] == NULL && | |
4207 | tcg_regset_test_reg(set, reg)) { | |
4208 | return reg; | |
4209 | } | |
4210 | } | |
4211 | } | |
c896fe29 FB |
4212 | } |
4213 | ||
b016486e RH |
4214 | /* We must spill something. */ |
4215 | for (j = f; j < 2; j++) { | |
4216 | TCGRegSet set = reg_ct[j]; | |
4217 | ||
4218 | if (tcg_regset_single(set)) { | |
4219 | /* One register in the set. */ | |
4220 | TCGReg reg = tcg_regset_first(set); | |
b3915dbb | 4221 | tcg_reg_free(s, reg, allocated_regs); |
c896fe29 | 4222 | return reg; |
b016486e RH |
4223 | } else { |
4224 | for (i = 0; i < n; i++) { | |
4225 | TCGReg reg = order[i]; | |
4226 | if (tcg_regset_test_reg(set, reg)) { | |
4227 | tcg_reg_free(s, reg, allocated_regs); | |
4228 | return reg; | |
4229 | } | |
4230 | } | |
c896fe29 FB |
4231 | } |
4232 | } | |
4233 | ||
732e89f4 | 4234 | g_assert_not_reached(); |
c896fe29 FB |
4235 | } |
4236 | ||
29f5e925 RH |
4237 | static TCGReg tcg_reg_alloc_pair(TCGContext *s, TCGRegSet required_regs, |
4238 | TCGRegSet allocated_regs, | |
4239 | TCGRegSet preferred_regs, bool rev) | |
4240 | { | |
4241 | int i, j, k, fmin, n = ARRAY_SIZE(tcg_target_reg_alloc_order); | |
4242 | TCGRegSet reg_ct[2]; | |
4243 | const int *order; | |
4244 | ||
4245 | /* Ensure that if I is not in allocated_regs, I+1 is not either. */ | |
4246 | reg_ct[1] = required_regs & ~(allocated_regs | (allocated_regs >> 1)); | |
4247 | tcg_debug_assert(reg_ct[1] != 0); | |
4248 | reg_ct[0] = reg_ct[1] & preferred_regs; | |
4249 | ||
4250 | order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; | |
4251 | ||
4252 | /* | |
4253 | * Skip the preferred_regs option if it cannot be satisfied, | |
4254 | * or if the preference made no difference. | |
4255 | */ | |
4256 | k = reg_ct[0] == 0 || reg_ct[0] == reg_ct[1]; | |
4257 | ||
4258 | /* | |
4259 | * Minimize the number of flushes by looking for 2 free registers first, | |
4260 | * then a single flush, then two flushes. | |
4261 | */ | |
4262 | for (fmin = 2; fmin >= 0; fmin--) { | |
4263 | for (j = k; j < 2; j++) { | |
4264 | TCGRegSet set = reg_ct[j]; | |
4265 | ||
4266 | for (i = 0; i < n; i++) { | |
4267 | TCGReg reg = order[i]; | |
4268 | ||
4269 | if (tcg_regset_test_reg(set, reg)) { | |
4270 | int f = !s->reg_to_temp[reg] + !s->reg_to_temp[reg + 1]; | |
4271 | if (f >= fmin) { | |
4272 | tcg_reg_free(s, reg, allocated_regs); | |
4273 | tcg_reg_free(s, reg + 1, allocated_regs); | |
4274 | return reg; | |
4275 | } | |
4276 | } | |
4277 | } | |
4278 | } | |
4279 | } | |
732e89f4 | 4280 | g_assert_not_reached(); |
29f5e925 RH |
4281 | } |
4282 | ||
40ae5c62 RH |
4283 | /* Make sure the temporary is in a register. If needed, allocate the register |
4284 | from DESIRED while avoiding ALLOCATED. */ | |
4285 | static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, | |
b722452a | 4286 | TCGRegSet allocated_regs, TCGRegSet preferred_regs) |
40ae5c62 RH |
4287 | { |
4288 | TCGReg reg; | |
4289 | ||
4290 | switch (ts->val_type) { | |
4291 | case TEMP_VAL_REG: | |
4292 | return; | |
4293 | case TEMP_VAL_CONST: | |
b016486e | 4294 | reg = tcg_reg_alloc(s, desired_regs, allocated_regs, |
b722452a | 4295 | preferred_regs, ts->indirect_base); |
0a6a8bc8 RH |
4296 | if (ts->type <= TCG_TYPE_I64) { |
4297 | tcg_out_movi(s, ts->type, reg, ts->val); | |
4298 | } else { | |
4e186175 RH |
4299 | uint64_t val = ts->val; |
4300 | MemOp vece = MO_64; | |
4301 | ||
4302 | /* | |
4303 | * Find the minimal vector element that matches the constant. | |
4304 | * The targets will, in general, have to do this search anyway, | |
4305 | * do this generically. | |
4306 | */ | |
4e186175 RH |
4307 | if (val == dup_const(MO_8, val)) { |
4308 | vece = MO_8; | |
4309 | } else if (val == dup_const(MO_16, val)) { | |
4310 | vece = MO_16; | |
0b4286dd | 4311 | } else if (val == dup_const(MO_32, val)) { |
4e186175 RH |
4312 | vece = MO_32; |
4313 | } | |
4314 | ||
4315 | tcg_out_dupi_vec(s, ts->type, vece, reg, ts->val); | |
0a6a8bc8 | 4316 | } |
40ae5c62 RH |
4317 | ts->mem_coherent = 0; |
4318 | break; | |
4319 | case TEMP_VAL_MEM: | |
b016486e | 4320 | reg = tcg_reg_alloc(s, desired_regs, allocated_regs, |
b722452a | 4321 | preferred_regs, ts->indirect_base); |
40ae5c62 RH |
4322 | tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); |
4323 | ts->mem_coherent = 1; | |
4324 | break; | |
4325 | case TEMP_VAL_DEAD: | |
4326 | default: | |
732e89f4 | 4327 | g_assert_not_reached(); |
40ae5c62 | 4328 | } |
098859f1 | 4329 | set_temp_val_reg(s, ts, reg); |
40ae5c62 RH |
4330 | } |
4331 | ||
59d7c14e RH |
4332 | /* Save a temporary to memory. 'allocated_regs' is used in case a |
4333 | temporary registers needs to be allocated to store a constant. */ | |
4334 | static void temp_save(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs) | |
1ad80729 | 4335 | { |
5a18407f RH |
4336 | /* The liveness analysis already ensures that globals are back |
4337 | in memory. Keep an tcg_debug_assert for safety. */ | |
e01fa97d | 4338 | tcg_debug_assert(ts->val_type == TEMP_VAL_MEM || temp_readonly(ts)); |
1ad80729 AJ |
4339 | } |
4340 | ||
9814dd27 | 4341 | /* save globals to their canonical location and assume they can be |
e8996ee0 FB |
4342 | modified be the following code. 'allocated_regs' is used in case a |
4343 | temporary registers needs to be allocated to store a constant. */ | |
4344 | static void save_globals(TCGContext *s, TCGRegSet allocated_regs) | |
c896fe29 | 4345 | { |
ac3b8891 | 4346 | int i, n; |
c896fe29 | 4347 | |
ac3b8891 | 4348 | for (i = 0, n = s->nb_globals; i < n; i++) { |
b13eb728 | 4349 | temp_save(s, &s->temps[i], allocated_regs); |
c896fe29 | 4350 | } |
e5097dc8 FB |
4351 | } |
4352 | ||
3d5c5f87 AJ |
4353 | /* sync globals to their canonical location and assume they can be |
4354 | read by the following code. 'allocated_regs' is used in case a | |
4355 | temporary registers needs to be allocated to store a constant. */ | |
4356 | static void sync_globals(TCGContext *s, TCGRegSet allocated_regs) | |
4357 | { | |
ac3b8891 | 4358 | int i, n; |
3d5c5f87 | 4359 | |
ac3b8891 | 4360 | for (i = 0, n = s->nb_globals; i < n; i++) { |
12b9b11a | 4361 | TCGTemp *ts = &s->temps[i]; |
5a18407f | 4362 | tcg_debug_assert(ts->val_type != TEMP_VAL_REG |
ee17db83 | 4363 | || ts->kind == TEMP_FIXED |
5a18407f | 4364 | || ts->mem_coherent); |
3d5c5f87 AJ |
4365 | } |
4366 | } | |
4367 | ||
e5097dc8 | 4368 | /* at the end of a basic block, we assume all temporaries are dead and |
e8996ee0 FB |
4369 | all globals are stored at their canonical location. */ |
4370 | static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) | |
e5097dc8 | 4371 | { |
e5097dc8 FB |
4372 | int i; |
4373 | ||
b13eb728 RH |
4374 | for (i = s->nb_globals; i < s->nb_temps; i++) { |
4375 | TCGTemp *ts = &s->temps[i]; | |
c0522136 RH |
4376 | |
4377 | switch (ts->kind) { | |
f57c6915 | 4378 | case TEMP_TB: |
b13eb728 | 4379 | temp_save(s, ts, allocated_regs); |
c0522136 | 4380 | break; |
c7482438 | 4381 | case TEMP_EBB: |
5a18407f RH |
4382 | /* The liveness analysis already ensures that temps are dead. |
4383 | Keep an tcg_debug_assert for safety. */ | |
4384 | tcg_debug_assert(ts->val_type == TEMP_VAL_DEAD); | |
c0522136 RH |
4385 | break; |
4386 | case TEMP_CONST: | |
4387 | /* Similarly, we should have freed any allocated register. */ | |
4388 | tcg_debug_assert(ts->val_type == TEMP_VAL_CONST); | |
4389 | break; | |
4390 | default: | |
4391 | g_assert_not_reached(); | |
c896fe29 FB |
4392 | } |
4393 | } | |
e8996ee0 FB |
4394 | |
4395 | save_globals(s, allocated_regs); | |
c896fe29 FB |
4396 | } |
4397 | ||
b4cb76e6 | 4398 | /* |
c7482438 RH |
4399 | * At a conditional branch, we assume all temporaries are dead unless |
4400 | * explicitly live-across-conditional-branch; all globals and local | |
4401 | * temps are synced to their location. | |
b4cb76e6 RH |
4402 | */ |
4403 | static void tcg_reg_alloc_cbranch(TCGContext *s, TCGRegSet allocated_regs) | |
4404 | { | |
4405 | sync_globals(s, allocated_regs); | |
4406 | ||
4407 | for (int i = s->nb_globals; i < s->nb_temps; i++) { | |
4408 | TCGTemp *ts = &s->temps[i]; | |
4409 | /* | |
4410 | * The liveness analysis already ensures that temps are dead. | |
4411 | * Keep tcg_debug_asserts for safety. | |
4412 | */ | |
c0522136 | 4413 | switch (ts->kind) { |
f57c6915 | 4414 | case TEMP_TB: |
b4cb76e6 | 4415 | tcg_debug_assert(ts->val_type != TEMP_VAL_REG || ts->mem_coherent); |
c0522136 | 4416 | break; |
c7482438 | 4417 | case TEMP_EBB: |
c0522136 RH |
4418 | case TEMP_CONST: |
4419 | break; | |
4420 | default: | |
4421 | g_assert_not_reached(); | |
b4cb76e6 RH |
4422 | } |
4423 | } | |
4424 | } | |
4425 | ||
bab1671f | 4426 | /* |
c58f4c97 | 4427 | * Specialized code generation for INDEX_op_mov_* with a constant. |
bab1671f | 4428 | */ |
0fe4fca4 | 4429 | static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, |
ba87719c RH |
4430 | tcg_target_ulong val, TCGLifeData arg_life, |
4431 | TCGRegSet preferred_regs) | |
e8996ee0 | 4432 | { |
d63e3b6e | 4433 | /* ENV should not be modified. */ |
e01fa97d | 4434 | tcg_debug_assert(!temp_readonly(ots)); |
59d7c14e RH |
4435 | |
4436 | /* The movi is not explicitly generated here. */ | |
098859f1 | 4437 | set_temp_val_nonreg(s, ots, TEMP_VAL_CONST); |
59d7c14e RH |
4438 | ots->val = val; |
4439 | ots->mem_coherent = 0; | |
4440 | if (NEED_SYNC_ARG(0)) { | |
ba87719c | 4441 | temp_sync(s, ots, s->reserved_regs, preferred_regs, IS_DEAD_ARG(0)); |
59d7c14e | 4442 | } else if (IS_DEAD_ARG(0)) { |
f8bf00f1 | 4443 | temp_dead(s, ots); |
4c4e1ab2 | 4444 | } |
e8996ee0 FB |
4445 | } |
4446 | ||
bab1671f RH |
4447 | /* |
4448 | * Specialized code generation for INDEX_op_mov_*. | |
4449 | */ | |
dd186292 | 4450 | static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) |
c896fe29 | 4451 | { |
dd186292 | 4452 | const TCGLifeData arg_life = op->life; |
69e3706d | 4453 | TCGRegSet allocated_regs, preferred_regs; |
c896fe29 | 4454 | TCGTemp *ts, *ots; |
450445d5 | 4455 | TCGType otype, itype; |
098859f1 | 4456 | TCGReg oreg, ireg; |
c896fe29 | 4457 | |
d21369f5 | 4458 | allocated_regs = s->reserved_regs; |
31fd884b | 4459 | preferred_regs = output_pref(op, 0); |
43439139 RH |
4460 | ots = arg_temp(op->args[0]); |
4461 | ts = arg_temp(op->args[1]); | |
450445d5 | 4462 | |
d63e3b6e | 4463 | /* ENV should not be modified. */ |
e01fa97d | 4464 | tcg_debug_assert(!temp_readonly(ots)); |
d63e3b6e | 4465 | |
450445d5 RH |
4466 | /* Note that otype != itype for no-op truncation. */ |
4467 | otype = ots->type; | |
4468 | itype = ts->type; | |
c29c1d7e | 4469 | |
0fe4fca4 PB |
4470 | if (ts->val_type == TEMP_VAL_CONST) { |
4471 | /* propagate constant or generate sti */ | |
4472 | tcg_target_ulong val = ts->val; | |
4473 | if (IS_DEAD_ARG(1)) { | |
4474 | temp_dead(s, ts); | |
4475 | } | |
69e3706d | 4476 | tcg_reg_alloc_do_movi(s, ots, val, arg_life, preferred_regs); |
0fe4fca4 PB |
4477 | return; |
4478 | } | |
4479 | ||
4480 | /* If the source value is in memory we're going to be forced | |
4481 | to have it in a register in order to perform the copy. Copy | |
4482 | the SOURCE value into its own register first, that way we | |
4483 | don't have to reload SOURCE the next time it is used. */ | |
4484 | if (ts->val_type == TEMP_VAL_MEM) { | |
69e3706d RH |
4485 | temp_load(s, ts, tcg_target_available_regs[itype], |
4486 | allocated_regs, preferred_regs); | |
c29c1d7e | 4487 | } |
0fe4fca4 | 4488 | tcg_debug_assert(ts->val_type == TEMP_VAL_REG); |
098859f1 RH |
4489 | ireg = ts->reg; |
4490 | ||
d63e3b6e | 4491 | if (IS_DEAD_ARG(0)) { |
c29c1d7e AJ |
4492 | /* mov to a non-saved dead register makes no sense (even with |
4493 | liveness analysis disabled). */ | |
eabb7b91 | 4494 | tcg_debug_assert(NEED_SYNC_ARG(0)); |
c29c1d7e | 4495 | if (!ots->mem_allocated) { |
2272e4a7 | 4496 | temp_allocate_frame(s, ots); |
c29c1d7e | 4497 | } |
098859f1 | 4498 | tcg_out_st(s, otype, ireg, ots->mem_base->reg, ots->mem_offset); |
c29c1d7e | 4499 | if (IS_DEAD_ARG(1)) { |
f8bf00f1 | 4500 | temp_dead(s, ts); |
c29c1d7e | 4501 | } |
f8bf00f1 | 4502 | temp_dead(s, ots); |
098859f1 RH |
4503 | return; |
4504 | } | |
4505 | ||
4506 | if (IS_DEAD_ARG(1) && ts->kind != TEMP_FIXED) { | |
4507 | /* | |
4508 | * The mov can be suppressed. Kill input first, so that it | |
4509 | * is unlinked from reg_to_temp, then set the output to the | |
4510 | * reg that we saved from the input. | |
4511 | */ | |
4512 | temp_dead(s, ts); | |
4513 | oreg = ireg; | |
c29c1d7e | 4514 | } else { |
098859f1 RH |
4515 | if (ots->val_type == TEMP_VAL_REG) { |
4516 | oreg = ots->reg; | |
c896fe29 | 4517 | } else { |
098859f1 RH |
4518 | /* Make sure to not spill the input register during allocation. */ |
4519 | oreg = tcg_reg_alloc(s, tcg_target_available_regs[otype], | |
4520 | allocated_regs | ((TCGRegSet)1 << ireg), | |
4521 | preferred_regs, ots->indirect_base); | |
c896fe29 | 4522 | } |
098859f1 RH |
4523 | if (!tcg_out_mov(s, otype, oreg, ireg)) { |
4524 | /* | |
4525 | * Cross register class move not supported. | |
4526 | * Store the source register into the destination slot | |
4527 | * and leave the destination temp as TEMP_VAL_MEM. | |
4528 | */ | |
4529 | assert(!temp_readonly(ots)); | |
4530 | if (!ts->mem_allocated) { | |
4531 | temp_allocate_frame(s, ots); | |
4532 | } | |
4533 | tcg_out_st(s, ts->type, ireg, ots->mem_base->reg, ots->mem_offset); | |
4534 | set_temp_val_nonreg(s, ts, TEMP_VAL_MEM); | |
4535 | ots->mem_coherent = 1; | |
4536 | return; | |
c896fe29 | 4537 | } |
ec7a869d | 4538 | } |
098859f1 RH |
4539 | set_temp_val_reg(s, ots, oreg); |
4540 | ots->mem_coherent = 0; | |
4541 | ||
4542 | if (NEED_SYNC_ARG(0)) { | |
4543 | temp_sync(s, ots, allocated_regs, 0, 0); | |
4544 | } | |
c896fe29 FB |
4545 | } |
4546 | ||
bab1671f RH |
4547 | /* |
4548 | * Specialized code generation for INDEX_op_dup_vec. | |
4549 | */ | |
4550 | static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op) | |
4551 | { | |
4552 | const TCGLifeData arg_life = op->life; | |
4553 | TCGRegSet dup_out_regs, dup_in_regs; | |
4554 | TCGTemp *its, *ots; | |
4555 | TCGType itype, vtype; | |
4556 | unsigned vece; | |
31c96417 | 4557 | int lowpart_ofs; |
bab1671f RH |
4558 | bool ok; |
4559 | ||
4560 | ots = arg_temp(op->args[0]); | |
4561 | its = arg_temp(op->args[1]); | |
4562 | ||
4563 | /* ENV should not be modified. */ | |
e01fa97d | 4564 | tcg_debug_assert(!temp_readonly(ots)); |
bab1671f RH |
4565 | |
4566 | itype = its->type; | |
4567 | vece = TCGOP_VECE(op); | |
4568 | vtype = TCGOP_VECL(op) + TCG_TYPE_V64; | |
4569 | ||
4570 | if (its->val_type == TEMP_VAL_CONST) { | |
4571 | /* Propagate constant via movi -> dupi. */ | |
4572 | tcg_target_ulong val = its->val; | |
4573 | if (IS_DEAD_ARG(1)) { | |
4574 | temp_dead(s, its); | |
4575 | } | |
31fd884b | 4576 | tcg_reg_alloc_do_movi(s, ots, val, arg_life, output_pref(op, 0)); |
bab1671f RH |
4577 | return; |
4578 | } | |
4579 | ||
9be0d080 RH |
4580 | dup_out_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs; |
4581 | dup_in_regs = tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs; | |
bab1671f RH |
4582 | |
4583 | /* Allocate the output register now. */ | |
4584 | if (ots->val_type != TEMP_VAL_REG) { | |
4585 | TCGRegSet allocated_regs = s->reserved_regs; | |
098859f1 | 4586 | TCGReg oreg; |
bab1671f RH |
4587 | |
4588 | if (!IS_DEAD_ARG(1) && its->val_type == TEMP_VAL_REG) { | |
4589 | /* Make sure to not spill the input register. */ | |
4590 | tcg_regset_set_reg(allocated_regs, its->reg); | |
4591 | } | |
098859f1 | 4592 | oreg = tcg_reg_alloc(s, dup_out_regs, allocated_regs, |
31fd884b | 4593 | output_pref(op, 0), ots->indirect_base); |
098859f1 | 4594 | set_temp_val_reg(s, ots, oreg); |
bab1671f RH |
4595 | } |
4596 | ||
4597 | switch (its->val_type) { | |
4598 | case TEMP_VAL_REG: | |
4599 | /* | |
4600 | * The dup constriaints must be broad, covering all possible VECE. | |
4601 | * However, tcg_op_dup_vec() gets to see the VECE and we allow it | |
4602 | * to fail, indicating that extra moves are required for that case. | |
4603 | */ | |
4604 | if (tcg_regset_test_reg(dup_in_regs, its->reg)) { | |
4605 | if (tcg_out_dup_vec(s, vtype, vece, ots->reg, its->reg)) { | |
4606 | goto done; | |
4607 | } | |
4608 | /* Try again from memory or a vector input register. */ | |
4609 | } | |
4610 | if (!its->mem_coherent) { | |
4611 | /* | |
4612 | * The input register is not synced, and so an extra store | |
4613 | * would be required to use memory. Attempt an integer-vector | |
4614 | * register move first. We do not have a TCGRegSet for this. | |
4615 | */ | |
4616 | if (tcg_out_mov(s, itype, ots->reg, its->reg)) { | |
4617 | break; | |
4618 | } | |
4619 | /* Sync the temp back to its slot and load from there. */ | |
4620 | temp_sync(s, its, s->reserved_regs, 0, 0); | |
4621 | } | |
4622 | /* fall through */ | |
4623 | ||
4624 | case TEMP_VAL_MEM: | |
31c96417 RH |
4625 | lowpart_ofs = 0; |
4626 | if (HOST_BIG_ENDIAN) { | |
4627 | lowpart_ofs = tcg_type_size(itype) - (1 << vece); | |
4628 | } | |
d6ecb4a9 | 4629 | if (tcg_out_dupm_vec(s, vtype, vece, ots->reg, its->mem_base->reg, |
31c96417 | 4630 | its->mem_offset + lowpart_ofs)) { |
d6ecb4a9 RH |
4631 | goto done; |
4632 | } | |
098859f1 | 4633 | /* Load the input into the destination vector register. */ |
bab1671f RH |
4634 | tcg_out_ld(s, itype, ots->reg, its->mem_base->reg, its->mem_offset); |
4635 | break; | |
4636 | ||
4637 | default: | |
4638 | g_assert_not_reached(); | |
4639 | } | |
4640 | ||
4641 | /* We now have a vector input register, so dup must succeed. */ | |
4642 | ok = tcg_out_dup_vec(s, vtype, vece, ots->reg, ots->reg); | |
4643 | tcg_debug_assert(ok); | |
4644 | ||
4645 | done: | |
36f5539c | 4646 | ots->mem_coherent = 0; |
bab1671f RH |
4647 | if (IS_DEAD_ARG(1)) { |
4648 | temp_dead(s, its); | |
4649 | } | |
4650 | if (NEED_SYNC_ARG(0)) { | |
4651 | temp_sync(s, ots, s->reserved_regs, 0, 0); | |
4652 | } | |
4653 | if (IS_DEAD_ARG(0)) { | |
4654 | temp_dead(s, ots); | |
4655 | } | |
4656 | } | |
4657 | ||
dd186292 | 4658 | static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) |
c896fe29 | 4659 | { |
dd186292 RH |
4660 | const TCGLifeData arg_life = op->life; |
4661 | const TCGOpDef * const def = &tcg_op_defs[op->opc]; | |
82790a87 RH |
4662 | TCGRegSet i_allocated_regs; |
4663 | TCGRegSet o_allocated_regs; | |
b6638662 RH |
4664 | int i, k, nb_iargs, nb_oargs; |
4665 | TCGReg reg; | |
c896fe29 FB |
4666 | TCGArg arg; |
4667 | const TCGArgConstraint *arg_ct; | |
4668 | TCGTemp *ts; | |
4669 | TCGArg new_args[TCG_MAX_OP_ARGS]; | |
4670 | int const_args[TCG_MAX_OP_ARGS]; | |
4671 | ||
4672 | nb_oargs = def->nb_oargs; | |
4673 | nb_iargs = def->nb_iargs; | |
4674 | ||
4675 | /* copy constants */ | |
a813e36f | 4676 | memcpy(new_args + nb_oargs + nb_iargs, |
dd186292 | 4677 | op->args + nb_oargs + nb_iargs, |
c896fe29 FB |
4678 | sizeof(TCGArg) * def->nb_cargs); |
4679 | ||
d21369f5 RH |
4680 | i_allocated_regs = s->reserved_regs; |
4681 | o_allocated_regs = s->reserved_regs; | |
82790a87 | 4682 | |
a813e36f | 4683 | /* satisfy input constraints */ |
dd186292 | 4684 | for (k = 0; k < nb_iargs; k++) { |
29f5e925 RH |
4685 | TCGRegSet i_preferred_regs, i_required_regs; |
4686 | bool allocate_new_reg, copyto_new_reg; | |
4687 | TCGTemp *ts2; | |
4688 | int i1, i2; | |
d62816f2 | 4689 | |
66792f90 | 4690 | i = def->args_ct[nb_oargs + k].sort_index; |
dd186292 | 4691 | arg = op->args[i]; |
c896fe29 | 4692 | arg_ct = &def->args_ct[i]; |
43439139 | 4693 | ts = arg_temp(arg); |
40ae5c62 RH |
4694 | |
4695 | if (ts->val_type == TEMP_VAL_CONST | |
ebe92db2 | 4696 | && tcg_target_const_match(ts->val, ts->type, arg_ct->ct, TCGOP_VECE(op))) { |
40ae5c62 RH |
4697 | /* constant is OK for instruction */ |
4698 | const_args[i] = 1; | |
4699 | new_args[i] = ts->val; | |
d62816f2 | 4700 | continue; |
c896fe29 | 4701 | } |
40ae5c62 | 4702 | |
1c1824dc RH |
4703 | reg = ts->reg; |
4704 | i_preferred_regs = 0; | |
29f5e925 | 4705 | i_required_regs = arg_ct->regs; |
1c1824dc | 4706 | allocate_new_reg = false; |
29f5e925 RH |
4707 | copyto_new_reg = false; |
4708 | ||
4709 | switch (arg_ct->pair) { | |
4710 | case 0: /* not paired */ | |
4711 | if (arg_ct->ialias) { | |
31fd884b | 4712 | i_preferred_regs = output_pref(op, arg_ct->alias_index); |
29f5e925 RH |
4713 | |
4714 | /* | |
4715 | * If the input is readonly, then it cannot also be an | |
4716 | * output and aliased to itself. If the input is not | |
4717 | * dead after the instruction, we must allocate a new | |
4718 | * register and move it. | |
4719 | */ | |
22d2e535 IL |
4720 | if (temp_readonly(ts) || !IS_DEAD_ARG(i) |
4721 | || def->args_ct[arg_ct->alias_index].newreg) { | |
29f5e925 RH |
4722 | allocate_new_reg = true; |
4723 | } else if (ts->val_type == TEMP_VAL_REG) { | |
4724 | /* | |
4725 | * Check if the current register has already been | |
4726 | * allocated for another input. | |
4727 | */ | |
4728 | allocate_new_reg = | |
4729 | tcg_regset_test_reg(i_allocated_regs, reg); | |
4730 | } | |
4731 | } | |
4732 | if (!allocate_new_reg) { | |
4733 | temp_load(s, ts, i_required_regs, i_allocated_regs, | |
4734 | i_preferred_regs); | |
4735 | reg = ts->reg; | |
4736 | allocate_new_reg = !tcg_regset_test_reg(i_required_regs, reg); | |
4737 | } | |
4738 | if (allocate_new_reg) { | |
4739 | /* | |
4740 | * Allocate a new register matching the constraint | |
4741 | * and move the temporary register into it. | |
4742 | */ | |
4743 | temp_load(s, ts, tcg_target_available_regs[ts->type], | |
4744 | i_allocated_regs, 0); | |
4745 | reg = tcg_reg_alloc(s, i_required_regs, i_allocated_regs, | |
4746 | i_preferred_regs, ts->indirect_base); | |
4747 | copyto_new_reg = true; | |
4748 | } | |
4749 | break; | |
4750 | ||
4751 | case 1: | |
4752 | /* First of an input pair; if i1 == i2, the second is an output. */ | |
4753 | i1 = i; | |
4754 | i2 = arg_ct->pair_index; | |
4755 | ts2 = i1 != i2 ? arg_temp(op->args[i2]) : NULL; | |
4756 | ||
4757 | /* | |
4758 | * It is easier to default to allocating a new pair | |
4759 | * and to identify a few cases where it's not required. | |
4760 | */ | |
4761 | if (arg_ct->ialias) { | |
31fd884b | 4762 | i_preferred_regs = output_pref(op, arg_ct->alias_index); |
29f5e925 RH |
4763 | if (IS_DEAD_ARG(i1) && |
4764 | IS_DEAD_ARG(i2) && | |
4765 | !temp_readonly(ts) && | |
4766 | ts->val_type == TEMP_VAL_REG && | |
4767 | ts->reg < TCG_TARGET_NB_REGS - 1 && | |
4768 | tcg_regset_test_reg(i_required_regs, reg) && | |
4769 | !tcg_regset_test_reg(i_allocated_regs, reg) && | |
4770 | !tcg_regset_test_reg(i_allocated_regs, reg + 1) && | |
4771 | (ts2 | |
4772 | ? ts2->val_type == TEMP_VAL_REG && | |
4773 | ts2->reg == reg + 1 && | |
4774 | !temp_readonly(ts2) | |
4775 | : s->reg_to_temp[reg + 1] == NULL)) { | |
4776 | break; | |
4777 | } | |
4778 | } else { | |
4779 | /* Without aliasing, the pair must also be an input. */ | |
4780 | tcg_debug_assert(ts2); | |
4781 | if (ts->val_type == TEMP_VAL_REG && | |
4782 | ts2->val_type == TEMP_VAL_REG && | |
4783 | ts2->reg == reg + 1 && | |
4784 | tcg_regset_test_reg(i_required_regs, reg)) { | |
4785 | break; | |
4786 | } | |
4787 | } | |
4788 | reg = tcg_reg_alloc_pair(s, i_required_regs, i_allocated_regs, | |
4789 | 0, ts->indirect_base); | |
4790 | goto do_pair; | |
4791 | ||
4792 | case 2: /* pair second */ | |
4793 | reg = new_args[arg_ct->pair_index] + 1; | |
4794 | goto do_pair; | |
1c1824dc | 4795 | |
29f5e925 RH |
4796 | case 3: /* ialias with second output, no first input */ |
4797 | tcg_debug_assert(arg_ct->ialias); | |
31fd884b | 4798 | i_preferred_regs = output_pref(op, arg_ct->alias_index); |
d62816f2 | 4799 | |
29f5e925 RH |
4800 | if (IS_DEAD_ARG(i) && |
4801 | !temp_readonly(ts) && | |
4802 | ts->val_type == TEMP_VAL_REG && | |
4803 | reg > 0 && | |
4804 | s->reg_to_temp[reg - 1] == NULL && | |
4805 | tcg_regset_test_reg(i_required_regs, reg) && | |
4806 | !tcg_regset_test_reg(i_allocated_regs, reg) && | |
4807 | !tcg_regset_test_reg(i_allocated_regs, reg - 1)) { | |
4808 | tcg_regset_set_reg(i_allocated_regs, reg - 1); | |
4809 | break; | |
4810 | } | |
4811 | reg = tcg_reg_alloc_pair(s, i_required_regs >> 1, | |
4812 | i_allocated_regs, 0, | |
4813 | ts->indirect_base); | |
4814 | tcg_regset_set_reg(i_allocated_regs, reg); | |
4815 | reg += 1; | |
4816 | goto do_pair; | |
4817 | ||
4818 | do_pair: | |
c0522136 | 4819 | /* |
29f5e925 RH |
4820 | * If an aliased input is not dead after the instruction, |
4821 | * we must allocate a new register and move it. | |
c0522136 | 4822 | */ |
29f5e925 RH |
4823 | if (arg_ct->ialias && (!IS_DEAD_ARG(i) || temp_readonly(ts))) { |
4824 | TCGRegSet t_allocated_regs = i_allocated_regs; | |
4825 | ||
1c1824dc | 4826 | /* |
29f5e925 RH |
4827 | * Because of the alias, and the continued life, make sure |
4828 | * that the temp is somewhere *other* than the reg pair, | |
4829 | * and we get a copy in reg. | |
1c1824dc | 4830 | */ |
29f5e925 RH |
4831 | tcg_regset_set_reg(t_allocated_regs, reg); |
4832 | tcg_regset_set_reg(t_allocated_regs, reg + 1); | |
4833 | if (ts->val_type == TEMP_VAL_REG && ts->reg == reg) { | |
4834 | /* If ts was already in reg, copy it somewhere else. */ | |
4835 | TCGReg nr; | |
4836 | bool ok; | |
4837 | ||
4838 | tcg_debug_assert(ts->kind != TEMP_FIXED); | |
4839 | nr = tcg_reg_alloc(s, tcg_target_available_regs[ts->type], | |
4840 | t_allocated_regs, 0, ts->indirect_base); | |
4841 | ok = tcg_out_mov(s, ts->type, nr, reg); | |
4842 | tcg_debug_assert(ok); | |
4843 | ||
4844 | set_temp_val_reg(s, ts, nr); | |
4845 | } else { | |
4846 | temp_load(s, ts, tcg_target_available_regs[ts->type], | |
4847 | t_allocated_regs, 0); | |
4848 | copyto_new_reg = true; | |
4849 | } | |
4850 | } else { | |
4851 | /* Preferably allocate to reg, otherwise copy. */ | |
4852 | i_required_regs = (TCGRegSet)1 << reg; | |
4853 | temp_load(s, ts, i_required_regs, i_allocated_regs, | |
4854 | i_preferred_regs); | |
4855 | copyto_new_reg = ts->reg != reg; | |
5ff9d6a4 | 4856 | } |
29f5e925 | 4857 | break; |
d62816f2 | 4858 | |
29f5e925 RH |
4859 | default: |
4860 | g_assert_not_reached(); | |
1c1824dc | 4861 | } |
d62816f2 | 4862 | |
29f5e925 | 4863 | if (copyto_new_reg) { |
78113e83 | 4864 | if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { |
240c08d0 RH |
4865 | /* |
4866 | * Cross register class move not supported. Sync the | |
4867 | * temp back to its slot and load from there. | |
4868 | */ | |
4869 | temp_sync(s, ts, i_allocated_regs, 0, 0); | |
4870 | tcg_out_ld(s, ts->type, reg, | |
4871 | ts->mem_base->reg, ts->mem_offset); | |
78113e83 | 4872 | } |
c896fe29 | 4873 | } |
c896fe29 FB |
4874 | new_args[i] = reg; |
4875 | const_args[i] = 0; | |
82790a87 | 4876 | tcg_regset_set_reg(i_allocated_regs, reg); |
c896fe29 | 4877 | } |
a813e36f | 4878 | |
a52ad07e AJ |
4879 | /* mark dead temporaries and free the associated registers */ |
4880 | for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { | |
4881 | if (IS_DEAD_ARG(i)) { | |
43439139 | 4882 | temp_dead(s, arg_temp(op->args[i])); |
a52ad07e AJ |
4883 | } |
4884 | } | |
4885 | ||
b4cb76e6 RH |
4886 | if (def->flags & TCG_OPF_COND_BRANCH) { |
4887 | tcg_reg_alloc_cbranch(s, i_allocated_regs); | |
4888 | } else if (def->flags & TCG_OPF_BB_END) { | |
82790a87 | 4889 | tcg_reg_alloc_bb_end(s, i_allocated_regs); |
e8996ee0 | 4890 | } else { |
e8996ee0 | 4891 | if (def->flags & TCG_OPF_CALL_CLOBBER) { |
a813e36f | 4892 | /* XXX: permit generic clobber register list ? */ |
c8074023 RH |
4893 | for (i = 0; i < TCG_TARGET_NB_REGS; i++) { |
4894 | if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { | |
82790a87 | 4895 | tcg_reg_free(s, i, i_allocated_regs); |
e8996ee0 | 4896 | } |
c896fe29 | 4897 | } |
3d5c5f87 AJ |
4898 | } |
4899 | if (def->flags & TCG_OPF_SIDE_EFFECTS) { | |
4900 | /* sync globals if the op has side effects and might trigger | |
4901 | an exception. */ | |
82790a87 | 4902 | sync_globals(s, i_allocated_regs); |
c896fe29 | 4903 | } |
a813e36f | 4904 | |
e8996ee0 | 4905 | /* satisfy the output constraints */ |
e8996ee0 | 4906 | for(k = 0; k < nb_oargs; k++) { |
66792f90 | 4907 | i = def->args_ct[k].sort_index; |
dd186292 | 4908 | arg = op->args[i]; |
e8996ee0 | 4909 | arg_ct = &def->args_ct[i]; |
43439139 | 4910 | ts = arg_temp(arg); |
d63e3b6e RH |
4911 | |
4912 | /* ENV should not be modified. */ | |
e01fa97d | 4913 | tcg_debug_assert(!temp_readonly(ts)); |
d63e3b6e | 4914 | |
29f5e925 RH |
4915 | switch (arg_ct->pair) { |
4916 | case 0: /* not paired */ | |
4917 | if (arg_ct->oalias && !const_args[arg_ct->alias_index]) { | |
4918 | reg = new_args[arg_ct->alias_index]; | |
4919 | } else if (arg_ct->newreg) { | |
4920 | reg = tcg_reg_alloc(s, arg_ct->regs, | |
4921 | i_allocated_regs | o_allocated_regs, | |
31fd884b | 4922 | output_pref(op, k), ts->indirect_base); |
29f5e925 RH |
4923 | } else { |
4924 | reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs, | |
31fd884b | 4925 | output_pref(op, k), ts->indirect_base); |
29f5e925 RH |
4926 | } |
4927 | break; | |
4928 | ||
4929 | case 1: /* first of pair */ | |
4930 | tcg_debug_assert(!arg_ct->newreg); | |
4931 | if (arg_ct->oalias) { | |
4932 | reg = new_args[arg_ct->alias_index]; | |
4933 | break; | |
4934 | } | |
4935 | reg = tcg_reg_alloc_pair(s, arg_ct->regs, o_allocated_regs, | |
31fd884b | 4936 | output_pref(op, k), ts->indirect_base); |
29f5e925 RH |
4937 | break; |
4938 | ||
4939 | case 2: /* second of pair */ | |
4940 | tcg_debug_assert(!arg_ct->newreg); | |
4941 | if (arg_ct->oalias) { | |
4942 | reg = new_args[arg_ct->alias_index]; | |
4943 | } else { | |
4944 | reg = new_args[arg_ct->pair_index] + 1; | |
4945 | } | |
4946 | break; | |
4947 | ||
4948 | case 3: /* first of pair, aliasing with a second input */ | |
4949 | tcg_debug_assert(!arg_ct->newreg); | |
4950 | reg = new_args[arg_ct->pair_index] - 1; | |
4951 | break; | |
4952 | ||
4953 | default: | |
4954 | g_assert_not_reached(); | |
c896fe29 | 4955 | } |
82790a87 | 4956 | tcg_regset_set_reg(o_allocated_regs, reg); |
098859f1 | 4957 | set_temp_val_reg(s, ts, reg); |
d63e3b6e | 4958 | ts->mem_coherent = 0; |
e8996ee0 | 4959 | new_args[i] = reg; |
c896fe29 | 4960 | } |
c896fe29 FB |
4961 | } |
4962 | ||
c896fe29 | 4963 | /* emit instruction */ |
678155b2 RH |
4964 | switch (op->opc) { |
4965 | case INDEX_op_ext8s_i32: | |
4966 | tcg_out_ext8s(s, TCG_TYPE_I32, new_args[0], new_args[1]); | |
4967 | break; | |
4968 | case INDEX_op_ext8s_i64: | |
4969 | tcg_out_ext8s(s, TCG_TYPE_I64, new_args[0], new_args[1]); | |
4970 | break; | |
d0e66c89 RH |
4971 | case INDEX_op_ext8u_i32: |
4972 | case INDEX_op_ext8u_i64: | |
4973 | tcg_out_ext8u(s, new_args[0], new_args[1]); | |
4974 | break; | |
753e42ea RH |
4975 | case INDEX_op_ext16s_i32: |
4976 | tcg_out_ext16s(s, TCG_TYPE_I32, new_args[0], new_args[1]); | |
4977 | break; | |
4978 | case INDEX_op_ext16s_i64: | |
4979 | tcg_out_ext16s(s, TCG_TYPE_I64, new_args[0], new_args[1]); | |
4980 | break; | |
379afdff RH |
4981 | case INDEX_op_ext16u_i32: |
4982 | case INDEX_op_ext16u_i64: | |
4983 | tcg_out_ext16u(s, new_args[0], new_args[1]); | |
4984 | break; | |
52bf3398 RH |
4985 | case INDEX_op_ext32s_i64: |
4986 | tcg_out_ext32s(s, new_args[0], new_args[1]); | |
4987 | break; | |
9ecf5f61 RH |
4988 | case INDEX_op_ext32u_i64: |
4989 | tcg_out_ext32u(s, new_args[0], new_args[1]); | |
4990 | break; | |
9c6aa274 RH |
4991 | case INDEX_op_ext_i32_i64: |
4992 | tcg_out_exts_i32_i64(s, new_args[0], new_args[1]); | |
4993 | break; | |
b9bfe000 RH |
4994 | case INDEX_op_extu_i32_i64: |
4995 | tcg_out_extu_i32_i64(s, new_args[0], new_args[1]); | |
4996 | break; | |
b8b94ac6 RH |
4997 | case INDEX_op_extrl_i64_i32: |
4998 | tcg_out_extrl_i64_i32(s, new_args[0], new_args[1]); | |
4999 | break; | |
678155b2 RH |
5000 | default: |
5001 | if (def->flags & TCG_OPF_VECTOR) { | |
5002 | tcg_out_vec_op(s, op->opc, TCGOP_VECL(op), TCGOP_VECE(op), | |
5003 | new_args, const_args); | |
5004 | } else { | |
5005 | tcg_out_op(s, op->opc, new_args, const_args); | |
5006 | } | |
5007 | break; | |
d2fd745f RH |
5008 | } |
5009 | ||
c896fe29 FB |
5010 | /* move the outputs in the correct register if needed */ |
5011 | for(i = 0; i < nb_oargs; i++) { | |
43439139 | 5012 | ts = arg_temp(op->args[i]); |
d63e3b6e RH |
5013 | |
5014 | /* ENV should not be modified. */ | |
e01fa97d | 5015 | tcg_debug_assert(!temp_readonly(ts)); |
d63e3b6e | 5016 | |
ec7a869d | 5017 | if (NEED_SYNC_ARG(i)) { |
98b4e186 | 5018 | temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i)); |
59d7c14e | 5019 | } else if (IS_DEAD_ARG(i)) { |
f8bf00f1 | 5020 | temp_dead(s, ts); |
ec7a869d | 5021 | } |
c896fe29 FB |
5022 | } |
5023 | } | |
5024 | ||
efe86b21 RH |
5025 | static bool tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op) |
5026 | { | |
5027 | const TCGLifeData arg_life = op->life; | |
5028 | TCGTemp *ots, *itsl, *itsh; | |
5029 | TCGType vtype = TCGOP_VECL(op) + TCG_TYPE_V64; | |
5030 | ||
5031 | /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */ | |
5032 | tcg_debug_assert(TCG_TARGET_REG_BITS == 32); | |
5033 | tcg_debug_assert(TCGOP_VECE(op) == MO_64); | |
5034 | ||
5035 | ots = arg_temp(op->args[0]); | |
5036 | itsl = arg_temp(op->args[1]); | |
5037 | itsh = arg_temp(op->args[2]); | |
5038 | ||
5039 | /* ENV should not be modified. */ | |
5040 | tcg_debug_assert(!temp_readonly(ots)); | |
5041 | ||
5042 | /* Allocate the output register now. */ | |
5043 | if (ots->val_type != TEMP_VAL_REG) { | |
5044 | TCGRegSet allocated_regs = s->reserved_regs; | |
5045 | TCGRegSet dup_out_regs = | |
5046 | tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs; | |
098859f1 | 5047 | TCGReg oreg; |
efe86b21 RH |
5048 | |
5049 | /* Make sure to not spill the input registers. */ | |
5050 | if (!IS_DEAD_ARG(1) && itsl->val_type == TEMP_VAL_REG) { | |
5051 | tcg_regset_set_reg(allocated_regs, itsl->reg); | |
5052 | } | |
5053 | if (!IS_DEAD_ARG(2) && itsh->val_type == TEMP_VAL_REG) { | |
5054 | tcg_regset_set_reg(allocated_regs, itsh->reg); | |
5055 | } | |
5056 | ||
098859f1 | 5057 | oreg = tcg_reg_alloc(s, dup_out_regs, allocated_regs, |
31fd884b | 5058 | output_pref(op, 0), ots->indirect_base); |
098859f1 | 5059 | set_temp_val_reg(s, ots, oreg); |
efe86b21 RH |
5060 | } |
5061 | ||
5062 | /* Promote dup2 of immediates to dupi_vec. */ | |
5063 | if (itsl->val_type == TEMP_VAL_CONST && itsh->val_type == TEMP_VAL_CONST) { | |
5064 | uint64_t val = deposit64(itsl->val, 32, 32, itsh->val); | |
5065 | MemOp vece = MO_64; | |
5066 | ||
5067 | if (val == dup_const(MO_8, val)) { | |
5068 | vece = MO_8; | |
5069 | } else if (val == dup_const(MO_16, val)) { | |
5070 | vece = MO_16; | |
5071 | } else if (val == dup_const(MO_32, val)) { | |
5072 | vece = MO_32; | |
5073 | } | |
5074 | ||
5075 | tcg_out_dupi_vec(s, vtype, vece, ots->reg, val); | |
5076 | goto done; | |
5077 | } | |
5078 | ||
5079 | /* If the two inputs form one 64-bit value, try dupm_vec. */ | |
aef85402 RH |
5080 | if (itsl->temp_subindex == HOST_BIG_ENDIAN && |
5081 | itsh->temp_subindex == !HOST_BIG_ENDIAN && | |
5082 | itsl == itsh + (HOST_BIG_ENDIAN ? 1 : -1)) { | |
5083 | TCGTemp *its = itsl - HOST_BIG_ENDIAN; | |
5084 | ||
5085 | temp_sync(s, its + 0, s->reserved_regs, 0, 0); | |
5086 | temp_sync(s, its + 1, s->reserved_regs, 0, 0); | |
5087 | ||
efe86b21 RH |
5088 | if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg, |
5089 | its->mem_base->reg, its->mem_offset)) { | |
5090 | goto done; | |
5091 | } | |
5092 | } | |
5093 | ||
5094 | /* Fall back to generic expansion. */ | |
5095 | return false; | |
5096 | ||
5097 | done: | |
36f5539c | 5098 | ots->mem_coherent = 0; |
efe86b21 RH |
5099 | if (IS_DEAD_ARG(1)) { |
5100 | temp_dead(s, itsl); | |
5101 | } | |
5102 | if (IS_DEAD_ARG(2)) { | |
5103 | temp_dead(s, itsh); | |
5104 | } | |
5105 | if (NEED_SYNC_ARG(0)) { | |
5106 | temp_sync(s, ots, s->reserved_regs, 0, IS_DEAD_ARG(0)); | |
5107 | } else if (IS_DEAD_ARG(0)) { | |
5108 | temp_dead(s, ots); | |
5109 | } | |
5110 | return true; | |
5111 | } | |
5112 | ||
39004a71 RH |
5113 | static void load_arg_reg(TCGContext *s, TCGReg reg, TCGTemp *ts, |
5114 | TCGRegSet allocated_regs) | |
c896fe29 | 5115 | { |
39004a71 RH |
5116 | if (ts->val_type == TEMP_VAL_REG) { |
5117 | if (ts->reg != reg) { | |
5118 | tcg_reg_free(s, reg, allocated_regs); | |
5119 | if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { | |
5120 | /* | |
5121 | * Cross register class move not supported. Sync the | |
5122 | * temp back to its slot and load from there. | |
5123 | */ | |
5124 | temp_sync(s, ts, allocated_regs, 0, 0); | |
5125 | tcg_out_ld(s, ts->type, reg, | |
5126 | ts->mem_base->reg, ts->mem_offset); | |
5127 | } | |
5128 | } | |
5129 | } else { | |
5130 | TCGRegSet arg_set = 0; | |
c896fe29 | 5131 | |
39004a71 RH |
5132 | tcg_reg_free(s, reg, allocated_regs); |
5133 | tcg_regset_set_reg(arg_set, reg); | |
5134 | temp_load(s, ts, arg_set, allocated_regs, 0); | |
b03cce8e | 5135 | } |
39004a71 | 5136 | } |
39cf05d3 | 5137 | |
d78e4a4f | 5138 | static void load_arg_stk(TCGContext *s, unsigned arg_slot, TCGTemp *ts, |
39004a71 RH |
5139 | TCGRegSet allocated_regs) |
5140 | { | |
5141 | /* | |
5142 | * When the destination is on the stack, load up the temp and store. | |
5143 | * If there are many call-saved registers, the temp might live to | |
5144 | * see another use; otherwise it'll be discarded. | |
5145 | */ | |
5146 | temp_load(s, ts, tcg_target_available_regs[ts->type], allocated_regs, 0); | |
5147 | tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, | |
d78e4a4f | 5148 | arg_slot_stk_ofs(arg_slot)); |
39004a71 | 5149 | } |
a813e36f | 5150 | |
39004a71 RH |
5151 | static void load_arg_normal(TCGContext *s, const TCGCallArgumentLoc *l, |
5152 | TCGTemp *ts, TCGRegSet *allocated_regs) | |
5153 | { | |
338b61e9 | 5154 | if (arg_slot_reg_p(l->arg_slot)) { |
39004a71 RH |
5155 | TCGReg reg = tcg_target_call_iarg_regs[l->arg_slot]; |
5156 | load_arg_reg(s, reg, ts, *allocated_regs); | |
5157 | tcg_regset_set_reg(*allocated_regs, reg); | |
5158 | } else { | |
d78e4a4f | 5159 | load_arg_stk(s, l->arg_slot, ts, *allocated_regs); |
39004a71 RH |
5160 | } |
5161 | } | |
40ae5c62 | 5162 | |
d78e4a4f | 5163 | static void load_arg_ref(TCGContext *s, unsigned arg_slot, TCGReg ref_base, |
313bdea8 RH |
5164 | intptr_t ref_off, TCGRegSet *allocated_regs) |
5165 | { | |
5166 | TCGReg reg; | |
313bdea8 | 5167 | |
d78e4a4f | 5168 | if (arg_slot_reg_p(arg_slot)) { |
313bdea8 RH |
5169 | reg = tcg_target_call_iarg_regs[arg_slot]; |
5170 | tcg_reg_free(s, reg, *allocated_regs); | |
5171 | tcg_out_addi_ptr(s, reg, ref_base, ref_off); | |
5172 | tcg_regset_set_reg(*allocated_regs, reg); | |
5173 | } else { | |
5174 | reg = tcg_reg_alloc(s, tcg_target_available_regs[TCG_TYPE_PTR], | |
5175 | *allocated_regs, 0, false); | |
5176 | tcg_out_addi_ptr(s, reg, ref_base, ref_off); | |
5177 | tcg_out_st(s, TCG_TYPE_PTR, reg, TCG_REG_CALL_STACK, | |
d78e4a4f | 5178 | arg_slot_stk_ofs(arg_slot)); |
313bdea8 RH |
5179 | } |
5180 | } | |
5181 | ||
39004a71 RH |
5182 | static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) |
5183 | { | |
5184 | const int nb_oargs = TCGOP_CALLO(op); | |
5185 | const int nb_iargs = TCGOP_CALLI(op); | |
5186 | const TCGLifeData arg_life = op->life; | |
5187 | const TCGHelperInfo *info = tcg_call_info(op); | |
5188 | TCGRegSet allocated_regs = s->reserved_regs; | |
5189 | int i; | |
40ae5c62 | 5190 | |
39004a71 RH |
5191 | /* |
5192 | * Move inputs into place in reverse order, | |
5193 | * so that we place stacked arguments first. | |
5194 | */ | |
5195 | for (i = nb_iargs - 1; i >= 0; --i) { | |
5196 | const TCGCallArgumentLoc *loc = &info->in[i]; | |
5197 | TCGTemp *ts = arg_temp(op->args[nb_oargs + i]); | |
40ae5c62 | 5198 | |
39004a71 RH |
5199 | switch (loc->kind) { |
5200 | case TCG_CALL_ARG_NORMAL: | |
5201 | case TCG_CALL_ARG_EXTEND_U: | |
5202 | case TCG_CALL_ARG_EXTEND_S: | |
5203 | load_arg_normal(s, loc, ts, &allocated_regs); | |
5204 | break; | |
313bdea8 RH |
5205 | case TCG_CALL_ARG_BY_REF: |
5206 | load_arg_stk(s, loc->ref_slot, ts, allocated_regs); | |
5207 | load_arg_ref(s, loc->arg_slot, TCG_REG_CALL_STACK, | |
d78e4a4f | 5208 | arg_slot_stk_ofs(loc->ref_slot), |
313bdea8 RH |
5209 | &allocated_regs); |
5210 | break; | |
5211 | case TCG_CALL_ARG_BY_REF_N: | |
5212 | load_arg_stk(s, loc->ref_slot, ts, allocated_regs); | |
5213 | break; | |
39004a71 RH |
5214 | default: |
5215 | g_assert_not_reached(); | |
c896fe29 | 5216 | } |
c896fe29 | 5217 | } |
a813e36f | 5218 | |
39004a71 | 5219 | /* Mark dead temporaries and free the associated registers. */ |
dd186292 | 5220 | for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { |
866cb6cb | 5221 | if (IS_DEAD_ARG(i)) { |
43439139 | 5222 | temp_dead(s, arg_temp(op->args[i])); |
c896fe29 FB |
5223 | } |
5224 | } | |
a813e36f | 5225 | |
39004a71 | 5226 | /* Clobber call registers. */ |
c8074023 RH |
5227 | for (i = 0; i < TCG_TARGET_NB_REGS; i++) { |
5228 | if (tcg_regset_test_reg(tcg_target_call_clobber_regs, i)) { | |
b3915dbb | 5229 | tcg_reg_free(s, i, allocated_regs); |
c896fe29 FB |
5230 | } |
5231 | } | |
78505279 | 5232 | |
39004a71 RH |
5233 | /* |
5234 | * Save globals if they might be written by the helper, | |
5235 | * sync them if they might be read. | |
5236 | */ | |
5237 | if (info->flags & TCG_CALL_NO_READ_GLOBALS) { | |
78505279 | 5238 | /* Nothing to do */ |
39004a71 | 5239 | } else if (info->flags & TCG_CALL_NO_WRITE_GLOBALS) { |
78505279 AJ |
5240 | sync_globals(s, allocated_regs); |
5241 | } else { | |
b9c18f56 AJ |
5242 | save_globals(s, allocated_regs); |
5243 | } | |
c896fe29 | 5244 | |
313bdea8 RH |
5245 | /* |
5246 | * If the ABI passes a pointer to the returned struct as the first | |
5247 | * argument, load that now. Pass a pointer to the output home slot. | |
5248 | */ | |
5249 | if (info->out_kind == TCG_CALL_RET_BY_REF) { | |
5250 | TCGTemp *ts = arg_temp(op->args[0]); | |
5251 | ||
5252 | if (!ts->mem_allocated) { | |
5253 | temp_allocate_frame(s, ts); | |
5254 | } | |
5255 | load_arg_ref(s, 0, ts->mem_base->reg, ts->mem_offset, &allocated_regs); | |
5256 | } | |
5257 | ||
cee44b03 | 5258 | tcg_out_call(s, tcg_call_func(op), info); |
c896fe29 | 5259 | |
39004a71 RH |
5260 | /* Assign output registers and emit moves if needed. */ |
5261 | switch (info->out_kind) { | |
5262 | case TCG_CALL_RET_NORMAL: | |
5263 | for (i = 0; i < nb_oargs; i++) { | |
5264 | TCGTemp *ts = arg_temp(op->args[i]); | |
5e3d0c19 | 5265 | TCGReg reg = tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, i); |
d63e3b6e | 5266 | |
39004a71 RH |
5267 | /* ENV should not be modified. */ |
5268 | tcg_debug_assert(!temp_readonly(ts)); | |
d63e3b6e | 5269 | |
39004a71 RH |
5270 | set_temp_val_reg(s, ts, reg); |
5271 | ts->mem_coherent = 0; | |
5272 | } | |
5273 | break; | |
313bdea8 | 5274 | |
c6556aa0 RH |
5275 | case TCG_CALL_RET_BY_VEC: |
5276 | { | |
5277 | TCGTemp *ts = arg_temp(op->args[0]); | |
5278 | ||
5279 | tcg_debug_assert(ts->base_type == TCG_TYPE_I128); | |
5280 | tcg_debug_assert(ts->temp_subindex == 0); | |
5281 | if (!ts->mem_allocated) { | |
5282 | temp_allocate_frame(s, ts); | |
5283 | } | |
5284 | tcg_out_st(s, TCG_TYPE_V128, | |
5285 | tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0), | |
5286 | ts->mem_base->reg, ts->mem_offset); | |
5287 | } | |
5288 | /* fall through to mark all parts in memory */ | |
5289 | ||
313bdea8 RH |
5290 | case TCG_CALL_RET_BY_REF: |
5291 | /* The callee has performed a write through the reference. */ | |
5292 | for (i = 0; i < nb_oargs; i++) { | |
5293 | TCGTemp *ts = arg_temp(op->args[i]); | |
5294 | ts->val_type = TEMP_VAL_MEM; | |
5295 | } | |
5296 | break; | |
5297 | ||
39004a71 RH |
5298 | default: |
5299 | g_assert_not_reached(); | |
5300 | } | |
5301 | ||
5302 | /* Flush or discard output registers as needed. */ | |
5303 | for (i = 0; i < nb_oargs; i++) { | |
5304 | TCGTemp *ts = arg_temp(op->args[i]); | |
d63e3b6e | 5305 | if (NEED_SYNC_ARG(i)) { |
39004a71 | 5306 | temp_sync(s, ts, s->reserved_regs, 0, IS_DEAD_ARG(i)); |
d63e3b6e RH |
5307 | } else if (IS_DEAD_ARG(i)) { |
5308 | temp_dead(s, ts); | |
c896fe29 FB |
5309 | } |
5310 | } | |
c896fe29 FB |
5311 | } |
5312 | ||
e63b8a29 RH |
5313 | /** |
5314 | * atom_and_align_for_opc: | |
5315 | * @s: tcg context | |
5316 | * @opc: memory operation code | |
5317 | * @host_atom: MO_ATOM_{IFALIGN,WITHIN16,SUBALIGN} for host operations | |
5318 | * @allow_two_ops: true if we are prepared to issue two operations | |
5319 | * | |
5320 | * Return the alignment and atomicity to use for the inline fast path | |
5321 | * for the given memory operation. The alignment may be larger than | |
5322 | * that specified in @opc, and the correct alignment will be diagnosed | |
5323 | * by the slow path helper. | |
5324 | * | |
5325 | * If @allow_two_ops, the host is prepared to test for 2x alignment, | |
5326 | * and issue two loads or stores for subalignment. | |
5327 | */ | |
5328 | static TCGAtomAlign atom_and_align_for_opc(TCGContext *s, MemOp opc, | |
5329 | MemOp host_atom, bool allow_two_ops) | |
5330 | { | |
5331 | MemOp align = get_alignment_bits(opc); | |
5332 | MemOp size = opc & MO_SIZE; | |
5333 | MemOp half = size ? size - 1 : 0; | |
5334 | MemOp atmax; | |
5335 | MemOp atom; | |
5336 | ||
5337 | /* When serialized, no further atomicity required. */ | |
5338 | if (s->gen_tb->cflags & CF_PARALLEL) { | |
5339 | atom = opc & MO_ATOM_MASK; | |
5340 | } else { | |
5341 | atom = MO_ATOM_NONE; | |
5342 | } | |
5343 | ||
5344 | switch (atom) { | |
5345 | case MO_ATOM_NONE: | |
5346 | /* The operation requires no specific atomicity. */ | |
5347 | atmax = MO_8; | |
5348 | break; | |
5349 | ||
5350 | case MO_ATOM_IFALIGN: | |
5351 | atmax = size; | |
5352 | break; | |
5353 | ||
5354 | case MO_ATOM_IFALIGN_PAIR: | |
5355 | atmax = half; | |
5356 | break; | |
5357 | ||
5358 | case MO_ATOM_WITHIN16: | |
5359 | atmax = size; | |
5360 | if (size == MO_128) { | |
5361 | /* Misalignment implies !within16, and therefore no atomicity. */ | |
5362 | } else if (host_atom != MO_ATOM_WITHIN16) { | |
5363 | /* The host does not implement within16, so require alignment. */ | |
5364 | align = MAX(align, size); | |
5365 | } | |
5366 | break; | |
5367 | ||
5368 | case MO_ATOM_WITHIN16_PAIR: | |
5369 | atmax = size; | |
5370 | /* | |
5371 | * Misalignment implies !within16, and therefore half atomicity. | |
5372 | * Any host prepared for two operations can implement this with | |
5373 | * half alignment. | |
5374 | */ | |
5375 | if (host_atom != MO_ATOM_WITHIN16 && allow_two_ops) { | |
5376 | align = MAX(align, half); | |
5377 | } | |
5378 | break; | |
5379 | ||
5380 | case MO_ATOM_SUBALIGN: | |
5381 | atmax = size; | |
5382 | if (host_atom != MO_ATOM_SUBALIGN) { | |
5383 | /* If unaligned but not odd, there are subobjects up to half. */ | |
5384 | if (allow_two_ops) { | |
5385 | align = MAX(align, half); | |
5386 | } else { | |
5387 | align = MAX(align, size); | |
5388 | } | |
5389 | } | |
5390 | break; | |
5391 | ||
5392 | default: | |
5393 | g_assert_not_reached(); | |
5394 | } | |
5395 | ||
5396 | return (TCGAtomAlign){ .atom = atmax, .align = align }; | |
5397 | } | |
5398 | ||
8429a1ca RH |
5399 | /* |
5400 | * Similarly for qemu_ld/st slow path helpers. | |
5401 | * We must re-implement tcg_gen_callN and tcg_reg_alloc_call simultaneously, | |
5402 | * using only the provided backend tcg_out_* functions. | |
5403 | */ | |
5404 | ||
5405 | static int tcg_out_helper_stk_ofs(TCGType type, unsigned slot) | |
5406 | { | |
5407 | int ofs = arg_slot_stk_ofs(slot); | |
5408 | ||
5409 | /* | |
5410 | * Each stack slot is TCG_TARGET_LONG_BITS. If the host does not | |
5411 | * require extension to uint64_t, adjust the address for uint32_t. | |
5412 | */ | |
5413 | if (HOST_BIG_ENDIAN && | |
5414 | TCG_TARGET_REG_BITS == 64 && | |
5415 | type == TCG_TYPE_I32) { | |
5416 | ofs += 4; | |
5417 | } | |
5418 | return ofs; | |
5419 | } | |
5420 | ||
8d314041 RH |
5421 | static void tcg_out_helper_load_slots(TCGContext *s, |
5422 | unsigned nmov, TCGMovExtend *mov, | |
5423 | const TCGLdstHelperParam *parm) | |
8429a1ca | 5424 | { |
8d314041 | 5425 | unsigned i; |
2462e30e RH |
5426 | TCGReg dst3; |
5427 | ||
8d314041 RH |
5428 | /* |
5429 | * Start from the end, storing to the stack first. | |
5430 | * This frees those registers, so we need not consider overlap. | |
5431 | */ | |
5432 | for (i = nmov; i-- > 0; ) { | |
5433 | unsigned slot = mov[i].dst; | |
5434 | ||
5435 | if (arg_slot_reg_p(slot)) { | |
5436 | goto found_reg; | |
5437 | } | |
5438 | ||
5439 | TCGReg src = mov[i].src; | |
5440 | TCGType dst_type = mov[i].dst_type; | |
5441 | MemOp dst_mo = dst_type == TCG_TYPE_I32 ? MO_32 : MO_64; | |
5442 | ||
5443 | /* The argument is going onto the stack; extend into scratch. */ | |
5444 | if ((mov[i].src_ext & MO_SIZE) != dst_mo) { | |
5445 | tcg_debug_assert(parm->ntmp != 0); | |
5446 | mov[i].dst = src = parm->tmp[0]; | |
5447 | tcg_out_movext1(s, &mov[i]); | |
5448 | } | |
5449 | ||
5450 | tcg_out_st(s, dst_type, src, TCG_REG_CALL_STACK, | |
5451 | tcg_out_helper_stk_ofs(dst_type, slot)); | |
5452 | } | |
5453 | return; | |
5454 | ||
5455 | found_reg: | |
5456 | /* | |
5457 | * The remaining arguments are in registers. | |
5458 | * Convert slot numbers to argument registers. | |
5459 | */ | |
5460 | nmov = i + 1; | |
5461 | for (i = 0; i < nmov; ++i) { | |
5462 | mov[i].dst = tcg_target_call_iarg_regs[mov[i].dst]; | |
5463 | } | |
5464 | ||
8429a1ca | 5465 | switch (nmov) { |
2462e30e | 5466 | case 4: |
8429a1ca | 5467 | /* The backend must have provided enough temps for the worst case. */ |
2462e30e | 5468 | tcg_debug_assert(parm->ntmp >= 2); |
8429a1ca | 5469 | |
2462e30e RH |
5470 | dst3 = mov[3].dst; |
5471 | for (unsigned j = 0; j < 3; ++j) { | |
5472 | if (dst3 == mov[j].src) { | |
5473 | /* | |
5474 | * Conflict. Copy the source to a temporary, perform the | |
5475 | * remaining moves, then the extension from our scratch | |
5476 | * on the way out. | |
5477 | */ | |
5478 | TCGReg scratch = parm->tmp[1]; | |
8429a1ca | 5479 | |
2462e30e RH |
5480 | tcg_out_mov(s, mov[3].src_type, scratch, mov[3].src); |
5481 | tcg_out_movext3(s, mov, mov + 1, mov + 2, parm->tmp[0]); | |
5482 | tcg_out_movext1_new_src(s, &mov[3], scratch); | |
5483 | break; | |
8429a1ca | 5484 | } |
8429a1ca | 5485 | } |
8429a1ca | 5486 | |
2462e30e RH |
5487 | /* No conflicts: perform this move and continue. */ |
5488 | tcg_out_movext1(s, &mov[3]); | |
5489 | /* fall through */ | |
5490 | ||
5491 | case 3: | |
5492 | tcg_out_movext3(s, mov, mov + 1, mov + 2, | |
5493 | parm->ntmp ? parm->tmp[0] : -1); | |
5494 | break; | |
8429a1ca | 5495 | case 2: |
2462e30e RH |
5496 | tcg_out_movext2(s, mov, mov + 1, |
5497 | parm->ntmp ? parm->tmp[0] : -1); | |
5498 | break; | |
8429a1ca RH |
5499 | case 1: |
5500 | tcg_out_movext1(s, mov); | |
2462e30e RH |
5501 | break; |
5502 | default: | |
8429a1ca RH |
5503 | g_assert_not_reached(); |
5504 | } | |
5505 | } | |
5506 | ||
8429a1ca RH |
5507 | static void tcg_out_helper_load_imm(TCGContext *s, unsigned slot, |
5508 | TCGType type, tcg_target_long imm, | |
5509 | const TCGLdstHelperParam *parm) | |
5510 | { | |
5511 | if (arg_slot_reg_p(slot)) { | |
5512 | tcg_out_movi(s, type, tcg_target_call_iarg_regs[slot], imm); | |
5513 | } else { | |
5514 | int ofs = tcg_out_helper_stk_ofs(type, slot); | |
5515 | if (!tcg_out_sti(s, type, imm, TCG_REG_CALL_STACK, ofs)) { | |
5516 | tcg_debug_assert(parm->ntmp != 0); | |
5517 | tcg_out_movi(s, type, parm->tmp[0], imm); | |
5518 | tcg_out_st(s, type, parm->tmp[0], TCG_REG_CALL_STACK, ofs); | |
5519 | } | |
5520 | } | |
5521 | } | |
5522 | ||
5523 | static void tcg_out_helper_load_common_args(TCGContext *s, | |
5524 | const TCGLabelQemuLdst *ldst, | |
5525 | const TCGLdstHelperParam *parm, | |
5526 | const TCGHelperInfo *info, | |
5527 | unsigned next_arg) | |
5528 | { | |
5529 | TCGMovExtend ptr_mov = { | |
5530 | .dst_type = TCG_TYPE_PTR, | |
5531 | .src_type = TCG_TYPE_PTR, | |
5532 | .src_ext = sizeof(void *) == 4 ? MO_32 : MO_64 | |
5533 | }; | |
5534 | const TCGCallArgumentLoc *loc = &info->in[0]; | |
5535 | TCGType type; | |
5536 | unsigned slot; | |
5537 | tcg_target_ulong imm; | |
5538 | ||
5539 | /* | |
5540 | * Handle env, which is always first. | |
5541 | */ | |
5542 | ptr_mov.dst = loc->arg_slot; | |
5543 | ptr_mov.src = TCG_AREG0; | |
5544 | tcg_out_helper_load_slots(s, 1, &ptr_mov, parm); | |
5545 | ||
5546 | /* | |
5547 | * Handle oi. | |
5548 | */ | |
5549 | imm = ldst->oi; | |
5550 | loc = &info->in[next_arg]; | |
5551 | type = TCG_TYPE_I32; | |
5552 | switch (loc->kind) { | |
5553 | case TCG_CALL_ARG_NORMAL: | |
5554 | break; | |
5555 | case TCG_CALL_ARG_EXTEND_U: | |
5556 | case TCG_CALL_ARG_EXTEND_S: | |
5557 | /* No extension required for MemOpIdx. */ | |
5558 | tcg_debug_assert(imm <= INT32_MAX); | |
5559 | type = TCG_TYPE_REG; | |
5560 | break; | |
5561 | default: | |
5562 | g_assert_not_reached(); | |
5563 | } | |
5564 | tcg_out_helper_load_imm(s, loc->arg_slot, type, imm, parm); | |
5565 | next_arg++; | |
5566 | ||
5567 | /* | |
5568 | * Handle ra. | |
5569 | */ | |
5570 | loc = &info->in[next_arg]; | |
5571 | slot = loc->arg_slot; | |
5572 | if (parm->ra_gen) { | |
5573 | int arg_reg = -1; | |
5574 | TCGReg ra_reg; | |
5575 | ||
5576 | if (arg_slot_reg_p(slot)) { | |
5577 | arg_reg = tcg_target_call_iarg_regs[slot]; | |
5578 | } | |
5579 | ra_reg = parm->ra_gen(s, ldst, arg_reg); | |
5580 | ||
5581 | ptr_mov.dst = slot; | |
5582 | ptr_mov.src = ra_reg; | |
5583 | tcg_out_helper_load_slots(s, 1, &ptr_mov, parm); | |
5584 | } else { | |
5585 | imm = (uintptr_t)ldst->raddr; | |
5586 | tcg_out_helper_load_imm(s, slot, TCG_TYPE_PTR, imm, parm); | |
5587 | } | |
5588 | } | |
5589 | ||
5590 | static unsigned tcg_out_helper_add_mov(TCGMovExtend *mov, | |
5591 | const TCGCallArgumentLoc *loc, | |
5592 | TCGType dst_type, TCGType src_type, | |
5593 | TCGReg lo, TCGReg hi) | |
5594 | { | |
ebebea53 RH |
5595 | MemOp reg_mo; |
5596 | ||
8429a1ca RH |
5597 | if (dst_type <= TCG_TYPE_REG) { |
5598 | MemOp src_ext; | |
5599 | ||
5600 | switch (loc->kind) { | |
5601 | case TCG_CALL_ARG_NORMAL: | |
5602 | src_ext = src_type == TCG_TYPE_I32 ? MO_32 : MO_64; | |
5603 | break; | |
5604 | case TCG_CALL_ARG_EXTEND_U: | |
5605 | dst_type = TCG_TYPE_REG; | |
5606 | src_ext = MO_UL; | |
5607 | break; | |
5608 | case TCG_CALL_ARG_EXTEND_S: | |
5609 | dst_type = TCG_TYPE_REG; | |
5610 | src_ext = MO_SL; | |
5611 | break; | |
5612 | default: | |
5613 | g_assert_not_reached(); | |
5614 | } | |
5615 | ||
5616 | mov[0].dst = loc->arg_slot; | |
5617 | mov[0].dst_type = dst_type; | |
5618 | mov[0].src = lo; | |
5619 | mov[0].src_type = src_type; | |
5620 | mov[0].src_ext = src_ext; | |
5621 | return 1; | |
5622 | } | |
5623 | ||
ebebea53 RH |
5624 | if (TCG_TARGET_REG_BITS == 32) { |
5625 | assert(dst_type == TCG_TYPE_I64); | |
5626 | reg_mo = MO_32; | |
5627 | } else { | |
5628 | assert(dst_type == TCG_TYPE_I128); | |
5629 | reg_mo = MO_64; | |
5630 | } | |
8429a1ca RH |
5631 | |
5632 | mov[0].dst = loc[HOST_BIG_ENDIAN].arg_slot; | |
5633 | mov[0].src = lo; | |
ebebea53 RH |
5634 | mov[0].dst_type = TCG_TYPE_REG; |
5635 | mov[0].src_type = TCG_TYPE_REG; | |
5636 | mov[0].src_ext = reg_mo; | |
8429a1ca RH |
5637 | |
5638 | mov[1].dst = loc[!HOST_BIG_ENDIAN].arg_slot; | |
5639 | mov[1].src = hi; | |
ebebea53 RH |
5640 | mov[1].dst_type = TCG_TYPE_REG; |
5641 | mov[1].src_type = TCG_TYPE_REG; | |
5642 | mov[1].src_ext = reg_mo; | |
8429a1ca RH |
5643 | |
5644 | return 2; | |
5645 | } | |
5646 | ||
5647 | static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst, | |
5648 | const TCGLdstHelperParam *parm) | |
5649 | { | |
5650 | const TCGHelperInfo *info; | |
5651 | const TCGCallArgumentLoc *loc; | |
5652 | TCGMovExtend mov[2]; | |
5653 | unsigned next_arg, nmov; | |
5654 | MemOp mop = get_memop(ldst->oi); | |
5655 | ||
5656 | switch (mop & MO_SIZE) { | |
5657 | case MO_8: | |
5658 | case MO_16: | |
5659 | case MO_32: | |
5660 | info = &info_helper_ld32_mmu; | |
5661 | break; | |
5662 | case MO_64: | |
5663 | info = &info_helper_ld64_mmu; | |
5664 | break; | |
ebebea53 RH |
5665 | case MO_128: |
5666 | info = &info_helper_ld128_mmu; | |
5667 | break; | |
8429a1ca RH |
5668 | default: |
5669 | g_assert_not_reached(); | |
5670 | } | |
5671 | ||
5672 | /* Defer env argument. */ | |
5673 | next_arg = 1; | |
5674 | ||
5675 | loc = &info->in[next_arg]; | |
c31e5fa4 | 5676 | if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I32) { |
24e46e6c RH |
5677 | /* |
5678 | * 32-bit host with 32-bit guest: zero-extend the guest address | |
5679 | * to 64-bits for the helper by storing the low part, then | |
5680 | * load a zero for the high part. | |
5681 | */ | |
5682 | tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN, | |
5683 | TCG_TYPE_I32, TCG_TYPE_I32, | |
5684 | ldst->addrlo_reg, -1); | |
5685 | tcg_out_helper_load_slots(s, 1, mov, parm); | |
8429a1ca | 5686 | |
24e46e6c RH |
5687 | tcg_out_helper_load_imm(s, loc[!HOST_BIG_ENDIAN].arg_slot, |
5688 | TCG_TYPE_I32, 0, parm); | |
5689 | next_arg += 2; | |
c31e5fa4 RH |
5690 | } else { |
5691 | nmov = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type, | |
5692 | ldst->addrlo_reg, ldst->addrhi_reg); | |
5693 | tcg_out_helper_load_slots(s, nmov, mov, parm); | |
5694 | next_arg += nmov; | |
24e46e6c | 5695 | } |
8429a1ca | 5696 | |
ebebea53 RH |
5697 | switch (info->out_kind) { |
5698 | case TCG_CALL_RET_NORMAL: | |
5699 | case TCG_CALL_RET_BY_VEC: | |
5700 | break; | |
5701 | case TCG_CALL_RET_BY_REF: | |
5702 | /* | |
5703 | * The return reference is in the first argument slot. | |
5704 | * We need memory in which to return: re-use the top of stack. | |
5705 | */ | |
5706 | { | |
5707 | int ofs_slot0 = TCG_TARGET_CALL_STACK_OFFSET; | |
5708 | ||
5709 | if (arg_slot_reg_p(0)) { | |
5710 | tcg_out_addi_ptr(s, tcg_target_call_iarg_regs[0], | |
5711 | TCG_REG_CALL_STACK, ofs_slot0); | |
5712 | } else { | |
5713 | tcg_debug_assert(parm->ntmp != 0); | |
5714 | tcg_out_addi_ptr(s, parm->tmp[0], | |
5715 | TCG_REG_CALL_STACK, ofs_slot0); | |
5716 | tcg_out_st(s, TCG_TYPE_PTR, parm->tmp[0], | |
5717 | TCG_REG_CALL_STACK, ofs_slot0); | |
5718 | } | |
5719 | } | |
5720 | break; | |
5721 | default: | |
5722 | g_assert_not_reached(); | |
5723 | } | |
8429a1ca RH |
5724 | |
5725 | tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); | |
5726 | } | |
5727 | ||
5728 | static void tcg_out_ld_helper_ret(TCGContext *s, const TCGLabelQemuLdst *ldst, | |
5729 | bool load_sign, | |
5730 | const TCGLdstHelperParam *parm) | |
5731 | { | |
ebebea53 | 5732 | MemOp mop = get_memop(ldst->oi); |
8429a1ca | 5733 | TCGMovExtend mov[2]; |
ebebea53 | 5734 | int ofs_slot0; |
8429a1ca | 5735 | |
ebebea53 RH |
5736 | switch (ldst->type) { |
5737 | case TCG_TYPE_I64: | |
5738 | if (TCG_TARGET_REG_BITS == 32) { | |
5739 | break; | |
5740 | } | |
5741 | /* fall through */ | |
8429a1ca | 5742 | |
ebebea53 | 5743 | case TCG_TYPE_I32: |
8429a1ca RH |
5744 | mov[0].dst = ldst->datalo_reg; |
5745 | mov[0].src = tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, 0); | |
5746 | mov[0].dst_type = ldst->type; | |
5747 | mov[0].src_type = TCG_TYPE_REG; | |
5748 | ||
5749 | /* | |
5750 | * If load_sign, then we allowed the helper to perform the | |
5751 | * appropriate sign extension to tcg_target_ulong, and all | |
5752 | * we need now is a plain move. | |
5753 | * | |
5754 | * If they do not, then we expect the relevant extension | |
5755 | * instruction to be no more expensive than a move, and | |
5756 | * we thus save the icache etc by only using one of two | |
5757 | * helper functions. | |
5758 | */ | |
5759 | if (load_sign || !(mop & MO_SIGN)) { | |
5760 | if (TCG_TARGET_REG_BITS == 32 || ldst->type == TCG_TYPE_I32) { | |
5761 | mov[0].src_ext = MO_32; | |
5762 | } else { | |
5763 | mov[0].src_ext = MO_64; | |
5764 | } | |
5765 | } else { | |
5766 | mov[0].src_ext = mop & MO_SSIZE; | |
5767 | } | |
5768 | tcg_out_movext1(s, mov); | |
ebebea53 | 5769 | return; |
8429a1ca | 5770 | |
ebebea53 RH |
5771 | case TCG_TYPE_I128: |
5772 | tcg_debug_assert(TCG_TARGET_REG_BITS == 64); | |
5773 | ofs_slot0 = TCG_TARGET_CALL_STACK_OFFSET; | |
5774 | switch (TCG_TARGET_CALL_RET_I128) { | |
5775 | case TCG_CALL_RET_NORMAL: | |
5776 | break; | |
5777 | case TCG_CALL_RET_BY_VEC: | |
5778 | tcg_out_st(s, TCG_TYPE_V128, | |
5779 | tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0), | |
5780 | TCG_REG_CALL_STACK, ofs_slot0); | |
5781 | /* fall through */ | |
5782 | case TCG_CALL_RET_BY_REF: | |
5783 | tcg_out_ld(s, TCG_TYPE_I64, ldst->datalo_reg, | |
5784 | TCG_REG_CALL_STACK, ofs_slot0 + 8 * HOST_BIG_ENDIAN); | |
5785 | tcg_out_ld(s, TCG_TYPE_I64, ldst->datahi_reg, | |
5786 | TCG_REG_CALL_STACK, ofs_slot0 + 8 * !HOST_BIG_ENDIAN); | |
5787 | return; | |
5788 | default: | |
5789 | g_assert_not_reached(); | |
5790 | } | |
5791 | break; | |
8429a1ca | 5792 | |
ebebea53 RH |
5793 | default: |
5794 | g_assert_not_reached(); | |
8429a1ca | 5795 | } |
ebebea53 RH |
5796 | |
5797 | mov[0].dst = ldst->datalo_reg; | |
5798 | mov[0].src = | |
5799 | tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, HOST_BIG_ENDIAN); | |
723d3a27 RH |
5800 | mov[0].dst_type = TCG_TYPE_REG; |
5801 | mov[0].src_type = TCG_TYPE_REG; | |
ebebea53 RH |
5802 | mov[0].src_ext = TCG_TARGET_REG_BITS == 32 ? MO_32 : MO_64; |
5803 | ||
5804 | mov[1].dst = ldst->datahi_reg; | |
5805 | mov[1].src = | |
5806 | tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, !HOST_BIG_ENDIAN); | |
5807 | mov[1].dst_type = TCG_TYPE_REG; | |
5808 | mov[1].src_type = TCG_TYPE_REG; | |
5809 | mov[1].src_ext = TCG_TARGET_REG_BITS == 32 ? MO_32 : MO_64; | |
5810 | ||
5811 | tcg_out_movext2(s, mov, mov + 1, parm->ntmp ? parm->tmp[0] : -1); | |
8429a1ca RH |
5812 | } |
5813 | ||
5814 | static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst, | |
5815 | const TCGLdstHelperParam *parm) | |
5816 | { | |
5817 | const TCGHelperInfo *info; | |
5818 | const TCGCallArgumentLoc *loc; | |
5819 | TCGMovExtend mov[4]; | |
5820 | TCGType data_type; | |
5821 | unsigned next_arg, nmov, n; | |
5822 | MemOp mop = get_memop(ldst->oi); | |
5823 | ||
5824 | switch (mop & MO_SIZE) { | |
5825 | case MO_8: | |
5826 | case MO_16: | |
5827 | case MO_32: | |
5828 | info = &info_helper_st32_mmu; | |
5829 | data_type = TCG_TYPE_I32; | |
5830 | break; | |
5831 | case MO_64: | |
5832 | info = &info_helper_st64_mmu; | |
5833 | data_type = TCG_TYPE_I64; | |
5834 | break; | |
ebebea53 RH |
5835 | case MO_128: |
5836 | info = &info_helper_st128_mmu; | |
5837 | data_type = TCG_TYPE_I128; | |
5838 | break; | |
8429a1ca RH |
5839 | default: |
5840 | g_assert_not_reached(); | |
5841 | } | |
5842 | ||
5843 | /* Defer env argument. */ | |
5844 | next_arg = 1; | |
5845 | nmov = 0; | |
5846 | ||
5847 | /* Handle addr argument. */ | |
5848 | loc = &info->in[next_arg]; | |
c31e5fa4 | 5849 | if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I32) { |
24e46e6c RH |
5850 | /* |
5851 | * 32-bit host with 32-bit guest: zero-extend the guest address | |
5852 | * to 64-bits for the helper by storing the low part. Later, | |
5853 | * after we have processed the register inputs, we will load a | |
5854 | * zero for the high part. | |
5855 | */ | |
5856 | tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN, | |
5857 | TCG_TYPE_I32, TCG_TYPE_I32, | |
5858 | ldst->addrlo_reg, -1); | |
5859 | next_arg += 2; | |
5860 | nmov += 1; | |
c31e5fa4 RH |
5861 | } else { |
5862 | n = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, s->addr_type, | |
5863 | ldst->addrlo_reg, ldst->addrhi_reg); | |
5864 | next_arg += n; | |
5865 | nmov += n; | |
24e46e6c | 5866 | } |
8429a1ca RH |
5867 | |
5868 | /* Handle data argument. */ | |
5869 | loc = &info->in[next_arg]; | |
ebebea53 RH |
5870 | switch (loc->kind) { |
5871 | case TCG_CALL_ARG_NORMAL: | |
5872 | case TCG_CALL_ARG_EXTEND_U: | |
5873 | case TCG_CALL_ARG_EXTEND_S: | |
5874 | n = tcg_out_helper_add_mov(mov + nmov, loc, data_type, ldst->type, | |
5875 | ldst->datalo_reg, ldst->datahi_reg); | |
5876 | next_arg += n; | |
5877 | nmov += n; | |
5878 | tcg_out_helper_load_slots(s, nmov, mov, parm); | |
5879 | break; | |
5880 | ||
5881 | case TCG_CALL_ARG_BY_REF: | |
5882 | tcg_debug_assert(TCG_TARGET_REG_BITS == 64); | |
5883 | tcg_debug_assert(data_type == TCG_TYPE_I128); | |
5884 | tcg_out_st(s, TCG_TYPE_I64, | |
5885 | HOST_BIG_ENDIAN ? ldst->datahi_reg : ldst->datalo_reg, | |
5886 | TCG_REG_CALL_STACK, arg_slot_stk_ofs(loc[0].ref_slot)); | |
5887 | tcg_out_st(s, TCG_TYPE_I64, | |
5888 | HOST_BIG_ENDIAN ? ldst->datalo_reg : ldst->datahi_reg, | |
5889 | TCG_REG_CALL_STACK, arg_slot_stk_ofs(loc[1].ref_slot)); | |
5890 | ||
5891 | tcg_out_helper_load_slots(s, nmov, mov, parm); | |
5892 | ||
5893 | if (arg_slot_reg_p(loc->arg_slot)) { | |
5894 | tcg_out_addi_ptr(s, tcg_target_call_iarg_regs[loc->arg_slot], | |
5895 | TCG_REG_CALL_STACK, | |
5896 | arg_slot_stk_ofs(loc->ref_slot)); | |
5897 | } else { | |
5898 | tcg_debug_assert(parm->ntmp != 0); | |
5899 | tcg_out_addi_ptr(s, parm->tmp[0], TCG_REG_CALL_STACK, | |
5900 | arg_slot_stk_ofs(loc->ref_slot)); | |
5901 | tcg_out_st(s, TCG_TYPE_PTR, parm->tmp[0], | |
5902 | TCG_REG_CALL_STACK, arg_slot_stk_ofs(loc->arg_slot)); | |
5903 | } | |
5904 | next_arg += 2; | |
5905 | break; | |
5906 | ||
5907 | default: | |
5908 | g_assert_not_reached(); | |
5909 | } | |
8429a1ca | 5910 | |
c31e5fa4 RH |
5911 | if (TCG_TARGET_REG_BITS == 32 && s->addr_type == TCG_TYPE_I32) { |
5912 | /* Zero extend the address by loading a zero for the high part. */ | |
24e46e6c RH |
5913 | loc = &info->in[1 + !HOST_BIG_ENDIAN]; |
5914 | tcg_out_helper_load_imm(s, loc->arg_slot, TCG_TYPE_I32, 0, parm); | |
5915 | } | |
5916 | ||
8429a1ca RH |
5917 | tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); |
5918 | } | |
5919 | ||
b6a7f3e0 | 5920 | void tcg_dump_op_count(GString *buf) |
246ae24d | 5921 | { |
b6a7f3e0 | 5922 | g_string_append_printf(buf, "[TCG profiler not compiled]\n"); |
246ae24d | 5923 | } |
72fd2efb | 5924 | |
76cef4b2 | 5925 | int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start) |
c896fe29 | 5926 | { |
747bd69d | 5927 | int i, start_words, num_insns; |
15fa08f8 | 5928 | TCGOp *op; |
c896fe29 | 5929 | |
d977e1c2 | 5930 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) |
fbf59aad | 5931 | && qemu_log_in_addr_range(pc_start))) { |
c60f599b | 5932 | FILE *logfile = qemu_log_trylock(); |
78b54858 RH |
5933 | if (logfile) { |
5934 | fprintf(logfile, "OP:\n"); | |
b7a83ff8 | 5935 | tcg_dump_ops(s, logfile, false); |
78b54858 RH |
5936 | fprintf(logfile, "\n"); |
5937 | qemu_log_unlock(logfile); | |
5938 | } | |
c896fe29 | 5939 | } |
c896fe29 | 5940 | |
bef16ab4 RH |
5941 | #ifdef CONFIG_DEBUG_TCG |
5942 | /* Ensure all labels referenced have been emitted. */ | |
5943 | { | |
5944 | TCGLabel *l; | |
5945 | bool error = false; | |
5946 | ||
5947 | QSIMPLEQ_FOREACH(l, &s->labels, next) { | |
f85b1fc4 | 5948 | if (unlikely(!l->present) && !QSIMPLEQ_EMPTY(&l->branches)) { |
bef16ab4 RH |
5949 | qemu_log_mask(CPU_LOG_TB_OP, |
5950 | "$L%d referenced but not present.\n", l->id); | |
5951 | error = true; | |
5952 | } | |
5953 | } | |
5954 | assert(!error); | |
5955 | } | |
5956 | #endif | |
5957 | ||
c45cb8bb | 5958 | tcg_optimize(s); |
8f2e8c07 | 5959 | |
b4fc67c7 | 5960 | reachable_code_pass(s); |
874b8574 | 5961 | liveness_pass_0(s); |
b83eabea | 5962 | liveness_pass_1(s); |
5a18407f | 5963 | |
b83eabea | 5964 | if (s->nb_indirects > 0) { |
b83eabea | 5965 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) |
fbf59aad | 5966 | && qemu_log_in_addr_range(pc_start))) { |
c60f599b | 5967 | FILE *logfile = qemu_log_trylock(); |
78b54858 RH |
5968 | if (logfile) { |
5969 | fprintf(logfile, "OP before indirect lowering:\n"); | |
b7a83ff8 | 5970 | tcg_dump_ops(s, logfile, false); |
78b54858 RH |
5971 | fprintf(logfile, "\n"); |
5972 | qemu_log_unlock(logfile); | |
5973 | } | |
b83eabea | 5974 | } |
645e3a81 | 5975 | |
b83eabea RH |
5976 | /* Replace indirect temps with direct temps. */ |
5977 | if (liveness_pass_2(s)) { | |
5978 | /* If changes were made, re-run liveness. */ | |
5979 | liveness_pass_1(s); | |
5a18407f RH |
5980 | } |
5981 | } | |
c5cc28ff | 5982 | |
d977e1c2 | 5983 | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) |
fbf59aad | 5984 | && qemu_log_in_addr_range(pc_start))) { |
c60f599b | 5985 | FILE *logfile = qemu_log_trylock(); |
78b54858 RH |
5986 | if (logfile) { |
5987 | fprintf(logfile, "OP after optimization and liveness analysis:\n"); | |
b7a83ff8 | 5988 | tcg_dump_ops(s, logfile, true); |
78b54858 RH |
5989 | fprintf(logfile, "\n"); |
5990 | qemu_log_unlock(logfile); | |
5991 | } | |
c896fe29 | 5992 | } |
c896fe29 | 5993 | |
35abb009 | 5994 | /* Initialize goto_tb jump offsets. */ |
3a50f424 RH |
5995 | tb->jmp_reset_offset[0] = TB_JMP_OFFSET_INVALID; |
5996 | tb->jmp_reset_offset[1] = TB_JMP_OFFSET_INVALID; | |
9da6079b RH |
5997 | tb->jmp_insn_offset[0] = TB_JMP_OFFSET_INVALID; |
5998 | tb->jmp_insn_offset[1] = TB_JMP_OFFSET_INVALID; | |
35abb009 | 5999 | |
c896fe29 FB |
6000 | tcg_reg_alloc_start(s); |
6001 | ||
db0c51a3 RH |
6002 | /* |
6003 | * Reset the buffer pointers when restarting after overflow. | |
6004 | * TODO: Move this into translate-all.c with the rest of the | |
6005 | * buffer management. Having only this done here is confusing. | |
6006 | */ | |
6007 | s->code_buf = tcg_splitwx_to_rw(tb->tc.ptr); | |
6008 | s->code_ptr = s->code_buf; | |
c896fe29 | 6009 | |
659ef5cb | 6010 | #ifdef TCG_TARGET_NEED_LDST_LABELS |
6001f772 | 6011 | QSIMPLEQ_INIT(&s->ldst_labels); |
659ef5cb | 6012 | #endif |
57a26946 RH |
6013 | #ifdef TCG_TARGET_NEED_POOL_LABELS |
6014 | s->pool_labels = NULL; | |
6015 | #endif | |
9ecefc84 | 6016 | |
747bd69d RH |
6017 | start_words = s->insn_start_words; |
6018 | s->gen_insn_data = | |
6019 | tcg_malloc(sizeof(uint64_t) * s->gen_tb->icount * start_words); | |
6020 | ||
9358fbbf RH |
6021 | tcg_out_tb_start(s); |
6022 | ||
fca8a500 | 6023 | num_insns = -1; |
15fa08f8 | 6024 | QTAILQ_FOREACH(op, &s->ops, link) { |
c45cb8bb | 6025 | TCGOpcode opc = op->opc; |
b3db8758 | 6026 | |
c45cb8bb | 6027 | switch (opc) { |
c896fe29 | 6028 | case INDEX_op_mov_i32: |
c896fe29 | 6029 | case INDEX_op_mov_i64: |
d2fd745f | 6030 | case INDEX_op_mov_vec: |
dd186292 | 6031 | tcg_reg_alloc_mov(s, op); |
c896fe29 | 6032 | break; |
bab1671f RH |
6033 | case INDEX_op_dup_vec: |
6034 | tcg_reg_alloc_dup(s, op); | |
6035 | break; | |
765b842a | 6036 | case INDEX_op_insn_start: |
fca8a500 | 6037 | if (num_insns >= 0) { |
9f754620 RH |
6038 | size_t off = tcg_current_code_size(s); |
6039 | s->gen_insn_end_off[num_insns] = off; | |
6040 | /* Assert that we do not overflow our stored offset. */ | |
6041 | assert(s->gen_insn_end_off[num_insns] == off); | |
fca8a500 RH |
6042 | } |
6043 | num_insns++; | |
747bd69d RH |
6044 | for (i = 0; i < start_words; ++i) { |
6045 | s->gen_insn_data[num_insns * start_words + i] = | |
c9ad8d27 | 6046 | tcg_get_insn_start_param(op, i); |
bad729e2 | 6047 | } |
c896fe29 | 6048 | break; |
5ff9d6a4 | 6049 | case INDEX_op_discard: |
43439139 | 6050 | temp_dead(s, arg_temp(op->args[0])); |
5ff9d6a4 | 6051 | break; |
c896fe29 | 6052 | case INDEX_op_set_label: |
e8996ee0 | 6053 | tcg_reg_alloc_bb_end(s, s->reserved_regs); |
92ab8e7d | 6054 | tcg_out_label(s, arg_label(op->args[0])); |
c896fe29 FB |
6055 | break; |
6056 | case INDEX_op_call: | |
dd186292 | 6057 | tcg_reg_alloc_call(s, op); |
c45cb8bb | 6058 | break; |
b55a8d9d RH |
6059 | case INDEX_op_exit_tb: |
6060 | tcg_out_exit_tb(s, op->args[0]); | |
6061 | break; | |
cf7d6b8e RH |
6062 | case INDEX_op_goto_tb: |
6063 | tcg_out_goto_tb(s, op->args[0]); | |
6064 | break; | |
efe86b21 RH |
6065 | case INDEX_op_dup2_vec: |
6066 | if (tcg_reg_alloc_dup2(s, op)) { | |
6067 | break; | |
6068 | } | |
6069 | /* fall through */ | |
c896fe29 | 6070 | default: |
25c4d9cc | 6071 | /* Sanity check that we've not introduced any unhandled opcodes. */ |
be0f34b5 | 6072 | tcg_debug_assert(tcg_op_supported(opc)); |
c896fe29 FB |
6073 | /* Note: in order to speed up the code, it would be much |
6074 | faster to have specialized register allocator functions for | |
6075 | some common argument patterns */ | |
dd186292 | 6076 | tcg_reg_alloc_op(s, op); |
c896fe29 FB |
6077 | break; |
6078 | } | |
b125f9dc RH |
6079 | /* Test for (pending) buffer overflow. The assumption is that any |
6080 | one operation beginning below the high water mark cannot overrun | |
6081 | the buffer completely. Thus we can test for overflow after | |
6082 | generating code without having to check during generation. */ | |
644da9b3 | 6083 | if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) { |
b125f9dc RH |
6084 | return -1; |
6085 | } | |
6e6c4efe RH |
6086 | /* Test for TB overflow, as seen by gen_insn_end_off. */ |
6087 | if (unlikely(tcg_current_code_size(s) > UINT16_MAX)) { | |
6088 | return -2; | |
6089 | } | |
c896fe29 | 6090 | } |
747bd69d | 6091 | tcg_debug_assert(num_insns + 1 == s->gen_tb->icount); |
fca8a500 | 6092 | s->gen_insn_end_off[num_insns] = tcg_current_code_size(s); |
c45cb8bb | 6093 | |
b76f0d8c | 6094 | /* Generate TB finalization at the end of block */ |
659ef5cb | 6095 | #ifdef TCG_TARGET_NEED_LDST_LABELS |
aeee05f5 RH |
6096 | i = tcg_out_ldst_finalize(s); |
6097 | if (i < 0) { | |
6098 | return i; | |
23dceda6 | 6099 | } |
659ef5cb | 6100 | #endif |
57a26946 | 6101 | #ifdef TCG_TARGET_NEED_POOL_LABELS |
1768987b RH |
6102 | i = tcg_out_pool_finalize(s); |
6103 | if (i < 0) { | |
6104 | return i; | |
57a26946 RH |
6105 | } |
6106 | #endif | |
7ecd02a0 RH |
6107 | if (!tcg_resolve_relocs(s)) { |
6108 | return -2; | |
6109 | } | |
c896fe29 | 6110 | |
df5d2b16 | 6111 | #ifndef CONFIG_TCG_INTERPRETER |
c896fe29 | 6112 | /* flush instruction cache */ |
db0c51a3 RH |
6113 | flush_idcache_range((uintptr_t)tcg_splitwx_to_rx(s->code_buf), |
6114 | (uintptr_t)s->code_buf, | |
1da8de39 | 6115 | tcg_ptr_byte_diff(s->code_ptr, s->code_buf)); |
df5d2b16 | 6116 | #endif |
2aeabc08 | 6117 | |
1813e175 | 6118 | return tcg_current_code_size(s); |
c896fe29 FB |
6119 | } |
6120 | ||
3a841ab5 | 6121 | void tcg_dump_info(GString *buf) |
a23a9ec6 | 6122 | { |
3a841ab5 | 6123 | g_string_append_printf(buf, "[TCG profiler not compiled]\n"); |
a23a9ec6 | 6124 | } |
813da627 RH |
6125 | |
6126 | #ifdef ELF_HOST_MACHINE | |
5872bbf2 RH |
6127 | /* In order to use this feature, the backend needs to do three things: |
6128 | ||
6129 | (1) Define ELF_HOST_MACHINE to indicate both what value to | |
6130 | put into the ELF image and to indicate support for the feature. | |
6131 | ||
6132 | (2) Define tcg_register_jit. This should create a buffer containing | |
6133 | the contents of a .debug_frame section that describes the post- | |
6134 | prologue unwind info for the tcg machine. | |
6135 | ||
6136 | (3) Call tcg_register_jit_int, with the constructed .debug_frame. | |
6137 | */ | |
813da627 RH |
6138 | |
6139 | /* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */ | |
6140 | typedef enum { | |
6141 | JIT_NOACTION = 0, | |
6142 | JIT_REGISTER_FN, | |
6143 | JIT_UNREGISTER_FN | |
6144 | } jit_actions_t; | |
6145 | ||
6146 | struct jit_code_entry { | |
6147 | struct jit_code_entry *next_entry; | |
6148 | struct jit_code_entry *prev_entry; | |
6149 | const void *symfile_addr; | |
6150 | uint64_t symfile_size; | |
6151 | }; | |
6152 | ||
6153 | struct jit_descriptor { | |
6154 | uint32_t version; | |
6155 | uint32_t action_flag; | |
6156 | struct jit_code_entry *relevant_entry; | |
6157 | struct jit_code_entry *first_entry; | |
6158 | }; | |
6159 | ||
6160 | void __jit_debug_register_code(void) __attribute__((noinline)); | |
6161 | void __jit_debug_register_code(void) | |
6162 | { | |
6163 | asm(""); | |
6164 | } | |
6165 | ||
6166 | /* Must statically initialize the version, because GDB may check | |
6167 | the version before we can set it. */ | |
6168 | struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 }; | |
6169 | ||
6170 | /* End GDB interface. */ | |
6171 | ||
6172 | static int find_string(const char *strtab, const char *str) | |
6173 | { | |
6174 | const char *p = strtab + 1; | |
6175 | ||
6176 | while (1) { | |
6177 | if (strcmp(p, str) == 0) { | |
6178 | return p - strtab; | |
6179 | } | |
6180 | p += strlen(p) + 1; | |
6181 | } | |
6182 | } | |
6183 | ||
755bf9e5 | 6184 | static void tcg_register_jit_int(const void *buf_ptr, size_t buf_size, |
2c90784a RH |
6185 | const void *debug_frame, |
6186 | size_t debug_frame_size) | |
813da627 | 6187 | { |
5872bbf2 RH |
6188 | struct __attribute__((packed)) DebugInfo { |
6189 | uint32_t len; | |
6190 | uint16_t version; | |
6191 | uint32_t abbrev; | |
6192 | uint8_t ptr_size; | |
6193 | uint8_t cu_die; | |
6194 | uint16_t cu_lang; | |
6195 | uintptr_t cu_low_pc; | |
6196 | uintptr_t cu_high_pc; | |
6197 | uint8_t fn_die; | |
6198 | char fn_name[16]; | |
6199 | uintptr_t fn_low_pc; | |
6200 | uintptr_t fn_high_pc; | |
6201 | uint8_t cu_eoc; | |
6202 | }; | |
813da627 RH |
6203 | |
6204 | struct ElfImage { | |
6205 | ElfW(Ehdr) ehdr; | |
6206 | ElfW(Phdr) phdr; | |
5872bbf2 RH |
6207 | ElfW(Shdr) shdr[7]; |
6208 | ElfW(Sym) sym[2]; | |
6209 | struct DebugInfo di; | |
6210 | uint8_t da[24]; | |
6211 | char str[80]; | |
6212 | }; | |
6213 | ||
6214 | struct ElfImage *img; | |
6215 | ||
6216 | static const struct ElfImage img_template = { | |
6217 | .ehdr = { | |
6218 | .e_ident[EI_MAG0] = ELFMAG0, | |
6219 | .e_ident[EI_MAG1] = ELFMAG1, | |
6220 | .e_ident[EI_MAG2] = ELFMAG2, | |
6221 | .e_ident[EI_MAG3] = ELFMAG3, | |
6222 | .e_ident[EI_CLASS] = ELF_CLASS, | |
6223 | .e_ident[EI_DATA] = ELF_DATA, | |
6224 | .e_ident[EI_VERSION] = EV_CURRENT, | |
6225 | .e_type = ET_EXEC, | |
6226 | .e_machine = ELF_HOST_MACHINE, | |
6227 | .e_version = EV_CURRENT, | |
6228 | .e_phoff = offsetof(struct ElfImage, phdr), | |
6229 | .e_shoff = offsetof(struct ElfImage, shdr), | |
6230 | .e_ehsize = sizeof(ElfW(Shdr)), | |
6231 | .e_phentsize = sizeof(ElfW(Phdr)), | |
6232 | .e_phnum = 1, | |
6233 | .e_shentsize = sizeof(ElfW(Shdr)), | |
6234 | .e_shnum = ARRAY_SIZE(img->shdr), | |
6235 | .e_shstrndx = ARRAY_SIZE(img->shdr) - 1, | |
abbb3eae RH |
6236 | #ifdef ELF_HOST_FLAGS |
6237 | .e_flags = ELF_HOST_FLAGS, | |
6238 | #endif | |
6239 | #ifdef ELF_OSABI | |
6240 | .e_ident[EI_OSABI] = ELF_OSABI, | |
6241 | #endif | |
5872bbf2 RH |
6242 | }, |
6243 | .phdr = { | |
6244 | .p_type = PT_LOAD, | |
6245 | .p_flags = PF_X, | |
6246 | }, | |
6247 | .shdr = { | |
6248 | [0] = { .sh_type = SHT_NULL }, | |
6249 | /* Trick: The contents of code_gen_buffer are not present in | |
6250 | this fake ELF file; that got allocated elsewhere. Therefore | |
6251 | we mark .text as SHT_NOBITS (similar to .bss) so that readers | |
6252 | will not look for contents. We can record any address. */ | |
6253 | [1] = { /* .text */ | |
6254 | .sh_type = SHT_NOBITS, | |
6255 | .sh_flags = SHF_EXECINSTR | SHF_ALLOC, | |
6256 | }, | |
6257 | [2] = { /* .debug_info */ | |
6258 | .sh_type = SHT_PROGBITS, | |
6259 | .sh_offset = offsetof(struct ElfImage, di), | |
6260 | .sh_size = sizeof(struct DebugInfo), | |
6261 | }, | |
6262 | [3] = { /* .debug_abbrev */ | |
6263 | .sh_type = SHT_PROGBITS, | |
6264 | .sh_offset = offsetof(struct ElfImage, da), | |
6265 | .sh_size = sizeof(img->da), | |
6266 | }, | |
6267 | [4] = { /* .debug_frame */ | |
6268 | .sh_type = SHT_PROGBITS, | |
6269 | .sh_offset = sizeof(struct ElfImage), | |
6270 | }, | |
6271 | [5] = { /* .symtab */ | |
6272 | .sh_type = SHT_SYMTAB, | |
6273 | .sh_offset = offsetof(struct ElfImage, sym), | |
6274 | .sh_size = sizeof(img->sym), | |
6275 | .sh_info = 1, | |
6276 | .sh_link = ARRAY_SIZE(img->shdr) - 1, | |
6277 | .sh_entsize = sizeof(ElfW(Sym)), | |
6278 | }, | |
6279 | [6] = { /* .strtab */ | |
6280 | .sh_type = SHT_STRTAB, | |
6281 | .sh_offset = offsetof(struct ElfImage, str), | |
6282 | .sh_size = sizeof(img->str), | |
6283 | } | |
6284 | }, | |
6285 | .sym = { | |
6286 | [1] = { /* code_gen_buffer */ | |
6287 | .st_info = ELF_ST_INFO(STB_GLOBAL, STT_FUNC), | |
6288 | .st_shndx = 1, | |
6289 | } | |
6290 | }, | |
6291 | .di = { | |
6292 | .len = sizeof(struct DebugInfo) - 4, | |
6293 | .version = 2, | |
6294 | .ptr_size = sizeof(void *), | |
6295 | .cu_die = 1, | |
6296 | .cu_lang = 0x8001, /* DW_LANG_Mips_Assembler */ | |
6297 | .fn_die = 2, | |
6298 | .fn_name = "code_gen_buffer" | |
6299 | }, | |
6300 | .da = { | |
6301 | 1, /* abbrev number (the cu) */ | |
6302 | 0x11, 1, /* DW_TAG_compile_unit, has children */ | |
6303 | 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */ | |
6304 | 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ | |
6305 | 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ | |
6306 | 0, 0, /* end of abbrev */ | |
6307 | 2, /* abbrev number (the fn) */ | |
6308 | 0x2e, 0, /* DW_TAG_subprogram, no children */ | |
6309 | 0x3, 0x8, /* DW_AT_name, DW_FORM_string */ | |
6310 | 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */ | |
6311 | 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */ | |
6312 | 0, 0, /* end of abbrev */ | |
6313 | 0 /* no more abbrev */ | |
6314 | }, | |
6315 | .str = "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0" | |
6316 | ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer", | |
813da627 RH |
6317 | }; |
6318 | ||
6319 | /* We only need a single jit entry; statically allocate it. */ | |
6320 | static struct jit_code_entry one_entry; | |
6321 | ||
5872bbf2 | 6322 | uintptr_t buf = (uintptr_t)buf_ptr; |
813da627 | 6323 | size_t img_size = sizeof(struct ElfImage) + debug_frame_size; |
2c90784a | 6324 | DebugFrameHeader *dfh; |
813da627 | 6325 | |
5872bbf2 RH |
6326 | img = g_malloc(img_size); |
6327 | *img = img_template; | |
813da627 | 6328 | |
5872bbf2 RH |
6329 | img->phdr.p_vaddr = buf; |
6330 | img->phdr.p_paddr = buf; | |
6331 | img->phdr.p_memsz = buf_size; | |
813da627 | 6332 | |
813da627 | 6333 | img->shdr[1].sh_name = find_string(img->str, ".text"); |
5872bbf2 | 6334 | img->shdr[1].sh_addr = buf; |
813da627 RH |
6335 | img->shdr[1].sh_size = buf_size; |
6336 | ||
5872bbf2 RH |
6337 | img->shdr[2].sh_name = find_string(img->str, ".debug_info"); |
6338 | img->shdr[3].sh_name = find_string(img->str, ".debug_abbrev"); | |
6339 | ||
6340 | img->shdr[4].sh_name = find_string(img->str, ".debug_frame"); | |
6341 | img->shdr[4].sh_size = debug_frame_size; | |
6342 | ||
6343 | img->shdr[5].sh_name = find_string(img->str, ".symtab"); | |
6344 | img->shdr[6].sh_name = find_string(img->str, ".strtab"); | |
6345 | ||
6346 | img->sym[1].st_name = find_string(img->str, "code_gen_buffer"); | |
6347 | img->sym[1].st_value = buf; | |
6348 | img->sym[1].st_size = buf_size; | |
813da627 | 6349 | |
5872bbf2 | 6350 | img->di.cu_low_pc = buf; |
45aba097 | 6351 | img->di.cu_high_pc = buf + buf_size; |
5872bbf2 | 6352 | img->di.fn_low_pc = buf; |
45aba097 | 6353 | img->di.fn_high_pc = buf + buf_size; |
813da627 | 6354 | |
2c90784a RH |
6355 | dfh = (DebugFrameHeader *)(img + 1); |
6356 | memcpy(dfh, debug_frame, debug_frame_size); | |
6357 | dfh->fde.func_start = buf; | |
6358 | dfh->fde.func_len = buf_size; | |
6359 | ||
813da627 RH |
6360 | #ifdef DEBUG_JIT |
6361 | /* Enable this block to be able to debug the ELF image file creation. | |
6362 | One can use readelf, objdump, or other inspection utilities. */ | |
6363 | { | |
eb6b2edf BM |
6364 | g_autofree char *jit = g_strdup_printf("%s/qemu.jit", g_get_tmp_dir()); |
6365 | FILE *f = fopen(jit, "w+b"); | |
813da627 | 6366 | if (f) { |
5872bbf2 | 6367 | if (fwrite(img, img_size, 1, f) != img_size) { |
813da627 RH |
6368 | /* Avoid stupid unused return value warning for fwrite. */ |
6369 | } | |
6370 | fclose(f); | |
6371 | } | |
6372 | } | |
6373 | #endif | |
6374 | ||
6375 | one_entry.symfile_addr = img; | |
6376 | one_entry.symfile_size = img_size; | |
6377 | ||
6378 | __jit_debug_descriptor.action_flag = JIT_REGISTER_FN; | |
6379 | __jit_debug_descriptor.relevant_entry = &one_entry; | |
6380 | __jit_debug_descriptor.first_entry = &one_entry; | |
6381 | __jit_debug_register_code(); | |
6382 | } | |
6383 | #else | |
5872bbf2 RH |
6384 | /* No support for the feature. Provide the entry point expected by exec.c, |
6385 | and implement the internal function we declared earlier. */ | |
813da627 | 6386 | |
755bf9e5 | 6387 | static void tcg_register_jit_int(const void *buf, size_t size, |
2c90784a RH |
6388 | const void *debug_frame, |
6389 | size_t debug_frame_size) | |
813da627 RH |
6390 | { |
6391 | } | |
6392 | ||
755bf9e5 | 6393 | void tcg_register_jit(const void *buf, size_t buf_size) |
813da627 RH |
6394 | { |
6395 | } | |
6396 | #endif /* ELF_HOST_MACHINE */ | |
db432672 RH |
6397 | |
6398 | #if !TCG_TARGET_MAYBE_vec | |
6399 | void tcg_expand_vec_op(TCGOpcode o, TCGType t, unsigned e, TCGArg a0, ...) | |
6400 | { | |
6401 | g_assert_not_reached(); | |
6402 | } | |
6403 | #endif |