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CommitLineData
c896fe29
FB
1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
c896fe29
FB
25/* define it to use liveness analysis (better code) */
26#define USE_LIVENESS_ANALYSIS
8f2e8c07 27#define USE_TCG_OPTIMIZATIONS
c896fe29 28
cca82982
AJ
29#include "config.h"
30
813da627
RH
31/* Define to jump the ELF file used to communicate with GDB. */
32#undef DEBUG_JIT
33
a6c6f76c 34#if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
cca82982
AJ
35/* define it to suppress various consistency checks (faster) */
36#define NDEBUG
37#endif
38
ca10f867 39#include "qemu-common.h"
1de7afc9
PB
40#include "qemu/host-utils.h"
41#include "qemu/timer.h"
c896fe29 42
c5d3c498 43/* Note: the long term plan is to reduce the dependencies on the QEMU
c896fe29
FB
44 CPU definitions. Currently they are used for qemu_ld/st
45 instructions */
46#define NO_CPU_IO_DEFS
47#include "cpu.h"
c896fe29
FB
48
49#include "tcg-op.h"
813da627 50
edee2579 51#if UINTPTR_MAX == UINT32_MAX
813da627 52# define ELF_CLASS ELFCLASS32
edee2579
RH
53#else
54# define ELF_CLASS ELFCLASS64
813da627
RH
55#endif
56#ifdef HOST_WORDS_BIGENDIAN
57# define ELF_DATA ELFDATA2MSB
58#else
59# define ELF_DATA ELFDATA2LSB
60#endif
61
c896fe29
FB
62#include "elf.h"
63
c0ad3001 64/* Forward declarations for functions declared in tcg-target.c and used here. */
e4d58b41
RH
65static void tcg_target_init(TCGContext *s);
66static void tcg_target_qemu_prologue(TCGContext *s);
1813e175 67static void patch_reloc(tcg_insn_unit *code_ptr, int type,
2ba7fae2 68 intptr_t value, intptr_t addend);
c896fe29 69
497a22eb
RH
70/* The CIE and FDE header definitions will be common to all hosts. */
71typedef struct {
72 uint32_t len __attribute__((aligned((sizeof(void *)))));
73 uint32_t id;
74 uint8_t version;
75 char augmentation[1];
76 uint8_t code_align;
77 uint8_t data_align;
78 uint8_t return_column;
79} DebugFrameCIE;
80
81typedef struct QEMU_PACKED {
82 uint32_t len __attribute__((aligned((sizeof(void *)))));
83 uint32_t cie_offset;
edee2579
RH
84 uintptr_t func_start;
85 uintptr_t func_len;
497a22eb
RH
86} DebugFrameFDEHeader;
87
2c90784a
RH
88typedef struct QEMU_PACKED {
89 DebugFrameCIE cie;
90 DebugFrameFDEHeader fde;
91} DebugFrameHeader;
92
813da627 93static void tcg_register_jit_int(void *buf, size_t size,
2c90784a
RH
94 const void *debug_frame,
95 size_t debug_frame_size)
813da627
RH
96 __attribute__((unused));
97
c0ad3001
SW
98/* Forward declarations for functions declared and used in tcg-target.c. */
99static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str);
2a534aff 100static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
a05b5b9b 101 intptr_t arg2);
2a534aff 102static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg);
c0ad3001 103static void tcg_out_movi(TCGContext *s, TCGType type,
2a534aff 104 TCGReg ret, tcg_target_long arg);
c0ad3001
SW
105static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
106 const int *const_args);
2a534aff 107static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
a05b5b9b 108 intptr_t arg2);
cf066674 109static void tcg_out_call(TCGContext *s, tcg_insn_unit *target);
f6c6afc1 110static int tcg_target_const_match(tcg_target_long val, TCGType type,
c0ad3001 111 const TCGArgConstraint *arg_ct);
9ecefc84
RH
112static void tcg_out_tb_init(TCGContext *s);
113static void tcg_out_tb_finalize(TCGContext *s);
114
c0ad3001 115
8399ad59 116TCGOpDef tcg_op_defs[] = {
0e2029a0 117#define DEF(s, oargs, iargs, cargs, flags) { #s, oargs, iargs, cargs, iargs + oargs + cargs, flags },
c896fe29
FB
118#include "tcg-opc.h"
119#undef DEF
c896fe29 120};
2a24374a 121const size_t tcg_op_defs_max = ARRAY_SIZE(tcg_op_defs);
c896fe29 122
b1d8e52e
BS
123static TCGRegSet tcg_target_available_regs[2];
124static TCGRegSet tcg_target_call_clobber_regs;
c896fe29 125
1813e175 126#if TCG_TARGET_INSN_UNIT_SIZE == 1
4196dca6 127static __attribute__((unused)) inline void tcg_out8(TCGContext *s, uint8_t v)
c896fe29
FB
128{
129 *s->code_ptr++ = v;
130}
131
4196dca6
PM
132static __attribute__((unused)) inline void tcg_patch8(tcg_insn_unit *p,
133 uint8_t v)
5c53bb81 134{
1813e175 135 *p = v;
5c53bb81 136}
1813e175 137#endif
5c53bb81 138
1813e175 139#if TCG_TARGET_INSN_UNIT_SIZE <= 2
4196dca6 140static __attribute__((unused)) inline void tcg_out16(TCGContext *s, uint16_t v)
c896fe29 141{
1813e175
RH
142 if (TCG_TARGET_INSN_UNIT_SIZE == 2) {
143 *s->code_ptr++ = v;
144 } else {
145 tcg_insn_unit *p = s->code_ptr;
146 memcpy(p, &v, sizeof(v));
147 s->code_ptr = p + (2 / TCG_TARGET_INSN_UNIT_SIZE);
148 }
c896fe29
FB
149}
150
4196dca6
PM
151static __attribute__((unused)) inline void tcg_patch16(tcg_insn_unit *p,
152 uint16_t v)
5c53bb81 153{
1813e175
RH
154 if (TCG_TARGET_INSN_UNIT_SIZE == 2) {
155 *p = v;
156 } else {
157 memcpy(p, &v, sizeof(v));
158 }
5c53bb81 159}
1813e175 160#endif
5c53bb81 161
1813e175 162#if TCG_TARGET_INSN_UNIT_SIZE <= 4
4196dca6 163static __attribute__((unused)) inline void tcg_out32(TCGContext *s, uint32_t v)
c896fe29 164{
1813e175
RH
165 if (TCG_TARGET_INSN_UNIT_SIZE == 4) {
166 *s->code_ptr++ = v;
167 } else {
168 tcg_insn_unit *p = s->code_ptr;
169 memcpy(p, &v, sizeof(v));
170 s->code_ptr = p + (4 / TCG_TARGET_INSN_UNIT_SIZE);
171 }
c896fe29
FB
172}
173
4196dca6
PM
174static __attribute__((unused)) inline void tcg_patch32(tcg_insn_unit *p,
175 uint32_t v)
5c53bb81 176{
1813e175
RH
177 if (TCG_TARGET_INSN_UNIT_SIZE == 4) {
178 *p = v;
179 } else {
180 memcpy(p, &v, sizeof(v));
181 }
5c53bb81 182}
1813e175 183#endif
5c53bb81 184
1813e175 185#if TCG_TARGET_INSN_UNIT_SIZE <= 8
4196dca6 186static __attribute__((unused)) inline void tcg_out64(TCGContext *s, uint64_t v)
ac26eb69 187{
1813e175
RH
188 if (TCG_TARGET_INSN_UNIT_SIZE == 8) {
189 *s->code_ptr++ = v;
190 } else {
191 tcg_insn_unit *p = s->code_ptr;
192 memcpy(p, &v, sizeof(v));
193 s->code_ptr = p + (8 / TCG_TARGET_INSN_UNIT_SIZE);
194 }
ac26eb69
RH
195}
196
4196dca6
PM
197static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p,
198 uint64_t v)
5c53bb81 199{
1813e175
RH
200 if (TCG_TARGET_INSN_UNIT_SIZE == 8) {
201 *p = v;
202 } else {
203 memcpy(p, &v, sizeof(v));
204 }
5c53bb81 205}
1813e175 206#endif
5c53bb81 207
c896fe29
FB
208/* label relocation processing */
209
1813e175 210static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type,
bec16311 211 TCGLabel *l, intptr_t addend)
c896fe29 212{
c896fe29
FB
213 TCGRelocation *r;
214
c896fe29 215 if (l->has_value) {
623e265c
PB
216 /* FIXME: This may break relocations on RISC targets that
217 modify instruction fields in place. The caller may not have
218 written the initial value. */
f54b3f92 219 patch_reloc(code_ptr, type, l->u.value, addend);
c896fe29
FB
220 } else {
221 /* add a new relocation entry */
222 r = tcg_malloc(sizeof(TCGRelocation));
223 r->type = type;
224 r->ptr = code_ptr;
225 r->addend = addend;
226 r->next = l->u.first_reloc;
227 l->u.first_reloc = r;
228 }
229}
230
bec16311 231static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr)
c896fe29 232{
2ba7fae2 233 intptr_t value = (intptr_t)ptr;
1813e175 234 TCGRelocation *r;
c896fe29 235
1813e175
RH
236 assert(!l->has_value);
237
238 for (r = l->u.first_reloc; r != NULL; r = r->next) {
f54b3f92 239 patch_reloc(r->ptr, r->type, value, r->addend);
c896fe29 240 }
1813e175 241
c896fe29 242 l->has_value = 1;
1813e175 243 l->u.value_ptr = ptr;
c896fe29
FB
244}
245
42a268c2 246TCGLabel *gen_new_label(void)
c896fe29
FB
247{
248 TCGContext *s = &tcg_ctx;
249 int idx;
250 TCGLabel *l;
251
252 if (s->nb_labels >= TCG_MAX_LABELS)
253 tcg_abort();
254 idx = s->nb_labels++;
255 l = &s->labels[idx];
256 l->has_value = 0;
257 l->u.first_reloc = NULL;
42a268c2
RH
258
259 return l;
c896fe29
FB
260}
261
262#include "tcg-target.c"
263
c896fe29
FB
264/* pool based memory allocation */
265void *tcg_malloc_internal(TCGContext *s, int size)
266{
267 TCGPool *p;
268 int pool_size;
269
270 if (size > TCG_POOL_CHUNK_SIZE) {
271 /* big malloc: insert a new pool (XXX: could optimize) */
7267c094 272 p = g_malloc(sizeof(TCGPool) + size);
c896fe29 273 p->size = size;
4055299e
KB
274 p->next = s->pool_first_large;
275 s->pool_first_large = p;
276 return p->data;
c896fe29
FB
277 } else {
278 p = s->pool_current;
279 if (!p) {
280 p = s->pool_first;
281 if (!p)
282 goto new_pool;
283 } else {
284 if (!p->next) {
285 new_pool:
286 pool_size = TCG_POOL_CHUNK_SIZE;
7267c094 287 p = g_malloc(sizeof(TCGPool) + pool_size);
c896fe29
FB
288 p->size = pool_size;
289 p->next = NULL;
290 if (s->pool_current)
291 s->pool_current->next = p;
292 else
293 s->pool_first = p;
294 } else {
295 p = p->next;
296 }
297 }
298 }
299 s->pool_current = p;
300 s->pool_cur = p->data + size;
301 s->pool_end = p->data + p->size;
302 return p->data;
303}
304
305void tcg_pool_reset(TCGContext *s)
306{
4055299e
KB
307 TCGPool *p, *t;
308 for (p = s->pool_first_large; p; p = t) {
309 t = p->next;
310 g_free(p);
311 }
312 s->pool_first_large = NULL;
c896fe29
FB
313 s->pool_cur = s->pool_end = NULL;
314 s->pool_current = NULL;
315}
316
100b5e01
RH
317typedef struct TCGHelperInfo {
318 void *func;
319 const char *name;
afb49896
RH
320 unsigned flags;
321 unsigned sizemask;
100b5e01
RH
322} TCGHelperInfo;
323
2ef6175a
RH
324#include "exec/helper-proto.h"
325
100b5e01 326static const TCGHelperInfo all_helpers[] = {
2ef6175a 327#include "exec/helper-tcg.h"
100b5e01
RH
328};
329
c896fe29
FB
330void tcg_context_init(TCGContext *s)
331{
100b5e01 332 int op, total_args, n, i;
c896fe29
FB
333 TCGOpDef *def;
334 TCGArgConstraint *args_ct;
335 int *sorted_args;
84fd9dd3 336 GHashTable *helper_table;
c896fe29
FB
337
338 memset(s, 0, sizeof(*s));
c896fe29
FB
339 s->nb_globals = 0;
340
341 /* Count total number of arguments and allocate the corresponding
342 space */
343 total_args = 0;
344 for(op = 0; op < NB_OPS; op++) {
345 def = &tcg_op_defs[op];
346 n = def->nb_iargs + def->nb_oargs;
347 total_args += n;
348 }
349
7267c094
AL
350 args_ct = g_malloc(sizeof(TCGArgConstraint) * total_args);
351 sorted_args = g_malloc(sizeof(int) * total_args);
c896fe29
FB
352
353 for(op = 0; op < NB_OPS; op++) {
354 def = &tcg_op_defs[op];
355 def->args_ct = args_ct;
356 def->sorted_args = sorted_args;
357 n = def->nb_iargs + def->nb_oargs;
358 sorted_args += n;
359 args_ct += n;
360 }
5cd8f621
RH
361
362 /* Register helpers. */
84fd9dd3
RH
363 /* Use g_direct_hash/equal for direct pointer comparisons on func. */
364 s->helpers = helper_table = g_hash_table_new(NULL, NULL);
365
100b5e01 366 for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) {
84fd9dd3 367 g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func,
72866e82 368 (gpointer)&all_helpers[i]);
100b5e01 369 }
5cd8f621 370
c896fe29 371 tcg_target_init(s);
9002ec79 372}
b03cce8e 373
9002ec79
RH
374void tcg_prologue_init(TCGContext *s)
375{
b03cce8e 376 /* init global prologue and epilogue */
0b0d3320 377 s->code_buf = s->code_gen_prologue;
b03cce8e
FB
378 s->code_ptr = s->code_buf;
379 tcg_target_qemu_prologue(s);
b93949ef 380 flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);
d6b64b2b
RH
381
382#ifdef DEBUG_DISAS
383 if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) {
1813e175 384 size_t size = tcg_current_code_size(s);
d6b64b2b
RH
385 qemu_log("PROLOGUE: [size=%zu]\n", size);
386 log_disas(s->code_buf, size);
387 qemu_log("\n");
388 qemu_log_flush();
389 }
390#endif
c896fe29
FB
391}
392
e2c6d1b4 393void tcg_set_frame(TCGContext *s, int reg, intptr_t start, intptr_t size)
c896fe29
FB
394{
395 s->frame_start = start;
396 s->frame_end = start + size;
397 s->frame_reg = reg;
398}
399
c896fe29
FB
400void tcg_func_start(TCGContext *s)
401{
402 tcg_pool_reset(s);
403 s->nb_temps = s->nb_globals;
0ec9eabc
RH
404
405 /* No temps have been previously allocated for size or locality. */
406 memset(s->free_temps, 0, sizeof(s->free_temps));
407
c896fe29
FB
408 s->nb_labels = 0;
409 s->current_frame_offset = s->frame_start;
410
0a209d4b
RH
411#ifdef CONFIG_DEBUG_TCG
412 s->goto_tb_issue_mask = 0;
413#endif
414
c45cb8bb
RH
415 s->gen_first_op_idx = 0;
416 s->gen_last_op_idx = -1;
417 s->gen_next_op_idx = 0;
418 s->gen_next_parm_idx = 0;
b76f0d8c 419
9ecefc84 420 s->be = tcg_malloc(sizeof(TCGBackendData));
c896fe29
FB
421}
422
423static inline void tcg_temp_alloc(TCGContext *s, int n)
424{
425 if (n > TCG_MAX_TEMPS)
426 tcg_abort();
427}
428
a7812ae4
PB
429static inline int tcg_global_reg_new_internal(TCGType type, int reg,
430 const char *name)
c896fe29
FB
431{
432 TCGContext *s = &tcg_ctx;
433 TCGTemp *ts;
434 int idx;
435
436#if TCG_TARGET_REG_BITS == 32
437 if (type != TCG_TYPE_I32)
438 tcg_abort();
439#endif
440 if (tcg_regset_test_reg(s->reserved_regs, reg))
441 tcg_abort();
442 idx = s->nb_globals;
443 tcg_temp_alloc(s, s->nb_globals + 1);
444 ts = &s->temps[s->nb_globals];
445 ts->base_type = type;
446 ts->type = type;
447 ts->fixed_reg = 1;
448 ts->reg = reg;
c896fe29
FB
449 ts->name = name;
450 s->nb_globals++;
451 tcg_regset_set_reg(s->reserved_regs, reg);
a7812ae4
PB
452 return idx;
453}
454
455TCGv_i32 tcg_global_reg_new_i32(int reg, const char *name)
456{
457 int idx;
458
459 idx = tcg_global_reg_new_internal(TCG_TYPE_I32, reg, name);
460 return MAKE_TCGV_I32(idx);
461}
462
463TCGv_i64 tcg_global_reg_new_i64(int reg, const char *name)
464{
465 int idx;
466
467 idx = tcg_global_reg_new_internal(TCG_TYPE_I64, reg, name);
468 return MAKE_TCGV_I64(idx);
c896fe29
FB
469}
470
a7812ae4 471static inline int tcg_global_mem_new_internal(TCGType type, int reg,
2f2f244d 472 intptr_t offset,
a7812ae4 473 const char *name)
c896fe29
FB
474{
475 TCGContext *s = &tcg_ctx;
476 TCGTemp *ts;
477 int idx;
478
479 idx = s->nb_globals;
480#if TCG_TARGET_REG_BITS == 32
481 if (type == TCG_TYPE_I64) {
482 char buf[64];
c588979b 483 tcg_temp_alloc(s, s->nb_globals + 2);
c896fe29
FB
484 ts = &s->temps[s->nb_globals];
485 ts->base_type = type;
486 ts->type = TCG_TYPE_I32;
487 ts->fixed_reg = 0;
488 ts->mem_allocated = 1;
489 ts->mem_reg = reg;
02eb19d0 490#ifdef HOST_WORDS_BIGENDIAN
c896fe29
FB
491 ts->mem_offset = offset + 4;
492#else
493 ts->mem_offset = offset;
494#endif
c896fe29
FB
495 pstrcpy(buf, sizeof(buf), name);
496 pstrcat(buf, sizeof(buf), "_0");
497 ts->name = strdup(buf);
498 ts++;
499
500 ts->base_type = type;
501 ts->type = TCG_TYPE_I32;
502 ts->fixed_reg = 0;
503 ts->mem_allocated = 1;
504 ts->mem_reg = reg;
02eb19d0 505#ifdef HOST_WORDS_BIGENDIAN
c896fe29
FB
506 ts->mem_offset = offset;
507#else
508 ts->mem_offset = offset + 4;
509#endif
c896fe29
FB
510 pstrcpy(buf, sizeof(buf), name);
511 pstrcat(buf, sizeof(buf), "_1");
512 ts->name = strdup(buf);
513
514 s->nb_globals += 2;
515 } else
516#endif
517 {
518 tcg_temp_alloc(s, s->nb_globals + 1);
519 ts = &s->temps[s->nb_globals];
520 ts->base_type = type;
521 ts->type = type;
522 ts->fixed_reg = 0;
523 ts->mem_allocated = 1;
524 ts->mem_reg = reg;
525 ts->mem_offset = offset;
c896fe29
FB
526 ts->name = name;
527 s->nb_globals++;
528 }
a7812ae4
PB
529 return idx;
530}
531
2f2f244d 532TCGv_i32 tcg_global_mem_new_i32(int reg, intptr_t offset, const char *name)
a7812ae4 533{
2f2f244d 534 int idx = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
a7812ae4
PB
535 return MAKE_TCGV_I32(idx);
536}
537
2f2f244d 538TCGv_i64 tcg_global_mem_new_i64(int reg, intptr_t offset, const char *name)
a7812ae4 539{
2f2f244d 540 int idx = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
a7812ae4 541 return MAKE_TCGV_I64(idx);
c896fe29
FB
542}
543
a7812ae4 544static inline int tcg_temp_new_internal(TCGType type, int temp_local)
c896fe29
FB
545{
546 TCGContext *s = &tcg_ctx;
547 TCGTemp *ts;
641d5fbe 548 int idx, k;
c896fe29 549
0ec9eabc
RH
550 k = type + (temp_local ? TCG_TYPE_COUNT : 0);
551 idx = find_first_bit(s->free_temps[k].l, TCG_MAX_TEMPS);
552 if (idx < TCG_MAX_TEMPS) {
553 /* There is already an available temp with the right type. */
554 clear_bit(idx, s->free_temps[k].l);
555
e8996ee0 556 ts = &s->temps[idx];
e8996ee0 557 ts->temp_allocated = 1;
0ec9eabc 558 assert(ts->base_type == type);
641d5fbe 559 assert(ts->temp_local == temp_local);
e8996ee0
FB
560 } else {
561 idx = s->nb_temps;
c896fe29 562#if TCG_TARGET_REG_BITS == 32
e8996ee0 563 if (type == TCG_TYPE_I64) {
8df1ca4b 564 tcg_temp_alloc(s, s->nb_temps + 2);
e8996ee0
FB
565 ts = &s->temps[s->nb_temps];
566 ts->base_type = type;
567 ts->type = TCG_TYPE_I32;
568 ts->temp_allocated = 1;
641d5fbe 569 ts->temp_local = temp_local;
e8996ee0
FB
570 ts->name = NULL;
571 ts++;
f6aa2f7d 572 ts->base_type = type;
e8996ee0
FB
573 ts->type = TCG_TYPE_I32;
574 ts->temp_allocated = 1;
641d5fbe 575 ts->temp_local = temp_local;
e8996ee0
FB
576 ts->name = NULL;
577 s->nb_temps += 2;
578 } else
c896fe29 579#endif
e8996ee0
FB
580 {
581 tcg_temp_alloc(s, s->nb_temps + 1);
582 ts = &s->temps[s->nb_temps];
583 ts->base_type = type;
584 ts->type = type;
585 ts->temp_allocated = 1;
641d5fbe 586 ts->temp_local = temp_local;
e8996ee0
FB
587 ts->name = NULL;
588 s->nb_temps++;
589 }
c896fe29 590 }
27bfd83c
PM
591
592#if defined(CONFIG_DEBUG_TCG)
593 s->temps_in_use++;
594#endif
a7812ae4 595 return idx;
c896fe29
FB
596}
597
a7812ae4
PB
598TCGv_i32 tcg_temp_new_internal_i32(int temp_local)
599{
600 int idx;
601
602 idx = tcg_temp_new_internal(TCG_TYPE_I32, temp_local);
603 return MAKE_TCGV_I32(idx);
604}
605
606TCGv_i64 tcg_temp_new_internal_i64(int temp_local)
607{
608 int idx;
609
610 idx = tcg_temp_new_internal(TCG_TYPE_I64, temp_local);
611 return MAKE_TCGV_I64(idx);
612}
613
0ec9eabc 614static void tcg_temp_free_internal(int idx)
c896fe29
FB
615{
616 TCGContext *s = &tcg_ctx;
617 TCGTemp *ts;
641d5fbe 618 int k;
c896fe29 619
27bfd83c
PM
620#if defined(CONFIG_DEBUG_TCG)
621 s->temps_in_use--;
622 if (s->temps_in_use < 0) {
623 fprintf(stderr, "More temporaries freed than allocated!\n");
624 }
625#endif
626
e8996ee0 627 assert(idx >= s->nb_globals && idx < s->nb_temps);
c896fe29 628 ts = &s->temps[idx];
e8996ee0
FB
629 assert(ts->temp_allocated != 0);
630 ts->temp_allocated = 0;
0ec9eabc 631
18d13fa2 632 k = ts->base_type + (ts->temp_local ? TCG_TYPE_COUNT : 0);
0ec9eabc 633 set_bit(idx, s->free_temps[k].l);
c896fe29
FB
634}
635
a7812ae4
PB
636void tcg_temp_free_i32(TCGv_i32 arg)
637{
638 tcg_temp_free_internal(GET_TCGV_I32(arg));
639}
640
641void tcg_temp_free_i64(TCGv_i64 arg)
642{
643 tcg_temp_free_internal(GET_TCGV_I64(arg));
644}
e8996ee0 645
a7812ae4 646TCGv_i32 tcg_const_i32(int32_t val)
c896fe29 647{
a7812ae4
PB
648 TCGv_i32 t0;
649 t0 = tcg_temp_new_i32();
e8996ee0
FB
650 tcg_gen_movi_i32(t0, val);
651 return t0;
652}
c896fe29 653
a7812ae4 654TCGv_i64 tcg_const_i64(int64_t val)
e8996ee0 655{
a7812ae4
PB
656 TCGv_i64 t0;
657 t0 = tcg_temp_new_i64();
e8996ee0
FB
658 tcg_gen_movi_i64(t0, val);
659 return t0;
c896fe29
FB
660}
661
a7812ae4 662TCGv_i32 tcg_const_local_i32(int32_t val)
bdffd4a9 663{
a7812ae4
PB
664 TCGv_i32 t0;
665 t0 = tcg_temp_local_new_i32();
bdffd4a9
AJ
666 tcg_gen_movi_i32(t0, val);
667 return t0;
668}
669
a7812ae4 670TCGv_i64 tcg_const_local_i64(int64_t val)
bdffd4a9 671{
a7812ae4
PB
672 TCGv_i64 t0;
673 t0 = tcg_temp_local_new_i64();
bdffd4a9
AJ
674 tcg_gen_movi_i64(t0, val);
675 return t0;
676}
677
27bfd83c
PM
678#if defined(CONFIG_DEBUG_TCG)
679void tcg_clear_temp_count(void)
680{
681 TCGContext *s = &tcg_ctx;
682 s->temps_in_use = 0;
683}
684
685int tcg_check_temp_count(void)
686{
687 TCGContext *s = &tcg_ctx;
688 if (s->temps_in_use) {
689 /* Clear the count so that we don't give another
690 * warning immediately next time around.
691 */
692 s->temps_in_use = 0;
693 return 1;
694 }
695 return 0;
696}
697#endif
698
39cf05d3
FB
699/* Note: we convert the 64 bit args to 32 bit and do some alignment
700 and endian swap. Maybe it would be better to do the alignment
701 and endian swap in tcg_reg_alloc_call(). */
bbb8a1b4
RH
702void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
703 int nargs, TCGArg *args)
c896fe29 704{
c45cb8bb 705 int i, real_args, nb_rets, pi, pi_first;
bbb8a1b4 706 unsigned sizemask, flags;
afb49896
RH
707 TCGHelperInfo *info;
708
709 info = g_hash_table_lookup(s->helpers, (gpointer)func);
bbb8a1b4
RH
710 flags = info->flags;
711 sizemask = info->sizemask;
2bece2c8 712
34b1a49c
RH
713#if defined(__sparc__) && !defined(__arch64__) \
714 && !defined(CONFIG_TCG_INTERPRETER)
715 /* We have 64-bit values in one register, but need to pass as two
716 separate parameters. Split them. */
717 int orig_sizemask = sizemask;
718 int orig_nargs = nargs;
719 TCGv_i64 retl, reth;
720
721 TCGV_UNUSED_I64(retl);
722 TCGV_UNUSED_I64(reth);
723 if (sizemask != 0) {
724 TCGArg *split_args = __builtin_alloca(sizeof(TCGArg) * nargs * 2);
725 for (i = real_args = 0; i < nargs; ++i) {
726 int is_64bit = sizemask & (1 << (i+1)*2);
727 if (is_64bit) {
728 TCGv_i64 orig = MAKE_TCGV_I64(args[i]);
729 TCGv_i32 h = tcg_temp_new_i32();
730 TCGv_i32 l = tcg_temp_new_i32();
731 tcg_gen_extr_i64_i32(l, h, orig);
732 split_args[real_args++] = GET_TCGV_I32(h);
733 split_args[real_args++] = GET_TCGV_I32(l);
734 } else {
735 split_args[real_args++] = args[i];
736 }
737 }
738 nargs = real_args;
739 args = split_args;
740 sizemask = 0;
741 }
742#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
2bece2c8
RH
743 for (i = 0; i < nargs; ++i) {
744 int is_64bit = sizemask & (1 << (i+1)*2);
745 int is_signed = sizemask & (2 << (i+1)*2);
746 if (!is_64bit) {
747 TCGv_i64 temp = tcg_temp_new_i64();
748 TCGv_i64 orig = MAKE_TCGV_I64(args[i]);
749 if (is_signed) {
750 tcg_gen_ext32s_i64(temp, orig);
751 } else {
752 tcg_gen_ext32u_i64(temp, orig);
753 }
754 args[i] = GET_TCGV_I64(temp);
755 }
756 }
757#endif /* TCG_TARGET_EXTEND_ARGS */
758
c45cb8bb 759 pi_first = pi = s->gen_next_parm_idx;
a7812ae4 760 if (ret != TCG_CALL_DUMMY_ARG) {
34b1a49c
RH
761#if defined(__sparc__) && !defined(__arch64__) \
762 && !defined(CONFIG_TCG_INTERPRETER)
763 if (orig_sizemask & 1) {
764 /* The 32-bit ABI is going to return the 64-bit value in
765 the %o0/%o1 register pair. Prepare for this by using
766 two return temporaries, and reassemble below. */
767 retl = tcg_temp_new_i64();
768 reth = tcg_temp_new_i64();
c45cb8bb
RH
769 s->gen_opparam_buf[pi++] = GET_TCGV_I64(reth);
770 s->gen_opparam_buf[pi++] = GET_TCGV_I64(retl);
34b1a49c
RH
771 nb_rets = 2;
772 } else {
c45cb8bb 773 s->gen_opparam_buf[pi++] = ret;
34b1a49c
RH
774 nb_rets = 1;
775 }
776#else
777 if (TCG_TARGET_REG_BITS < 64 && (sizemask & 1)) {
02eb19d0 778#ifdef HOST_WORDS_BIGENDIAN
c45cb8bb
RH
779 s->gen_opparam_buf[pi++] = ret + 1;
780 s->gen_opparam_buf[pi++] = ret;
39cf05d3 781#else
c45cb8bb
RH
782 s->gen_opparam_buf[pi++] = ret;
783 s->gen_opparam_buf[pi++] = ret + 1;
39cf05d3 784#endif
a7812ae4 785 nb_rets = 2;
34b1a49c 786 } else {
c45cb8bb 787 s->gen_opparam_buf[pi++] = ret;
a7812ae4 788 nb_rets = 1;
c896fe29 789 }
34b1a49c 790#endif
a7812ae4
PB
791 } else {
792 nb_rets = 0;
c896fe29 793 }
a7812ae4
PB
794 real_args = 0;
795 for (i = 0; i < nargs; i++) {
2bece2c8 796 int is_64bit = sizemask & (1 << (i+1)*2);
bbb8a1b4 797 if (TCG_TARGET_REG_BITS < 64 && is_64bit) {
39cf05d3
FB
798#ifdef TCG_TARGET_CALL_ALIGN_ARGS
799 /* some targets want aligned 64 bit args */
ebd486d5 800 if (real_args & 1) {
c45cb8bb 801 s->gen_opparam_buf[pi++] = TCG_CALL_DUMMY_ARG;
ebd486d5 802 real_args++;
39cf05d3
FB
803 }
804#endif
3f90f252
RH
805 /* If stack grows up, then we will be placing successive
806 arguments at lower addresses, which means we need to
807 reverse the order compared to how we would normally
808 treat either big or little-endian. For those arguments
809 that will wind up in registers, this still works for
810 HPPA (the only current STACK_GROWSUP target) since the
811 argument registers are *also* allocated in decreasing
812 order. If another such target is added, this logic may
813 have to get more complicated to differentiate between
814 stack arguments and register arguments. */
02eb19d0 815#if defined(HOST_WORDS_BIGENDIAN) != defined(TCG_TARGET_STACK_GROWSUP)
c45cb8bb
RH
816 s->gen_opparam_buf[pi++] = args[i] + 1;
817 s->gen_opparam_buf[pi++] = args[i];
c896fe29 818#else
c45cb8bb
RH
819 s->gen_opparam_buf[pi++] = args[i];
820 s->gen_opparam_buf[pi++] = args[i] + 1;
c896fe29 821#endif
a7812ae4 822 real_args += 2;
2bece2c8 823 continue;
c896fe29 824 }
2bece2c8 825
c45cb8bb 826 s->gen_opparam_buf[pi++] = args[i];
2bece2c8 827 real_args++;
c896fe29 828 }
c45cb8bb
RH
829 s->gen_opparam_buf[pi++] = (uintptr_t)func;
830 s->gen_opparam_buf[pi++] = flags;
a7812ae4 831
c45cb8bb
RH
832 i = s->gen_next_op_idx;
833 tcg_debug_assert(i < OPC_BUF_SIZE);
834 tcg_debug_assert(pi <= OPPARAM_BUF_SIZE);
a7812ae4 835
c45cb8bb
RH
836 /* Set links for sequential allocation during translation. */
837 s->gen_op_buf[i] = (TCGOp){
838 .opc = INDEX_op_call,
839 .callo = nb_rets,
840 .calli = real_args,
841 .args = pi_first,
842 .prev = i - 1,
843 .next = i + 1
844 };
845
846 /* Make sure the calli field didn't overflow. */
847 tcg_debug_assert(s->gen_op_buf[i].calli == real_args);
848
849 s->gen_last_op_idx = i;
850 s->gen_next_op_idx = i + 1;
851 s->gen_next_parm_idx = pi;
2bece2c8 852
34b1a49c
RH
853#if defined(__sparc__) && !defined(__arch64__) \
854 && !defined(CONFIG_TCG_INTERPRETER)
855 /* Free all of the parts we allocated above. */
856 for (i = real_args = 0; i < orig_nargs; ++i) {
857 int is_64bit = orig_sizemask & (1 << (i+1)*2);
858 if (is_64bit) {
859 TCGv_i32 h = MAKE_TCGV_I32(args[real_args++]);
860 TCGv_i32 l = MAKE_TCGV_I32(args[real_args++]);
861 tcg_temp_free_i32(h);
862 tcg_temp_free_i32(l);
863 } else {
864 real_args++;
865 }
866 }
867 if (orig_sizemask & 1) {
868 /* The 32-bit ABI returned two 32-bit pieces. Re-assemble them.
869 Note that describing these as TCGv_i64 eliminates an unnecessary
870 zero-extension that tcg_gen_concat_i32_i64 would create. */
871 tcg_gen_concat32_i64(MAKE_TCGV_I64(ret), retl, reth);
872 tcg_temp_free_i64(retl);
873 tcg_temp_free_i64(reth);
874 }
875#elif defined(TCG_TARGET_EXTEND_ARGS) && TCG_TARGET_REG_BITS == 64
2bece2c8
RH
876 for (i = 0; i < nargs; ++i) {
877 int is_64bit = sizemask & (1 << (i+1)*2);
878 if (!is_64bit) {
879 TCGv_i64 temp = MAKE_TCGV_I64(args[i]);
880 tcg_temp_free_i64(temp);
881 }
882 }
883#endif /* TCG_TARGET_EXTEND_ARGS */
c896fe29 884}
c896fe29 885
8fcd3692 886static void tcg_reg_alloc_start(TCGContext *s)
c896fe29
FB
887{
888 int i;
889 TCGTemp *ts;
890 for(i = 0; i < s->nb_globals; i++) {
891 ts = &s->temps[i];
892 if (ts->fixed_reg) {
893 ts->val_type = TEMP_VAL_REG;
894 } else {
895 ts->val_type = TEMP_VAL_MEM;
896 }
897 }
e8996ee0
FB
898 for(i = s->nb_globals; i < s->nb_temps; i++) {
899 ts = &s->temps[i];
7dfd8c6a
AJ
900 if (ts->temp_local) {
901 ts->val_type = TEMP_VAL_MEM;
902 } else {
903 ts->val_type = TEMP_VAL_DEAD;
904 }
e8996ee0
FB
905 ts->mem_allocated = 0;
906 ts->fixed_reg = 0;
907 }
c896fe29
FB
908 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
909 s->reg_to_temp[i] = -1;
910 }
911}
912
ac56dd48
PB
913static char *tcg_get_arg_str_idx(TCGContext *s, char *buf, int buf_size,
914 int idx)
c896fe29
FB
915{
916 TCGTemp *ts;
ac56dd48 917
7f6f0ae5 918 assert(idx >= 0 && idx < s->nb_temps);
ac56dd48
PB
919 ts = &s->temps[idx];
920 if (idx < s->nb_globals) {
921 pstrcpy(buf, buf_size, ts->name);
c896fe29 922 } else {
641d5fbe
FB
923 if (ts->temp_local)
924 snprintf(buf, buf_size, "loc%d", idx - s->nb_globals);
925 else
926 snprintf(buf, buf_size, "tmp%d", idx - s->nb_globals);
c896fe29
FB
927 }
928 return buf;
929}
930
a7812ae4
PB
931char *tcg_get_arg_str_i32(TCGContext *s, char *buf, int buf_size, TCGv_i32 arg)
932{
933 return tcg_get_arg_str_idx(s, buf, buf_size, GET_TCGV_I32(arg));
934}
935
936char *tcg_get_arg_str_i64(TCGContext *s, char *buf, int buf_size, TCGv_i64 arg)
ac56dd48 937{
a810a2de 938 return tcg_get_arg_str_idx(s, buf, buf_size, GET_TCGV_I64(arg));
ac56dd48
PB
939}
940
6e085f72
RH
941/* Find helper name. */
942static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val)
4dc81f28 943{
6e085f72
RH
944 const char *ret = NULL;
945 if (s->helpers) {
72866e82
RH
946 TCGHelperInfo *info = g_hash_table_lookup(s->helpers, (gpointer)val);
947 if (info) {
948 ret = info->name;
949 }
4dc81f28 950 }
6e085f72 951 return ret;
4dc81f28
FB
952}
953
f48f3ede
BS
954static const char * const cond_name[] =
955{
0aed257f
RH
956 [TCG_COND_NEVER] = "never",
957 [TCG_COND_ALWAYS] = "always",
f48f3ede
BS
958 [TCG_COND_EQ] = "eq",
959 [TCG_COND_NE] = "ne",
960 [TCG_COND_LT] = "lt",
961 [TCG_COND_GE] = "ge",
962 [TCG_COND_LE] = "le",
963 [TCG_COND_GT] = "gt",
964 [TCG_COND_LTU] = "ltu",
965 [TCG_COND_GEU] = "geu",
966 [TCG_COND_LEU] = "leu",
967 [TCG_COND_GTU] = "gtu"
968};
969
f713d6ad
RH
970static const char * const ldst_name[] =
971{
972 [MO_UB] = "ub",
973 [MO_SB] = "sb",
974 [MO_LEUW] = "leuw",
975 [MO_LESW] = "lesw",
976 [MO_LEUL] = "leul",
977 [MO_LESL] = "lesl",
978 [MO_LEQ] = "leq",
979 [MO_BEUW] = "beuw",
980 [MO_BESW] = "besw",
981 [MO_BEUL] = "beul",
982 [MO_BESL] = "besl",
983 [MO_BEQ] = "beq",
984};
985
eeacee4d 986void tcg_dump_ops(TCGContext *s)
c896fe29 987{
c896fe29 988 char buf[128];
c45cb8bb
RH
989 TCGOp *op;
990 int oi;
991
992 for (oi = s->gen_first_op_idx; oi >= 0; oi = op->next) {
993 int i, k, nb_oargs, nb_iargs, nb_cargs;
994 const TCGOpDef *def;
995 const TCGArg *args;
996 TCGOpcode c;
c896fe29 997
c45cb8bb
RH
998 op = &s->gen_op_buf[oi];
999 c = op->opc;
c896fe29 1000 def = &tcg_op_defs[c];
c45cb8bb
RH
1001 args = &s->gen_opparam_buf[op->args];
1002
7e4597d7
FB
1003 if (c == INDEX_op_debug_insn_start) {
1004 uint64_t pc;
1005#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1006 pc = ((uint64_t)args[1] << 32) | args[0];
1007#else
1008 pc = args[0];
1009#endif
c45cb8bb 1010 if (oi != s->gen_first_op_idx) {
eeacee4d
BS
1011 qemu_log("\n");
1012 }
1013 qemu_log(" ---- 0x%" PRIx64, pc);
7e4597d7 1014 } else if (c == INDEX_op_call) {
c896fe29 1015 /* variable number of arguments */
c45cb8bb
RH
1016 nb_oargs = op->callo;
1017 nb_iargs = op->calli;
c896fe29 1018 nb_cargs = def->nb_cargs;
c896fe29 1019
cf066674
RH
1020 /* function name, flags, out args */
1021 qemu_log(" %s %s,$0x%" TCG_PRIlx ",$%d", def->name,
1022 tcg_find_helper(s, args[nb_oargs + nb_iargs]),
1023 args[nb_oargs + nb_iargs + 1], nb_oargs);
1024 for (i = 0; i < nb_oargs; i++) {
1025 qemu_log(",%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
eeacee4d 1026 args[i]));
b03cce8e 1027 }
cf066674
RH
1028 for (i = 0; i < nb_iargs; i++) {
1029 TCGArg arg = args[nb_oargs + i];
1030 const char *t = "<dummy>";
1031 if (arg != TCG_CALL_DUMMY_ARG) {
1032 t = tcg_get_arg_str_idx(s, buf, sizeof(buf), arg);
eeacee4d 1033 }
cf066674 1034 qemu_log(",%s", t);
e8996ee0 1035 }
b03cce8e 1036 } else {
eeacee4d 1037 qemu_log(" %s ", def->name);
c45cb8bb
RH
1038
1039 nb_oargs = def->nb_oargs;
1040 nb_iargs = def->nb_iargs;
1041 nb_cargs = def->nb_cargs;
1042
b03cce8e 1043 k = 0;
c45cb8bb 1044 for (i = 0; i < nb_oargs; i++) {
eeacee4d
BS
1045 if (k != 0) {
1046 qemu_log(",");
1047 }
1048 qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
1049 args[k++]));
b03cce8e 1050 }
c45cb8bb 1051 for (i = 0; i < nb_iargs; i++) {
eeacee4d
BS
1052 if (k != 0) {
1053 qemu_log(",");
1054 }
1055 qemu_log("%s", tcg_get_arg_str_idx(s, buf, sizeof(buf),
1056 args[k++]));
b03cce8e 1057 }
be210acb
RH
1058 switch (c) {
1059 case INDEX_op_brcond_i32:
be210acb 1060 case INDEX_op_setcond_i32:
ffc5ea09 1061 case INDEX_op_movcond_i32:
ffc5ea09 1062 case INDEX_op_brcond2_i32:
be210acb 1063 case INDEX_op_setcond2_i32:
ffc5ea09 1064 case INDEX_op_brcond_i64:
be210acb 1065 case INDEX_op_setcond_i64:
ffc5ea09 1066 case INDEX_op_movcond_i64:
eeacee4d
BS
1067 if (args[k] < ARRAY_SIZE(cond_name) && cond_name[args[k]]) {
1068 qemu_log(",%s", cond_name[args[k++]]);
1069 } else {
1070 qemu_log(",$0x%" TCG_PRIlx, args[k++]);
1071 }
f48f3ede 1072 i = 1;
be210acb 1073 break;
f713d6ad
RH
1074 case INDEX_op_qemu_ld_i32:
1075 case INDEX_op_qemu_st_i32:
1076 case INDEX_op_qemu_ld_i64:
1077 case INDEX_op_qemu_st_i64:
1078 if (args[k] < ARRAY_SIZE(ldst_name) && ldst_name[args[k]]) {
1079 qemu_log(",%s", ldst_name[args[k++]]);
1080 } else {
1081 qemu_log(",$0x%" TCG_PRIlx, args[k++]);
1082 }
1083 i = 1;
1084 break;
be210acb 1085 default:
f48f3ede 1086 i = 0;
be210acb
RH
1087 break;
1088 }
c45cb8bb 1089 for (; i < nb_cargs; i++) {
eeacee4d
BS
1090 if (k != 0) {
1091 qemu_log(",");
1092 }
c45cb8bb 1093 qemu_log("$0x%" TCG_PRIlx, args[k++]);
b03cce8e 1094 }
c896fe29 1095 }
eeacee4d 1096 qemu_log("\n");
c896fe29
FB
1097 }
1098}
1099
1100/* we give more priority to constraints with less registers */
1101static int get_constraint_priority(const TCGOpDef *def, int k)
1102{
1103 const TCGArgConstraint *arg_ct;
1104
1105 int i, n;
1106 arg_ct = &def->args_ct[k];
1107 if (arg_ct->ct & TCG_CT_ALIAS) {
1108 /* an alias is equivalent to a single register */
1109 n = 1;
1110 } else {
1111 if (!(arg_ct->ct & TCG_CT_REG))
1112 return 0;
1113 n = 0;
1114 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
1115 if (tcg_regset_test_reg(arg_ct->u.regs, i))
1116 n++;
1117 }
1118 }
1119 return TCG_TARGET_NB_REGS - n + 1;
1120}
1121
1122/* sort from highest priority to lowest */
1123static void sort_constraints(TCGOpDef *def, int start, int n)
1124{
1125 int i, j, p1, p2, tmp;
1126
1127 for(i = 0; i < n; i++)
1128 def->sorted_args[start + i] = start + i;
1129 if (n <= 1)
1130 return;
1131 for(i = 0; i < n - 1; i++) {
1132 for(j = i + 1; j < n; j++) {
1133 p1 = get_constraint_priority(def, def->sorted_args[start + i]);
1134 p2 = get_constraint_priority(def, def->sorted_args[start + j]);
1135 if (p1 < p2) {
1136 tmp = def->sorted_args[start + i];
1137 def->sorted_args[start + i] = def->sorted_args[start + j];
1138 def->sorted_args[start + j] = tmp;
1139 }
1140 }
1141 }
1142}
1143
1144void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs)
1145{
a9751609 1146 TCGOpcode op;
c896fe29
FB
1147 TCGOpDef *def;
1148 const char *ct_str;
1149 int i, nb_args;
1150
1151 for(;;) {
a9751609 1152 if (tdefs->op == (TCGOpcode)-1)
c896fe29
FB
1153 break;
1154 op = tdefs->op;
c3b08d0e 1155 assert((unsigned)op < NB_OPS);
c896fe29 1156 def = &tcg_op_defs[op];
c68aaa18
SW
1157#if defined(CONFIG_DEBUG_TCG)
1158 /* Duplicate entry in op definitions? */
1159 assert(!def->used);
1160 def->used = 1;
1161#endif
c896fe29
FB
1162 nb_args = def->nb_iargs + def->nb_oargs;
1163 for(i = 0; i < nb_args; i++) {
1164 ct_str = tdefs->args_ct_str[i];
c68aaa18
SW
1165 /* Incomplete TCGTargetOpDef entry? */
1166 assert(ct_str != NULL);
c896fe29
FB
1167 tcg_regset_clear(def->args_ct[i].u.regs);
1168 def->args_ct[i].ct = 0;
1169 if (ct_str[0] >= '0' && ct_str[0] <= '9') {
1170 int oarg;
1171 oarg = ct_str[0] - '0';
1172 assert(oarg < def->nb_oargs);
1173 assert(def->args_ct[oarg].ct & TCG_CT_REG);
1174 /* TCG_CT_ALIAS is for the output arguments. The input
5ff9d6a4 1175 argument is tagged with TCG_CT_IALIAS. */
c896fe29 1176 def->args_ct[i] = def->args_ct[oarg];
5ff9d6a4
FB
1177 def->args_ct[oarg].ct = TCG_CT_ALIAS;
1178 def->args_ct[oarg].alias_index = i;
c896fe29 1179 def->args_ct[i].ct |= TCG_CT_IALIAS;
5ff9d6a4 1180 def->args_ct[i].alias_index = oarg;
c896fe29
FB
1181 } else {
1182 for(;;) {
1183 if (*ct_str == '\0')
1184 break;
1185 switch(*ct_str) {
1186 case 'i':
1187 def->args_ct[i].ct |= TCG_CT_CONST;
1188 ct_str++;
1189 break;
1190 default:
1191 if (target_parse_constraint(&def->args_ct[i], &ct_str) < 0) {
1192 fprintf(stderr, "Invalid constraint '%s' for arg %d of operation '%s'\n",
1193 ct_str, i, def->name);
1194 exit(1);
1195 }
1196 }
1197 }
1198 }
1199 }
1200
c68aaa18
SW
1201 /* TCGTargetOpDef entry with too much information? */
1202 assert(i == TCG_MAX_OP_ARGS || tdefs->args_ct_str[i] == NULL);
1203
c896fe29
FB
1204 /* sort the constraints (XXX: this is just an heuristic) */
1205 sort_constraints(def, 0, def->nb_oargs);
1206 sort_constraints(def, def->nb_oargs, def->nb_iargs);
1207
1208#if 0
1209 {
1210 int i;
1211
1212 printf("%s: sorted=", def->name);
1213 for(i = 0; i < def->nb_oargs + def->nb_iargs; i++)
1214 printf(" %d", def->sorted_args[i]);
1215 printf("\n");
1216 }
1217#endif
1218 tdefs++;
1219 }
1220
c68aaa18 1221#if defined(CONFIG_DEBUG_TCG)
a9751609 1222 i = 0;
c68aaa18 1223 for (op = 0; op < ARRAY_SIZE(tcg_op_defs); op++) {
f412c762 1224 const TCGOpDef *def = &tcg_op_defs[op];
c1a61f6c 1225 if (def->flags & TCG_OPF_NOT_PRESENT) {
c68aaa18 1226 /* Wrong entry in op definitions? */
f412c762
RH
1227 if (def->used) {
1228 fprintf(stderr, "Invalid op definition for %s\n", def->name);
a9751609
RH
1229 i = 1;
1230 }
c68aaa18
SW
1231 } else {
1232 /* Missing entry in op definitions? */
f412c762
RH
1233 if (!def->used) {
1234 fprintf(stderr, "Missing op definition for %s\n", def->name);
a9751609
RH
1235 i = 1;
1236 }
c68aaa18
SW
1237 }
1238 }
a9751609
RH
1239 if (i == 1) {
1240 tcg_abort();
1241 }
c68aaa18 1242#endif
c896fe29
FB
1243}
1244
0c627cdc
RH
1245void tcg_op_remove(TCGContext *s, TCGOp *op)
1246{
1247 int next = op->next;
1248 int prev = op->prev;
1249
1250 if (next >= 0) {
1251 s->gen_op_buf[next].prev = prev;
1252 } else {
1253 s->gen_last_op_idx = prev;
1254 }
1255 if (prev >= 0) {
1256 s->gen_op_buf[prev].next = next;
1257 } else {
1258 s->gen_first_op_idx = next;
1259 }
1260
15fc7daa 1261 memset(op, -1, sizeof(*op));
0c627cdc
RH
1262
1263#ifdef CONFIG_PROFILER
1264 s->del_op_count++;
1265#endif
1266}
1267
c896fe29 1268#ifdef USE_LIVENESS_ANALYSIS
9c43b68d
AJ
1269/* liveness analysis: end of function: all temps are dead, and globals
1270 should be in memory. */
1271static inline void tcg_la_func_end(TCGContext *s, uint8_t *dead_temps,
1272 uint8_t *mem_temps)
c896fe29 1273{
9c43b68d
AJ
1274 memset(dead_temps, 1, s->nb_temps);
1275 memset(mem_temps, 1, s->nb_globals);
1276 memset(mem_temps + s->nb_globals, 0, s->nb_temps - s->nb_globals);
c896fe29
FB
1277}
1278
9c43b68d
AJ
1279/* liveness analysis: end of basic block: all temps are dead, globals
1280 and local temps should be in memory. */
1281static inline void tcg_la_bb_end(TCGContext *s, uint8_t *dead_temps,
1282 uint8_t *mem_temps)
641d5fbe
FB
1283{
1284 int i;
641d5fbe 1285
9c43b68d
AJ
1286 memset(dead_temps, 1, s->nb_temps);
1287 memset(mem_temps, 1, s->nb_globals);
641d5fbe 1288 for(i = s->nb_globals; i < s->nb_temps; i++) {
9c43b68d 1289 mem_temps[i] = s->temps[i].temp_local;
641d5fbe
FB
1290 }
1291}
1292
866cb6cb 1293/* Liveness analysis : update the opc_dead_args array to tell if a
c896fe29
FB
1294 given input arguments is dead. Instructions updating dead
1295 temporaries are removed. */
8fcd3692 1296static void tcg_liveness_analysis(TCGContext *s)
c896fe29 1297{
9c43b68d 1298 uint8_t *dead_temps, *mem_temps;
c45cb8bb 1299 int oi, oi_prev, nb_ops;
c896fe29 1300
c45cb8bb 1301 nb_ops = s->gen_next_op_idx;
866cb6cb 1302 s->op_dead_args = tcg_malloc(nb_ops * sizeof(uint16_t));
ec7a869d 1303 s->op_sync_args = tcg_malloc(nb_ops * sizeof(uint8_t));
c896fe29
FB
1304
1305 dead_temps = tcg_malloc(s->nb_temps);
9c43b68d
AJ
1306 mem_temps = tcg_malloc(s->nb_temps);
1307 tcg_la_func_end(s, dead_temps, mem_temps);
c896fe29 1308
c45cb8bb
RH
1309 for (oi = s->gen_last_op_idx; oi >= 0; oi = oi_prev) {
1310 int i, nb_iargs, nb_oargs;
1311 TCGOpcode opc_new, opc_new2;
1312 bool have_opc_new2;
1313 uint16_t dead_args;
1314 uint8_t sync_args;
1315 TCGArg arg;
1316
1317 TCGOp * const op = &s->gen_op_buf[oi];
1318 TCGArg * const args = &s->gen_opparam_buf[op->args];
1319 TCGOpcode opc = op->opc;
1320 const TCGOpDef *def = &tcg_op_defs[opc];
1321
1322 oi_prev = op->prev;
1323
1324 switch (opc) {
c896fe29 1325 case INDEX_op_call:
c6e113f5
FB
1326 {
1327 int call_flags;
c896fe29 1328
c45cb8bb
RH
1329 nb_oargs = op->callo;
1330 nb_iargs = op->calli;
cf066674 1331 call_flags = args[nb_oargs + nb_iargs + 1];
c6e113f5 1332
c45cb8bb 1333 /* pure functions can be removed if their result is unused */
78505279 1334 if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) {
cf066674 1335 for (i = 0; i < nb_oargs; i++) {
c6e113f5 1336 arg = args[i];
9c43b68d 1337 if (!dead_temps[arg] || mem_temps[arg]) {
c6e113f5 1338 goto do_not_remove_call;
9c43b68d 1339 }
c6e113f5 1340 }
c45cb8bb 1341 goto do_remove;
c6e113f5
FB
1342 } else {
1343 do_not_remove_call:
c896fe29 1344
c6e113f5 1345 /* output args are dead */
6b64b624 1346 dead_args = 0;
ec7a869d 1347 sync_args = 0;
cf066674 1348 for (i = 0; i < nb_oargs; i++) {
c6e113f5 1349 arg = args[i];
6b64b624
AJ
1350 if (dead_temps[arg]) {
1351 dead_args |= (1 << i);
1352 }
9c43b68d
AJ
1353 if (mem_temps[arg]) {
1354 sync_args |= (1 << i);
1355 }
c6e113f5 1356 dead_temps[arg] = 1;
9c43b68d 1357 mem_temps[arg] = 0;
c6e113f5 1358 }
78505279
AJ
1359
1360 if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) {
1361 /* globals should be synced to memory */
1362 memset(mem_temps, 1, s->nb_globals);
1363 }
1364 if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS |
1365 TCG_CALL_NO_READ_GLOBALS))) {
9c43b68d
AJ
1366 /* globals should go back to memory */
1367 memset(dead_temps, 1, s->nb_globals);
b9c18f56
AJ
1368 }
1369
c6e113f5 1370 /* input args are live */
cf066674 1371 for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
866cb6cb 1372 arg = args[i];
39cf05d3
FB
1373 if (arg != TCG_CALL_DUMMY_ARG) {
1374 if (dead_temps[arg]) {
866cb6cb 1375 dead_args |= (1 << i);
39cf05d3
FB
1376 }
1377 dead_temps[arg] = 0;
c6e113f5 1378 }
c6e113f5 1379 }
c45cb8bb
RH
1380 s->op_dead_args[oi] = dead_args;
1381 s->op_sync_args[oi] = sync_args;
c896fe29 1382 }
c896fe29 1383 }
c896fe29 1384 break;
7e4597d7 1385 case INDEX_op_debug_insn_start:
c896fe29 1386 break;
5ff9d6a4 1387 case INDEX_op_discard:
5ff9d6a4
FB
1388 /* mark the temporary as dead */
1389 dead_temps[args[0]] = 1;
9c43b68d 1390 mem_temps[args[0]] = 0;
5ff9d6a4 1391 break;
1305c451
RH
1392
1393 case INDEX_op_add2_i32:
c45cb8bb 1394 opc_new = INDEX_op_add_i32;
f1fae40c 1395 goto do_addsub2;
1305c451 1396 case INDEX_op_sub2_i32:
c45cb8bb 1397 opc_new = INDEX_op_sub_i32;
f1fae40c
RH
1398 goto do_addsub2;
1399 case INDEX_op_add2_i64:
c45cb8bb 1400 opc_new = INDEX_op_add_i64;
f1fae40c
RH
1401 goto do_addsub2;
1402 case INDEX_op_sub2_i64:
c45cb8bb 1403 opc_new = INDEX_op_sub_i64;
f1fae40c 1404 do_addsub2:
1305c451
RH
1405 nb_iargs = 4;
1406 nb_oargs = 2;
1407 /* Test if the high part of the operation is dead, but not
1408 the low part. The result can be optimized to a simple
1409 add or sub. This happens often for x86_64 guest when the
1410 cpu mode is set to 32 bit. */
3c5645fa
KB
1411 if (dead_temps[args[1]] && !mem_temps[args[1]]) {
1412 if (dead_temps[args[0]] && !mem_temps[args[0]]) {
1305c451
RH
1413 goto do_remove;
1414 }
c45cb8bb
RH
1415 /* Replace the opcode and adjust the args in place,
1416 leaving 3 unused args at the end. */
1417 op->opc = opc = opc_new;
1305c451
RH
1418 args[1] = args[2];
1419 args[2] = args[4];
1305c451
RH
1420 /* Fall through and mark the single-word operation live. */
1421 nb_iargs = 2;
1422 nb_oargs = 1;
1423 }
1424 goto do_not_remove;
1425
1414968a 1426 case INDEX_op_mulu2_i32:
c45cb8bb
RH
1427 opc_new = INDEX_op_mul_i32;
1428 opc_new2 = INDEX_op_muluh_i32;
1429 have_opc_new2 = TCG_TARGET_HAS_muluh_i32;
03271524 1430 goto do_mul2;
f1fae40c 1431 case INDEX_op_muls2_i32:
c45cb8bb
RH
1432 opc_new = INDEX_op_mul_i32;
1433 opc_new2 = INDEX_op_mulsh_i32;
1434 have_opc_new2 = TCG_TARGET_HAS_mulsh_i32;
f1fae40c
RH
1435 goto do_mul2;
1436 case INDEX_op_mulu2_i64:
c45cb8bb
RH
1437 opc_new = INDEX_op_mul_i64;
1438 opc_new2 = INDEX_op_muluh_i64;
1439 have_opc_new2 = TCG_TARGET_HAS_muluh_i64;
03271524 1440 goto do_mul2;
f1fae40c 1441 case INDEX_op_muls2_i64:
c45cb8bb
RH
1442 opc_new = INDEX_op_mul_i64;
1443 opc_new2 = INDEX_op_mulsh_i64;
1444 have_opc_new2 = TCG_TARGET_HAS_mulsh_i64;
03271524 1445 goto do_mul2;
f1fae40c 1446 do_mul2:
1414968a
RH
1447 nb_iargs = 2;
1448 nb_oargs = 2;
3c5645fa
KB
1449 if (dead_temps[args[1]] && !mem_temps[args[1]]) {
1450 if (dead_temps[args[0]] && !mem_temps[args[0]]) {
03271524 1451 /* Both parts of the operation are dead. */
1414968a
RH
1452 goto do_remove;
1453 }
03271524 1454 /* The high part of the operation is dead; generate the low. */
c45cb8bb 1455 op->opc = opc = opc_new;
1414968a
RH
1456 args[1] = args[2];
1457 args[2] = args[3];
c45cb8bb 1458 } else if (have_opc_new2 && dead_temps[args[0]]
03271524 1459 && !mem_temps[args[0]]) {
c45cb8bb
RH
1460 /* The low part of the operation is dead; generate the high. */
1461 op->opc = opc = opc_new2;
03271524
RH
1462 args[0] = args[1];
1463 args[1] = args[2];
1464 args[2] = args[3];
1465 } else {
1466 goto do_not_remove;
1414968a 1467 }
03271524
RH
1468 /* Mark the single-word operation live. */
1469 nb_oargs = 1;
1414968a
RH
1470 goto do_not_remove;
1471
c896fe29 1472 default:
1305c451 1473 /* XXX: optimize by hardcoding common cases (e.g. triadic ops) */
49516bc0
AJ
1474 nb_iargs = def->nb_iargs;
1475 nb_oargs = def->nb_oargs;
c896fe29 1476
49516bc0
AJ
1477 /* Test if the operation can be removed because all
1478 its outputs are dead. We assume that nb_oargs == 0
1479 implies side effects */
1480 if (!(def->flags & TCG_OPF_SIDE_EFFECTS) && nb_oargs != 0) {
c45cb8bb 1481 for (i = 0; i < nb_oargs; i++) {
49516bc0 1482 arg = args[i];
9c43b68d 1483 if (!dead_temps[arg] || mem_temps[arg]) {
49516bc0 1484 goto do_not_remove;
9c43b68d 1485 }
49516bc0 1486 }
1305c451 1487 do_remove:
0c627cdc 1488 tcg_op_remove(s, op);
49516bc0
AJ
1489 } else {
1490 do_not_remove:
49516bc0 1491 /* output args are dead */
6b64b624 1492 dead_args = 0;
ec7a869d 1493 sync_args = 0;
c45cb8bb 1494 for (i = 0; i < nb_oargs; i++) {
49516bc0 1495 arg = args[i];
6b64b624
AJ
1496 if (dead_temps[arg]) {
1497 dead_args |= (1 << i);
1498 }
9c43b68d
AJ
1499 if (mem_temps[arg]) {
1500 sync_args |= (1 << i);
1501 }
49516bc0 1502 dead_temps[arg] = 1;
9c43b68d 1503 mem_temps[arg] = 0;
49516bc0
AJ
1504 }
1505
1506 /* if end of basic block, update */
1507 if (def->flags & TCG_OPF_BB_END) {
9c43b68d 1508 tcg_la_bb_end(s, dead_temps, mem_temps);
3d5c5f87
AJ
1509 } else if (def->flags & TCG_OPF_SIDE_EFFECTS) {
1510 /* globals should be synced to memory */
9c43b68d 1511 memset(mem_temps, 1, s->nb_globals);
49516bc0
AJ
1512 }
1513
1514 /* input args are live */
c45cb8bb 1515 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
866cb6cb 1516 arg = args[i];
49516bc0 1517 if (dead_temps[arg]) {
866cb6cb 1518 dead_args |= (1 << i);
c896fe29 1519 }
49516bc0 1520 dead_temps[arg] = 0;
c896fe29 1521 }
c45cb8bb
RH
1522 s->op_dead_args[oi] = dead_args;
1523 s->op_sync_args[oi] = sync_args;
c896fe29
FB
1524 }
1525 break;
1526 }
1ff0a2c5 1527 }
c896fe29
FB
1528}
1529#else
1530/* dummy liveness analysis */
655feed5 1531static void tcg_liveness_analysis(TCGContext *s)
c896fe29
FB
1532{
1533 int nb_ops;
92414b31 1534 nb_ops = s->gen_opc_ptr - s->gen_opc_buf;
c896fe29 1535
866cb6cb
AJ
1536 s->op_dead_args = tcg_malloc(nb_ops * sizeof(uint16_t));
1537 memset(s->op_dead_args, 0, nb_ops * sizeof(uint16_t));
ec7a869d
AJ
1538 s->op_sync_args = tcg_malloc(nb_ops * sizeof(uint8_t));
1539 memset(s->op_sync_args, 0, nb_ops * sizeof(uint8_t));
c896fe29
FB
1540}
1541#endif
1542
1543#ifndef NDEBUG
1544static void dump_regs(TCGContext *s)
1545{
1546 TCGTemp *ts;
1547 int i;
1548 char buf[64];
1549
1550 for(i = 0; i < s->nb_temps; i++) {
1551 ts = &s->temps[i];
ac56dd48 1552 printf(" %10s: ", tcg_get_arg_str_idx(s, buf, sizeof(buf), i));
c896fe29
FB
1553 switch(ts->val_type) {
1554 case TEMP_VAL_REG:
1555 printf("%s", tcg_target_reg_names[ts->reg]);
1556 break;
1557 case TEMP_VAL_MEM:
1558 printf("%d(%s)", (int)ts->mem_offset, tcg_target_reg_names[ts->mem_reg]);
1559 break;
1560 case TEMP_VAL_CONST:
1561 printf("$0x%" TCG_PRIlx, ts->val);
1562 break;
1563 case TEMP_VAL_DEAD:
1564 printf("D");
1565 break;
1566 default:
1567 printf("???");
1568 break;
1569 }
1570 printf("\n");
1571 }
1572
1573 for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
1574 if (s->reg_to_temp[i] >= 0) {
1575 printf("%s: %s\n",
1576 tcg_target_reg_names[i],
ac56dd48 1577 tcg_get_arg_str_idx(s, buf, sizeof(buf), s->reg_to_temp[i]));
c896fe29
FB
1578 }
1579 }
1580}
1581
1582static void check_regs(TCGContext *s)
1583{
1584 int reg, k;
1585 TCGTemp *ts;
1586 char buf[64];
1587
1588 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
1589 k = s->reg_to_temp[reg];
1590 if (k >= 0) {
1591 ts = &s->temps[k];
1592 if (ts->val_type != TEMP_VAL_REG ||
1593 ts->reg != reg) {
1594 printf("Inconsistency for register %s:\n",
1595 tcg_target_reg_names[reg]);
b03cce8e 1596 goto fail;
c896fe29
FB
1597 }
1598 }
1599 }
1600 for(k = 0; k < s->nb_temps; k++) {
1601 ts = &s->temps[k];
1602 if (ts->val_type == TEMP_VAL_REG &&
1603 !ts->fixed_reg &&
1604 s->reg_to_temp[ts->reg] != k) {
1605 printf("Inconsistency for temp %s:\n",
ac56dd48 1606 tcg_get_arg_str_idx(s, buf, sizeof(buf), k));
b03cce8e 1607 fail:
c896fe29
FB
1608 printf("reg state:\n");
1609 dump_regs(s);
1610 tcg_abort();
1611 }
1612 }
1613}
1614#endif
1615
1616static void temp_allocate_frame(TCGContext *s, int temp)
1617{
1618 TCGTemp *ts;
1619 ts = &s->temps[temp];
9b9c37c3
RH
1620#if !(defined(__sparc__) && TCG_TARGET_REG_BITS == 64)
1621 /* Sparc64 stack is accessed with offset of 2047 */
b591dc59
BS
1622 s->current_frame_offset = (s->current_frame_offset +
1623 (tcg_target_long)sizeof(tcg_target_long) - 1) &
1624 ~(sizeof(tcg_target_long) - 1);
f44c9960 1625#endif
b591dc59
BS
1626 if (s->current_frame_offset + (tcg_target_long)sizeof(tcg_target_long) >
1627 s->frame_end) {
5ff9d6a4 1628 tcg_abort();
b591dc59 1629 }
c896fe29
FB
1630 ts->mem_offset = s->current_frame_offset;
1631 ts->mem_reg = s->frame_reg;
1632 ts->mem_allocated = 1;
e2c6d1b4 1633 s->current_frame_offset += sizeof(tcg_target_long);
c896fe29
FB
1634}
1635
7f6ceedf
AJ
1636/* sync register 'reg' by saving it to the corresponding temporary */
1637static inline void tcg_reg_sync(TCGContext *s, int reg)
1638{
1639 TCGTemp *ts;
1640 int temp;
1641
1642 temp = s->reg_to_temp[reg];
1643 ts = &s->temps[temp];
1644 assert(ts->val_type == TEMP_VAL_REG);
1645 if (!ts->mem_coherent && !ts->fixed_reg) {
1646 if (!ts->mem_allocated) {
1647 temp_allocate_frame(s, temp);
1648 }
1649 tcg_out_st(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
1650 }
1651 ts->mem_coherent = 1;
1652}
1653
c896fe29
FB
1654/* free register 'reg' by spilling the corresponding temporary if necessary */
1655static void tcg_reg_free(TCGContext *s, int reg)
1656{
c896fe29
FB
1657 int temp;
1658
1659 temp = s->reg_to_temp[reg];
1660 if (temp != -1) {
7f6ceedf
AJ
1661 tcg_reg_sync(s, reg);
1662 s->temps[temp].val_type = TEMP_VAL_MEM;
c896fe29
FB
1663 s->reg_to_temp[reg] = -1;
1664 }
1665}
1666
1667/* Allocate a register belonging to reg1 & ~reg2 */
1668static int tcg_reg_alloc(TCGContext *s, TCGRegSet reg1, TCGRegSet reg2)
1669{
1670 int i, reg;
1671 TCGRegSet reg_ct;
1672
1673 tcg_regset_andnot(reg_ct, reg1, reg2);
1674
1675 /* first try free registers */
0954d0d9 1676 for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
c896fe29
FB
1677 reg = tcg_target_reg_alloc_order[i];
1678 if (tcg_regset_test_reg(reg_ct, reg) && s->reg_to_temp[reg] == -1)
1679 return reg;
1680 }
1681
1682 /* XXX: do better spill choice */
0954d0d9 1683 for(i = 0; i < ARRAY_SIZE(tcg_target_reg_alloc_order); i++) {
c896fe29
FB
1684 reg = tcg_target_reg_alloc_order[i];
1685 if (tcg_regset_test_reg(reg_ct, reg)) {
1686 tcg_reg_free(s, reg);
1687 return reg;
1688 }
1689 }
1690
1691 tcg_abort();
1692}
1693
639368dd
AJ
1694/* mark a temporary as dead. */
1695static inline void temp_dead(TCGContext *s, int temp)
1696{
1697 TCGTemp *ts;
1698
1699 ts = &s->temps[temp];
1700 if (!ts->fixed_reg) {
1701 if (ts->val_type == TEMP_VAL_REG) {
1702 s->reg_to_temp[ts->reg] = -1;
1703 }
e5138db5 1704 if (temp < s->nb_globals || ts->temp_local) {
639368dd
AJ
1705 ts->val_type = TEMP_VAL_MEM;
1706 } else {
1707 ts->val_type = TEMP_VAL_DEAD;
1708 }
1709 }
1710}
1711
1ad80729 1712/* sync a temporary to memory. 'allocated_regs' is used in case a
641d5fbe 1713 temporary registers needs to be allocated to store a constant. */
1ad80729 1714static inline void temp_sync(TCGContext *s, int temp, TCGRegSet allocated_regs)
641d5fbe
FB
1715{
1716 TCGTemp *ts;
641d5fbe
FB
1717
1718 ts = &s->temps[temp];
1719 if (!ts->fixed_reg) {
1720 switch(ts->val_type) {
1ad80729
AJ
1721 case TEMP_VAL_CONST:
1722 ts->reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
1723 allocated_regs);
1724 ts->val_type = TEMP_VAL_REG;
1725 s->reg_to_temp[ts->reg] = temp;
1726 ts->mem_coherent = 0;
1727 tcg_out_movi(s, ts->type, ts->reg, ts->val);
1728 /* fallthrough*/
641d5fbe 1729 case TEMP_VAL_REG:
1ad80729 1730 tcg_reg_sync(s, ts->reg);
641d5fbe
FB
1731 break;
1732 case TEMP_VAL_DEAD:
641d5fbe
FB
1733 case TEMP_VAL_MEM:
1734 break;
1735 default:
1736 tcg_abort();
1737 }
1738 }
1739}
1740
1ad80729
AJ
1741/* save a temporary to memory. 'allocated_regs' is used in case a
1742 temporary registers needs to be allocated to store a constant. */
1743static inline void temp_save(TCGContext *s, int temp, TCGRegSet allocated_regs)
1744{
2c0366f0
AJ
1745#ifdef USE_LIVENESS_ANALYSIS
1746 /* The liveness analysis already ensures that globals are back
1747 in memory. Keep an assert for safety. */
1748 assert(s->temps[temp].val_type == TEMP_VAL_MEM || s->temps[temp].fixed_reg);
1749#else
1ad80729
AJ
1750 temp_sync(s, temp, allocated_regs);
1751 temp_dead(s, temp);
2c0366f0 1752#endif
1ad80729
AJ
1753}
1754
9814dd27 1755/* save globals to their canonical location and assume they can be
e8996ee0
FB
1756 modified be the following code. 'allocated_regs' is used in case a
1757 temporary registers needs to be allocated to store a constant. */
1758static void save_globals(TCGContext *s, TCGRegSet allocated_regs)
c896fe29 1759{
641d5fbe 1760 int i;
c896fe29
FB
1761
1762 for(i = 0; i < s->nb_globals; i++) {
641d5fbe 1763 temp_save(s, i, allocated_regs);
c896fe29 1764 }
e5097dc8
FB
1765}
1766
3d5c5f87
AJ
1767/* sync globals to their canonical location and assume they can be
1768 read by the following code. 'allocated_regs' is used in case a
1769 temporary registers needs to be allocated to store a constant. */
1770static void sync_globals(TCGContext *s, TCGRegSet allocated_regs)
1771{
1772 int i;
1773
1774 for (i = 0; i < s->nb_globals; i++) {
1775#ifdef USE_LIVENESS_ANALYSIS
1776 assert(s->temps[i].val_type != TEMP_VAL_REG || s->temps[i].fixed_reg ||
1777 s->temps[i].mem_coherent);
1778#else
1779 temp_sync(s, i, allocated_regs);
1780#endif
1781 }
1782}
1783
e5097dc8 1784/* at the end of a basic block, we assume all temporaries are dead and
e8996ee0
FB
1785 all globals are stored at their canonical location. */
1786static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs)
e5097dc8
FB
1787{
1788 TCGTemp *ts;
1789 int i;
1790
c896fe29
FB
1791 for(i = s->nb_globals; i < s->nb_temps; i++) {
1792 ts = &s->temps[i];
641d5fbe
FB
1793 if (ts->temp_local) {
1794 temp_save(s, i, allocated_regs);
1795 } else {
2c0366f0
AJ
1796#ifdef USE_LIVENESS_ANALYSIS
1797 /* The liveness analysis already ensures that temps are dead.
1798 Keep an assert for safety. */
1799 assert(ts->val_type == TEMP_VAL_DEAD);
1800#else
639368dd 1801 temp_dead(s, i);
2c0366f0 1802#endif
c896fe29
FB
1803 }
1804 }
e8996ee0
FB
1805
1806 save_globals(s, allocated_regs);
c896fe29
FB
1807}
1808
866cb6cb 1809#define IS_DEAD_ARG(n) ((dead_args >> (n)) & 1)
ec7a869d 1810#define NEED_SYNC_ARG(n) ((sync_args >> (n)) & 1)
c896fe29 1811
ec7a869d
AJ
1812static void tcg_reg_alloc_movi(TCGContext *s, const TCGArg *args,
1813 uint16_t dead_args, uint8_t sync_args)
e8996ee0
FB
1814{
1815 TCGTemp *ots;
1816 tcg_target_ulong val;
1817
1818 ots = &s->temps[args[0]];
1819 val = args[1];
1820
1821 if (ots->fixed_reg) {
1822 /* for fixed registers, we do not do any constant
1823 propagation */
1824 tcg_out_movi(s, ots->type, ots->reg, val);
1825 } else {
1235fc06 1826 /* The movi is not explicitly generated here */
e8996ee0
FB
1827 if (ots->val_type == TEMP_VAL_REG)
1828 s->reg_to_temp[ots->reg] = -1;
1829 ots->val_type = TEMP_VAL_CONST;
1830 ots->val = val;
1831 }
ec7a869d
AJ
1832 if (NEED_SYNC_ARG(0)) {
1833 temp_sync(s, args[0], s->reserved_regs);
1834 }
4c4e1ab2
AJ
1835 if (IS_DEAD_ARG(0)) {
1836 temp_dead(s, args[0]);
1837 }
e8996ee0
FB
1838}
1839
c896fe29 1840static void tcg_reg_alloc_mov(TCGContext *s, const TCGOpDef *def,
ec7a869d
AJ
1841 const TCGArg *args, uint16_t dead_args,
1842 uint8_t sync_args)
c896fe29 1843{
c29c1d7e 1844 TCGRegSet allocated_regs;
c896fe29 1845 TCGTemp *ts, *ots;
450445d5 1846 TCGType otype, itype;
c896fe29 1847
c29c1d7e 1848 tcg_regset_set(allocated_regs, s->reserved_regs);
c896fe29
FB
1849 ots = &s->temps[args[0]];
1850 ts = &s->temps[args[1]];
450445d5
RH
1851
1852 /* Note that otype != itype for no-op truncation. */
1853 otype = ots->type;
1854 itype = ts->type;
c29c1d7e
AJ
1855
1856 /* If the source value is not in a register, and we're going to be
1857 forced to have it in a register in order to perform the copy,
1858 then copy the SOURCE value into its own register first. That way
1859 we don't have to reload SOURCE the next time it is used. */
1860 if (((NEED_SYNC_ARG(0) || ots->fixed_reg) && ts->val_type != TEMP_VAL_REG)
1861 || ts->val_type == TEMP_VAL_MEM) {
450445d5 1862 ts->reg = tcg_reg_alloc(s, tcg_target_available_regs[itype],
af3cbfbe 1863 allocated_regs);
c29c1d7e 1864 if (ts->val_type == TEMP_VAL_MEM) {
450445d5 1865 tcg_out_ld(s, itype, ts->reg, ts->mem_reg, ts->mem_offset);
c29c1d7e
AJ
1866 ts->mem_coherent = 1;
1867 } else if (ts->val_type == TEMP_VAL_CONST) {
450445d5 1868 tcg_out_movi(s, itype, ts->reg, ts->val);
c29c1d7e
AJ
1869 }
1870 s->reg_to_temp[ts->reg] = args[1];
1871 ts->val_type = TEMP_VAL_REG;
1872 }
c896fe29 1873
c29c1d7e
AJ
1874 if (IS_DEAD_ARG(0) && !ots->fixed_reg) {
1875 /* mov to a non-saved dead register makes no sense (even with
1876 liveness analysis disabled). */
1877 assert(NEED_SYNC_ARG(0));
1878 /* The code above should have moved the temp to a register. */
1879 assert(ts->val_type == TEMP_VAL_REG);
1880 if (!ots->mem_allocated) {
1881 temp_allocate_frame(s, args[0]);
1882 }
450445d5 1883 tcg_out_st(s, otype, ts->reg, ots->mem_reg, ots->mem_offset);
c29c1d7e
AJ
1884 if (IS_DEAD_ARG(1)) {
1885 temp_dead(s, args[1]);
1886 }
1887 temp_dead(s, args[0]);
1888 } else if (ts->val_type == TEMP_VAL_CONST) {
1889 /* propagate constant */
1890 if (ots->val_type == TEMP_VAL_REG) {
1891 s->reg_to_temp[ots->reg] = -1;
1892 }
1893 ots->val_type = TEMP_VAL_CONST;
1894 ots->val = ts->val;
1895 } else {
1896 /* The code in the first if block should have moved the
1897 temp to a register. */
1898 assert(ts->val_type == TEMP_VAL_REG);
866cb6cb 1899 if (IS_DEAD_ARG(1) && !ts->fixed_reg && !ots->fixed_reg) {
c896fe29 1900 /* the mov can be suppressed */
c29c1d7e 1901 if (ots->val_type == TEMP_VAL_REG) {
c896fe29 1902 s->reg_to_temp[ots->reg] = -1;
c29c1d7e
AJ
1903 }
1904 ots->reg = ts->reg;
639368dd 1905 temp_dead(s, args[1]);
c896fe29 1906 } else {
c29c1d7e
AJ
1907 if (ots->val_type != TEMP_VAL_REG) {
1908 /* When allocating a new register, make sure to not spill the
1909 input one. */
1910 tcg_regset_set_reg(allocated_regs, ts->reg);
450445d5 1911 ots->reg = tcg_reg_alloc(s, tcg_target_available_regs[otype],
af3cbfbe 1912 allocated_regs);
c896fe29 1913 }
450445d5 1914 tcg_out_mov(s, otype, ots->reg, ts->reg);
c896fe29 1915 }
c29c1d7e
AJ
1916 ots->val_type = TEMP_VAL_REG;
1917 ots->mem_coherent = 0;
1918 s->reg_to_temp[ots->reg] = args[0];
1919 if (NEED_SYNC_ARG(0)) {
1920 tcg_reg_sync(s, ots->reg);
c896fe29 1921 }
ec7a869d 1922 }
c896fe29
FB
1923}
1924
1925static void tcg_reg_alloc_op(TCGContext *s,
a9751609 1926 const TCGOpDef *def, TCGOpcode opc,
ec7a869d
AJ
1927 const TCGArg *args, uint16_t dead_args,
1928 uint8_t sync_args)
c896fe29
FB
1929{
1930 TCGRegSet allocated_regs;
1931 int i, k, nb_iargs, nb_oargs, reg;
1932 TCGArg arg;
1933 const TCGArgConstraint *arg_ct;
1934 TCGTemp *ts;
1935 TCGArg new_args[TCG_MAX_OP_ARGS];
1936 int const_args[TCG_MAX_OP_ARGS];
1937
1938 nb_oargs = def->nb_oargs;
1939 nb_iargs = def->nb_iargs;
1940
1941 /* copy constants */
1942 memcpy(new_args + nb_oargs + nb_iargs,
1943 args + nb_oargs + nb_iargs,
1944 sizeof(TCGArg) * def->nb_cargs);
1945
1946 /* satisfy input constraints */
1947 tcg_regset_set(allocated_regs, s->reserved_regs);
1948 for(k = 0; k < nb_iargs; k++) {
1949 i = def->sorted_args[nb_oargs + k];
1950 arg = args[i];
1951 arg_ct = &def->args_ct[i];
1952 ts = &s->temps[arg];
1953 if (ts->val_type == TEMP_VAL_MEM) {
1954 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
e4d5434c 1955 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
c896fe29
FB
1956 ts->val_type = TEMP_VAL_REG;
1957 ts->reg = reg;
1958 ts->mem_coherent = 1;
1959 s->reg_to_temp[reg] = arg;
1960 } else if (ts->val_type == TEMP_VAL_CONST) {
f6c6afc1 1961 if (tcg_target_const_match(ts->val, ts->type, arg_ct)) {
c896fe29
FB
1962 /* constant is OK for instruction */
1963 const_args[i] = 1;
1964 new_args[i] = ts->val;
1965 goto iarg_end;
1966 } else {
e8996ee0 1967 /* need to move to a register */
c896fe29
FB
1968 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
1969 tcg_out_movi(s, ts->type, reg, ts->val);
e8996ee0
FB
1970 ts->val_type = TEMP_VAL_REG;
1971 ts->reg = reg;
1972 ts->mem_coherent = 0;
1973 s->reg_to_temp[reg] = arg;
c896fe29
FB
1974 }
1975 }
1976 assert(ts->val_type == TEMP_VAL_REG);
5ff9d6a4
FB
1977 if (arg_ct->ct & TCG_CT_IALIAS) {
1978 if (ts->fixed_reg) {
1979 /* if fixed register, we must allocate a new register
1980 if the alias is not the same register */
1981 if (arg != args[arg_ct->alias_index])
1982 goto allocate_in_reg;
1983 } else {
1984 /* if the input is aliased to an output and if it is
1985 not dead after the instruction, we must allocate
1986 a new register and move it */
866cb6cb 1987 if (!IS_DEAD_ARG(i)) {
5ff9d6a4 1988 goto allocate_in_reg;
866cb6cb 1989 }
5ff9d6a4 1990 }
c896fe29
FB
1991 }
1992 reg = ts->reg;
1993 if (tcg_regset_test_reg(arg_ct->u.regs, reg)) {
1994 /* nothing to do : the constraint is satisfied */
1995 } else {
1996 allocate_in_reg:
1997 /* allocate a new register matching the constraint
1998 and move the temporary register into it */
1999 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
3b6dac34 2000 tcg_out_mov(s, ts->type, reg, ts->reg);
c896fe29 2001 }
c896fe29
FB
2002 new_args[i] = reg;
2003 const_args[i] = 0;
2004 tcg_regset_set_reg(allocated_regs, reg);
2005 iarg_end: ;
2006 }
2007
a52ad07e
AJ
2008 /* mark dead temporaries and free the associated registers */
2009 for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) {
2010 if (IS_DEAD_ARG(i)) {
2011 temp_dead(s, args[i]);
2012 }
2013 }
2014
e8996ee0
FB
2015 if (def->flags & TCG_OPF_BB_END) {
2016 tcg_reg_alloc_bb_end(s, allocated_regs);
2017 } else {
e8996ee0
FB
2018 if (def->flags & TCG_OPF_CALL_CLOBBER) {
2019 /* XXX: permit generic clobber register list ? */
2020 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
2021 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, reg)) {
2022 tcg_reg_free(s, reg);
2023 }
c896fe29 2024 }
3d5c5f87
AJ
2025 }
2026 if (def->flags & TCG_OPF_SIDE_EFFECTS) {
2027 /* sync globals if the op has side effects and might trigger
2028 an exception. */
2029 sync_globals(s, allocated_regs);
c896fe29 2030 }
e8996ee0
FB
2031
2032 /* satisfy the output constraints */
2033 tcg_regset_set(allocated_regs, s->reserved_regs);
2034 for(k = 0; k < nb_oargs; k++) {
2035 i = def->sorted_args[k];
2036 arg = args[i];
2037 arg_ct = &def->args_ct[i];
2038 ts = &s->temps[arg];
2039 if (arg_ct->ct & TCG_CT_ALIAS) {
2040 reg = new_args[arg_ct->alias_index];
2041 } else {
2042 /* if fixed register, we try to use it */
2043 reg = ts->reg;
2044 if (ts->fixed_reg &&
2045 tcg_regset_test_reg(arg_ct->u.regs, reg)) {
2046 goto oarg_end;
2047 }
2048 reg = tcg_reg_alloc(s, arg_ct->u.regs, allocated_regs);
c896fe29 2049 }
e8996ee0
FB
2050 tcg_regset_set_reg(allocated_regs, reg);
2051 /* if a fixed register is used, then a move will be done afterwards */
2052 if (!ts->fixed_reg) {
ec7a869d
AJ
2053 if (ts->val_type == TEMP_VAL_REG) {
2054 s->reg_to_temp[ts->reg] = -1;
2055 }
2056 ts->val_type = TEMP_VAL_REG;
2057 ts->reg = reg;
2058 /* temp value is modified, so the value kept in memory is
2059 potentially not the same */
2060 ts->mem_coherent = 0;
2061 s->reg_to_temp[reg] = arg;
e8996ee0
FB
2062 }
2063 oarg_end:
2064 new_args[i] = reg;
c896fe29 2065 }
c896fe29
FB
2066 }
2067
c896fe29
FB
2068 /* emit instruction */
2069 tcg_out_op(s, opc, new_args, const_args);
2070
2071 /* move the outputs in the correct register if needed */
2072 for(i = 0; i < nb_oargs; i++) {
2073 ts = &s->temps[args[i]];
2074 reg = new_args[i];
2075 if (ts->fixed_reg && ts->reg != reg) {
3b6dac34 2076 tcg_out_mov(s, ts->type, ts->reg, reg);
c896fe29 2077 }
ec7a869d
AJ
2078 if (NEED_SYNC_ARG(i)) {
2079 tcg_reg_sync(s, reg);
2080 }
2081 if (IS_DEAD_ARG(i)) {
2082 temp_dead(s, args[i]);
2083 }
c896fe29
FB
2084 }
2085}
2086
b03cce8e
FB
2087#ifdef TCG_TARGET_STACK_GROWSUP
2088#define STACK_DIR(x) (-(x))
2089#else
2090#define STACK_DIR(x) (x)
2091#endif
2092
c45cb8bb
RH
2093static void tcg_reg_alloc_call(TCGContext *s, int nb_oargs, int nb_iargs,
2094 const TCGArg * const args, uint16_t dead_args,
2095 uint8_t sync_args)
c896fe29 2096{
c45cb8bb 2097 int flags, nb_regs, i, reg;
cf066674 2098 TCGArg arg;
c896fe29 2099 TCGTemp *ts;
d3452f1f
RH
2100 intptr_t stack_offset;
2101 size_t call_stack_size;
cf066674
RH
2102 tcg_insn_unit *func_addr;
2103 int allocate_args;
c896fe29 2104 TCGRegSet allocated_regs;
c896fe29 2105
cf066674
RH
2106 func_addr = (tcg_insn_unit *)(intptr_t)args[nb_oargs + nb_iargs];
2107 flags = args[nb_oargs + nb_iargs + 1];
c896fe29 2108
6e17d0c5 2109 nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs);
c45cb8bb
RH
2110 if (nb_regs > nb_iargs) {
2111 nb_regs = nb_iargs;
cf066674 2112 }
c896fe29
FB
2113
2114 /* assign stack slots first */
c45cb8bb 2115 call_stack_size = (nb_iargs - nb_regs) * sizeof(tcg_target_long);
c896fe29
FB
2116 call_stack_size = (call_stack_size + TCG_TARGET_STACK_ALIGN - 1) &
2117 ~(TCG_TARGET_STACK_ALIGN - 1);
b03cce8e
FB
2118 allocate_args = (call_stack_size > TCG_STATIC_CALL_ARGS_SIZE);
2119 if (allocate_args) {
345649c0
BS
2120 /* XXX: if more than TCG_STATIC_CALL_ARGS_SIZE is needed,
2121 preallocate call stack */
2122 tcg_abort();
b03cce8e 2123 }
39cf05d3
FB
2124
2125 stack_offset = TCG_TARGET_CALL_STACK_OFFSET;
c45cb8bb 2126 for(i = nb_regs; i < nb_iargs; i++) {
c896fe29 2127 arg = args[nb_oargs + i];
39cf05d3
FB
2128#ifdef TCG_TARGET_STACK_GROWSUP
2129 stack_offset -= sizeof(tcg_target_long);
2130#endif
2131 if (arg != TCG_CALL_DUMMY_ARG) {
2132 ts = &s->temps[arg];
2133 if (ts->val_type == TEMP_VAL_REG) {
2134 tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_offset);
2135 } else if (ts->val_type == TEMP_VAL_MEM) {
2136 reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
2137 s->reserved_regs);
2138 /* XXX: not correct if reading values from the stack */
2139 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
2140 tcg_out_st(s, ts->type, reg, TCG_REG_CALL_STACK, stack_offset);
2141 } else if (ts->val_type == TEMP_VAL_CONST) {
2142 reg = tcg_reg_alloc(s, tcg_target_available_regs[ts->type],
2143 s->reserved_regs);
2144 /* XXX: sign extend may be needed on some targets */
2145 tcg_out_movi(s, ts->type, reg, ts->val);
2146 tcg_out_st(s, ts->type, reg, TCG_REG_CALL_STACK, stack_offset);
2147 } else {
2148 tcg_abort();
2149 }
c896fe29 2150 }
39cf05d3
FB
2151#ifndef TCG_TARGET_STACK_GROWSUP
2152 stack_offset += sizeof(tcg_target_long);
2153#endif
c896fe29
FB
2154 }
2155
2156 /* assign input registers */
2157 tcg_regset_set(allocated_regs, s->reserved_regs);
2158 for(i = 0; i < nb_regs; i++) {
2159 arg = args[nb_oargs + i];
39cf05d3
FB
2160 if (arg != TCG_CALL_DUMMY_ARG) {
2161 ts = &s->temps[arg];
2162 reg = tcg_target_call_iarg_regs[i];
2163 tcg_reg_free(s, reg);
2164 if (ts->val_type == TEMP_VAL_REG) {
2165 if (ts->reg != reg) {
3b6dac34 2166 tcg_out_mov(s, ts->type, reg, ts->reg);
39cf05d3
FB
2167 }
2168 } else if (ts->val_type == TEMP_VAL_MEM) {
2169 tcg_out_ld(s, ts->type, reg, ts->mem_reg, ts->mem_offset);
2170 } else if (ts->val_type == TEMP_VAL_CONST) {
2171 /* XXX: sign extend ? */
2172 tcg_out_movi(s, ts->type, reg, ts->val);
2173 } else {
2174 tcg_abort();
c896fe29 2175 }
39cf05d3 2176 tcg_regset_set_reg(allocated_regs, reg);
c896fe29 2177 }
c896fe29
FB
2178 }
2179
c896fe29 2180 /* mark dead temporaries and free the associated registers */
866cb6cb 2181 for(i = nb_oargs; i < nb_iargs + nb_oargs; i++) {
866cb6cb 2182 if (IS_DEAD_ARG(i)) {
639368dd 2183 temp_dead(s, args[i]);
c896fe29
FB
2184 }
2185 }
2186
2187 /* clobber call registers */
2188 for(reg = 0; reg < TCG_TARGET_NB_REGS; reg++) {
2189 if (tcg_regset_test_reg(tcg_target_call_clobber_regs, reg)) {
2190 tcg_reg_free(s, reg);
2191 }
2192 }
78505279
AJ
2193
2194 /* Save globals if they might be written by the helper, sync them if
2195 they might be read. */
2196 if (flags & TCG_CALL_NO_READ_GLOBALS) {
2197 /* Nothing to do */
2198 } else if (flags & TCG_CALL_NO_WRITE_GLOBALS) {
2199 sync_globals(s, allocated_regs);
2200 } else {
b9c18f56
AJ
2201 save_globals(s, allocated_regs);
2202 }
c896fe29 2203
cf066674 2204 tcg_out_call(s, func_addr);
c896fe29
FB
2205
2206 /* assign output registers and emit moves if needed */
2207 for(i = 0; i < nb_oargs; i++) {
2208 arg = args[i];
2209 ts = &s->temps[arg];
2210 reg = tcg_target_call_oarg_regs[i];
e8996ee0 2211 assert(s->reg_to_temp[reg] == -1);
34b1a49c 2212
c896fe29
FB
2213 if (ts->fixed_reg) {
2214 if (ts->reg != reg) {
3b6dac34 2215 tcg_out_mov(s, ts->type, ts->reg, reg);
c896fe29
FB
2216 }
2217 } else {
ec7a869d
AJ
2218 if (ts->val_type == TEMP_VAL_REG) {
2219 s->reg_to_temp[ts->reg] = -1;
2220 }
2221 ts->val_type = TEMP_VAL_REG;
2222 ts->reg = reg;
2223 ts->mem_coherent = 0;
2224 s->reg_to_temp[reg] = arg;
2225 if (NEED_SYNC_ARG(i)) {
2226 tcg_reg_sync(s, reg);
2227 }
8c11ad25 2228 if (IS_DEAD_ARG(i)) {
639368dd 2229 temp_dead(s, args[i]);
8c11ad25 2230 }
c896fe29
FB
2231 }
2232 }
c896fe29
FB
2233}
2234
2235#ifdef CONFIG_PROFILER
2236
54604f74 2237static int64_t tcg_table_op_count[NB_OPS];
c896fe29 2238
246ae24d 2239void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf)
c896fe29
FB
2240{
2241 int i;
d70724ce 2242
15fc7daa 2243 for (i = 0; i < NB_OPS; i++) {
246ae24d
MF
2244 cpu_fprintf(f, "%s %" PRId64 "\n", tcg_op_defs[i].name,
2245 tcg_table_op_count[i]);
c896fe29 2246 }
c896fe29 2247}
246ae24d
MF
2248#else
2249void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf)
2250{
2251 cpu_fprintf(f, "[TCG profiler not compiled]\n");
2252}
c896fe29
FB
2253#endif
2254
2255
1813e175
RH
2256static inline int tcg_gen_code_common(TCGContext *s,
2257 tcg_insn_unit *gen_code_buf,
2ba1eeb6 2258 long search_pc)
c896fe29 2259{
c45cb8bb 2260 int oi, oi_next;
c896fe29
FB
2261
2262#ifdef DEBUG_DISAS
8fec2b8c 2263 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
93fcfe39 2264 qemu_log("OP:\n");
eeacee4d 2265 tcg_dump_ops(s);
93fcfe39 2266 qemu_log("\n");
c896fe29
FB
2267 }
2268#endif
2269
c5cc28ff
AJ
2270#ifdef CONFIG_PROFILER
2271 s->opt_time -= profile_getclock();
2272#endif
2273
8f2e8c07 2274#ifdef USE_TCG_OPTIMIZATIONS
c45cb8bb 2275 tcg_optimize(s);
8f2e8c07
KB
2276#endif
2277
a23a9ec6 2278#ifdef CONFIG_PROFILER
c5cc28ff 2279 s->opt_time += profile_getclock();
a23a9ec6
FB
2280 s->la_time -= profile_getclock();
2281#endif
c5cc28ff 2282
c896fe29 2283 tcg_liveness_analysis(s);
c5cc28ff 2284
a23a9ec6
FB
2285#ifdef CONFIG_PROFILER
2286 s->la_time += profile_getclock();
2287#endif
c896fe29
FB
2288
2289#ifdef DEBUG_DISAS
8fec2b8c 2290 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) {
c5cc28ff 2291 qemu_log("OP after optimization and liveness analysis:\n");
eeacee4d 2292 tcg_dump_ops(s);
93fcfe39 2293 qemu_log("\n");
c896fe29
FB
2294 }
2295#endif
2296
2297 tcg_reg_alloc_start(s);
2298
2299 s->code_buf = gen_code_buf;
2300 s->code_ptr = gen_code_buf;
2301
9ecefc84
RH
2302 tcg_out_tb_init(s);
2303
c45cb8bb
RH
2304 for (oi = s->gen_first_op_idx; oi >= 0; oi = oi_next) {
2305 TCGOp * const op = &s->gen_op_buf[oi];
2306 TCGArg * const args = &s->gen_opparam_buf[op->args];
2307 TCGOpcode opc = op->opc;
2308 const TCGOpDef *def = &tcg_op_defs[opc];
2309 uint16_t dead_args = s->op_dead_args[oi];
2310 uint8_t sync_args = s->op_sync_args[oi];
b3db8758 2311
c45cb8bb 2312 oi_next = op->next;
c896fe29 2313#ifdef CONFIG_PROFILER
54604f74 2314 tcg_table_op_count[opc]++;
c896fe29 2315#endif
c45cb8bb
RH
2316
2317 switch (opc) {
c896fe29 2318 case INDEX_op_mov_i32:
c896fe29 2319 case INDEX_op_mov_i64:
c45cb8bb 2320 tcg_reg_alloc_mov(s, def, args, dead_args, sync_args);
c896fe29 2321 break;
e8996ee0 2322 case INDEX_op_movi_i32:
e8996ee0 2323 case INDEX_op_movi_i64:
c45cb8bb 2324 tcg_reg_alloc_movi(s, args, dead_args, sync_args);
e8996ee0 2325 break;
7e4597d7 2326 case INDEX_op_debug_insn_start:
c896fe29 2327 break;
5ff9d6a4 2328 case INDEX_op_discard:
639368dd 2329 temp_dead(s, args[0]);
5ff9d6a4 2330 break;
c896fe29 2331 case INDEX_op_set_label:
e8996ee0 2332 tcg_reg_alloc_bb_end(s, s->reserved_regs);
bec16311 2333 tcg_out_label(s, arg_label(args[0]), s->code_ptr);
c896fe29
FB
2334 break;
2335 case INDEX_op_call:
c45cb8bb
RH
2336 tcg_reg_alloc_call(s, op->callo, op->calli, args,
2337 dead_args, sync_args);
2338 break;
c896fe29 2339 default:
25c4d9cc
RH
2340 /* Sanity check that we've not introduced any unhandled opcodes. */
2341 if (def->flags & TCG_OPF_NOT_PRESENT) {
2342 tcg_abort();
2343 }
c896fe29
FB
2344 /* Note: in order to speed up the code, it would be much
2345 faster to have specialized register allocator functions for
2346 some common argument patterns */
c45cb8bb 2347 tcg_reg_alloc_op(s, def, opc, args, dead_args, sync_args);
c896fe29
FB
2348 break;
2349 }
1813e175 2350 if (search_pc >= 0 && search_pc < tcg_current_code_size(s)) {
c45cb8bb 2351 return oi;
c896fe29 2352 }
c896fe29
FB
2353#ifndef NDEBUG
2354 check_regs(s);
2355#endif
2356 }
c45cb8bb 2357
b76f0d8c
YL
2358 /* Generate TB finalization at the end of block */
2359 tcg_out_tb_finalize(s);
c896fe29
FB
2360 return -1;
2361}
2362
1813e175 2363int tcg_gen_code(TCGContext *s, tcg_insn_unit *gen_code_buf)
c896fe29
FB
2364{
2365#ifdef CONFIG_PROFILER
2366 {
c896fe29 2367 int n;
c45cb8bb
RH
2368
2369 n = s->gen_last_op_idx + 1;
a23a9ec6 2370 s->op_count += n;
c45cb8bb 2371 if (n > s->op_count_max) {
a23a9ec6 2372 s->op_count_max = n;
c45cb8bb 2373 }
a23a9ec6 2374
c45cb8bb
RH
2375 n = s->nb_temps;
2376 s->temp_count += n;
2377 if (n > s->temp_count_max) {
2378 s->temp_count_max = n;
2379 }
c896fe29
FB
2380 }
2381#endif
2382
2ba1eeb6 2383 tcg_gen_code_common(s, gen_code_buf, -1);
c896fe29
FB
2384
2385 /* flush instruction cache */
1813e175 2386 flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);
2aeabc08 2387
1813e175 2388 return tcg_current_code_size(s);
c896fe29
FB
2389}
2390
2ba1eeb6 2391/* Return the index of the micro operation such as the pc after is <
623e265c
PB
2392 offset bytes from the start of the TB. The contents of gen_code_buf must
2393 not be changed, though writing the same values is ok.
2394 Return -1 if not found. */
1813e175
RH
2395int tcg_gen_code_search_pc(TCGContext *s, tcg_insn_unit *gen_code_buf,
2396 long offset)
c896fe29 2397{
623e265c 2398 return tcg_gen_code_common(s, gen_code_buf, offset);
c896fe29 2399}
a23a9ec6
FB
2400
2401#ifdef CONFIG_PROFILER
405cf9ff 2402void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
a23a9ec6
FB
2403{
2404 TCGContext *s = &tcg_ctx;
2405 int64_t tot;
2406
2407 tot = s->interm_time + s->code_time;
2408 cpu_fprintf(f, "JIT cycles %" PRId64 " (%0.3f s at 2.4 GHz)\n",
2409 tot, tot / 2.4e9);
2410 cpu_fprintf(f, "translated TBs %" PRId64 " (aborted=%" PRId64 " %0.1f%%)\n",
2411 s->tb_count,
2412 s->tb_count1 - s->tb_count,
2413 s->tb_count1 ? (double)(s->tb_count1 - s->tb_count) / s->tb_count1 * 100.0 : 0);
2414 cpu_fprintf(f, "avg ops/TB %0.1f max=%d\n",
2415 s->tb_count ? (double)s->op_count / s->tb_count : 0, s->op_count_max);
a23a9ec6
FB
2416 cpu_fprintf(f, "deleted ops/TB %0.2f\n",
2417 s->tb_count ?
2418 (double)s->del_op_count / s->tb_count : 0);
2419 cpu_fprintf(f, "avg temps/TB %0.2f max=%d\n",
2420 s->tb_count ?
2421 (double)s->temp_count / s->tb_count : 0,
2422 s->temp_count_max);
2423
2424 cpu_fprintf(f, "cycles/op %0.1f\n",
2425 s->op_count ? (double)tot / s->op_count : 0);
2426 cpu_fprintf(f, "cycles/in byte %0.1f\n",
2427 s->code_in_len ? (double)tot / s->code_in_len : 0);
2428 cpu_fprintf(f, "cycles/out byte %0.1f\n",
2429 s->code_out_len ? (double)tot / s->code_out_len : 0);
2430 if (tot == 0)
2431 tot = 1;
2432 cpu_fprintf(f, " gen_interm time %0.1f%%\n",
2433 (double)s->interm_time / tot * 100.0);
2434 cpu_fprintf(f, " gen_code time %0.1f%%\n",
2435 (double)s->code_time / tot * 100.0);
c5cc28ff
AJ
2436 cpu_fprintf(f, "optim./code time %0.1f%%\n",
2437 (double)s->opt_time / (s->code_time ? s->code_time : 1)
2438 * 100.0);
a23a9ec6
FB
2439 cpu_fprintf(f, "liveness/code time %0.1f%%\n",
2440 (double)s->la_time / (s->code_time ? s->code_time : 1) * 100.0);
2441 cpu_fprintf(f, "cpu_restore count %" PRId64 "\n",
2442 s->restore_count);
2443 cpu_fprintf(f, " avg cycles %0.1f\n",
2444 s->restore_count ? (double)s->restore_time / s->restore_count : 0);
a23a9ec6
FB
2445}
2446#else
405cf9ff 2447void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
a23a9ec6 2448{
24bf7b3a 2449 cpu_fprintf(f, "[TCG profiler not compiled]\n");
a23a9ec6
FB
2450}
2451#endif
813da627
RH
2452
2453#ifdef ELF_HOST_MACHINE
5872bbf2
RH
2454/* In order to use this feature, the backend needs to do three things:
2455
2456 (1) Define ELF_HOST_MACHINE to indicate both what value to
2457 put into the ELF image and to indicate support for the feature.
2458
2459 (2) Define tcg_register_jit. This should create a buffer containing
2460 the contents of a .debug_frame section that describes the post-
2461 prologue unwind info for the tcg machine.
2462
2463 (3) Call tcg_register_jit_int, with the constructed .debug_frame.
2464*/
813da627
RH
2465
2466/* Begin GDB interface. THE FOLLOWING MUST MATCH GDB DOCS. */
2467typedef enum {
2468 JIT_NOACTION = 0,
2469 JIT_REGISTER_FN,
2470 JIT_UNREGISTER_FN
2471} jit_actions_t;
2472
2473struct jit_code_entry {
2474 struct jit_code_entry *next_entry;
2475 struct jit_code_entry *prev_entry;
2476 const void *symfile_addr;
2477 uint64_t symfile_size;
2478};
2479
2480struct jit_descriptor {
2481 uint32_t version;
2482 uint32_t action_flag;
2483 struct jit_code_entry *relevant_entry;
2484 struct jit_code_entry *first_entry;
2485};
2486
2487void __jit_debug_register_code(void) __attribute__((noinline));
2488void __jit_debug_register_code(void)
2489{
2490 asm("");
2491}
2492
2493/* Must statically initialize the version, because GDB may check
2494 the version before we can set it. */
2495struct jit_descriptor __jit_debug_descriptor = { 1, 0, 0, 0 };
2496
2497/* End GDB interface. */
2498
2499static int find_string(const char *strtab, const char *str)
2500{
2501 const char *p = strtab + 1;
2502
2503 while (1) {
2504 if (strcmp(p, str) == 0) {
2505 return p - strtab;
2506 }
2507 p += strlen(p) + 1;
2508 }
2509}
2510
5872bbf2 2511static void tcg_register_jit_int(void *buf_ptr, size_t buf_size,
2c90784a
RH
2512 const void *debug_frame,
2513 size_t debug_frame_size)
813da627 2514{
5872bbf2
RH
2515 struct __attribute__((packed)) DebugInfo {
2516 uint32_t len;
2517 uint16_t version;
2518 uint32_t abbrev;
2519 uint8_t ptr_size;
2520 uint8_t cu_die;
2521 uint16_t cu_lang;
2522 uintptr_t cu_low_pc;
2523 uintptr_t cu_high_pc;
2524 uint8_t fn_die;
2525 char fn_name[16];
2526 uintptr_t fn_low_pc;
2527 uintptr_t fn_high_pc;
2528 uint8_t cu_eoc;
2529 };
813da627
RH
2530
2531 struct ElfImage {
2532 ElfW(Ehdr) ehdr;
2533 ElfW(Phdr) phdr;
5872bbf2
RH
2534 ElfW(Shdr) shdr[7];
2535 ElfW(Sym) sym[2];
2536 struct DebugInfo di;
2537 uint8_t da[24];
2538 char str[80];
2539 };
2540
2541 struct ElfImage *img;
2542
2543 static const struct ElfImage img_template = {
2544 .ehdr = {
2545 .e_ident[EI_MAG0] = ELFMAG0,
2546 .e_ident[EI_MAG1] = ELFMAG1,
2547 .e_ident[EI_MAG2] = ELFMAG2,
2548 .e_ident[EI_MAG3] = ELFMAG3,
2549 .e_ident[EI_CLASS] = ELF_CLASS,
2550 .e_ident[EI_DATA] = ELF_DATA,
2551 .e_ident[EI_VERSION] = EV_CURRENT,
2552 .e_type = ET_EXEC,
2553 .e_machine = ELF_HOST_MACHINE,
2554 .e_version = EV_CURRENT,
2555 .e_phoff = offsetof(struct ElfImage, phdr),
2556 .e_shoff = offsetof(struct ElfImage, shdr),
2557 .e_ehsize = sizeof(ElfW(Shdr)),
2558 .e_phentsize = sizeof(ElfW(Phdr)),
2559 .e_phnum = 1,
2560 .e_shentsize = sizeof(ElfW(Shdr)),
2561 .e_shnum = ARRAY_SIZE(img->shdr),
2562 .e_shstrndx = ARRAY_SIZE(img->shdr) - 1,
abbb3eae
RH
2563#ifdef ELF_HOST_FLAGS
2564 .e_flags = ELF_HOST_FLAGS,
2565#endif
2566#ifdef ELF_OSABI
2567 .e_ident[EI_OSABI] = ELF_OSABI,
2568#endif
5872bbf2
RH
2569 },
2570 .phdr = {
2571 .p_type = PT_LOAD,
2572 .p_flags = PF_X,
2573 },
2574 .shdr = {
2575 [0] = { .sh_type = SHT_NULL },
2576 /* Trick: The contents of code_gen_buffer are not present in
2577 this fake ELF file; that got allocated elsewhere. Therefore
2578 we mark .text as SHT_NOBITS (similar to .bss) so that readers
2579 will not look for contents. We can record any address. */
2580 [1] = { /* .text */
2581 .sh_type = SHT_NOBITS,
2582 .sh_flags = SHF_EXECINSTR | SHF_ALLOC,
2583 },
2584 [2] = { /* .debug_info */
2585 .sh_type = SHT_PROGBITS,
2586 .sh_offset = offsetof(struct ElfImage, di),
2587 .sh_size = sizeof(struct DebugInfo),
2588 },
2589 [3] = { /* .debug_abbrev */
2590 .sh_type = SHT_PROGBITS,
2591 .sh_offset = offsetof(struct ElfImage, da),
2592 .sh_size = sizeof(img->da),
2593 },
2594 [4] = { /* .debug_frame */
2595 .sh_type = SHT_PROGBITS,
2596 .sh_offset = sizeof(struct ElfImage),
2597 },
2598 [5] = { /* .symtab */
2599 .sh_type = SHT_SYMTAB,
2600 .sh_offset = offsetof(struct ElfImage, sym),
2601 .sh_size = sizeof(img->sym),
2602 .sh_info = 1,
2603 .sh_link = ARRAY_SIZE(img->shdr) - 1,
2604 .sh_entsize = sizeof(ElfW(Sym)),
2605 },
2606 [6] = { /* .strtab */
2607 .sh_type = SHT_STRTAB,
2608 .sh_offset = offsetof(struct ElfImage, str),
2609 .sh_size = sizeof(img->str),
2610 }
2611 },
2612 .sym = {
2613 [1] = { /* code_gen_buffer */
2614 .st_info = ELF_ST_INFO(STB_GLOBAL, STT_FUNC),
2615 .st_shndx = 1,
2616 }
2617 },
2618 .di = {
2619 .len = sizeof(struct DebugInfo) - 4,
2620 .version = 2,
2621 .ptr_size = sizeof(void *),
2622 .cu_die = 1,
2623 .cu_lang = 0x8001, /* DW_LANG_Mips_Assembler */
2624 .fn_die = 2,
2625 .fn_name = "code_gen_buffer"
2626 },
2627 .da = {
2628 1, /* abbrev number (the cu) */
2629 0x11, 1, /* DW_TAG_compile_unit, has children */
2630 0x13, 0x5, /* DW_AT_language, DW_FORM_data2 */
2631 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2632 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2633 0, 0, /* end of abbrev */
2634 2, /* abbrev number (the fn) */
2635 0x2e, 0, /* DW_TAG_subprogram, no children */
2636 0x3, 0x8, /* DW_AT_name, DW_FORM_string */
2637 0x11, 0x1, /* DW_AT_low_pc, DW_FORM_addr */
2638 0x12, 0x1, /* DW_AT_high_pc, DW_FORM_addr */
2639 0, 0, /* end of abbrev */
2640 0 /* no more abbrev */
2641 },
2642 .str = "\0" ".text\0" ".debug_info\0" ".debug_abbrev\0"
2643 ".debug_frame\0" ".symtab\0" ".strtab\0" "code_gen_buffer",
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2644 };
2645
2646 /* We only need a single jit entry; statically allocate it. */
2647 static struct jit_code_entry one_entry;
2648
5872bbf2 2649 uintptr_t buf = (uintptr_t)buf_ptr;
813da627 2650 size_t img_size = sizeof(struct ElfImage) + debug_frame_size;
2c90784a 2651 DebugFrameHeader *dfh;
813da627 2652
5872bbf2
RH
2653 img = g_malloc(img_size);
2654 *img = img_template;
813da627 2655
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RH
2656 img->phdr.p_vaddr = buf;
2657 img->phdr.p_paddr = buf;
2658 img->phdr.p_memsz = buf_size;
813da627 2659
813da627 2660 img->shdr[1].sh_name = find_string(img->str, ".text");
5872bbf2 2661 img->shdr[1].sh_addr = buf;
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2662 img->shdr[1].sh_size = buf_size;
2663
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RH
2664 img->shdr[2].sh_name = find_string(img->str, ".debug_info");
2665 img->shdr[3].sh_name = find_string(img->str, ".debug_abbrev");
2666
2667 img->shdr[4].sh_name = find_string(img->str, ".debug_frame");
2668 img->shdr[4].sh_size = debug_frame_size;
2669
2670 img->shdr[5].sh_name = find_string(img->str, ".symtab");
2671 img->shdr[6].sh_name = find_string(img->str, ".strtab");
2672
2673 img->sym[1].st_name = find_string(img->str, "code_gen_buffer");
2674 img->sym[1].st_value = buf;
2675 img->sym[1].st_size = buf_size;
813da627 2676
5872bbf2 2677 img->di.cu_low_pc = buf;
45aba097 2678 img->di.cu_high_pc = buf + buf_size;
5872bbf2 2679 img->di.fn_low_pc = buf;
45aba097 2680 img->di.fn_high_pc = buf + buf_size;
813da627 2681
2c90784a
RH
2682 dfh = (DebugFrameHeader *)(img + 1);
2683 memcpy(dfh, debug_frame, debug_frame_size);
2684 dfh->fde.func_start = buf;
2685 dfh->fde.func_len = buf_size;
2686
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2687#ifdef DEBUG_JIT
2688 /* Enable this block to be able to debug the ELF image file creation.
2689 One can use readelf, objdump, or other inspection utilities. */
2690 {
2691 FILE *f = fopen("/tmp/qemu.jit", "w+b");
2692 if (f) {
5872bbf2 2693 if (fwrite(img, img_size, 1, f) != img_size) {
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2694 /* Avoid stupid unused return value warning for fwrite. */
2695 }
2696 fclose(f);
2697 }
2698 }
2699#endif
2700
2701 one_entry.symfile_addr = img;
2702 one_entry.symfile_size = img_size;
2703
2704 __jit_debug_descriptor.action_flag = JIT_REGISTER_FN;
2705 __jit_debug_descriptor.relevant_entry = &one_entry;
2706 __jit_debug_descriptor.first_entry = &one_entry;
2707 __jit_debug_register_code();
2708}
2709#else
5872bbf2
RH
2710/* No support for the feature. Provide the entry point expected by exec.c,
2711 and implement the internal function we declared earlier. */
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2712
2713static void tcg_register_jit_int(void *buf, size_t size,
2c90784a
RH
2714 const void *debug_frame,
2715 size_t debug_frame_size)
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2716{
2717}
2718
2719void tcg_register_jit(void *buf, size_t buf_size)
2720{
2721}
2722#endif /* ELF_HOST_MACHINE */