]>
Commit | Line | Data |
---|---|---|
c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e58eb534 RH |
24 | |
25 | #ifndef TCG_H | |
26 | #define TCG_H | |
27 | ||
f8393946 | 28 | #include "qemu-common.h" |
33c11879 | 29 | #include "cpu.h" |
00f6da6a | 30 | #include "exec/tb-context.h" |
0ec9eabc | 31 | #include "qemu/bitops.h" |
78cd7b83 RH |
32 | #include "tcg-target.h" |
33 | ||
00f6da6a PB |
34 | /* XXX: make safe guess about sizes */ |
35 | #define MAX_OP_PER_INSTR 266 | |
36 | ||
37 | #if HOST_LONG_BITS == 32 | |
38 | #define MAX_OPC_PARAM_PER_ARG 2 | |
39 | #else | |
40 | #define MAX_OPC_PARAM_PER_ARG 1 | |
41 | #endif | |
42 | #define MAX_OPC_PARAM_IARGS 5 | |
43 | #define MAX_OPC_PARAM_OARGS 1 | |
44 | #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS) | |
45 | ||
46 | /* A Call op needs up to 4 + 2N parameters on 32-bit archs, | |
47 | * and up to 4 + N parameters on 64-bit archs | |
48 | * (N = number of input arguments + output arguments). */ | |
49 | #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) | |
50 | #define OPC_BUF_SIZE 640 | |
51 | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) | |
52 | ||
53 | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM) | |
54 | ||
6e0b0730 PC |
55 | #define CPU_TEMP_BUF_NLONGS 128 |
56 | ||
78cd7b83 RH |
57 | /* Default target word size to pointer size. */ |
58 | #ifndef TCG_TARGET_REG_BITS | |
59 | # if UINTPTR_MAX == UINT32_MAX | |
60 | # define TCG_TARGET_REG_BITS 32 | |
61 | # elif UINTPTR_MAX == UINT64_MAX | |
62 | # define TCG_TARGET_REG_BITS 64 | |
63 | # else | |
64 | # error Unknown pointer size for tcg target | |
65 | # endif | |
817b838e SW |
66 | #endif |
67 | ||
c896fe29 FB |
68 | #if TCG_TARGET_REG_BITS == 32 |
69 | typedef int32_t tcg_target_long; | |
70 | typedef uint32_t tcg_target_ulong; | |
71 | #define TCG_PRIlx PRIx32 | |
72 | #define TCG_PRIld PRId32 | |
73 | #elif TCG_TARGET_REG_BITS == 64 | |
74 | typedef int64_t tcg_target_long; | |
75 | typedef uint64_t tcg_target_ulong; | |
76 | #define TCG_PRIlx PRIx64 | |
77 | #define TCG_PRIld PRId64 | |
78 | #else | |
79 | #error unsupported | |
80 | #endif | |
81 | ||
82 | #if TCG_TARGET_NB_REGS <= 32 | |
83 | typedef uint32_t TCGRegSet; | |
84 | #elif TCG_TARGET_NB_REGS <= 64 | |
85 | typedef uint64_t TCGRegSet; | |
86 | #else | |
87 | #error unsupported | |
88 | #endif | |
89 | ||
25c4d9cc | 90 | #if TCG_TARGET_REG_BITS == 32 |
e6a72734 | 91 | /* Turn some undef macros into false macros. */ |
609ad705 RH |
92 | #define TCG_TARGET_HAS_extrl_i64_i32 0 |
93 | #define TCG_TARGET_HAS_extrh_i64_i32 0 | |
25c4d9cc | 94 | #define TCG_TARGET_HAS_div_i64 0 |
ca675f46 | 95 | #define TCG_TARGET_HAS_rem_i64 0 |
25c4d9cc RH |
96 | #define TCG_TARGET_HAS_div2_i64 0 |
97 | #define TCG_TARGET_HAS_rot_i64 0 | |
98 | #define TCG_TARGET_HAS_ext8s_i64 0 | |
99 | #define TCG_TARGET_HAS_ext16s_i64 0 | |
100 | #define TCG_TARGET_HAS_ext32s_i64 0 | |
101 | #define TCG_TARGET_HAS_ext8u_i64 0 | |
102 | #define TCG_TARGET_HAS_ext16u_i64 0 | |
103 | #define TCG_TARGET_HAS_ext32u_i64 0 | |
104 | #define TCG_TARGET_HAS_bswap16_i64 0 | |
105 | #define TCG_TARGET_HAS_bswap32_i64 0 | |
106 | #define TCG_TARGET_HAS_bswap64_i64 0 | |
107 | #define TCG_TARGET_HAS_neg_i64 0 | |
108 | #define TCG_TARGET_HAS_not_i64 0 | |
109 | #define TCG_TARGET_HAS_andc_i64 0 | |
110 | #define TCG_TARGET_HAS_orc_i64 0 | |
111 | #define TCG_TARGET_HAS_eqv_i64 0 | |
112 | #define TCG_TARGET_HAS_nand_i64 0 | |
113 | #define TCG_TARGET_HAS_nor_i64 0 | |
0e28d006 RH |
114 | #define TCG_TARGET_HAS_clz_i64 0 |
115 | #define TCG_TARGET_HAS_ctz_i64 0 | |
a768e4e9 | 116 | #define TCG_TARGET_HAS_ctpop_i64 0 |
25c4d9cc | 117 | #define TCG_TARGET_HAS_deposit_i64 0 |
7ec8bab3 RH |
118 | #define TCG_TARGET_HAS_extract_i64 0 |
119 | #define TCG_TARGET_HAS_sextract_i64 0 | |
ffc5ea09 | 120 | #define TCG_TARGET_HAS_movcond_i64 0 |
d7156f7c RH |
121 | #define TCG_TARGET_HAS_add2_i64 0 |
122 | #define TCG_TARGET_HAS_sub2_i64 0 | |
123 | #define TCG_TARGET_HAS_mulu2_i64 0 | |
4d3203fd | 124 | #define TCG_TARGET_HAS_muls2_i64 0 |
03271524 RH |
125 | #define TCG_TARGET_HAS_muluh_i64 0 |
126 | #define TCG_TARGET_HAS_mulsh_i64 0 | |
e6a72734 RH |
127 | /* Turn some undef macros into true macros. */ |
128 | #define TCG_TARGET_HAS_add2_i32 1 | |
129 | #define TCG_TARGET_HAS_sub2_i32 1 | |
25c4d9cc RH |
130 | #endif |
131 | ||
a4773324 JK |
132 | #ifndef TCG_TARGET_deposit_i32_valid |
133 | #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 | |
134 | #endif | |
135 | #ifndef TCG_TARGET_deposit_i64_valid | |
136 | #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 | |
137 | #endif | |
7ec8bab3 RH |
138 | #ifndef TCG_TARGET_extract_i32_valid |
139 | #define TCG_TARGET_extract_i32_valid(ofs, len) 1 | |
140 | #endif | |
141 | #ifndef TCG_TARGET_extract_i64_valid | |
142 | #define TCG_TARGET_extract_i64_valid(ofs, len) 1 | |
143 | #endif | |
a4773324 | 144 | |
25c4d9cc RH |
145 | /* Only one of DIV or DIV2 should be defined. */ |
146 | #if defined(TCG_TARGET_HAS_div_i32) | |
147 | #define TCG_TARGET_HAS_div2_i32 0 | |
148 | #elif defined(TCG_TARGET_HAS_div2_i32) | |
149 | #define TCG_TARGET_HAS_div_i32 0 | |
ca675f46 | 150 | #define TCG_TARGET_HAS_rem_i32 0 |
25c4d9cc RH |
151 | #endif |
152 | #if defined(TCG_TARGET_HAS_div_i64) | |
153 | #define TCG_TARGET_HAS_div2_i64 0 | |
154 | #elif defined(TCG_TARGET_HAS_div2_i64) | |
155 | #define TCG_TARGET_HAS_div_i64 0 | |
ca675f46 | 156 | #define TCG_TARGET_HAS_rem_i64 0 |
25c4d9cc RH |
157 | #endif |
158 | ||
df9ebea5 RH |
159 | /* For 32-bit targets, some sort of unsigned widening multiply is required. */ |
160 | #if TCG_TARGET_REG_BITS == 32 \ | |
161 | && !(defined(TCG_TARGET_HAS_mulu2_i32) \ | |
162 | || defined(TCG_TARGET_HAS_muluh_i32)) | |
163 | # error "Missing unsigned widening multiply" | |
164 | #endif | |
165 | ||
9aef40ed RH |
166 | #ifndef TARGET_INSN_START_EXTRA_WORDS |
167 | # define TARGET_INSN_START_WORDS 1 | |
168 | #else | |
169 | # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) | |
170 | #endif | |
171 | ||
a9751609 | 172 | typedef enum TCGOpcode { |
c61aaf7a | 173 | #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, |
c896fe29 FB |
174 | #include "tcg-opc.h" |
175 | #undef DEF | |
176 | NB_OPS, | |
a9751609 | 177 | } TCGOpcode; |
c896fe29 FB |
178 | |
179 | #define tcg_regset_clear(d) (d) = 0 | |
180 | #define tcg_regset_set(d, s) (d) = (s) | |
181 | #define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg) | |
7d301752 AJ |
182 | #define tcg_regset_set_reg(d, r) (d) |= 1L << (r) |
183 | #define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r)) | |
c896fe29 FB |
184 | #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) |
185 | #define tcg_regset_or(d, a, b) (d) = (a) | (b) | |
186 | #define tcg_regset_and(d, a, b) (d) = (a) & (b) | |
187 | #define tcg_regset_andnot(d, a, b) (d) = (a) & ~(b) | |
188 | #define tcg_regset_not(d, a) (d) = ~(a) | |
189 | ||
1813e175 | 190 | #ifndef TCG_TARGET_INSN_UNIT_SIZE |
5053361b RH |
191 | # error "Missing TCG_TARGET_INSN_UNIT_SIZE" |
192 | #elif TCG_TARGET_INSN_UNIT_SIZE == 1 | |
1813e175 RH |
193 | typedef uint8_t tcg_insn_unit; |
194 | #elif TCG_TARGET_INSN_UNIT_SIZE == 2 | |
195 | typedef uint16_t tcg_insn_unit; | |
196 | #elif TCG_TARGET_INSN_UNIT_SIZE == 4 | |
197 | typedef uint32_t tcg_insn_unit; | |
198 | #elif TCG_TARGET_INSN_UNIT_SIZE == 8 | |
199 | typedef uint64_t tcg_insn_unit; | |
200 | #else | |
201 | /* The port better have done this. */ | |
202 | #endif | |
203 | ||
204 | ||
8bff06a0 | 205 | #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS |
1f00b27f SS |
206 | # define tcg_debug_assert(X) do { assert(X); } while (0) |
207 | #elif QEMU_GNUC_PREREQ(4, 5) | |
208 | # define tcg_debug_assert(X) \ | |
209 | do { if (!(X)) { __builtin_unreachable(); } } while (0) | |
210 | #else | |
211 | # define tcg_debug_assert(X) do { (void)(X); } while (0) | |
212 | #endif | |
213 | ||
c896fe29 FB |
214 | typedef struct TCGRelocation { |
215 | struct TCGRelocation *next; | |
216 | int type; | |
1813e175 | 217 | tcg_insn_unit *ptr; |
2ba7fae2 | 218 | intptr_t addend; |
c896fe29 FB |
219 | } TCGRelocation; |
220 | ||
221 | typedef struct TCGLabel { | |
51e3972c RH |
222 | unsigned has_value : 1; |
223 | unsigned id : 31; | |
c896fe29 | 224 | union { |
2ba7fae2 | 225 | uintptr_t value; |
1813e175 | 226 | tcg_insn_unit *value_ptr; |
c896fe29 FB |
227 | TCGRelocation *first_reloc; |
228 | } u; | |
229 | } TCGLabel; | |
230 | ||
231 | typedef struct TCGPool { | |
232 | struct TCGPool *next; | |
c44f945a BS |
233 | int size; |
234 | uint8_t data[0] __attribute__ ((aligned)); | |
c896fe29 FB |
235 | } TCGPool; |
236 | ||
237 | #define TCG_POOL_CHUNK_SIZE 32768 | |
238 | ||
c4071c90 | 239 | #define TCG_MAX_TEMPS 512 |
190ce7fb | 240 | #define TCG_MAX_INSNS 512 |
c896fe29 | 241 | |
b03cce8e FB |
242 | /* when the size of the arguments of a called function is smaller than |
243 | this value, they are statically allocated in the TB stack frame */ | |
244 | #define TCG_STATIC_CALL_ARGS_SIZE 128 | |
245 | ||
c02244a5 RH |
246 | typedef enum TCGType { |
247 | TCG_TYPE_I32, | |
248 | TCG_TYPE_I64, | |
249 | TCG_TYPE_COUNT, /* number of different types */ | |
c896fe29 | 250 | |
3b6dac34 | 251 | /* An alias for the size of the host register. */ |
c896fe29 | 252 | #if TCG_TARGET_REG_BITS == 32 |
3b6dac34 | 253 | TCG_TYPE_REG = TCG_TYPE_I32, |
c02244a5 | 254 | #else |
3b6dac34 | 255 | TCG_TYPE_REG = TCG_TYPE_I64, |
c02244a5 | 256 | #endif |
3b6dac34 | 257 | |
d289837e RH |
258 | /* An alias for the size of the native pointer. */ |
259 | #if UINTPTR_MAX == UINT32_MAX | |
260 | TCG_TYPE_PTR = TCG_TYPE_I32, | |
261 | #else | |
262 | TCG_TYPE_PTR = TCG_TYPE_I64, | |
263 | #endif | |
3b6dac34 RH |
264 | |
265 | /* An alias for the size of the target "long", aka register. */ | |
c02244a5 RH |
266 | #if TARGET_LONG_BITS == 64 |
267 | TCG_TYPE_TL = TCG_TYPE_I64, | |
c896fe29 | 268 | #else |
c02244a5 | 269 | TCG_TYPE_TL = TCG_TYPE_I32, |
c896fe29 | 270 | #endif |
c02244a5 | 271 | } TCGType; |
c896fe29 | 272 | |
6c5f4ead RH |
273 | /* Constants for qemu_ld and qemu_st for the Memory Operation field. */ |
274 | typedef enum TCGMemOp { | |
275 | MO_8 = 0, | |
276 | MO_16 = 1, | |
277 | MO_32 = 2, | |
278 | MO_64 = 3, | |
279 | MO_SIZE = 3, /* Mask for the above. */ | |
280 | ||
281 | MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */ | |
282 | ||
283 | MO_BSWAP = 8, /* Host reverse endian. */ | |
284 | #ifdef HOST_WORDS_BIGENDIAN | |
285 | MO_LE = MO_BSWAP, | |
286 | MO_BE = 0, | |
287 | #else | |
288 | MO_LE = 0, | |
289 | MO_BE = MO_BSWAP, | |
290 | #endif | |
291 | #ifdef TARGET_WORDS_BIGENDIAN | |
292 | MO_TE = MO_BE, | |
293 | #else | |
294 | MO_TE = MO_LE, | |
295 | #endif | |
296 | ||
dfb36305 | 297 | /* MO_UNALN accesses are never checked for alignment. |
1f00b27f SS |
298 | * MO_ALIGN accesses will result in a call to the CPU's |
299 | * do_unaligned_access hook if the guest address is not aligned. | |
300 | * The default depends on whether the target CPU defines ALIGNED_ONLY. | |
85aa8081 | 301 | * |
1f00b27f SS |
302 | * Some architectures (e.g. ARMv8) need the address which is aligned |
303 | * to a size more than the size of the memory access. | |
85aa8081 RH |
304 | * Some architectures (e.g. SPARCv9) need an address which is aligned, |
305 | * but less strictly than the natural alignment. | |
306 | * | |
307 | * MO_ALIGN supposes the alignment size is the size of a memory access. | |
308 | * | |
1f00b27f | 309 | * There are three options: |
1f00b27f | 310 | * - unaligned access permitted (MO_UNALN). |
85aa8081 RH |
311 | * - an alignment to the size of an access (MO_ALIGN); |
312 | * - an alignment to a specified size, which may be more or less than | |
313 | * the access size (MO_ALIGN_x where 'x' is a size in bytes); | |
1f00b27f SS |
314 | */ |
315 | MO_ASHIFT = 4, | |
316 | MO_AMASK = 7 << MO_ASHIFT, | |
dfb36305 RH |
317 | #ifdef ALIGNED_ONLY |
318 | MO_ALIGN = 0, | |
319 | MO_UNALN = MO_AMASK, | |
320 | #else | |
321 | MO_ALIGN = MO_AMASK, | |
322 | MO_UNALN = 0, | |
323 | #endif | |
1f00b27f SS |
324 | MO_ALIGN_2 = 1 << MO_ASHIFT, |
325 | MO_ALIGN_4 = 2 << MO_ASHIFT, | |
326 | MO_ALIGN_8 = 3 << MO_ASHIFT, | |
327 | MO_ALIGN_16 = 4 << MO_ASHIFT, | |
328 | MO_ALIGN_32 = 5 << MO_ASHIFT, | |
329 | MO_ALIGN_64 = 6 << MO_ASHIFT, | |
dfb36305 | 330 | |
6c5f4ead RH |
331 | /* Combinations of the above, for ease of use. */ |
332 | MO_UB = MO_8, | |
333 | MO_UW = MO_16, | |
334 | MO_UL = MO_32, | |
335 | MO_SB = MO_SIGN | MO_8, | |
336 | MO_SW = MO_SIGN | MO_16, | |
337 | MO_SL = MO_SIGN | MO_32, | |
338 | MO_Q = MO_64, | |
339 | ||
340 | MO_LEUW = MO_LE | MO_UW, | |
341 | MO_LEUL = MO_LE | MO_UL, | |
342 | MO_LESW = MO_LE | MO_SW, | |
343 | MO_LESL = MO_LE | MO_SL, | |
344 | MO_LEQ = MO_LE | MO_Q, | |
345 | ||
346 | MO_BEUW = MO_BE | MO_UW, | |
347 | MO_BEUL = MO_BE | MO_UL, | |
348 | MO_BESW = MO_BE | MO_SW, | |
349 | MO_BESL = MO_BE | MO_SL, | |
350 | MO_BEQ = MO_BE | MO_Q, | |
351 | ||
352 | MO_TEUW = MO_TE | MO_UW, | |
353 | MO_TEUL = MO_TE | MO_UL, | |
354 | MO_TESW = MO_TE | MO_SW, | |
355 | MO_TESL = MO_TE | MO_SL, | |
356 | MO_TEQ = MO_TE | MO_Q, | |
357 | ||
358 | MO_SSIZE = MO_SIZE | MO_SIGN, | |
359 | } TCGMemOp; | |
360 | ||
1f00b27f SS |
361 | /** |
362 | * get_alignment_bits | |
363 | * @memop: TCGMemOp value | |
364 | * | |
365 | * Extract the alignment size from the memop. | |
1f00b27f | 366 | */ |
85aa8081 | 367 | static inline unsigned get_alignment_bits(TCGMemOp memop) |
1f00b27f | 368 | { |
85aa8081 | 369 | unsigned a = memop & MO_AMASK; |
1f00b27f SS |
370 | |
371 | if (a == MO_UNALN) { | |
85aa8081 RH |
372 | /* No alignment required. */ |
373 | a = 0; | |
1f00b27f | 374 | } else if (a == MO_ALIGN) { |
85aa8081 RH |
375 | /* A natural alignment requirement. */ |
376 | a = memop & MO_SIZE; | |
1f00b27f | 377 | } else { |
85aa8081 RH |
378 | /* A specific alignment requirement. */ |
379 | a = a >> MO_ASHIFT; | |
1f00b27f SS |
380 | } |
381 | #if defined(CONFIG_SOFTMMU) | |
382 | /* The requested alignment cannot overlap the TLB flags. */ | |
85aa8081 | 383 | tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); |
1f00b27f | 384 | #endif |
85aa8081 | 385 | return a; |
1f00b27f SS |
386 | } |
387 | ||
c896fe29 FB |
388 | typedef tcg_target_ulong TCGArg; |
389 | ||
a40d4701 PM |
390 | /* Define type and accessor macros for TCG variables. |
391 | ||
392 | TCG variables are the inputs and outputs of TCG ops, as described | |
393 | in tcg/README. Target CPU front-end code uses these types to deal | |
394 | with TCG variables as it emits TCG code via the tcg_gen_* functions. | |
395 | They come in several flavours: | |
396 | * TCGv_i32 : 32 bit integer type | |
397 | * TCGv_i64 : 64 bit integer type | |
398 | * TCGv_ptr : a host pointer type | |
399 | * TCGv : an integer type the same size as target_ulong | |
400 | (an alias for either TCGv_i32 or TCGv_i64) | |
401 | The compiler's type checking will complain if you mix them | |
402 | up and pass the wrong sized TCGv to a function. | |
403 | ||
404 | Users of tcg_gen_* don't need to know about any of the internal | |
405 | details of these, and should treat them as opaque types. | |
406 | You won't be able to look inside them in a debugger either. | |
407 | ||
408 | Internal implementation details follow: | |
409 | ||
410 | Note that there is no definition of the structs TCGv_i32_d etc anywhere. | |
411 | This is deliberate, because the values we store in variables of type | |
412 | TCGv_i32 are not really pointers-to-structures. They're just small | |
413 | integers, but keeping them in pointer types like this means that the | |
414 | compiler will complain if you accidentally pass a TCGv_i32 to a | |
415 | function which takes a TCGv_i64, and so on. Only the internals of | |
416 | TCG need to care about the actual contents of the types, and they always | |
417 | box and unbox via the MAKE_TCGV_* and GET_TCGV_* functions. | |
418 | Converting to and from intptr_t rather than int reduces the number | |
419 | of sign-extension instructions that get implied on 64-bit hosts. */ | |
ac56dd48 | 420 | |
b6c73a6d RH |
421 | typedef struct TCGv_i32_d *TCGv_i32; |
422 | typedef struct TCGv_i64_d *TCGv_i64; | |
423 | typedef struct TCGv_ptr_d *TCGv_ptr; | |
1bcea73e | 424 | typedef TCGv_ptr TCGv_env; |
5d4e1a10 LV |
425 | #if TARGET_LONG_BITS == 32 |
426 | #define TCGv TCGv_i32 | |
427 | #elif TARGET_LONG_BITS == 64 | |
428 | #define TCGv TCGv_i64 | |
429 | #else | |
430 | #error Unhandled TARGET_LONG_BITS value | |
431 | #endif | |
ac56dd48 | 432 | |
b6c73a6d RH |
433 | static inline TCGv_i32 QEMU_ARTIFICIAL MAKE_TCGV_I32(intptr_t i) |
434 | { | |
435 | return (TCGv_i32)i; | |
436 | } | |
ac56dd48 | 437 | |
b6c73a6d | 438 | static inline TCGv_i64 QEMU_ARTIFICIAL MAKE_TCGV_I64(intptr_t i) |
ac56dd48 | 439 | { |
b6c73a6d RH |
440 | return (TCGv_i64)i; |
441 | } | |
ac56dd48 | 442 | |
b6c73a6d | 443 | static inline TCGv_ptr QEMU_ARTIFICIAL MAKE_TCGV_PTR(intptr_t i) |
a7812ae4 | 444 | { |
b6c73a6d RH |
445 | return (TCGv_ptr)i; |
446 | } | |
ac56dd48 | 447 | |
b6c73a6d RH |
448 | static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I32(TCGv_i32 t) |
449 | { | |
450 | return (intptr_t)t; | |
451 | } | |
ac56dd48 | 452 | |
b6c73a6d RH |
453 | static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I64(TCGv_i64 t) |
454 | { | |
455 | return (intptr_t)t; | |
456 | } | |
457 | ||
458 | static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t) | |
459 | { | |
460 | return (intptr_t)t; | |
461 | } | |
44e6acb0 | 462 | |
ac56dd48 | 463 | #if TCG_TARGET_REG_BITS == 32 |
b6c73a6d RH |
464 | #define TCGV_LOW(t) MAKE_TCGV_I32(GET_TCGV_I64(t)) |
465 | #define TCGV_HIGH(t) MAKE_TCGV_I32(GET_TCGV_I64(t) + 1) | |
ac56dd48 PB |
466 | #endif |
467 | ||
43e860ef AJ |
468 | #define TCGV_EQUAL_I32(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b)) |
469 | #define TCGV_EQUAL_I64(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b)) | |
c1de788a | 470 | #define TCGV_EQUAL_PTR(a, b) (GET_TCGV_PTR(a) == GET_TCGV_PTR(b)) |
43e860ef | 471 | |
a50f5b91 | 472 | /* Dummy definition to avoid compiler warnings. */ |
a7812ae4 PB |
473 | #define TCGV_UNUSED_I32(x) x = MAKE_TCGV_I32(-1) |
474 | #define TCGV_UNUSED_I64(x) x = MAKE_TCGV_I64(-1) | |
c1de788a | 475 | #define TCGV_UNUSED_PTR(x) x = MAKE_TCGV_PTR(-1) |
a50f5b91 | 476 | |
afcb92be RH |
477 | #define TCGV_IS_UNUSED_I32(x) (GET_TCGV_I32(x) == -1) |
478 | #define TCGV_IS_UNUSED_I64(x) (GET_TCGV_I64(x) == -1) | |
c1de788a | 479 | #define TCGV_IS_UNUSED_PTR(x) (GET_TCGV_PTR(x) == -1) |
afcb92be | 480 | |
c896fe29 | 481 | /* call flags */ |
78505279 AJ |
482 | /* Helper does not read globals (either directly or through an exception). It |
483 | implies TCG_CALL_NO_WRITE_GLOBALS. */ | |
484 | #define TCG_CALL_NO_READ_GLOBALS 0x0010 | |
485 | /* Helper does not write globals */ | |
486 | #define TCG_CALL_NO_WRITE_GLOBALS 0x0020 | |
487 | /* Helper can be safely suppressed if the return value is not used. */ | |
488 | #define TCG_CALL_NO_SIDE_EFFECTS 0x0040 | |
489 | ||
490 | /* convenience version of most used call flags */ | |
491 | #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS | |
492 | #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS | |
493 | #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS | |
494 | #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) | |
495 | #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) | |
496 | ||
39cf05d3 | 497 | /* used to align parameters */ |
a7812ae4 | 498 | #define TCG_CALL_DUMMY_TCGV MAKE_TCGV_I32(-1) |
39cf05d3 FB |
499 | #define TCG_CALL_DUMMY_ARG ((TCGArg)(-1)) |
500 | ||
f65e19bc PK |
501 | typedef enum { |
502 | /* Used to indicate the type of accesses on which ordering | |
503 | is to be ensured. Modeled after SPARC barriers. */ | |
504 | TCG_MO_LD_LD = 0x01, | |
505 | TCG_MO_ST_LD = 0x02, | |
506 | TCG_MO_LD_ST = 0x04, | |
507 | TCG_MO_ST_ST = 0x08, | |
508 | TCG_MO_ALL = 0x0F, /* OR of the above */ | |
509 | ||
510 | /* Used to indicate the kind of ordering which is to be ensured by the | |
511 | instruction. These types are derived from x86/aarch64 instructions. | |
512 | It should be noted that these are different from C11 semantics. */ | |
513 | TCG_BAR_LDAQ = 0x10, /* Following ops will not come forward */ | |
514 | TCG_BAR_STRL = 0x20, /* Previous ops will not be delayed */ | |
515 | TCG_BAR_SC = 0x30, /* No ops cross barrier; OR of the above */ | |
516 | } TCGBar; | |
517 | ||
a93cf9df SW |
518 | /* Conditions. Note that these are laid out for easy manipulation by |
519 | the functions below: | |
0aed257f RH |
520 | bit 0 is used for inverting; |
521 | bit 1 is signed, | |
522 | bit 2 is unsigned, | |
523 | bit 3 is used with bit 0 for swapping signed/unsigned. */ | |
c896fe29 | 524 | typedef enum { |
0aed257f RH |
525 | /* non-signed */ |
526 | TCG_COND_NEVER = 0 | 0 | 0 | 0, | |
527 | TCG_COND_ALWAYS = 0 | 0 | 0 | 1, | |
528 | TCG_COND_EQ = 8 | 0 | 0 | 0, | |
529 | TCG_COND_NE = 8 | 0 | 0 | 1, | |
530 | /* signed */ | |
531 | TCG_COND_LT = 0 | 0 | 2 | 0, | |
532 | TCG_COND_GE = 0 | 0 | 2 | 1, | |
533 | TCG_COND_LE = 8 | 0 | 2 | 0, | |
534 | TCG_COND_GT = 8 | 0 | 2 | 1, | |
c896fe29 | 535 | /* unsigned */ |
0aed257f RH |
536 | TCG_COND_LTU = 0 | 4 | 0 | 0, |
537 | TCG_COND_GEU = 0 | 4 | 0 | 1, | |
538 | TCG_COND_LEU = 8 | 4 | 0 | 0, | |
539 | TCG_COND_GTU = 8 | 4 | 0 | 1, | |
c896fe29 FB |
540 | } TCGCond; |
541 | ||
1c086220 | 542 | /* Invert the sense of the comparison. */ |
401d466d RH |
543 | static inline TCGCond tcg_invert_cond(TCGCond c) |
544 | { | |
545 | return (TCGCond)(c ^ 1); | |
546 | } | |
547 | ||
1c086220 RH |
548 | /* Swap the operands in a comparison. */ |
549 | static inline TCGCond tcg_swap_cond(TCGCond c) | |
550 | { | |
0aed257f | 551 | return c & 6 ? (TCGCond)(c ^ 9) : c; |
1c086220 RH |
552 | } |
553 | ||
d1e321b8 | 554 | /* Create an "unsigned" version of a "signed" comparison. */ |
ff44c2f3 RH |
555 | static inline TCGCond tcg_unsigned_cond(TCGCond c) |
556 | { | |
0aed257f | 557 | return c & 2 ? (TCGCond)(c ^ 6) : c; |
ff44c2f3 RH |
558 | } |
559 | ||
d1e321b8 | 560 | /* Must a comparison be considered unsigned? */ |
bcc66562 RH |
561 | static inline bool is_unsigned_cond(TCGCond c) |
562 | { | |
0aed257f | 563 | return (c & 4) != 0; |
bcc66562 RH |
564 | } |
565 | ||
d1e321b8 RH |
566 | /* Create a "high" version of a double-word comparison. |
567 | This removes equality from a LTE or GTE comparison. */ | |
568 | static inline TCGCond tcg_high_cond(TCGCond c) | |
569 | { | |
570 | switch (c) { | |
571 | case TCG_COND_GE: | |
572 | case TCG_COND_LE: | |
573 | case TCG_COND_GEU: | |
574 | case TCG_COND_LEU: | |
575 | return (TCGCond)(c ^ 8); | |
576 | default: | |
577 | return c; | |
578 | } | |
579 | } | |
580 | ||
00c8fa9f EC |
581 | typedef enum TCGTempVal { |
582 | TEMP_VAL_DEAD, | |
583 | TEMP_VAL_REG, | |
584 | TEMP_VAL_MEM, | |
585 | TEMP_VAL_CONST, | |
586 | } TCGTempVal; | |
c896fe29 | 587 | |
c896fe29 | 588 | typedef struct TCGTemp { |
b6638662 | 589 | TCGReg reg:8; |
00c8fa9f EC |
590 | TCGTempVal val_type:8; |
591 | TCGType base_type:8; | |
592 | TCGType type:8; | |
c896fe29 | 593 | unsigned int fixed_reg:1; |
b3915dbb RH |
594 | unsigned int indirect_reg:1; |
595 | unsigned int indirect_base:1; | |
c896fe29 FB |
596 | unsigned int mem_coherent:1; |
597 | unsigned int mem_allocated:1; | |
5225d669 | 598 | unsigned int temp_local:1; /* If true, the temp is saved across |
641d5fbe | 599 | basic blocks. Otherwise, it is not |
5225d669 | 600 | preserved across basic blocks. */ |
e8996ee0 | 601 | unsigned int temp_allocated:1; /* never used for code gen */ |
00c8fa9f EC |
602 | |
603 | tcg_target_long val; | |
b3a62939 | 604 | struct TCGTemp *mem_base; |
00c8fa9f | 605 | intptr_t mem_offset; |
c896fe29 FB |
606 | const char *name; |
607 | } TCGTemp; | |
608 | ||
c896fe29 FB |
609 | typedef struct TCGContext TCGContext; |
610 | ||
0ec9eabc RH |
611 | typedef struct TCGTempSet { |
612 | unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; | |
613 | } TCGTempSet; | |
614 | ||
a1b3c48d RH |
615 | /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding, |
616 | this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands. | |
617 | There are never more than 2 outputs, which means that we can store all | |
618 | dead + sync data within 16 bits. */ | |
619 | #define DEAD_ARG 4 | |
620 | #define SYNC_ARG 1 | |
621 | typedef uint16_t TCGLifeData; | |
622 | ||
bee158cb RH |
623 | /* The layout here is designed to avoid crossing of a 32-bit boundary. |
624 | If we do so, gcc adds padding, expanding the size to 12. */ | |
c45cb8bb | 625 | typedef struct TCGOp { |
bee158cb RH |
626 | TCGOpcode opc : 8; /* 8 */ |
627 | ||
628 | /* Index of the prev/next op, or 0 for the end of the list. */ | |
629 | unsigned prev : 10; /* 18 */ | |
630 | unsigned next : 10; /* 28 */ | |
c45cb8bb RH |
631 | |
632 | /* The number of out and in parameter for a call. */ | |
bee158cb RH |
633 | unsigned calli : 4; /* 32 */ |
634 | unsigned callo : 2; /* 34 */ | |
c45cb8bb | 635 | |
dcb8e758 | 636 | /* Index of the arguments for this op, or 0 for zero-operand ops. */ |
bee158cb | 637 | unsigned args : 14; /* 48 */ |
c45cb8bb | 638 | |
bee158cb RH |
639 | /* Lifetime data of the operands. */ |
640 | unsigned life : 16; /* 64 */ | |
c45cb8bb RH |
641 | } TCGOp; |
642 | ||
dcb8e758 RH |
643 | /* Make sure operands fit in the bitfields above. */ |
644 | QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); | |
bee158cb RH |
645 | QEMU_BUILD_BUG_ON(OPC_BUF_SIZE > (1 << 10)); |
646 | QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE > (1 << 14)); | |
dcb8e758 RH |
647 | |
648 | /* Make sure that we don't overflow 64 bits without noticing. */ | |
649 | QEMU_BUILD_BUG_ON(sizeof(TCGOp) > 8); | |
c45cb8bb | 650 | |
c896fe29 FB |
651 | struct TCGContext { |
652 | uint8_t *pool_cur, *pool_end; | |
4055299e | 653 | TCGPool *pool_first, *pool_current, *pool_first_large; |
c896fe29 | 654 | int nb_labels; |
c896fe29 FB |
655 | int nb_globals; |
656 | int nb_temps; | |
5a18407f | 657 | int nb_indirects; |
c896fe29 FB |
658 | |
659 | /* goto_tb support */ | |
1813e175 | 660 | tcg_insn_unit *code_buf; |
f309101c SF |
661 | uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */ |
662 | uint16_t *tb_jmp_insn_offset; /* tb->jmp_insn_offset if USE_DIRECT_JUMP */ | |
663 | uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_addr if !USE_DIRECT_JUMP */ | |
c896fe29 | 664 | |
c896fe29 | 665 | TCGRegSet reserved_regs; |
e2c6d1b4 RH |
666 | intptr_t current_frame_offset; |
667 | intptr_t frame_start; | |
668 | intptr_t frame_end; | |
b3a62939 | 669 | TCGTemp *frame_temp; |
c896fe29 | 670 | |
1813e175 | 671 | tcg_insn_unit *code_ptr; |
c896fe29 | 672 | |
6e085f72 | 673 | GHashTable *helpers; |
a23a9ec6 FB |
674 | |
675 | #ifdef CONFIG_PROFILER | |
676 | /* profiling info */ | |
677 | int64_t tb_count1; | |
678 | int64_t tb_count; | |
679 | int64_t op_count; /* total insn count */ | |
680 | int op_count_max; /* max insn per TB */ | |
681 | int64_t temp_count; | |
682 | int temp_count_max; | |
a23a9ec6 FB |
683 | int64_t del_op_count; |
684 | int64_t code_in_len; | |
685 | int64_t code_out_len; | |
fca8a500 | 686 | int64_t search_out_len; |
a23a9ec6 FB |
687 | int64_t interm_time; |
688 | int64_t code_time; | |
689 | int64_t la_time; | |
c5cc28ff | 690 | int64_t opt_time; |
a23a9ec6 FB |
691 | int64_t restore_count; |
692 | int64_t restore_time; | |
693 | #endif | |
27bfd83c PM |
694 | |
695 | #ifdef CONFIG_DEBUG_TCG | |
696 | int temps_in_use; | |
0a209d4b | 697 | int goto_tb_issue_mask; |
27bfd83c | 698 | #endif |
b76f0d8c | 699 | |
c45cb8bb RH |
700 | int gen_next_op_idx; |
701 | int gen_next_parm_idx; | |
8232a46a | 702 | |
1813e175 RH |
703 | /* Code generation. Note that we specifically do not use tcg_insn_unit |
704 | here, because there's too much arithmetic throughout that relies | |
705 | on addition and subtraction working on bytes. Rely on the GCC | |
706 | extension that allows arithmetic on void*. */ | |
0b0d3320 | 707 | int code_gen_max_blocks; |
1813e175 RH |
708 | void *code_gen_prologue; |
709 | void *code_gen_buffer; | |
0b0d3320 | 710 | size_t code_gen_buffer_size; |
1813e175 | 711 | void *code_gen_ptr; |
0b0d3320 | 712 | |
b125f9dc RH |
713 | /* Threshold to flush the translated code buffer. */ |
714 | void *code_gen_highwater; | |
715 | ||
5e5f07e0 EV |
716 | TBContext tb_ctx; |
717 | ||
7c255043 LV |
718 | /* Track which vCPU triggers events */ |
719 | CPUState *cpu; /* *_trans */ | |
720 | TCGv_env tcg_env; /* *_exec */ | |
721 | ||
ce151109 | 722 | /* The TCGBackendData structure is private to tcg-target.inc.c. */ |
9ecefc84 | 723 | struct TCGBackendData *be; |
c45cb8bb RH |
724 | |
725 | TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; | |
726 | TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ | |
727 | ||
f8b2f202 RH |
728 | /* Tells which temporary holds a given register. |
729 | It does not take into account fixed registers */ | |
730 | TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; | |
c45cb8bb RH |
731 | |
732 | TCGOp gen_op_buf[OPC_BUF_SIZE]; | |
733 | TCGArg gen_opparam_buf[OPPARAM_BUF_SIZE]; | |
734 | ||
fca8a500 RH |
735 | uint16_t gen_insn_end_off[TCG_MAX_INSNS]; |
736 | target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; | |
c896fe29 FB |
737 | }; |
738 | ||
739 | extern TCGContext tcg_ctx; | |
fdbc2b57 | 740 | extern bool parallel_cpus; |
c896fe29 | 741 | |
1d41478f EI |
742 | static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) |
743 | { | |
744 | int op_argi = tcg_ctx.gen_op_buf[op_idx].args; | |
745 | tcg_ctx.gen_opparam_buf[op_argi + arg] = v; | |
746 | } | |
747 | ||
fe700adb RH |
748 | /* The number of opcodes emitted so far. */ |
749 | static inline int tcg_op_buf_count(void) | |
750 | { | |
c45cb8bb | 751 | return tcg_ctx.gen_next_op_idx; |
fe700adb RH |
752 | } |
753 | ||
754 | /* Test for whether to terminate the TB for using too many opcodes. */ | |
755 | static inline bool tcg_op_buf_full(void) | |
756 | { | |
757 | return tcg_op_buf_count() >= OPC_MAX_SIZE; | |
758 | } | |
759 | ||
c896fe29 FB |
760 | /* pool based memory allocation */ |
761 | ||
7d7500d9 | 762 | /* tb_lock must be held for tcg_malloc_internal. */ |
c896fe29 FB |
763 | void *tcg_malloc_internal(TCGContext *s, int size); |
764 | void tcg_pool_reset(TCGContext *s); | |
c896fe29 | 765 | |
677ef623 FK |
766 | void tb_lock(void); |
767 | void tb_unlock(void); | |
768 | void tb_lock_reset(void); | |
769 | ||
7d7500d9 | 770 | /* Called with tb_lock held. */ |
c896fe29 FB |
771 | static inline void *tcg_malloc(int size) |
772 | { | |
773 | TCGContext *s = &tcg_ctx; | |
774 | uint8_t *ptr, *ptr_end; | |
775 | size = (size + sizeof(long) - 1) & ~(sizeof(long) - 1); | |
776 | ptr = s->pool_cur; | |
777 | ptr_end = ptr + size; | |
778 | if (unlikely(ptr_end > s->pool_end)) { | |
779 | return tcg_malloc_internal(&tcg_ctx, size); | |
780 | } else { | |
781 | s->pool_cur = ptr_end; | |
782 | return ptr; | |
783 | } | |
784 | } | |
785 | ||
786 | void tcg_context_init(TCGContext *s); | |
9002ec79 | 787 | void tcg_prologue_init(TCGContext *s); |
c896fe29 FB |
788 | void tcg_func_start(TCGContext *s); |
789 | ||
5bd2ec3d | 790 | int tcg_gen_code(TCGContext *s, TranslationBlock *tb); |
c896fe29 | 791 | |
b6638662 | 792 | void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); |
a7812ae4 | 793 | |
e1ccc054 RH |
794 | int tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *); |
795 | ||
b6638662 RH |
796 | TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name); |
797 | TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name); | |
e1ccc054 | 798 | |
a7812ae4 | 799 | TCGv_i32 tcg_temp_new_internal_i32(int temp_local); |
e1ccc054 RH |
800 | TCGv_i64 tcg_temp_new_internal_i64(int temp_local); |
801 | ||
802 | void tcg_temp_free_i32(TCGv_i32 arg); | |
803 | void tcg_temp_free_i64(TCGv_i64 arg); | |
804 | ||
e1ccc054 RH |
805 | static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, |
806 | const char *name) | |
807 | { | |
808 | int idx = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); | |
809 | return MAKE_TCGV_I32(idx); | |
810 | } | |
811 | ||
a7812ae4 PB |
812 | static inline TCGv_i32 tcg_temp_new_i32(void) |
813 | { | |
814 | return tcg_temp_new_internal_i32(0); | |
815 | } | |
e1ccc054 | 816 | |
a7812ae4 PB |
817 | static inline TCGv_i32 tcg_temp_local_new_i32(void) |
818 | { | |
819 | return tcg_temp_new_internal_i32(1); | |
820 | } | |
a7812ae4 | 821 | |
e1ccc054 RH |
822 | static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, |
823 | const char *name) | |
824 | { | |
825 | int idx = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); | |
826 | return MAKE_TCGV_I64(idx); | |
827 | } | |
828 | ||
a7812ae4 | 829 | static inline TCGv_i64 tcg_temp_new_i64(void) |
641d5fbe | 830 | { |
a7812ae4 | 831 | return tcg_temp_new_internal_i64(0); |
641d5fbe | 832 | } |
e1ccc054 | 833 | |
a7812ae4 | 834 | static inline TCGv_i64 tcg_temp_local_new_i64(void) |
641d5fbe | 835 | { |
a7812ae4 | 836 | return tcg_temp_new_internal_i64(1); |
641d5fbe | 837 | } |
a7812ae4 | 838 | |
27bfd83c PM |
839 | #if defined(CONFIG_DEBUG_TCG) |
840 | /* If you call tcg_clear_temp_count() at the start of a section of | |
841 | * code which is not supposed to leak any TCG temporaries, then | |
842 | * calling tcg_check_temp_count() at the end of the section will | |
843 | * return 1 if the section did in fact leak a temporary. | |
844 | */ | |
845 | void tcg_clear_temp_count(void); | |
846 | int tcg_check_temp_count(void); | |
847 | #else | |
848 | #define tcg_clear_temp_count() do { } while (0) | |
849 | #define tcg_check_temp_count() 0 | |
850 | #endif | |
851 | ||
405cf9ff | 852 | void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf); |
246ae24d | 853 | void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf); |
c896fe29 FB |
854 | |
855 | #define TCG_CT_ALIAS 0x80 | |
856 | #define TCG_CT_IALIAS 0x40 | |
82790a87 | 857 | #define TCG_CT_NEWREG 0x20 /* output requires a new register */ |
c896fe29 FB |
858 | #define TCG_CT_REG 0x01 |
859 | #define TCG_CT_CONST 0x02 /* any constant of register size */ | |
860 | ||
861 | typedef struct TCGArgConstraint { | |
5ff9d6a4 FB |
862 | uint16_t ct; |
863 | uint8_t alias_index; | |
c896fe29 FB |
864 | union { |
865 | TCGRegSet regs; | |
866 | } u; | |
867 | } TCGArgConstraint; | |
868 | ||
869 | #define TCG_MAX_OP_ARGS 16 | |
870 | ||
8399ad59 RH |
871 | /* Bits for TCGOpDef->flags, 8 bits available. */ |
872 | enum { | |
873 | /* Instruction defines the end of a basic block. */ | |
874 | TCG_OPF_BB_END = 0x01, | |
875 | /* Instruction clobbers call registers and potentially update globals. */ | |
876 | TCG_OPF_CALL_CLOBBER = 0x02, | |
3d5c5f87 AJ |
877 | /* Instruction has side effects: it cannot be removed if its outputs |
878 | are not used, and might trigger exceptions. */ | |
8399ad59 RH |
879 | TCG_OPF_SIDE_EFFECTS = 0x04, |
880 | /* Instruction operands are 64-bits (otherwise 32-bits). */ | |
881 | TCG_OPF_64BIT = 0x08, | |
c1a61f6c RH |
882 | /* Instruction is optional and not implemented by the host, or insn |
883 | is generic and should not be implemened by the host. */ | |
25c4d9cc | 884 | TCG_OPF_NOT_PRESENT = 0x10, |
8399ad59 | 885 | }; |
c896fe29 FB |
886 | |
887 | typedef struct TCGOpDef { | |
888 | const char *name; | |
889 | uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; | |
890 | uint8_t flags; | |
c896fe29 FB |
891 | TCGArgConstraint *args_ct; |
892 | int *sorted_args; | |
c68aaa18 SW |
893 | #if defined(CONFIG_DEBUG_TCG) |
894 | int used; | |
895 | #endif | |
c896fe29 | 896 | } TCGOpDef; |
8399ad59 RH |
897 | |
898 | extern TCGOpDef tcg_op_defs[]; | |
2a24374a SW |
899 | extern const size_t tcg_op_defs_max; |
900 | ||
c896fe29 | 901 | typedef struct TCGTargetOpDef { |
a9751609 | 902 | TCGOpcode op; |
c896fe29 FB |
903 | const char *args_ct_str[TCG_MAX_OP_ARGS]; |
904 | } TCGTargetOpDef; | |
905 | ||
c896fe29 FB |
906 | #define tcg_abort() \ |
907 | do {\ | |
908 | fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\ | |
909 | abort();\ | |
910 | } while (0) | |
911 | ||
8b73d49f | 912 | #if UINTPTR_MAX == UINT32_MAX |
ebecf363 PM |
913 | #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I32(n)) |
914 | #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I32(GET_TCGV_PTR(n)) | |
915 | ||
8b73d49f | 916 | #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V))) |
ebecf363 PM |
917 | #define tcg_global_reg_new_ptr(R, N) \ |
918 | TCGV_NAT_TO_PTR(tcg_global_reg_new_i32((R), (N))) | |
919 | #define tcg_global_mem_new_ptr(R, O, N) \ | |
920 | TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N))) | |
921 | #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32()) | |
922 | #define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T)) | |
c896fe29 | 923 | #else |
ebecf363 PM |
924 | #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I64(n)) |
925 | #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I64(GET_TCGV_PTR(n)) | |
926 | ||
8b73d49f | 927 | #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V))) |
ebecf363 PM |
928 | #define tcg_global_reg_new_ptr(R, N) \ |
929 | TCGV_NAT_TO_PTR(tcg_global_reg_new_i64((R), (N))) | |
930 | #define tcg_global_mem_new_ptr(R, O, N) \ | |
931 | TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N))) | |
932 | #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64()) | |
933 | #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T)) | |
c896fe29 FB |
934 | #endif |
935 | ||
bbb8a1b4 RH |
936 | void tcg_gen_callN(TCGContext *s, void *func, |
937 | TCGArg ret, int nargs, TCGArg *args); | |
a7812ae4 | 938 | |
0c627cdc | 939 | void tcg_op_remove(TCGContext *s, TCGOp *op); |
5a18407f RH |
940 | TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg); |
941 | TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg); | |
942 | ||
c45cb8bb | 943 | void tcg_optimize(TCGContext *s); |
8f2e8c07 | 944 | |
a7812ae4 | 945 | /* only used for debugging purposes */ |
eeacee4d | 946 | void tcg_dump_ops(TCGContext *s); |
a7812ae4 | 947 | |
a7812ae4 PB |
948 | TCGv_i32 tcg_const_i32(int32_t val); |
949 | TCGv_i64 tcg_const_i64(int64_t val); | |
950 | TCGv_i32 tcg_const_local_i32(int32_t val); | |
951 | TCGv_i64 tcg_const_local_i64(int64_t val); | |
952 | ||
42a268c2 RH |
953 | TCGLabel *gen_new_label(void); |
954 | ||
955 | /** | |
956 | * label_arg | |
957 | * @l: label | |
958 | * | |
959 | * Encode a label for storage in the TCG opcode stream. | |
960 | */ | |
961 | ||
962 | static inline TCGArg label_arg(TCGLabel *l) | |
963 | { | |
51e3972c | 964 | return (uintptr_t)l; |
42a268c2 RH |
965 | } |
966 | ||
967 | /** | |
968 | * arg_label | |
969 | * @i: value | |
970 | * | |
971 | * The opposite of label_arg. Retrieve a label from the | |
972 | * encoding of the TCG opcode stream. | |
973 | */ | |
974 | ||
51e3972c | 975 | static inline TCGLabel *arg_label(TCGArg i) |
42a268c2 | 976 | { |
51e3972c | 977 | return (TCGLabel *)(uintptr_t)i; |
42a268c2 RH |
978 | } |
979 | ||
52a1f64e RH |
980 | /** |
981 | * tcg_ptr_byte_diff | |
982 | * @a, @b: addresses to be differenced | |
983 | * | |
984 | * There are many places within the TCG backends where we need a byte | |
985 | * difference between two pointers. While this can be accomplished | |
986 | * with local casting, it's easy to get wrong -- especially if one is | |
987 | * concerned with the signedness of the result. | |
988 | * | |
989 | * This version relies on GCC's void pointer arithmetic to get the | |
990 | * correct result. | |
991 | */ | |
992 | ||
993 | static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b) | |
994 | { | |
995 | return a - b; | |
996 | } | |
997 | ||
998 | /** | |
999 | * tcg_pcrel_diff | |
1000 | * @s: the tcg context | |
1001 | * @target: address of the target | |
1002 | * | |
1003 | * Produce a pc-relative difference, from the current code_ptr | |
1004 | * to the destination address. | |
1005 | */ | |
1006 | ||
1007 | static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target) | |
1008 | { | |
1009 | return tcg_ptr_byte_diff(target, s->code_ptr); | |
1010 | } | |
1011 | ||
1012 | /** | |
1013 | * tcg_current_code_size | |
1014 | * @s: the tcg context | |
1015 | * | |
1016 | * Compute the current code size within the translation block. | |
1017 | * This is used to fill in qemu's data structures for goto_tb. | |
1018 | */ | |
1019 | ||
1020 | static inline size_t tcg_current_code_size(TCGContext *s) | |
1021 | { | |
1022 | return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); | |
1023 | } | |
1024 | ||
59227d5d RH |
1025 | /* Combine the TCGMemOp and mmu_idx parameters into a single value. */ |
1026 | typedef uint32_t TCGMemOpIdx; | |
1027 | ||
1028 | /** | |
1029 | * make_memop_idx | |
1030 | * @op: memory operation | |
1031 | * @idx: mmu index | |
1032 | * | |
1033 | * Encode these values into a single parameter. | |
1034 | */ | |
1035 | static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx) | |
1036 | { | |
1037 | tcg_debug_assert(idx <= 15); | |
1038 | return (op << 4) | idx; | |
1039 | } | |
1040 | ||
1041 | /** | |
1042 | * get_memop | |
1043 | * @oi: combined op/idx parameter | |
1044 | * | |
1045 | * Extract the memory operation from the combined value. | |
1046 | */ | |
1047 | static inline TCGMemOp get_memop(TCGMemOpIdx oi) | |
1048 | { | |
1049 | return oi >> 4; | |
1050 | } | |
1051 | ||
1052 | /** | |
1053 | * get_mmuidx | |
1054 | * @oi: combined op/idx parameter | |
1055 | * | |
1056 | * Extract the mmu index from the combined value. | |
1057 | */ | |
1058 | static inline unsigned get_mmuidx(TCGMemOpIdx oi) | |
1059 | { | |
1060 | return oi & 15; | |
1061 | } | |
1062 | ||
0980011b PM |
1063 | /** |
1064 | * tcg_qemu_tb_exec: | |
819af24b | 1065 | * @env: pointer to CPUArchState for the CPU |
0980011b PM |
1066 | * @tb_ptr: address of generated code for the TB to execute |
1067 | * | |
1068 | * Start executing code from a given translation block. | |
1069 | * Where translation blocks have been linked, execution | |
1070 | * may proceed from the given TB into successive ones. | |
1071 | * Control eventually returns only when some action is needed | |
1072 | * from the top-level loop: either control must pass to a TB | |
1073 | * which has not yet been directly linked, or an asynchronous | |
1074 | * event such as an interrupt needs handling. | |
1075 | * | |
819af24b SF |
1076 | * Return: The return value is the value passed to the corresponding |
1077 | * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. | |
1078 | * The value is either zero or a 4-byte aligned pointer to that TB combined | |
1079 | * with additional information in its two least significant bits. The | |
1080 | * additional information is encoded as follows: | |
0980011b PM |
1081 | * 0, 1: the link between this TB and the next is via the specified |
1082 | * TB index (0 or 1). That is, we left the TB via (the equivalent | |
1083 | * of) "goto_tb <index>". The main loop uses this to determine | |
1084 | * how to link the TB just executed to the next. | |
1085 | * 2: we are using instruction counting code generation, and we | |
1086 | * did not start executing this TB because the instruction counter | |
819af24b | 1087 | * would hit zero midway through it. In this case the pointer |
0980011b PM |
1088 | * returned is the TB we were about to execute, and the caller must |
1089 | * arrange to execute the remaining count of instructions. | |
378df4b2 PM |
1090 | * 3: we stopped because the CPU's exit_request flag was set |
1091 | * (usually meaning that there is an interrupt that needs to be | |
819af24b SF |
1092 | * handled). The pointer returned is the TB we were about to execute |
1093 | * when we noticed the pending exit request. | |
0980011b PM |
1094 | * |
1095 | * If the bottom two bits indicate an exit-via-index then the CPU | |
1096 | * state is correctly synchronised and ready for execution of the next | |
1097 | * TB (and in particular the guest PC is the address to execute next). | |
1098 | * Otherwise, we gave up on execution of this TB before it started, and | |
fee068e4 | 1099 | * the caller must fix up the CPU state by calling the CPU's |
819af24b | 1100 | * synchronize_from_tb() method with the TB pointer we return (falling |
fee068e4 PC |
1101 | * back to calling the CPU's set_pc method with tb->pb if no |
1102 | * synchronize_from_tb() method exists). | |
0980011b PM |
1103 | * |
1104 | * Note that TCG targets may use a different definition of tcg_qemu_tb_exec | |
1105 | * to this default (which just calls the prologue.code emitted by | |
1106 | * tcg_target_qemu_prologue()). | |
1107 | */ | |
1108 | #define TB_EXIT_MASK 3 | |
1109 | #define TB_EXIT_IDX0 0 | |
1110 | #define TB_EXIT_IDX1 1 | |
1111 | #define TB_EXIT_ICOUNT_EXPIRED 2 | |
378df4b2 | 1112 | #define TB_EXIT_REQUESTED 3 |
0980011b | 1113 | |
5a58e884 PB |
1114 | #ifdef HAVE_TCG_QEMU_TB_EXEC |
1115 | uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); | |
1116 | #else | |
ce285b17 | 1117 | # define tcg_qemu_tb_exec(env, tb_ptr) \ |
04d5a1da | 1118 | ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr) |
932a6909 | 1119 | #endif |
813da627 RH |
1120 | |
1121 | void tcg_register_jit(void *buf, size_t buf_size); | |
b76f0d8c | 1122 | |
e58eb534 RH |
1123 | /* |
1124 | * Memory helpers that will be used by TCG generated code. | |
1125 | */ | |
1126 | #ifdef CONFIG_SOFTMMU | |
c8f94df5 RH |
1127 | /* Value zero-extended to tcg register size. */ |
1128 | tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, | |
3972ef6f | 1129 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1130 | tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1131 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1132 | tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1133 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1134 | uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1135 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1136 | tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1137 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1138 | tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1139 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1140 | uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1141 | TCGMemOpIdx oi, uintptr_t retaddr); |
e58eb534 | 1142 | |
c8f94df5 RH |
1143 | /* Value sign-extended to tcg register size. */ |
1144 | tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, | |
3972ef6f | 1145 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1146 | tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1147 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1148 | tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1149 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1150 | tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1151 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1152 | tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1153 | TCGMemOpIdx oi, uintptr_t retaddr); |
c8f94df5 | 1154 | |
e58eb534 | 1155 | void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, |
3972ef6f | 1156 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1157 | void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, |
3972ef6f | 1158 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1159 | void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, |
3972ef6f | 1160 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1161 | void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, |
3972ef6f | 1162 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1163 | void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, |
3972ef6f | 1164 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1165 | void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, |
3972ef6f | 1166 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1167 | void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, |
3972ef6f | 1168 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1169 | |
282dffc8 PD |
1170 | uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, |
1171 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1172 | uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, | |
1173 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1174 | uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr, | |
1175 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1176 | uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, | |
1177 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1178 | uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, | |
1179 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1180 | uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr, | |
1181 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1182 | uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, | |
1183 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1184 | ||
867b3201 RH |
1185 | /* Temporary aliases until backends are converted. */ |
1186 | #ifdef TARGET_WORDS_BIGENDIAN | |
1187 | # define helper_ret_ldsw_mmu helper_be_ldsw_mmu | |
1188 | # define helper_ret_lduw_mmu helper_be_lduw_mmu | |
1189 | # define helper_ret_ldsl_mmu helper_be_ldsl_mmu | |
1190 | # define helper_ret_ldul_mmu helper_be_ldul_mmu | |
282dffc8 | 1191 | # define helper_ret_ldl_mmu helper_be_ldul_mmu |
867b3201 RH |
1192 | # define helper_ret_ldq_mmu helper_be_ldq_mmu |
1193 | # define helper_ret_stw_mmu helper_be_stw_mmu | |
1194 | # define helper_ret_stl_mmu helper_be_stl_mmu | |
1195 | # define helper_ret_stq_mmu helper_be_stq_mmu | |
282dffc8 PD |
1196 | # define helper_ret_ldw_cmmu helper_be_ldw_cmmu |
1197 | # define helper_ret_ldl_cmmu helper_be_ldl_cmmu | |
1198 | # define helper_ret_ldq_cmmu helper_be_ldq_cmmu | |
867b3201 RH |
1199 | #else |
1200 | # define helper_ret_ldsw_mmu helper_le_ldsw_mmu | |
1201 | # define helper_ret_lduw_mmu helper_le_lduw_mmu | |
1202 | # define helper_ret_ldsl_mmu helper_le_ldsl_mmu | |
1203 | # define helper_ret_ldul_mmu helper_le_ldul_mmu | |
282dffc8 | 1204 | # define helper_ret_ldl_mmu helper_le_ldul_mmu |
867b3201 RH |
1205 | # define helper_ret_ldq_mmu helper_le_ldq_mmu |
1206 | # define helper_ret_stw_mmu helper_le_stw_mmu | |
1207 | # define helper_ret_stl_mmu helper_le_stl_mmu | |
1208 | # define helper_ret_stq_mmu helper_le_stq_mmu | |
282dffc8 PD |
1209 | # define helper_ret_ldw_cmmu helper_le_ldw_cmmu |
1210 | # define helper_ret_ldl_cmmu helper_le_ldl_cmmu | |
1211 | # define helper_ret_ldq_cmmu helper_le_ldq_cmmu | |
867b3201 | 1212 | #endif |
e58eb534 | 1213 | |
c482cb11 RH |
1214 | uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, |
1215 | uint32_t cmpv, uint32_t newv, | |
1216 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1217 | uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr, | |
1218 | uint32_t cmpv, uint32_t newv, | |
1219 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1220 | uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr, | |
1221 | uint32_t cmpv, uint32_t newv, | |
1222 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1223 | uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr, | |
1224 | uint64_t cmpv, uint64_t newv, | |
1225 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1226 | uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr, | |
1227 | uint32_t cmpv, uint32_t newv, | |
1228 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1229 | uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr, | |
1230 | uint32_t cmpv, uint32_t newv, | |
1231 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1232 | uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr, | |
1233 | uint64_t cmpv, uint64_t newv, | |
1234 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1235 | ||
1236 | #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ | |
1237 | TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu \ | |
1238 | (CPUArchState *env, target_ulong addr, TYPE val, \ | |
1239 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1240 | ||
df79b996 | 1241 | #ifdef CONFIG_ATOMIC64 |
c482cb11 | 1242 | #define GEN_ATOMIC_HELPER_ALL(NAME) \ |
df79b996 | 1243 | GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ |
c482cb11 | 1244 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ |
c482cb11 | 1245 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ |
df79b996 | 1246 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ |
c482cb11 | 1247 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ |
df79b996 | 1248 | GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ |
c482cb11 | 1249 | GEN_ATOMIC_HELPER(NAME, uint64_t, q_be) |
df79b996 RH |
1250 | #else |
1251 | #define GEN_ATOMIC_HELPER_ALL(NAME) \ | |
1252 | GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ | |
1253 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ | |
1254 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ | |
1255 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ | |
1256 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) | |
1257 | #endif | |
c482cb11 RH |
1258 | |
1259 | GEN_ATOMIC_HELPER_ALL(fetch_add) | |
1260 | GEN_ATOMIC_HELPER_ALL(fetch_sub) | |
1261 | GEN_ATOMIC_HELPER_ALL(fetch_and) | |
1262 | GEN_ATOMIC_HELPER_ALL(fetch_or) | |
1263 | GEN_ATOMIC_HELPER_ALL(fetch_xor) | |
1264 | ||
1265 | GEN_ATOMIC_HELPER_ALL(add_fetch) | |
1266 | GEN_ATOMIC_HELPER_ALL(sub_fetch) | |
1267 | GEN_ATOMIC_HELPER_ALL(and_fetch) | |
1268 | GEN_ATOMIC_HELPER_ALL(or_fetch) | |
1269 | GEN_ATOMIC_HELPER_ALL(xor_fetch) | |
1270 | ||
1271 | GEN_ATOMIC_HELPER_ALL(xchg) | |
1272 | ||
1273 | #undef GEN_ATOMIC_HELPER_ALL | |
1274 | #undef GEN_ATOMIC_HELPER | |
e58eb534 RH |
1275 | #endif /* CONFIG_SOFTMMU */ |
1276 | ||
7ebee43e RH |
1277 | #ifdef CONFIG_ATOMIC128 |
1278 | #include "qemu/int128.h" | |
1279 | ||
1280 | /* These aren't really a "proper" helpers because TCG cannot manage Int128. | |
1281 | However, use the same format as the others, for use by the backends. */ | |
1282 | Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, | |
1283 | Int128 cmpv, Int128 newv, | |
1284 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1285 | Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr, | |
1286 | Int128 cmpv, Int128 newv, | |
1287 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1288 | ||
1289 | Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, | |
1290 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1291 | Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, | |
1292 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1293 | void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val, | |
1294 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1295 | void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val, | |
1296 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1297 | ||
1298 | #endif /* CONFIG_ATOMIC128 */ | |
1299 | ||
e58eb534 | 1300 | #endif /* TCG_H */ |