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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e58eb534 RH |
24 | |
25 | #ifndef TCG_H | |
26 | #define TCG_H | |
27 | ||
f8393946 | 28 | #include "qemu-common.h" |
0ec9eabc | 29 | #include "qemu/bitops.h" |
78cd7b83 RH |
30 | #include "tcg-target.h" |
31 | ||
6e0b0730 PC |
32 | #define CPU_TEMP_BUF_NLONGS 128 |
33 | ||
78cd7b83 RH |
34 | /* Default target word size to pointer size. */ |
35 | #ifndef TCG_TARGET_REG_BITS | |
36 | # if UINTPTR_MAX == UINT32_MAX | |
37 | # define TCG_TARGET_REG_BITS 32 | |
38 | # elif UINTPTR_MAX == UINT64_MAX | |
39 | # define TCG_TARGET_REG_BITS 64 | |
40 | # else | |
41 | # error Unknown pointer size for tcg target | |
42 | # endif | |
817b838e SW |
43 | #endif |
44 | ||
c896fe29 FB |
45 | #if TCG_TARGET_REG_BITS == 32 |
46 | typedef int32_t tcg_target_long; | |
47 | typedef uint32_t tcg_target_ulong; | |
48 | #define TCG_PRIlx PRIx32 | |
49 | #define TCG_PRIld PRId32 | |
50 | #elif TCG_TARGET_REG_BITS == 64 | |
51 | typedef int64_t tcg_target_long; | |
52 | typedef uint64_t tcg_target_ulong; | |
53 | #define TCG_PRIlx PRIx64 | |
54 | #define TCG_PRIld PRId64 | |
55 | #else | |
56 | #error unsupported | |
57 | #endif | |
58 | ||
59 | #if TCG_TARGET_NB_REGS <= 32 | |
60 | typedef uint32_t TCGRegSet; | |
61 | #elif TCG_TARGET_NB_REGS <= 64 | |
62 | typedef uint64_t TCGRegSet; | |
63 | #else | |
64 | #error unsupported | |
65 | #endif | |
66 | ||
25c4d9cc | 67 | #if TCG_TARGET_REG_BITS == 32 |
e6a72734 | 68 | /* Turn some undef macros into false macros. */ |
609ad705 RH |
69 | #define TCG_TARGET_HAS_extrl_i64_i32 0 |
70 | #define TCG_TARGET_HAS_extrh_i64_i32 0 | |
25c4d9cc | 71 | #define TCG_TARGET_HAS_div_i64 0 |
ca675f46 | 72 | #define TCG_TARGET_HAS_rem_i64 0 |
25c4d9cc RH |
73 | #define TCG_TARGET_HAS_div2_i64 0 |
74 | #define TCG_TARGET_HAS_rot_i64 0 | |
75 | #define TCG_TARGET_HAS_ext8s_i64 0 | |
76 | #define TCG_TARGET_HAS_ext16s_i64 0 | |
77 | #define TCG_TARGET_HAS_ext32s_i64 0 | |
78 | #define TCG_TARGET_HAS_ext8u_i64 0 | |
79 | #define TCG_TARGET_HAS_ext16u_i64 0 | |
80 | #define TCG_TARGET_HAS_ext32u_i64 0 | |
81 | #define TCG_TARGET_HAS_bswap16_i64 0 | |
82 | #define TCG_TARGET_HAS_bswap32_i64 0 | |
83 | #define TCG_TARGET_HAS_bswap64_i64 0 | |
84 | #define TCG_TARGET_HAS_neg_i64 0 | |
85 | #define TCG_TARGET_HAS_not_i64 0 | |
86 | #define TCG_TARGET_HAS_andc_i64 0 | |
87 | #define TCG_TARGET_HAS_orc_i64 0 | |
88 | #define TCG_TARGET_HAS_eqv_i64 0 | |
89 | #define TCG_TARGET_HAS_nand_i64 0 | |
90 | #define TCG_TARGET_HAS_nor_i64 0 | |
91 | #define TCG_TARGET_HAS_deposit_i64 0 | |
ffc5ea09 | 92 | #define TCG_TARGET_HAS_movcond_i64 0 |
d7156f7c RH |
93 | #define TCG_TARGET_HAS_add2_i64 0 |
94 | #define TCG_TARGET_HAS_sub2_i64 0 | |
95 | #define TCG_TARGET_HAS_mulu2_i64 0 | |
4d3203fd | 96 | #define TCG_TARGET_HAS_muls2_i64 0 |
03271524 RH |
97 | #define TCG_TARGET_HAS_muluh_i64 0 |
98 | #define TCG_TARGET_HAS_mulsh_i64 0 | |
e6a72734 RH |
99 | /* Turn some undef macros into true macros. */ |
100 | #define TCG_TARGET_HAS_add2_i32 1 | |
101 | #define TCG_TARGET_HAS_sub2_i32 1 | |
25c4d9cc RH |
102 | #endif |
103 | ||
a4773324 JK |
104 | #ifndef TCG_TARGET_deposit_i32_valid |
105 | #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 | |
106 | #endif | |
107 | #ifndef TCG_TARGET_deposit_i64_valid | |
108 | #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 | |
109 | #endif | |
110 | ||
25c4d9cc RH |
111 | /* Only one of DIV or DIV2 should be defined. */ |
112 | #if defined(TCG_TARGET_HAS_div_i32) | |
113 | #define TCG_TARGET_HAS_div2_i32 0 | |
114 | #elif defined(TCG_TARGET_HAS_div2_i32) | |
115 | #define TCG_TARGET_HAS_div_i32 0 | |
ca675f46 | 116 | #define TCG_TARGET_HAS_rem_i32 0 |
25c4d9cc RH |
117 | #endif |
118 | #if defined(TCG_TARGET_HAS_div_i64) | |
119 | #define TCG_TARGET_HAS_div2_i64 0 | |
120 | #elif defined(TCG_TARGET_HAS_div2_i64) | |
121 | #define TCG_TARGET_HAS_div_i64 0 | |
ca675f46 | 122 | #define TCG_TARGET_HAS_rem_i64 0 |
25c4d9cc RH |
123 | #endif |
124 | ||
df9ebea5 RH |
125 | /* For 32-bit targets, some sort of unsigned widening multiply is required. */ |
126 | #if TCG_TARGET_REG_BITS == 32 \ | |
127 | && !(defined(TCG_TARGET_HAS_mulu2_i32) \ | |
128 | || defined(TCG_TARGET_HAS_muluh_i32)) | |
129 | # error "Missing unsigned widening multiply" | |
130 | #endif | |
131 | ||
9aef40ed RH |
132 | #ifndef TARGET_INSN_START_EXTRA_WORDS |
133 | # define TARGET_INSN_START_WORDS 1 | |
134 | #else | |
135 | # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) | |
136 | #endif | |
137 | ||
a9751609 | 138 | typedef enum TCGOpcode { |
c61aaf7a | 139 | #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, |
c896fe29 FB |
140 | #include "tcg-opc.h" |
141 | #undef DEF | |
142 | NB_OPS, | |
a9751609 | 143 | } TCGOpcode; |
c896fe29 FB |
144 | |
145 | #define tcg_regset_clear(d) (d) = 0 | |
146 | #define tcg_regset_set(d, s) (d) = (s) | |
147 | #define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg) | |
7d301752 AJ |
148 | #define tcg_regset_set_reg(d, r) (d) |= 1L << (r) |
149 | #define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r)) | |
c896fe29 FB |
150 | #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) |
151 | #define tcg_regset_or(d, a, b) (d) = (a) | (b) | |
152 | #define tcg_regset_and(d, a, b) (d) = (a) & (b) | |
153 | #define tcg_regset_andnot(d, a, b) (d) = (a) & ~(b) | |
154 | #define tcg_regset_not(d, a) (d) = ~(a) | |
155 | ||
1813e175 | 156 | #ifndef TCG_TARGET_INSN_UNIT_SIZE |
5053361b RH |
157 | # error "Missing TCG_TARGET_INSN_UNIT_SIZE" |
158 | #elif TCG_TARGET_INSN_UNIT_SIZE == 1 | |
1813e175 RH |
159 | typedef uint8_t tcg_insn_unit; |
160 | #elif TCG_TARGET_INSN_UNIT_SIZE == 2 | |
161 | typedef uint16_t tcg_insn_unit; | |
162 | #elif TCG_TARGET_INSN_UNIT_SIZE == 4 | |
163 | typedef uint32_t tcg_insn_unit; | |
164 | #elif TCG_TARGET_INSN_UNIT_SIZE == 8 | |
165 | typedef uint64_t tcg_insn_unit; | |
166 | #else | |
167 | /* The port better have done this. */ | |
168 | #endif | |
169 | ||
170 | ||
c896fe29 FB |
171 | typedef struct TCGRelocation { |
172 | struct TCGRelocation *next; | |
173 | int type; | |
1813e175 | 174 | tcg_insn_unit *ptr; |
2ba7fae2 | 175 | intptr_t addend; |
c896fe29 FB |
176 | } TCGRelocation; |
177 | ||
178 | typedef struct TCGLabel { | |
51e3972c RH |
179 | unsigned has_value : 1; |
180 | unsigned id : 31; | |
c896fe29 | 181 | union { |
2ba7fae2 | 182 | uintptr_t value; |
1813e175 | 183 | tcg_insn_unit *value_ptr; |
c896fe29 FB |
184 | TCGRelocation *first_reloc; |
185 | } u; | |
186 | } TCGLabel; | |
187 | ||
188 | typedef struct TCGPool { | |
189 | struct TCGPool *next; | |
c44f945a BS |
190 | int size; |
191 | uint8_t data[0] __attribute__ ((aligned)); | |
c896fe29 FB |
192 | } TCGPool; |
193 | ||
194 | #define TCG_POOL_CHUNK_SIZE 32768 | |
195 | ||
c4071c90 | 196 | #define TCG_MAX_TEMPS 512 |
190ce7fb | 197 | #define TCG_MAX_INSNS 512 |
c896fe29 | 198 | |
b03cce8e FB |
199 | /* when the size of the arguments of a called function is smaller than |
200 | this value, they are statically allocated in the TB stack frame */ | |
201 | #define TCG_STATIC_CALL_ARGS_SIZE 128 | |
202 | ||
c02244a5 RH |
203 | typedef enum TCGType { |
204 | TCG_TYPE_I32, | |
205 | TCG_TYPE_I64, | |
206 | TCG_TYPE_COUNT, /* number of different types */ | |
c896fe29 | 207 | |
3b6dac34 | 208 | /* An alias for the size of the host register. */ |
c896fe29 | 209 | #if TCG_TARGET_REG_BITS == 32 |
3b6dac34 | 210 | TCG_TYPE_REG = TCG_TYPE_I32, |
c02244a5 | 211 | #else |
3b6dac34 | 212 | TCG_TYPE_REG = TCG_TYPE_I64, |
c02244a5 | 213 | #endif |
3b6dac34 | 214 | |
d289837e RH |
215 | /* An alias for the size of the native pointer. */ |
216 | #if UINTPTR_MAX == UINT32_MAX | |
217 | TCG_TYPE_PTR = TCG_TYPE_I32, | |
218 | #else | |
219 | TCG_TYPE_PTR = TCG_TYPE_I64, | |
220 | #endif | |
3b6dac34 RH |
221 | |
222 | /* An alias for the size of the target "long", aka register. */ | |
c02244a5 RH |
223 | #if TARGET_LONG_BITS == 64 |
224 | TCG_TYPE_TL = TCG_TYPE_I64, | |
c896fe29 | 225 | #else |
c02244a5 | 226 | TCG_TYPE_TL = TCG_TYPE_I32, |
c896fe29 | 227 | #endif |
c02244a5 | 228 | } TCGType; |
c896fe29 | 229 | |
6c5f4ead RH |
230 | /* Constants for qemu_ld and qemu_st for the Memory Operation field. */ |
231 | typedef enum TCGMemOp { | |
232 | MO_8 = 0, | |
233 | MO_16 = 1, | |
234 | MO_32 = 2, | |
235 | MO_64 = 3, | |
236 | MO_SIZE = 3, /* Mask for the above. */ | |
237 | ||
238 | MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */ | |
239 | ||
240 | MO_BSWAP = 8, /* Host reverse endian. */ | |
241 | #ifdef HOST_WORDS_BIGENDIAN | |
242 | MO_LE = MO_BSWAP, | |
243 | MO_BE = 0, | |
244 | #else | |
245 | MO_LE = 0, | |
246 | MO_BE = MO_BSWAP, | |
247 | #endif | |
248 | #ifdef TARGET_WORDS_BIGENDIAN | |
249 | MO_TE = MO_BE, | |
250 | #else | |
251 | MO_TE = MO_LE, | |
252 | #endif | |
253 | ||
dfb36305 RH |
254 | /* MO_UNALN accesses are never checked for alignment. |
255 | MO_ALIGN accesses will result in a call to the CPU's | |
256 | do_unaligned_access hook if the guest address is not aligned. | |
257 | The default depends on whether the target CPU defines ALIGNED_ONLY. */ | |
258 | MO_AMASK = 16, | |
259 | #ifdef ALIGNED_ONLY | |
260 | MO_ALIGN = 0, | |
261 | MO_UNALN = MO_AMASK, | |
262 | #else | |
263 | MO_ALIGN = MO_AMASK, | |
264 | MO_UNALN = 0, | |
265 | #endif | |
266 | ||
6c5f4ead RH |
267 | /* Combinations of the above, for ease of use. */ |
268 | MO_UB = MO_8, | |
269 | MO_UW = MO_16, | |
270 | MO_UL = MO_32, | |
271 | MO_SB = MO_SIGN | MO_8, | |
272 | MO_SW = MO_SIGN | MO_16, | |
273 | MO_SL = MO_SIGN | MO_32, | |
274 | MO_Q = MO_64, | |
275 | ||
276 | MO_LEUW = MO_LE | MO_UW, | |
277 | MO_LEUL = MO_LE | MO_UL, | |
278 | MO_LESW = MO_LE | MO_SW, | |
279 | MO_LESL = MO_LE | MO_SL, | |
280 | MO_LEQ = MO_LE | MO_Q, | |
281 | ||
282 | MO_BEUW = MO_BE | MO_UW, | |
283 | MO_BEUL = MO_BE | MO_UL, | |
284 | MO_BESW = MO_BE | MO_SW, | |
285 | MO_BESL = MO_BE | MO_SL, | |
286 | MO_BEQ = MO_BE | MO_Q, | |
287 | ||
288 | MO_TEUW = MO_TE | MO_UW, | |
289 | MO_TEUL = MO_TE | MO_UL, | |
290 | MO_TESW = MO_TE | MO_SW, | |
291 | MO_TESL = MO_TE | MO_SL, | |
292 | MO_TEQ = MO_TE | MO_Q, | |
293 | ||
294 | MO_SSIZE = MO_SIZE | MO_SIGN, | |
295 | } TCGMemOp; | |
296 | ||
c896fe29 FB |
297 | typedef tcg_target_ulong TCGArg; |
298 | ||
b6c73a6d RH |
299 | /* Define a type and accessor macros for variables. Using pointer types |
300 | is nice because it gives some level of type safely. Converting to and | |
301 | from intptr_t rather than int reduces the number of sign-extension | |
302 | instructions that get implied on 64-bit hosts. Users of tcg_gen_* don't | |
303 | need to know about any of this, and should treat TCGv as an opaque type. | |
06ea77bc | 304 | In addition we do typechecking for different types of variables. TCGv_i32 |
a7812ae4 | 305 | and TCGv_i64 are 32/64-bit variables respectively. TCGv and TCGv_ptr |
b6c73a6d | 306 | are aliases for target_ulong and host pointer sized values respectively. */ |
ac56dd48 | 307 | |
b6c73a6d RH |
308 | typedef struct TCGv_i32_d *TCGv_i32; |
309 | typedef struct TCGv_i64_d *TCGv_i64; | |
310 | typedef struct TCGv_ptr_d *TCGv_ptr; | |
ac56dd48 | 311 | |
b6c73a6d RH |
312 | static inline TCGv_i32 QEMU_ARTIFICIAL MAKE_TCGV_I32(intptr_t i) |
313 | { | |
314 | return (TCGv_i32)i; | |
315 | } | |
ac56dd48 | 316 | |
b6c73a6d | 317 | static inline TCGv_i64 QEMU_ARTIFICIAL MAKE_TCGV_I64(intptr_t i) |
ac56dd48 | 318 | { |
b6c73a6d RH |
319 | return (TCGv_i64)i; |
320 | } | |
ac56dd48 | 321 | |
b6c73a6d | 322 | static inline TCGv_ptr QEMU_ARTIFICIAL MAKE_TCGV_PTR(intptr_t i) |
a7812ae4 | 323 | { |
b6c73a6d RH |
324 | return (TCGv_ptr)i; |
325 | } | |
ac56dd48 | 326 | |
b6c73a6d RH |
327 | static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I32(TCGv_i32 t) |
328 | { | |
329 | return (intptr_t)t; | |
330 | } | |
ac56dd48 | 331 | |
b6c73a6d RH |
332 | static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I64(TCGv_i64 t) |
333 | { | |
334 | return (intptr_t)t; | |
335 | } | |
336 | ||
337 | static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t) | |
338 | { | |
339 | return (intptr_t)t; | |
340 | } | |
44e6acb0 | 341 | |
ac56dd48 | 342 | #if TCG_TARGET_REG_BITS == 32 |
b6c73a6d RH |
343 | #define TCGV_LOW(t) MAKE_TCGV_I32(GET_TCGV_I64(t)) |
344 | #define TCGV_HIGH(t) MAKE_TCGV_I32(GET_TCGV_I64(t) + 1) | |
ac56dd48 PB |
345 | #endif |
346 | ||
43e860ef AJ |
347 | #define TCGV_EQUAL_I32(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b)) |
348 | #define TCGV_EQUAL_I64(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b)) | |
c1de788a | 349 | #define TCGV_EQUAL_PTR(a, b) (GET_TCGV_PTR(a) == GET_TCGV_PTR(b)) |
43e860ef | 350 | |
a50f5b91 | 351 | /* Dummy definition to avoid compiler warnings. */ |
a7812ae4 PB |
352 | #define TCGV_UNUSED_I32(x) x = MAKE_TCGV_I32(-1) |
353 | #define TCGV_UNUSED_I64(x) x = MAKE_TCGV_I64(-1) | |
c1de788a | 354 | #define TCGV_UNUSED_PTR(x) x = MAKE_TCGV_PTR(-1) |
a50f5b91 | 355 | |
afcb92be RH |
356 | #define TCGV_IS_UNUSED_I32(x) (GET_TCGV_I32(x) == -1) |
357 | #define TCGV_IS_UNUSED_I64(x) (GET_TCGV_I64(x) == -1) | |
c1de788a | 358 | #define TCGV_IS_UNUSED_PTR(x) (GET_TCGV_PTR(x) == -1) |
afcb92be | 359 | |
c896fe29 | 360 | /* call flags */ |
78505279 AJ |
361 | /* Helper does not read globals (either directly or through an exception). It |
362 | implies TCG_CALL_NO_WRITE_GLOBALS. */ | |
363 | #define TCG_CALL_NO_READ_GLOBALS 0x0010 | |
364 | /* Helper does not write globals */ | |
365 | #define TCG_CALL_NO_WRITE_GLOBALS 0x0020 | |
366 | /* Helper can be safely suppressed if the return value is not used. */ | |
367 | #define TCG_CALL_NO_SIDE_EFFECTS 0x0040 | |
368 | ||
369 | /* convenience version of most used call flags */ | |
370 | #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS | |
371 | #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS | |
372 | #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS | |
373 | #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) | |
374 | #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) | |
375 | ||
39cf05d3 | 376 | /* used to align parameters */ |
a7812ae4 | 377 | #define TCG_CALL_DUMMY_TCGV MAKE_TCGV_I32(-1) |
39cf05d3 FB |
378 | #define TCG_CALL_DUMMY_ARG ((TCGArg)(-1)) |
379 | ||
a93cf9df SW |
380 | /* Conditions. Note that these are laid out for easy manipulation by |
381 | the functions below: | |
0aed257f RH |
382 | bit 0 is used for inverting; |
383 | bit 1 is signed, | |
384 | bit 2 is unsigned, | |
385 | bit 3 is used with bit 0 for swapping signed/unsigned. */ | |
c896fe29 | 386 | typedef enum { |
0aed257f RH |
387 | /* non-signed */ |
388 | TCG_COND_NEVER = 0 | 0 | 0 | 0, | |
389 | TCG_COND_ALWAYS = 0 | 0 | 0 | 1, | |
390 | TCG_COND_EQ = 8 | 0 | 0 | 0, | |
391 | TCG_COND_NE = 8 | 0 | 0 | 1, | |
392 | /* signed */ | |
393 | TCG_COND_LT = 0 | 0 | 2 | 0, | |
394 | TCG_COND_GE = 0 | 0 | 2 | 1, | |
395 | TCG_COND_LE = 8 | 0 | 2 | 0, | |
396 | TCG_COND_GT = 8 | 0 | 2 | 1, | |
c896fe29 | 397 | /* unsigned */ |
0aed257f RH |
398 | TCG_COND_LTU = 0 | 4 | 0 | 0, |
399 | TCG_COND_GEU = 0 | 4 | 0 | 1, | |
400 | TCG_COND_LEU = 8 | 4 | 0 | 0, | |
401 | TCG_COND_GTU = 8 | 4 | 0 | 1, | |
c896fe29 FB |
402 | } TCGCond; |
403 | ||
1c086220 | 404 | /* Invert the sense of the comparison. */ |
401d466d RH |
405 | static inline TCGCond tcg_invert_cond(TCGCond c) |
406 | { | |
407 | return (TCGCond)(c ^ 1); | |
408 | } | |
409 | ||
1c086220 RH |
410 | /* Swap the operands in a comparison. */ |
411 | static inline TCGCond tcg_swap_cond(TCGCond c) | |
412 | { | |
0aed257f | 413 | return c & 6 ? (TCGCond)(c ^ 9) : c; |
1c086220 RH |
414 | } |
415 | ||
d1e321b8 | 416 | /* Create an "unsigned" version of a "signed" comparison. */ |
ff44c2f3 RH |
417 | static inline TCGCond tcg_unsigned_cond(TCGCond c) |
418 | { | |
0aed257f | 419 | return c & 2 ? (TCGCond)(c ^ 6) : c; |
ff44c2f3 RH |
420 | } |
421 | ||
d1e321b8 | 422 | /* Must a comparison be considered unsigned? */ |
bcc66562 RH |
423 | static inline bool is_unsigned_cond(TCGCond c) |
424 | { | |
0aed257f | 425 | return (c & 4) != 0; |
bcc66562 RH |
426 | } |
427 | ||
d1e321b8 RH |
428 | /* Create a "high" version of a double-word comparison. |
429 | This removes equality from a LTE or GTE comparison. */ | |
430 | static inline TCGCond tcg_high_cond(TCGCond c) | |
431 | { | |
432 | switch (c) { | |
433 | case TCG_COND_GE: | |
434 | case TCG_COND_LE: | |
435 | case TCG_COND_GEU: | |
436 | case TCG_COND_LEU: | |
437 | return (TCGCond)(c ^ 8); | |
438 | default: | |
439 | return c; | |
440 | } | |
441 | } | |
442 | ||
00c8fa9f EC |
443 | typedef enum TCGTempVal { |
444 | TEMP_VAL_DEAD, | |
445 | TEMP_VAL_REG, | |
446 | TEMP_VAL_MEM, | |
447 | TEMP_VAL_CONST, | |
448 | } TCGTempVal; | |
c896fe29 | 449 | |
c896fe29 | 450 | typedef struct TCGTemp { |
00c8fa9f EC |
451 | unsigned int reg:8; |
452 | unsigned int mem_reg:8; | |
453 | TCGTempVal val_type:8; | |
454 | TCGType base_type:8; | |
455 | TCGType type:8; | |
c896fe29 FB |
456 | unsigned int fixed_reg:1; |
457 | unsigned int mem_coherent:1; | |
458 | unsigned int mem_allocated:1; | |
5225d669 | 459 | unsigned int temp_local:1; /* If true, the temp is saved across |
641d5fbe | 460 | basic blocks. Otherwise, it is not |
5225d669 | 461 | preserved across basic blocks. */ |
e8996ee0 | 462 | unsigned int temp_allocated:1; /* never used for code gen */ |
00c8fa9f EC |
463 | |
464 | tcg_target_long val; | |
465 | intptr_t mem_offset; | |
c896fe29 FB |
466 | const char *name; |
467 | } TCGTemp; | |
468 | ||
c896fe29 FB |
469 | typedef struct TCGContext TCGContext; |
470 | ||
0ec9eabc RH |
471 | typedef struct TCGTempSet { |
472 | unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; | |
473 | } TCGTempSet; | |
474 | ||
c45cb8bb RH |
475 | typedef struct TCGOp { |
476 | TCGOpcode opc : 8; | |
477 | ||
478 | /* The number of out and in parameter for a call. */ | |
479 | unsigned callo : 2; | |
480 | unsigned calli : 6; | |
481 | ||
482 | /* Index of the arguments for this op, or -1 for zero-operand ops. */ | |
483 | signed args : 16; | |
484 | ||
485 | /* Index of the prex/next op, or -1 for the end of the list. */ | |
486 | signed prev : 16; | |
487 | signed next : 16; | |
488 | } TCGOp; | |
489 | ||
490 | QEMU_BUILD_BUG_ON(NB_OPS > 0xff); | |
491 | QEMU_BUILD_BUG_ON(OPC_BUF_SIZE >= 0x7fff); | |
492 | QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE >= 0x7fff); | |
493 | ||
c896fe29 FB |
494 | struct TCGContext { |
495 | uint8_t *pool_cur, *pool_end; | |
4055299e | 496 | TCGPool *pool_first, *pool_current, *pool_first_large; |
c896fe29 | 497 | int nb_labels; |
c896fe29 FB |
498 | int nb_globals; |
499 | int nb_temps; | |
c896fe29 FB |
500 | |
501 | /* goto_tb support */ | |
1813e175 | 502 | tcg_insn_unit *code_buf; |
fe7e1d3e | 503 | uintptr_t *tb_next; |
c896fe29 FB |
504 | uint16_t *tb_next_offset; |
505 | uint16_t *tb_jmp_offset; /* != NULL if USE_DIRECT_JUMP */ | |
506 | ||
641d5fbe | 507 | /* liveness analysis */ |
866cb6cb AJ |
508 | uint16_t *op_dead_args; /* for each operation, each bit tells if the |
509 | corresponding argument is dead */ | |
ec7a869d AJ |
510 | uint8_t *op_sync_args; /* for each operation, each bit tells if the |
511 | corresponding output argument needs to be | |
512 | sync to memory. */ | |
641d5fbe | 513 | |
c896fe29 | 514 | TCGRegSet reserved_regs; |
e2c6d1b4 RH |
515 | intptr_t current_frame_offset; |
516 | intptr_t frame_start; | |
517 | intptr_t frame_end; | |
c896fe29 FB |
518 | int frame_reg; |
519 | ||
1813e175 | 520 | tcg_insn_unit *code_ptr; |
c896fe29 | 521 | |
6e085f72 | 522 | GHashTable *helpers; |
a23a9ec6 FB |
523 | |
524 | #ifdef CONFIG_PROFILER | |
525 | /* profiling info */ | |
526 | int64_t tb_count1; | |
527 | int64_t tb_count; | |
528 | int64_t op_count; /* total insn count */ | |
529 | int op_count_max; /* max insn per TB */ | |
530 | int64_t temp_count; | |
531 | int temp_count_max; | |
a23a9ec6 FB |
532 | int64_t del_op_count; |
533 | int64_t code_in_len; | |
534 | int64_t code_out_len; | |
fca8a500 | 535 | int64_t search_out_len; |
a23a9ec6 FB |
536 | int64_t interm_time; |
537 | int64_t code_time; | |
538 | int64_t la_time; | |
c5cc28ff | 539 | int64_t opt_time; |
a23a9ec6 FB |
540 | int64_t restore_count; |
541 | int64_t restore_time; | |
542 | #endif | |
27bfd83c PM |
543 | |
544 | #ifdef CONFIG_DEBUG_TCG | |
545 | int temps_in_use; | |
0a209d4b | 546 | int goto_tb_issue_mask; |
27bfd83c | 547 | #endif |
b76f0d8c | 548 | |
c45cb8bb RH |
549 | int gen_first_op_idx; |
550 | int gen_last_op_idx; | |
551 | int gen_next_op_idx; | |
552 | int gen_next_parm_idx; | |
8232a46a | 553 | |
1813e175 RH |
554 | /* Code generation. Note that we specifically do not use tcg_insn_unit |
555 | here, because there's too much arithmetic throughout that relies | |
556 | on addition and subtraction working on bytes. Rely on the GCC | |
557 | extension that allows arithmetic on void*. */ | |
0b0d3320 | 558 | int code_gen_max_blocks; |
1813e175 RH |
559 | void *code_gen_prologue; |
560 | void *code_gen_buffer; | |
0b0d3320 | 561 | size_t code_gen_buffer_size; |
1813e175 | 562 | void *code_gen_ptr; |
0b0d3320 | 563 | |
b125f9dc RH |
564 | /* Threshold to flush the translated code buffer. */ |
565 | void *code_gen_highwater; | |
566 | ||
5e5f07e0 EV |
567 | TBContext tb_ctx; |
568 | ||
9ecefc84 RH |
569 | /* The TCGBackendData structure is private to tcg-target.c. */ |
570 | struct TCGBackendData *be; | |
c45cb8bb RH |
571 | |
572 | TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; | |
573 | TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ | |
574 | ||
575 | /* tells in which temporary a given register is. It does not take | |
576 | into account fixed registers */ | |
577 | int reg_to_temp[TCG_TARGET_NB_REGS]; | |
578 | ||
579 | TCGOp gen_op_buf[OPC_BUF_SIZE]; | |
580 | TCGArg gen_opparam_buf[OPPARAM_BUF_SIZE]; | |
581 | ||
fca8a500 RH |
582 | uint16_t gen_insn_end_off[TCG_MAX_INSNS]; |
583 | target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; | |
c896fe29 FB |
584 | }; |
585 | ||
586 | extern TCGContext tcg_ctx; | |
c896fe29 | 587 | |
fe700adb RH |
588 | /* The number of opcodes emitted so far. */ |
589 | static inline int tcg_op_buf_count(void) | |
590 | { | |
c45cb8bb | 591 | return tcg_ctx.gen_next_op_idx; |
fe700adb RH |
592 | } |
593 | ||
594 | /* Test for whether to terminate the TB for using too many opcodes. */ | |
595 | static inline bool tcg_op_buf_full(void) | |
596 | { | |
597 | return tcg_op_buf_count() >= OPC_MAX_SIZE; | |
598 | } | |
599 | ||
c896fe29 FB |
600 | /* pool based memory allocation */ |
601 | ||
602 | void *tcg_malloc_internal(TCGContext *s, int size); | |
603 | void tcg_pool_reset(TCGContext *s); | |
604 | void tcg_pool_delete(TCGContext *s); | |
605 | ||
677ef623 FK |
606 | void tb_lock(void); |
607 | void tb_unlock(void); | |
608 | void tb_lock_reset(void); | |
609 | ||
c896fe29 FB |
610 | static inline void *tcg_malloc(int size) |
611 | { | |
612 | TCGContext *s = &tcg_ctx; | |
613 | uint8_t *ptr, *ptr_end; | |
614 | size = (size + sizeof(long) - 1) & ~(sizeof(long) - 1); | |
615 | ptr = s->pool_cur; | |
616 | ptr_end = ptr + size; | |
617 | if (unlikely(ptr_end > s->pool_end)) { | |
618 | return tcg_malloc_internal(&tcg_ctx, size); | |
619 | } else { | |
620 | s->pool_cur = ptr_end; | |
621 | return ptr; | |
622 | } | |
623 | } | |
624 | ||
625 | void tcg_context_init(TCGContext *s); | |
9002ec79 | 626 | void tcg_prologue_init(TCGContext *s); |
c896fe29 FB |
627 | void tcg_func_start(TCGContext *s); |
628 | ||
1813e175 | 629 | int tcg_gen_code(TCGContext *s, tcg_insn_unit *gen_code_buf); |
c896fe29 | 630 | |
e2c6d1b4 | 631 | void tcg_set_frame(TCGContext *s, int reg, intptr_t start, intptr_t size); |
a7812ae4 PB |
632 | |
633 | TCGv_i32 tcg_global_reg_new_i32(int reg, const char *name); | |
2f2f244d | 634 | TCGv_i32 tcg_global_mem_new_i32(int reg, intptr_t offset, const char *name); |
a7812ae4 PB |
635 | TCGv_i32 tcg_temp_new_internal_i32(int temp_local); |
636 | static inline TCGv_i32 tcg_temp_new_i32(void) | |
637 | { | |
638 | return tcg_temp_new_internal_i32(0); | |
639 | } | |
640 | static inline TCGv_i32 tcg_temp_local_new_i32(void) | |
641 | { | |
642 | return tcg_temp_new_internal_i32(1); | |
643 | } | |
644 | void tcg_temp_free_i32(TCGv_i32 arg); | |
645 | char *tcg_get_arg_str_i32(TCGContext *s, char *buf, int buf_size, TCGv_i32 arg); | |
646 | ||
647 | TCGv_i64 tcg_global_reg_new_i64(int reg, const char *name); | |
2f2f244d | 648 | TCGv_i64 tcg_global_mem_new_i64(int reg, intptr_t offset, const char *name); |
a7812ae4 PB |
649 | TCGv_i64 tcg_temp_new_internal_i64(int temp_local); |
650 | static inline TCGv_i64 tcg_temp_new_i64(void) | |
641d5fbe | 651 | { |
a7812ae4 | 652 | return tcg_temp_new_internal_i64(0); |
641d5fbe | 653 | } |
a7812ae4 | 654 | static inline TCGv_i64 tcg_temp_local_new_i64(void) |
641d5fbe | 655 | { |
a7812ae4 | 656 | return tcg_temp_new_internal_i64(1); |
641d5fbe | 657 | } |
a7812ae4 PB |
658 | void tcg_temp_free_i64(TCGv_i64 arg); |
659 | char *tcg_get_arg_str_i64(TCGContext *s, char *buf, int buf_size, TCGv_i64 arg); | |
660 | ||
27bfd83c PM |
661 | #if defined(CONFIG_DEBUG_TCG) |
662 | /* If you call tcg_clear_temp_count() at the start of a section of | |
663 | * code which is not supposed to leak any TCG temporaries, then | |
664 | * calling tcg_check_temp_count() at the end of the section will | |
665 | * return 1 if the section did in fact leak a temporary. | |
666 | */ | |
667 | void tcg_clear_temp_count(void); | |
668 | int tcg_check_temp_count(void); | |
669 | #else | |
670 | #define tcg_clear_temp_count() do { } while (0) | |
671 | #define tcg_check_temp_count() 0 | |
672 | #endif | |
673 | ||
405cf9ff | 674 | void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf); |
246ae24d | 675 | void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf); |
c896fe29 FB |
676 | |
677 | #define TCG_CT_ALIAS 0x80 | |
678 | #define TCG_CT_IALIAS 0x40 | |
679 | #define TCG_CT_REG 0x01 | |
680 | #define TCG_CT_CONST 0x02 /* any constant of register size */ | |
681 | ||
682 | typedef struct TCGArgConstraint { | |
5ff9d6a4 FB |
683 | uint16_t ct; |
684 | uint8_t alias_index; | |
c896fe29 FB |
685 | union { |
686 | TCGRegSet regs; | |
687 | } u; | |
688 | } TCGArgConstraint; | |
689 | ||
690 | #define TCG_MAX_OP_ARGS 16 | |
691 | ||
8399ad59 RH |
692 | /* Bits for TCGOpDef->flags, 8 bits available. */ |
693 | enum { | |
694 | /* Instruction defines the end of a basic block. */ | |
695 | TCG_OPF_BB_END = 0x01, | |
696 | /* Instruction clobbers call registers and potentially update globals. */ | |
697 | TCG_OPF_CALL_CLOBBER = 0x02, | |
3d5c5f87 AJ |
698 | /* Instruction has side effects: it cannot be removed if its outputs |
699 | are not used, and might trigger exceptions. */ | |
8399ad59 RH |
700 | TCG_OPF_SIDE_EFFECTS = 0x04, |
701 | /* Instruction operands are 64-bits (otherwise 32-bits). */ | |
702 | TCG_OPF_64BIT = 0x08, | |
c1a61f6c RH |
703 | /* Instruction is optional and not implemented by the host, or insn |
704 | is generic and should not be implemened by the host. */ | |
25c4d9cc | 705 | TCG_OPF_NOT_PRESENT = 0x10, |
8399ad59 | 706 | }; |
c896fe29 FB |
707 | |
708 | typedef struct TCGOpDef { | |
709 | const char *name; | |
710 | uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; | |
711 | uint8_t flags; | |
c896fe29 FB |
712 | TCGArgConstraint *args_ct; |
713 | int *sorted_args; | |
c68aaa18 SW |
714 | #if defined(CONFIG_DEBUG_TCG) |
715 | int used; | |
716 | #endif | |
c896fe29 | 717 | } TCGOpDef; |
8399ad59 RH |
718 | |
719 | extern TCGOpDef tcg_op_defs[]; | |
2a24374a SW |
720 | extern const size_t tcg_op_defs_max; |
721 | ||
c896fe29 | 722 | typedef struct TCGTargetOpDef { |
a9751609 | 723 | TCGOpcode op; |
c896fe29 FB |
724 | const char *args_ct_str[TCG_MAX_OP_ARGS]; |
725 | } TCGTargetOpDef; | |
726 | ||
c896fe29 FB |
727 | #define tcg_abort() \ |
728 | do {\ | |
729 | fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\ | |
730 | abort();\ | |
731 | } while (0) | |
732 | ||
c552d6c0 RH |
733 | #ifdef CONFIG_DEBUG_TCG |
734 | # define tcg_debug_assert(X) do { assert(X); } while (0) | |
735 | #elif QEMU_GNUC_PREREQ(4, 5) | |
736 | # define tcg_debug_assert(X) \ | |
737 | do { if (!(X)) { __builtin_unreachable(); } } while (0) | |
738 | #else | |
739 | # define tcg_debug_assert(X) do { (void)(X); } while (0) | |
740 | #endif | |
741 | ||
c896fe29 FB |
742 | void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs); |
743 | ||
8b73d49f | 744 | #if UINTPTR_MAX == UINT32_MAX |
ebecf363 PM |
745 | #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I32(n)) |
746 | #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I32(GET_TCGV_PTR(n)) | |
747 | ||
8b73d49f | 748 | #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V))) |
ebecf363 PM |
749 | #define tcg_global_reg_new_ptr(R, N) \ |
750 | TCGV_NAT_TO_PTR(tcg_global_reg_new_i32((R), (N))) | |
751 | #define tcg_global_mem_new_ptr(R, O, N) \ | |
752 | TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N))) | |
753 | #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32()) | |
754 | #define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T)) | |
c896fe29 | 755 | #else |
ebecf363 PM |
756 | #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I64(n)) |
757 | #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I64(GET_TCGV_PTR(n)) | |
758 | ||
8b73d49f | 759 | #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V))) |
ebecf363 PM |
760 | #define tcg_global_reg_new_ptr(R, N) \ |
761 | TCGV_NAT_TO_PTR(tcg_global_reg_new_i64((R), (N))) | |
762 | #define tcg_global_mem_new_ptr(R, O, N) \ | |
763 | TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N))) | |
764 | #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64()) | |
765 | #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T)) | |
c896fe29 FB |
766 | #endif |
767 | ||
bbb8a1b4 RH |
768 | void tcg_gen_callN(TCGContext *s, void *func, |
769 | TCGArg ret, int nargs, TCGArg *args); | |
a7812ae4 | 770 | |
0c627cdc | 771 | void tcg_op_remove(TCGContext *s, TCGOp *op); |
c45cb8bb | 772 | void tcg_optimize(TCGContext *s); |
8f2e8c07 | 773 | |
a7812ae4 | 774 | /* only used for debugging purposes */ |
eeacee4d | 775 | void tcg_dump_ops(TCGContext *s); |
a7812ae4 PB |
776 | |
777 | void dump_ops(const uint16_t *opc_buf, const TCGArg *opparam_buf); | |
778 | TCGv_i32 tcg_const_i32(int32_t val); | |
779 | TCGv_i64 tcg_const_i64(int64_t val); | |
780 | TCGv_i32 tcg_const_local_i32(int32_t val); | |
781 | TCGv_i64 tcg_const_local_i64(int64_t val); | |
782 | ||
42a268c2 RH |
783 | TCGLabel *gen_new_label(void); |
784 | ||
785 | /** | |
786 | * label_arg | |
787 | * @l: label | |
788 | * | |
789 | * Encode a label for storage in the TCG opcode stream. | |
790 | */ | |
791 | ||
792 | static inline TCGArg label_arg(TCGLabel *l) | |
793 | { | |
51e3972c | 794 | return (uintptr_t)l; |
42a268c2 RH |
795 | } |
796 | ||
797 | /** | |
798 | * arg_label | |
799 | * @i: value | |
800 | * | |
801 | * The opposite of label_arg. Retrieve a label from the | |
802 | * encoding of the TCG opcode stream. | |
803 | */ | |
804 | ||
51e3972c | 805 | static inline TCGLabel *arg_label(TCGArg i) |
42a268c2 | 806 | { |
51e3972c | 807 | return (TCGLabel *)(uintptr_t)i; |
42a268c2 RH |
808 | } |
809 | ||
52a1f64e RH |
810 | /** |
811 | * tcg_ptr_byte_diff | |
812 | * @a, @b: addresses to be differenced | |
813 | * | |
814 | * There are many places within the TCG backends where we need a byte | |
815 | * difference between two pointers. While this can be accomplished | |
816 | * with local casting, it's easy to get wrong -- especially if one is | |
817 | * concerned with the signedness of the result. | |
818 | * | |
819 | * This version relies on GCC's void pointer arithmetic to get the | |
820 | * correct result. | |
821 | */ | |
822 | ||
823 | static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b) | |
824 | { | |
825 | return a - b; | |
826 | } | |
827 | ||
828 | /** | |
829 | * tcg_pcrel_diff | |
830 | * @s: the tcg context | |
831 | * @target: address of the target | |
832 | * | |
833 | * Produce a pc-relative difference, from the current code_ptr | |
834 | * to the destination address. | |
835 | */ | |
836 | ||
837 | static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target) | |
838 | { | |
839 | return tcg_ptr_byte_diff(target, s->code_ptr); | |
840 | } | |
841 | ||
842 | /** | |
843 | * tcg_current_code_size | |
844 | * @s: the tcg context | |
845 | * | |
846 | * Compute the current code size within the translation block. | |
847 | * This is used to fill in qemu's data structures for goto_tb. | |
848 | */ | |
849 | ||
850 | static inline size_t tcg_current_code_size(TCGContext *s) | |
851 | { | |
852 | return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); | |
853 | } | |
854 | ||
59227d5d RH |
855 | /* Combine the TCGMemOp and mmu_idx parameters into a single value. */ |
856 | typedef uint32_t TCGMemOpIdx; | |
857 | ||
858 | /** | |
859 | * make_memop_idx | |
860 | * @op: memory operation | |
861 | * @idx: mmu index | |
862 | * | |
863 | * Encode these values into a single parameter. | |
864 | */ | |
865 | static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx) | |
866 | { | |
867 | tcg_debug_assert(idx <= 15); | |
868 | return (op << 4) | idx; | |
869 | } | |
870 | ||
871 | /** | |
872 | * get_memop | |
873 | * @oi: combined op/idx parameter | |
874 | * | |
875 | * Extract the memory operation from the combined value. | |
876 | */ | |
877 | static inline TCGMemOp get_memop(TCGMemOpIdx oi) | |
878 | { | |
879 | return oi >> 4; | |
880 | } | |
881 | ||
882 | /** | |
883 | * get_mmuidx | |
884 | * @oi: combined op/idx parameter | |
885 | * | |
886 | * Extract the mmu index from the combined value. | |
887 | */ | |
888 | static inline unsigned get_mmuidx(TCGMemOpIdx oi) | |
889 | { | |
890 | return oi & 15; | |
891 | } | |
892 | ||
0980011b PM |
893 | /** |
894 | * tcg_qemu_tb_exec: | |
895 | * @env: CPUArchState * for the CPU | |
896 | * @tb_ptr: address of generated code for the TB to execute | |
897 | * | |
898 | * Start executing code from a given translation block. | |
899 | * Where translation blocks have been linked, execution | |
900 | * may proceed from the given TB into successive ones. | |
901 | * Control eventually returns only when some action is needed | |
902 | * from the top-level loop: either control must pass to a TB | |
903 | * which has not yet been directly linked, or an asynchronous | |
904 | * event such as an interrupt needs handling. | |
905 | * | |
906 | * The return value is a pointer to the next TB to execute | |
907 | * (if known; otherwise zero). This pointer is assumed to be | |
908 | * 4-aligned, and the bottom two bits are used to return further | |
909 | * information: | |
910 | * 0, 1: the link between this TB and the next is via the specified | |
911 | * TB index (0 or 1). That is, we left the TB via (the equivalent | |
912 | * of) "goto_tb <index>". The main loop uses this to determine | |
913 | * how to link the TB just executed to the next. | |
914 | * 2: we are using instruction counting code generation, and we | |
915 | * did not start executing this TB because the instruction counter | |
916 | * would hit zero midway through it. In this case the next-TB pointer | |
917 | * returned is the TB we were about to execute, and the caller must | |
918 | * arrange to execute the remaining count of instructions. | |
378df4b2 PM |
919 | * 3: we stopped because the CPU's exit_request flag was set |
920 | * (usually meaning that there is an interrupt that needs to be | |
921 | * handled). The next-TB pointer returned is the TB we were | |
922 | * about to execute when we noticed the pending exit request. | |
0980011b PM |
923 | * |
924 | * If the bottom two bits indicate an exit-via-index then the CPU | |
925 | * state is correctly synchronised and ready for execution of the next | |
926 | * TB (and in particular the guest PC is the address to execute next). | |
927 | * Otherwise, we gave up on execution of this TB before it started, and | |
fee068e4 PC |
928 | * the caller must fix up the CPU state by calling the CPU's |
929 | * synchronize_from_tb() method with the next-TB pointer we return (falling | |
930 | * back to calling the CPU's set_pc method with tb->pb if no | |
931 | * synchronize_from_tb() method exists). | |
0980011b PM |
932 | * |
933 | * Note that TCG targets may use a different definition of tcg_qemu_tb_exec | |
934 | * to this default (which just calls the prologue.code emitted by | |
935 | * tcg_target_qemu_prologue()). | |
936 | */ | |
937 | #define TB_EXIT_MASK 3 | |
938 | #define TB_EXIT_IDX0 0 | |
939 | #define TB_EXIT_IDX1 1 | |
940 | #define TB_EXIT_ICOUNT_EXPIRED 2 | |
378df4b2 | 941 | #define TB_EXIT_REQUESTED 3 |
0980011b | 942 | |
5a58e884 PB |
943 | #ifdef HAVE_TCG_QEMU_TB_EXEC |
944 | uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); | |
945 | #else | |
ce285b17 | 946 | # define tcg_qemu_tb_exec(env, tb_ptr) \ |
04d5a1da | 947 | ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr) |
932a6909 | 948 | #endif |
813da627 RH |
949 | |
950 | void tcg_register_jit(void *buf, size_t buf_size); | |
b76f0d8c | 951 | |
e58eb534 RH |
952 | /* |
953 | * Memory helpers that will be used by TCG generated code. | |
954 | */ | |
955 | #ifdef CONFIG_SOFTMMU | |
c8f94df5 RH |
956 | /* Value zero-extended to tcg register size. */ |
957 | tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, | |
3972ef6f | 958 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 959 | tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 960 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 961 | tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 962 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 963 | uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 964 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 965 | tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 966 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 967 | tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 968 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 969 | uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 970 | TCGMemOpIdx oi, uintptr_t retaddr); |
e58eb534 | 971 | |
c8f94df5 RH |
972 | /* Value sign-extended to tcg register size. */ |
973 | tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, | |
3972ef6f | 974 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 975 | tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 976 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 977 | tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 978 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 979 | tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 980 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 981 | tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 982 | TCGMemOpIdx oi, uintptr_t retaddr); |
c8f94df5 | 983 | |
e58eb534 | 984 | void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, |
3972ef6f | 985 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 986 | void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, |
3972ef6f | 987 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 988 | void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, |
3972ef6f | 989 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 990 | void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, |
3972ef6f | 991 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 992 | void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, |
3972ef6f | 993 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 994 | void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, |
3972ef6f | 995 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 996 | void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, |
3972ef6f | 997 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 998 | |
282dffc8 PD |
999 | uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, |
1000 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1001 | uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, | |
1002 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1003 | uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr, | |
1004 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1005 | uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, | |
1006 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1007 | uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, | |
1008 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1009 | uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr, | |
1010 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1011 | uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, | |
1012 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1013 | ||
867b3201 RH |
1014 | /* Temporary aliases until backends are converted. */ |
1015 | #ifdef TARGET_WORDS_BIGENDIAN | |
1016 | # define helper_ret_ldsw_mmu helper_be_ldsw_mmu | |
1017 | # define helper_ret_lduw_mmu helper_be_lduw_mmu | |
1018 | # define helper_ret_ldsl_mmu helper_be_ldsl_mmu | |
1019 | # define helper_ret_ldul_mmu helper_be_ldul_mmu | |
282dffc8 | 1020 | # define helper_ret_ldl_mmu helper_be_ldul_mmu |
867b3201 RH |
1021 | # define helper_ret_ldq_mmu helper_be_ldq_mmu |
1022 | # define helper_ret_stw_mmu helper_be_stw_mmu | |
1023 | # define helper_ret_stl_mmu helper_be_stl_mmu | |
1024 | # define helper_ret_stq_mmu helper_be_stq_mmu | |
282dffc8 PD |
1025 | # define helper_ret_ldw_cmmu helper_be_ldw_cmmu |
1026 | # define helper_ret_ldl_cmmu helper_be_ldl_cmmu | |
1027 | # define helper_ret_ldq_cmmu helper_be_ldq_cmmu | |
867b3201 RH |
1028 | #else |
1029 | # define helper_ret_ldsw_mmu helper_le_ldsw_mmu | |
1030 | # define helper_ret_lduw_mmu helper_le_lduw_mmu | |
1031 | # define helper_ret_ldsl_mmu helper_le_ldsl_mmu | |
1032 | # define helper_ret_ldul_mmu helper_le_ldul_mmu | |
282dffc8 | 1033 | # define helper_ret_ldl_mmu helper_le_ldul_mmu |
867b3201 RH |
1034 | # define helper_ret_ldq_mmu helper_le_ldq_mmu |
1035 | # define helper_ret_stw_mmu helper_le_stw_mmu | |
1036 | # define helper_ret_stl_mmu helper_le_stl_mmu | |
1037 | # define helper_ret_stq_mmu helper_le_stq_mmu | |
282dffc8 PD |
1038 | # define helper_ret_ldw_cmmu helper_le_ldw_cmmu |
1039 | # define helper_ret_ldl_cmmu helper_le_ldl_cmmu | |
1040 | # define helper_ret_ldq_cmmu helper_le_ldq_cmmu | |
867b3201 | 1041 | #endif |
e58eb534 | 1042 | |
e58eb534 RH |
1043 | #endif /* CONFIG_SOFTMMU */ |
1044 | ||
1045 | #endif /* TCG_H */ |