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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e58eb534 RH |
24 | |
25 | #ifndef TCG_H | |
26 | #define TCG_H | |
27 | ||
f8393946 | 28 | #include "qemu-common.h" |
33c11879 | 29 | #include "cpu.h" |
00f6da6a | 30 | #include "exec/tb-context.h" |
0ec9eabc | 31 | #include "qemu/bitops.h" |
20937143 | 32 | #include "tcg-mo.h" |
78cd7b83 RH |
33 | #include "tcg-target.h" |
34 | ||
00f6da6a PB |
35 | /* XXX: make safe guess about sizes */ |
36 | #define MAX_OP_PER_INSTR 266 | |
37 | ||
38 | #if HOST_LONG_BITS == 32 | |
39 | #define MAX_OPC_PARAM_PER_ARG 2 | |
40 | #else | |
41 | #define MAX_OPC_PARAM_PER_ARG 1 | |
42 | #endif | |
43 | #define MAX_OPC_PARAM_IARGS 5 | |
44 | #define MAX_OPC_PARAM_OARGS 1 | |
45 | #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS) | |
46 | ||
47 | /* A Call op needs up to 4 + 2N parameters on 32-bit archs, | |
48 | * and up to 4 + N parameters on 64-bit archs | |
49 | * (N = number of input arguments + output arguments). */ | |
50 | #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) | |
51 | #define OPC_BUF_SIZE 640 | |
52 | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) | |
53 | ||
6e0b0730 PC |
54 | #define CPU_TEMP_BUF_NLONGS 128 |
55 | ||
78cd7b83 RH |
56 | /* Default target word size to pointer size. */ |
57 | #ifndef TCG_TARGET_REG_BITS | |
58 | # if UINTPTR_MAX == UINT32_MAX | |
59 | # define TCG_TARGET_REG_BITS 32 | |
60 | # elif UINTPTR_MAX == UINT64_MAX | |
61 | # define TCG_TARGET_REG_BITS 64 | |
62 | # else | |
63 | # error Unknown pointer size for tcg target | |
64 | # endif | |
817b838e SW |
65 | #endif |
66 | ||
c896fe29 FB |
67 | #if TCG_TARGET_REG_BITS == 32 |
68 | typedef int32_t tcg_target_long; | |
69 | typedef uint32_t tcg_target_ulong; | |
70 | #define TCG_PRIlx PRIx32 | |
71 | #define TCG_PRIld PRId32 | |
72 | #elif TCG_TARGET_REG_BITS == 64 | |
73 | typedef int64_t tcg_target_long; | |
74 | typedef uint64_t tcg_target_ulong; | |
75 | #define TCG_PRIlx PRIx64 | |
76 | #define TCG_PRIld PRId64 | |
77 | #else | |
78 | #error unsupported | |
79 | #endif | |
80 | ||
8d4e9146 FK |
81 | /* Oversized TCG guests make things like MTTCG hard |
82 | * as we can't use atomics for cputlb updates. | |
83 | */ | |
84 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS | |
85 | #define TCG_OVERSIZED_GUEST 1 | |
86 | #else | |
87 | #define TCG_OVERSIZED_GUEST 0 | |
88 | #endif | |
89 | ||
c896fe29 FB |
90 | #if TCG_TARGET_NB_REGS <= 32 |
91 | typedef uint32_t TCGRegSet; | |
92 | #elif TCG_TARGET_NB_REGS <= 64 | |
93 | typedef uint64_t TCGRegSet; | |
94 | #else | |
95 | #error unsupported | |
96 | #endif | |
97 | ||
25c4d9cc | 98 | #if TCG_TARGET_REG_BITS == 32 |
e6a72734 | 99 | /* Turn some undef macros into false macros. */ |
609ad705 RH |
100 | #define TCG_TARGET_HAS_extrl_i64_i32 0 |
101 | #define TCG_TARGET_HAS_extrh_i64_i32 0 | |
25c4d9cc | 102 | #define TCG_TARGET_HAS_div_i64 0 |
ca675f46 | 103 | #define TCG_TARGET_HAS_rem_i64 0 |
25c4d9cc RH |
104 | #define TCG_TARGET_HAS_div2_i64 0 |
105 | #define TCG_TARGET_HAS_rot_i64 0 | |
106 | #define TCG_TARGET_HAS_ext8s_i64 0 | |
107 | #define TCG_TARGET_HAS_ext16s_i64 0 | |
108 | #define TCG_TARGET_HAS_ext32s_i64 0 | |
109 | #define TCG_TARGET_HAS_ext8u_i64 0 | |
110 | #define TCG_TARGET_HAS_ext16u_i64 0 | |
111 | #define TCG_TARGET_HAS_ext32u_i64 0 | |
112 | #define TCG_TARGET_HAS_bswap16_i64 0 | |
113 | #define TCG_TARGET_HAS_bswap32_i64 0 | |
114 | #define TCG_TARGET_HAS_bswap64_i64 0 | |
115 | #define TCG_TARGET_HAS_neg_i64 0 | |
116 | #define TCG_TARGET_HAS_not_i64 0 | |
117 | #define TCG_TARGET_HAS_andc_i64 0 | |
118 | #define TCG_TARGET_HAS_orc_i64 0 | |
119 | #define TCG_TARGET_HAS_eqv_i64 0 | |
120 | #define TCG_TARGET_HAS_nand_i64 0 | |
121 | #define TCG_TARGET_HAS_nor_i64 0 | |
0e28d006 RH |
122 | #define TCG_TARGET_HAS_clz_i64 0 |
123 | #define TCG_TARGET_HAS_ctz_i64 0 | |
a768e4e9 | 124 | #define TCG_TARGET_HAS_ctpop_i64 0 |
25c4d9cc | 125 | #define TCG_TARGET_HAS_deposit_i64 0 |
7ec8bab3 RH |
126 | #define TCG_TARGET_HAS_extract_i64 0 |
127 | #define TCG_TARGET_HAS_sextract_i64 0 | |
ffc5ea09 | 128 | #define TCG_TARGET_HAS_movcond_i64 0 |
d7156f7c RH |
129 | #define TCG_TARGET_HAS_add2_i64 0 |
130 | #define TCG_TARGET_HAS_sub2_i64 0 | |
131 | #define TCG_TARGET_HAS_mulu2_i64 0 | |
4d3203fd | 132 | #define TCG_TARGET_HAS_muls2_i64 0 |
03271524 RH |
133 | #define TCG_TARGET_HAS_muluh_i64 0 |
134 | #define TCG_TARGET_HAS_mulsh_i64 0 | |
e6a72734 RH |
135 | /* Turn some undef macros into true macros. */ |
136 | #define TCG_TARGET_HAS_add2_i32 1 | |
137 | #define TCG_TARGET_HAS_sub2_i32 1 | |
25c4d9cc RH |
138 | #endif |
139 | ||
a4773324 JK |
140 | #ifndef TCG_TARGET_deposit_i32_valid |
141 | #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 | |
142 | #endif | |
143 | #ifndef TCG_TARGET_deposit_i64_valid | |
144 | #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 | |
145 | #endif | |
7ec8bab3 RH |
146 | #ifndef TCG_TARGET_extract_i32_valid |
147 | #define TCG_TARGET_extract_i32_valid(ofs, len) 1 | |
148 | #endif | |
149 | #ifndef TCG_TARGET_extract_i64_valid | |
150 | #define TCG_TARGET_extract_i64_valid(ofs, len) 1 | |
151 | #endif | |
a4773324 | 152 | |
25c4d9cc RH |
153 | /* Only one of DIV or DIV2 should be defined. */ |
154 | #if defined(TCG_TARGET_HAS_div_i32) | |
155 | #define TCG_TARGET_HAS_div2_i32 0 | |
156 | #elif defined(TCG_TARGET_HAS_div2_i32) | |
157 | #define TCG_TARGET_HAS_div_i32 0 | |
ca675f46 | 158 | #define TCG_TARGET_HAS_rem_i32 0 |
25c4d9cc RH |
159 | #endif |
160 | #if defined(TCG_TARGET_HAS_div_i64) | |
161 | #define TCG_TARGET_HAS_div2_i64 0 | |
162 | #elif defined(TCG_TARGET_HAS_div2_i64) | |
163 | #define TCG_TARGET_HAS_div_i64 0 | |
ca675f46 | 164 | #define TCG_TARGET_HAS_rem_i64 0 |
25c4d9cc RH |
165 | #endif |
166 | ||
df9ebea5 RH |
167 | /* For 32-bit targets, some sort of unsigned widening multiply is required. */ |
168 | #if TCG_TARGET_REG_BITS == 32 \ | |
169 | && !(defined(TCG_TARGET_HAS_mulu2_i32) \ | |
170 | || defined(TCG_TARGET_HAS_muluh_i32)) | |
171 | # error "Missing unsigned widening multiply" | |
172 | #endif | |
173 | ||
9aef40ed RH |
174 | #ifndef TARGET_INSN_START_EXTRA_WORDS |
175 | # define TARGET_INSN_START_WORDS 1 | |
176 | #else | |
177 | # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) | |
178 | #endif | |
179 | ||
a9751609 | 180 | typedef enum TCGOpcode { |
c61aaf7a | 181 | #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, |
c896fe29 FB |
182 | #include "tcg-opc.h" |
183 | #undef DEF | |
184 | NB_OPS, | |
a9751609 | 185 | } TCGOpcode; |
c896fe29 | 186 | |
80a8b9a9 RH |
187 | #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) |
188 | #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) | |
189 | #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) | |
c896fe29 | 190 | |
1813e175 | 191 | #ifndef TCG_TARGET_INSN_UNIT_SIZE |
5053361b RH |
192 | # error "Missing TCG_TARGET_INSN_UNIT_SIZE" |
193 | #elif TCG_TARGET_INSN_UNIT_SIZE == 1 | |
1813e175 RH |
194 | typedef uint8_t tcg_insn_unit; |
195 | #elif TCG_TARGET_INSN_UNIT_SIZE == 2 | |
196 | typedef uint16_t tcg_insn_unit; | |
197 | #elif TCG_TARGET_INSN_UNIT_SIZE == 4 | |
198 | typedef uint32_t tcg_insn_unit; | |
199 | #elif TCG_TARGET_INSN_UNIT_SIZE == 8 | |
200 | typedef uint64_t tcg_insn_unit; | |
201 | #else | |
202 | /* The port better have done this. */ | |
203 | #endif | |
204 | ||
205 | ||
8bff06a0 | 206 | #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS |
1f00b27f SS |
207 | # define tcg_debug_assert(X) do { assert(X); } while (0) |
208 | #elif QEMU_GNUC_PREREQ(4, 5) | |
209 | # define tcg_debug_assert(X) \ | |
210 | do { if (!(X)) { __builtin_unreachable(); } } while (0) | |
211 | #else | |
212 | # define tcg_debug_assert(X) do { (void)(X); } while (0) | |
213 | #endif | |
214 | ||
c896fe29 FB |
215 | typedef struct TCGRelocation { |
216 | struct TCGRelocation *next; | |
217 | int type; | |
1813e175 | 218 | tcg_insn_unit *ptr; |
2ba7fae2 | 219 | intptr_t addend; |
c896fe29 FB |
220 | } TCGRelocation; |
221 | ||
222 | typedef struct TCGLabel { | |
51e3972c RH |
223 | unsigned has_value : 1; |
224 | unsigned id : 31; | |
c896fe29 | 225 | union { |
2ba7fae2 | 226 | uintptr_t value; |
1813e175 | 227 | tcg_insn_unit *value_ptr; |
c896fe29 FB |
228 | TCGRelocation *first_reloc; |
229 | } u; | |
230 | } TCGLabel; | |
231 | ||
232 | typedef struct TCGPool { | |
233 | struct TCGPool *next; | |
c44f945a BS |
234 | int size; |
235 | uint8_t data[0] __attribute__ ((aligned)); | |
c896fe29 FB |
236 | } TCGPool; |
237 | ||
238 | #define TCG_POOL_CHUNK_SIZE 32768 | |
239 | ||
c4071c90 | 240 | #define TCG_MAX_TEMPS 512 |
190ce7fb | 241 | #define TCG_MAX_INSNS 512 |
c896fe29 | 242 | |
b03cce8e FB |
243 | /* when the size of the arguments of a called function is smaller than |
244 | this value, they are statically allocated in the TB stack frame */ | |
245 | #define TCG_STATIC_CALL_ARGS_SIZE 128 | |
246 | ||
c02244a5 RH |
247 | typedef enum TCGType { |
248 | TCG_TYPE_I32, | |
249 | TCG_TYPE_I64, | |
250 | TCG_TYPE_COUNT, /* number of different types */ | |
c896fe29 | 251 | |
3b6dac34 | 252 | /* An alias for the size of the host register. */ |
c896fe29 | 253 | #if TCG_TARGET_REG_BITS == 32 |
3b6dac34 | 254 | TCG_TYPE_REG = TCG_TYPE_I32, |
c02244a5 | 255 | #else |
3b6dac34 | 256 | TCG_TYPE_REG = TCG_TYPE_I64, |
c02244a5 | 257 | #endif |
3b6dac34 | 258 | |
d289837e RH |
259 | /* An alias for the size of the native pointer. */ |
260 | #if UINTPTR_MAX == UINT32_MAX | |
261 | TCG_TYPE_PTR = TCG_TYPE_I32, | |
262 | #else | |
263 | TCG_TYPE_PTR = TCG_TYPE_I64, | |
264 | #endif | |
3b6dac34 RH |
265 | |
266 | /* An alias for the size of the target "long", aka register. */ | |
c02244a5 RH |
267 | #if TARGET_LONG_BITS == 64 |
268 | TCG_TYPE_TL = TCG_TYPE_I64, | |
c896fe29 | 269 | #else |
c02244a5 | 270 | TCG_TYPE_TL = TCG_TYPE_I32, |
c896fe29 | 271 | #endif |
c02244a5 | 272 | } TCGType; |
c896fe29 | 273 | |
6c5f4ead RH |
274 | /* Constants for qemu_ld and qemu_st for the Memory Operation field. */ |
275 | typedef enum TCGMemOp { | |
276 | MO_8 = 0, | |
277 | MO_16 = 1, | |
278 | MO_32 = 2, | |
279 | MO_64 = 3, | |
280 | MO_SIZE = 3, /* Mask for the above. */ | |
281 | ||
282 | MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */ | |
283 | ||
284 | MO_BSWAP = 8, /* Host reverse endian. */ | |
285 | #ifdef HOST_WORDS_BIGENDIAN | |
286 | MO_LE = MO_BSWAP, | |
287 | MO_BE = 0, | |
288 | #else | |
289 | MO_LE = 0, | |
290 | MO_BE = MO_BSWAP, | |
291 | #endif | |
292 | #ifdef TARGET_WORDS_BIGENDIAN | |
293 | MO_TE = MO_BE, | |
294 | #else | |
295 | MO_TE = MO_LE, | |
296 | #endif | |
297 | ||
dfb36305 | 298 | /* MO_UNALN accesses are never checked for alignment. |
1f00b27f SS |
299 | * MO_ALIGN accesses will result in a call to the CPU's |
300 | * do_unaligned_access hook if the guest address is not aligned. | |
301 | * The default depends on whether the target CPU defines ALIGNED_ONLY. | |
85aa8081 | 302 | * |
1f00b27f SS |
303 | * Some architectures (e.g. ARMv8) need the address which is aligned |
304 | * to a size more than the size of the memory access. | |
85aa8081 RH |
305 | * Some architectures (e.g. SPARCv9) need an address which is aligned, |
306 | * but less strictly than the natural alignment. | |
307 | * | |
308 | * MO_ALIGN supposes the alignment size is the size of a memory access. | |
309 | * | |
1f00b27f | 310 | * There are three options: |
1f00b27f | 311 | * - unaligned access permitted (MO_UNALN). |
85aa8081 RH |
312 | * - an alignment to the size of an access (MO_ALIGN); |
313 | * - an alignment to a specified size, which may be more or less than | |
314 | * the access size (MO_ALIGN_x where 'x' is a size in bytes); | |
1f00b27f SS |
315 | */ |
316 | MO_ASHIFT = 4, | |
317 | MO_AMASK = 7 << MO_ASHIFT, | |
dfb36305 RH |
318 | #ifdef ALIGNED_ONLY |
319 | MO_ALIGN = 0, | |
320 | MO_UNALN = MO_AMASK, | |
321 | #else | |
322 | MO_ALIGN = MO_AMASK, | |
323 | MO_UNALN = 0, | |
324 | #endif | |
1f00b27f SS |
325 | MO_ALIGN_2 = 1 << MO_ASHIFT, |
326 | MO_ALIGN_4 = 2 << MO_ASHIFT, | |
327 | MO_ALIGN_8 = 3 << MO_ASHIFT, | |
328 | MO_ALIGN_16 = 4 << MO_ASHIFT, | |
329 | MO_ALIGN_32 = 5 << MO_ASHIFT, | |
330 | MO_ALIGN_64 = 6 << MO_ASHIFT, | |
dfb36305 | 331 | |
6c5f4ead RH |
332 | /* Combinations of the above, for ease of use. */ |
333 | MO_UB = MO_8, | |
334 | MO_UW = MO_16, | |
335 | MO_UL = MO_32, | |
336 | MO_SB = MO_SIGN | MO_8, | |
337 | MO_SW = MO_SIGN | MO_16, | |
338 | MO_SL = MO_SIGN | MO_32, | |
339 | MO_Q = MO_64, | |
340 | ||
341 | MO_LEUW = MO_LE | MO_UW, | |
342 | MO_LEUL = MO_LE | MO_UL, | |
343 | MO_LESW = MO_LE | MO_SW, | |
344 | MO_LESL = MO_LE | MO_SL, | |
345 | MO_LEQ = MO_LE | MO_Q, | |
346 | ||
347 | MO_BEUW = MO_BE | MO_UW, | |
348 | MO_BEUL = MO_BE | MO_UL, | |
349 | MO_BESW = MO_BE | MO_SW, | |
350 | MO_BESL = MO_BE | MO_SL, | |
351 | MO_BEQ = MO_BE | MO_Q, | |
352 | ||
353 | MO_TEUW = MO_TE | MO_UW, | |
354 | MO_TEUL = MO_TE | MO_UL, | |
355 | MO_TESW = MO_TE | MO_SW, | |
356 | MO_TESL = MO_TE | MO_SL, | |
357 | MO_TEQ = MO_TE | MO_Q, | |
358 | ||
359 | MO_SSIZE = MO_SIZE | MO_SIGN, | |
360 | } TCGMemOp; | |
361 | ||
1f00b27f SS |
362 | /** |
363 | * get_alignment_bits | |
364 | * @memop: TCGMemOp value | |
365 | * | |
366 | * Extract the alignment size from the memop. | |
1f00b27f | 367 | */ |
85aa8081 | 368 | static inline unsigned get_alignment_bits(TCGMemOp memop) |
1f00b27f | 369 | { |
85aa8081 | 370 | unsigned a = memop & MO_AMASK; |
1f00b27f SS |
371 | |
372 | if (a == MO_UNALN) { | |
85aa8081 RH |
373 | /* No alignment required. */ |
374 | a = 0; | |
1f00b27f | 375 | } else if (a == MO_ALIGN) { |
85aa8081 RH |
376 | /* A natural alignment requirement. */ |
377 | a = memop & MO_SIZE; | |
1f00b27f | 378 | } else { |
85aa8081 RH |
379 | /* A specific alignment requirement. */ |
380 | a = a >> MO_ASHIFT; | |
1f00b27f SS |
381 | } |
382 | #if defined(CONFIG_SOFTMMU) | |
383 | /* The requested alignment cannot overlap the TLB flags. */ | |
85aa8081 | 384 | tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); |
1f00b27f | 385 | #endif |
85aa8081 | 386 | return a; |
1f00b27f SS |
387 | } |
388 | ||
c896fe29 FB |
389 | typedef tcg_target_ulong TCGArg; |
390 | ||
a40d4701 PM |
391 | /* Define type and accessor macros for TCG variables. |
392 | ||
393 | TCG variables are the inputs and outputs of TCG ops, as described | |
394 | in tcg/README. Target CPU front-end code uses these types to deal | |
395 | with TCG variables as it emits TCG code via the tcg_gen_* functions. | |
396 | They come in several flavours: | |
397 | * TCGv_i32 : 32 bit integer type | |
398 | * TCGv_i64 : 64 bit integer type | |
399 | * TCGv_ptr : a host pointer type | |
400 | * TCGv : an integer type the same size as target_ulong | |
401 | (an alias for either TCGv_i32 or TCGv_i64) | |
402 | The compiler's type checking will complain if you mix them | |
403 | up and pass the wrong sized TCGv to a function. | |
404 | ||
405 | Users of tcg_gen_* don't need to know about any of the internal | |
406 | details of these, and should treat them as opaque types. | |
407 | You won't be able to look inside them in a debugger either. | |
408 | ||
409 | Internal implementation details follow: | |
410 | ||
411 | Note that there is no definition of the structs TCGv_i32_d etc anywhere. | |
412 | This is deliberate, because the values we store in variables of type | |
413 | TCGv_i32 are not really pointers-to-structures. They're just small | |
414 | integers, but keeping them in pointer types like this means that the | |
415 | compiler will complain if you accidentally pass a TCGv_i32 to a | |
416 | function which takes a TCGv_i64, and so on. Only the internals of | |
dc41aa7d | 417 | TCG need to care about the actual contents of the types. */ |
ac56dd48 | 418 | |
b6c73a6d RH |
419 | typedef struct TCGv_i32_d *TCGv_i32; |
420 | typedef struct TCGv_i64_d *TCGv_i64; | |
421 | typedef struct TCGv_ptr_d *TCGv_ptr; | |
1bcea73e | 422 | typedef TCGv_ptr TCGv_env; |
5d4e1a10 LV |
423 | #if TARGET_LONG_BITS == 32 |
424 | #define TCGv TCGv_i32 | |
425 | #elif TARGET_LONG_BITS == 64 | |
426 | #define TCGv TCGv_i64 | |
427 | #else | |
428 | #error Unhandled TARGET_LONG_BITS value | |
429 | #endif | |
ac56dd48 | 430 | |
e89b28a6 RH |
431 | /* See the comment before tcgv_i32_temp. */ |
432 | #define TCGV_UNUSED_I32(x) (x = (TCGv_i32)NULL) | |
433 | #define TCGV_UNUSED_I64(x) (x = (TCGv_i64)NULL) | |
434 | #define TCGV_UNUSED_PTR(x) (x = (TCGv_ptr)NULL) | |
a50f5b91 | 435 | |
e89b28a6 RH |
436 | #define TCGV_IS_UNUSED_I32(x) ((x) == (TCGv_i32)NULL) |
437 | #define TCGV_IS_UNUSED_I64(x) ((x) == (TCGv_i64)NULL) | |
438 | #define TCGV_IS_UNUSED_PTR(x) ((x) == (TCGv_ptr)NULL) | |
afcb92be | 439 | |
c896fe29 | 440 | /* call flags */ |
78505279 AJ |
441 | /* Helper does not read globals (either directly or through an exception). It |
442 | implies TCG_CALL_NO_WRITE_GLOBALS. */ | |
443 | #define TCG_CALL_NO_READ_GLOBALS 0x0010 | |
444 | /* Helper does not write globals */ | |
445 | #define TCG_CALL_NO_WRITE_GLOBALS 0x0020 | |
446 | /* Helper can be safely suppressed if the return value is not used. */ | |
447 | #define TCG_CALL_NO_SIDE_EFFECTS 0x0040 | |
448 | ||
449 | /* convenience version of most used call flags */ | |
450 | #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS | |
451 | #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS | |
452 | #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS | |
453 | #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) | |
454 | #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) | |
455 | ||
e89b28a6 RH |
456 | /* Used to align parameters. See the comment before tcgv_i32_temp. */ |
457 | #define TCG_CALL_DUMMY_ARG ((TCGArg)0) | |
39cf05d3 | 458 | |
a93cf9df SW |
459 | /* Conditions. Note that these are laid out for easy manipulation by |
460 | the functions below: | |
0aed257f RH |
461 | bit 0 is used for inverting; |
462 | bit 1 is signed, | |
463 | bit 2 is unsigned, | |
464 | bit 3 is used with bit 0 for swapping signed/unsigned. */ | |
c896fe29 | 465 | typedef enum { |
0aed257f RH |
466 | /* non-signed */ |
467 | TCG_COND_NEVER = 0 | 0 | 0 | 0, | |
468 | TCG_COND_ALWAYS = 0 | 0 | 0 | 1, | |
469 | TCG_COND_EQ = 8 | 0 | 0 | 0, | |
470 | TCG_COND_NE = 8 | 0 | 0 | 1, | |
471 | /* signed */ | |
472 | TCG_COND_LT = 0 | 0 | 2 | 0, | |
473 | TCG_COND_GE = 0 | 0 | 2 | 1, | |
474 | TCG_COND_LE = 8 | 0 | 2 | 0, | |
475 | TCG_COND_GT = 8 | 0 | 2 | 1, | |
c896fe29 | 476 | /* unsigned */ |
0aed257f RH |
477 | TCG_COND_LTU = 0 | 4 | 0 | 0, |
478 | TCG_COND_GEU = 0 | 4 | 0 | 1, | |
479 | TCG_COND_LEU = 8 | 4 | 0 | 0, | |
480 | TCG_COND_GTU = 8 | 4 | 0 | 1, | |
c896fe29 FB |
481 | } TCGCond; |
482 | ||
1c086220 | 483 | /* Invert the sense of the comparison. */ |
401d466d RH |
484 | static inline TCGCond tcg_invert_cond(TCGCond c) |
485 | { | |
486 | return (TCGCond)(c ^ 1); | |
487 | } | |
488 | ||
1c086220 RH |
489 | /* Swap the operands in a comparison. */ |
490 | static inline TCGCond tcg_swap_cond(TCGCond c) | |
491 | { | |
0aed257f | 492 | return c & 6 ? (TCGCond)(c ^ 9) : c; |
1c086220 RH |
493 | } |
494 | ||
d1e321b8 | 495 | /* Create an "unsigned" version of a "signed" comparison. */ |
ff44c2f3 RH |
496 | static inline TCGCond tcg_unsigned_cond(TCGCond c) |
497 | { | |
0aed257f | 498 | return c & 2 ? (TCGCond)(c ^ 6) : c; |
ff44c2f3 RH |
499 | } |
500 | ||
d1e321b8 | 501 | /* Must a comparison be considered unsigned? */ |
bcc66562 RH |
502 | static inline bool is_unsigned_cond(TCGCond c) |
503 | { | |
0aed257f | 504 | return (c & 4) != 0; |
bcc66562 RH |
505 | } |
506 | ||
d1e321b8 RH |
507 | /* Create a "high" version of a double-word comparison. |
508 | This removes equality from a LTE or GTE comparison. */ | |
509 | static inline TCGCond tcg_high_cond(TCGCond c) | |
510 | { | |
511 | switch (c) { | |
512 | case TCG_COND_GE: | |
513 | case TCG_COND_LE: | |
514 | case TCG_COND_GEU: | |
515 | case TCG_COND_LEU: | |
516 | return (TCGCond)(c ^ 8); | |
517 | default: | |
518 | return c; | |
519 | } | |
520 | } | |
521 | ||
00c8fa9f EC |
522 | typedef enum TCGTempVal { |
523 | TEMP_VAL_DEAD, | |
524 | TEMP_VAL_REG, | |
525 | TEMP_VAL_MEM, | |
526 | TEMP_VAL_CONST, | |
527 | } TCGTempVal; | |
c896fe29 | 528 | |
c896fe29 | 529 | typedef struct TCGTemp { |
b6638662 | 530 | TCGReg reg:8; |
00c8fa9f EC |
531 | TCGTempVal val_type:8; |
532 | TCGType base_type:8; | |
533 | TCGType type:8; | |
c896fe29 | 534 | unsigned int fixed_reg:1; |
b3915dbb RH |
535 | unsigned int indirect_reg:1; |
536 | unsigned int indirect_base:1; | |
c896fe29 FB |
537 | unsigned int mem_coherent:1; |
538 | unsigned int mem_allocated:1; | |
fa477d25 RH |
539 | /* If true, the temp is saved across both basic blocks and |
540 | translation blocks. */ | |
541 | unsigned int temp_global:1; | |
542 | /* If true, the temp is saved across basic blocks but dead | |
543 | at the end of translation blocks. If false, the temp is | |
544 | dead at the end of basic blocks. */ | |
545 | unsigned int temp_local:1; | |
546 | unsigned int temp_allocated:1; | |
00c8fa9f EC |
547 | |
548 | tcg_target_long val; | |
b3a62939 | 549 | struct TCGTemp *mem_base; |
00c8fa9f | 550 | intptr_t mem_offset; |
c896fe29 | 551 | const char *name; |
b83eabea RH |
552 | |
553 | /* Pass-specific information that can be stored for a temporary. | |
554 | One word worth of integer data, and one pointer to data | |
555 | allocated separately. */ | |
556 | uintptr_t state; | |
557 | void *state_ptr; | |
c896fe29 FB |
558 | } TCGTemp; |
559 | ||
c896fe29 FB |
560 | typedef struct TCGContext TCGContext; |
561 | ||
0ec9eabc RH |
562 | typedef struct TCGTempSet { |
563 | unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; | |
564 | } TCGTempSet; | |
565 | ||
a1b3c48d RH |
566 | /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding, |
567 | this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands. | |
568 | There are never more than 2 outputs, which means that we can store all | |
569 | dead + sync data within 16 bits. */ | |
570 | #define DEAD_ARG 4 | |
571 | #define SYNC_ARG 1 | |
572 | typedef uint16_t TCGLifeData; | |
573 | ||
75e8b9b7 RH |
574 | /* The layout here is designed to avoid a bitfield crossing of |
575 | a 32-bit boundary, which would cause GCC to add extra padding. */ | |
c45cb8bb | 576 | typedef struct TCGOp { |
bee158cb RH |
577 | TCGOpcode opc : 8; /* 8 */ |
578 | ||
c45cb8bb | 579 | /* The number of out and in parameter for a call. */ |
75e8b9b7 RH |
580 | unsigned calli : 4; /* 12 */ |
581 | unsigned callo : 2; /* 14 */ | |
582 | unsigned : 2; /* 16 */ | |
c45cb8bb | 583 | |
75e8b9b7 RH |
584 | /* Index of the prev/next op, or 0 for the end of the list. */ |
585 | unsigned prev : 16; /* 32 */ | |
586 | unsigned next : 16; /* 48 */ | |
c45cb8bb | 587 | |
bee158cb RH |
588 | /* Lifetime data of the operands. */ |
589 | unsigned life : 16; /* 64 */ | |
75e8b9b7 RH |
590 | |
591 | /* Arguments for the opcode. */ | |
592 | TCGArg args[MAX_OPC_PARAM]; | |
c45cb8bb RH |
593 | } TCGOp; |
594 | ||
75e8b9b7 RH |
595 | /* Make sure that we don't expand the structure without noticing. */ |
596 | QEMU_BUILD_BUG_ON(sizeof(TCGOp) != 8 + sizeof(TCGArg) * MAX_OPC_PARAM); | |
597 | ||
dcb8e758 RH |
598 | /* Make sure operands fit in the bitfields above. */ |
599 | QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); | |
75e8b9b7 | 600 | QEMU_BUILD_BUG_ON(OPC_BUF_SIZE > (1 << 16)); |
c45cb8bb | 601 | |
c896fe29 FB |
602 | struct TCGContext { |
603 | uint8_t *pool_cur, *pool_end; | |
4055299e | 604 | TCGPool *pool_first, *pool_current, *pool_first_large; |
c896fe29 | 605 | int nb_labels; |
c896fe29 FB |
606 | int nb_globals; |
607 | int nb_temps; | |
5a18407f | 608 | int nb_indirects; |
c896fe29 FB |
609 | |
610 | /* goto_tb support */ | |
1813e175 | 611 | tcg_insn_unit *code_buf; |
f309101c | 612 | uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */ |
a8583393 RH |
613 | uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */ |
614 | uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */ | |
c896fe29 | 615 | |
c896fe29 | 616 | TCGRegSet reserved_regs; |
e82d5a24 | 617 | uint32_t tb_cflags; /* cflags of the current TB */ |
e2c6d1b4 RH |
618 | intptr_t current_frame_offset; |
619 | intptr_t frame_start; | |
620 | intptr_t frame_end; | |
b3a62939 | 621 | TCGTemp *frame_temp; |
c896fe29 | 622 | |
1813e175 | 623 | tcg_insn_unit *code_ptr; |
c896fe29 | 624 | |
a23a9ec6 FB |
625 | #ifdef CONFIG_PROFILER |
626 | /* profiling info */ | |
627 | int64_t tb_count1; | |
628 | int64_t tb_count; | |
629 | int64_t op_count; /* total insn count */ | |
630 | int op_count_max; /* max insn per TB */ | |
631 | int64_t temp_count; | |
632 | int temp_count_max; | |
a23a9ec6 FB |
633 | int64_t del_op_count; |
634 | int64_t code_in_len; | |
635 | int64_t code_out_len; | |
fca8a500 | 636 | int64_t search_out_len; |
a23a9ec6 FB |
637 | int64_t interm_time; |
638 | int64_t code_time; | |
639 | int64_t la_time; | |
c5cc28ff | 640 | int64_t opt_time; |
a23a9ec6 FB |
641 | int64_t restore_count; |
642 | int64_t restore_time; | |
643 | #endif | |
27bfd83c PM |
644 | |
645 | #ifdef CONFIG_DEBUG_TCG | |
646 | int temps_in_use; | |
0a209d4b | 647 | int goto_tb_issue_mask; |
27bfd83c | 648 | #endif |
b76f0d8c | 649 | |
c45cb8bb | 650 | int gen_next_op_idx; |
8232a46a | 651 | |
1813e175 RH |
652 | /* Code generation. Note that we specifically do not use tcg_insn_unit |
653 | here, because there's too much arithmetic throughout that relies | |
654 | on addition and subtraction working on bytes. Rely on the GCC | |
655 | extension that allows arithmetic on void*. */ | |
1813e175 | 656 | void *code_gen_prologue; |
cedbcb01 | 657 | void *code_gen_epilogue; |
1813e175 | 658 | void *code_gen_buffer; |
0b0d3320 | 659 | size_t code_gen_buffer_size; |
1813e175 | 660 | void *code_gen_ptr; |
57a26946 | 661 | void *data_gen_ptr; |
0b0d3320 | 662 | |
b125f9dc RH |
663 | /* Threshold to flush the translated code buffer. */ |
664 | void *code_gen_highwater; | |
665 | ||
7c255043 LV |
666 | /* Track which vCPU triggers events */ |
667 | CPUState *cpu; /* *_trans */ | |
668 | TCGv_env tcg_env; /* *_exec */ | |
669 | ||
659ef5cb RH |
670 | /* These structures are private to tcg-target.inc.c. */ |
671 | #ifdef TCG_TARGET_NEED_LDST_LABELS | |
672 | struct TCGLabelQemuLdst *ldst_labels; | |
673 | #endif | |
57a26946 RH |
674 | #ifdef TCG_TARGET_NEED_POOL_LABELS |
675 | struct TCGLabelPoolData *pool_labels; | |
676 | #endif | |
c45cb8bb RH |
677 | |
678 | TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; | |
679 | TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ | |
680 | ||
f8b2f202 RH |
681 | /* Tells which temporary holds a given register. |
682 | It does not take into account fixed registers */ | |
683 | TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; | |
c45cb8bb RH |
684 | |
685 | TCGOp gen_op_buf[OPC_BUF_SIZE]; | |
c45cb8bb | 686 | |
fca8a500 RH |
687 | uint16_t gen_insn_end_off[TCG_MAX_INSNS]; |
688 | target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; | |
c896fe29 FB |
689 | }; |
690 | ||
691 | extern TCGContext tcg_ctx; | |
c896fe29 | 692 | |
1807f4c4 RH |
693 | static inline size_t temp_idx(TCGTemp *ts) |
694 | { | |
695 | ptrdiff_t n = ts - tcg_ctx.temps; | |
696 | tcg_debug_assert(n >= 0 && n < tcg_ctx.nb_temps); | |
697 | return n; | |
698 | } | |
699 | ||
700 | static inline TCGArg temp_arg(TCGTemp *ts) | |
701 | { | |
e89b28a6 | 702 | return (uintptr_t)ts; |
1807f4c4 RH |
703 | } |
704 | ||
43439139 RH |
705 | static inline TCGTemp *arg_temp(TCGArg a) |
706 | { | |
e89b28a6 | 707 | return (TCGTemp *)(uintptr_t)a; |
43439139 RH |
708 | } |
709 | ||
e89b28a6 RH |
710 | /* Using the offset of a temporary, relative to TCGContext, rather than |
711 | its index means that we don't use 0. That leaves offset 0 free for | |
712 | a NULL representation without having to leave index 0 unused. */ | |
713 | static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) | |
6349039d | 714 | { |
e89b28a6 RH |
715 | uintptr_t o = (uintptr_t)v; |
716 | TCGTemp *t = (void *)&tcg_ctx + o; | |
717 | tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o); | |
718 | return t; | |
ae8b75dc RH |
719 | } |
720 | ||
e89b28a6 | 721 | static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) |
ae8b75dc | 722 | { |
e89b28a6 | 723 | return tcgv_i32_temp((TCGv_i32)v); |
ae8b75dc RH |
724 | } |
725 | ||
e89b28a6 | 726 | static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) |
ae8b75dc | 727 | { |
e89b28a6 | 728 | return tcgv_i32_temp((TCGv_i32)v); |
ae8b75dc RH |
729 | } |
730 | ||
e89b28a6 | 731 | static inline TCGArg tcgv_i32_arg(TCGv_i32 v) |
ae8b75dc | 732 | { |
e89b28a6 | 733 | return temp_arg(tcgv_i32_temp(v)); |
ae8b75dc RH |
734 | } |
735 | ||
e89b28a6 | 736 | static inline TCGArg tcgv_i64_arg(TCGv_i64 v) |
ae8b75dc | 737 | { |
e89b28a6 | 738 | return temp_arg(tcgv_i64_temp(v)); |
ae8b75dc RH |
739 | } |
740 | ||
e89b28a6 | 741 | static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) |
ae8b75dc | 742 | { |
e89b28a6 | 743 | return temp_arg(tcgv_ptr_temp(v)); |
ae8b75dc RH |
744 | } |
745 | ||
085272b3 RH |
746 | static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) |
747 | { | |
e89b28a6 RH |
748 | (void)temp_idx(t); /* trigger embedded assert */ |
749 | return (TCGv_i32)((void *)t - (void *)&tcg_ctx); | |
085272b3 RH |
750 | } |
751 | ||
752 | static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) | |
753 | { | |
e89b28a6 | 754 | return (TCGv_i64)temp_tcgv_i32(t); |
085272b3 RH |
755 | } |
756 | ||
757 | static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) | |
758 | { | |
e89b28a6 | 759 | return (TCGv_ptr)temp_tcgv_i32(t); |
085272b3 RH |
760 | } |
761 | ||
dc41aa7d RH |
762 | #if TCG_TARGET_REG_BITS == 32 |
763 | static inline TCGv_i32 TCGV_LOW(TCGv_i64 t) | |
764 | { | |
765 | return temp_tcgv_i32(tcgv_i64_temp(t)); | |
766 | } | |
767 | ||
768 | static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) | |
769 | { | |
770 | return temp_tcgv_i32(tcgv_i64_temp(t) + 1); | |
771 | } | |
772 | #endif | |
773 | ||
1d41478f EI |
774 | static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) |
775 | { | |
75e8b9b7 | 776 | tcg_ctx.gen_op_buf[op_idx].args[arg] = v; |
1d41478f EI |
777 | } |
778 | ||
fe700adb RH |
779 | /* The number of opcodes emitted so far. */ |
780 | static inline int tcg_op_buf_count(void) | |
781 | { | |
c45cb8bb | 782 | return tcg_ctx.gen_next_op_idx; |
fe700adb RH |
783 | } |
784 | ||
785 | /* Test for whether to terminate the TB for using too many opcodes. */ | |
786 | static inline bool tcg_op_buf_full(void) | |
787 | { | |
788 | return tcg_op_buf_count() >= OPC_MAX_SIZE; | |
789 | } | |
790 | ||
c896fe29 FB |
791 | /* pool based memory allocation */ |
792 | ||
7d7500d9 | 793 | /* tb_lock must be held for tcg_malloc_internal. */ |
c896fe29 FB |
794 | void *tcg_malloc_internal(TCGContext *s, int size); |
795 | void tcg_pool_reset(TCGContext *s); | |
6e3b2bfd | 796 | TranslationBlock *tcg_tb_alloc(TCGContext *s); |
c896fe29 | 797 | |
7d7500d9 | 798 | /* Called with tb_lock held. */ |
c896fe29 FB |
799 | static inline void *tcg_malloc(int size) |
800 | { | |
801 | TCGContext *s = &tcg_ctx; | |
802 | uint8_t *ptr, *ptr_end; | |
13aaef67 RH |
803 | |
804 | /* ??? This is a weak placeholder for minimum malloc alignment. */ | |
805 | size = QEMU_ALIGN_UP(size, 8); | |
806 | ||
c896fe29 FB |
807 | ptr = s->pool_cur; |
808 | ptr_end = ptr + size; | |
809 | if (unlikely(ptr_end > s->pool_end)) { | |
810 | return tcg_malloc_internal(&tcg_ctx, size); | |
811 | } else { | |
812 | s->pool_cur = ptr_end; | |
813 | return ptr; | |
814 | } | |
815 | } | |
816 | ||
817 | void tcg_context_init(TCGContext *s); | |
9002ec79 | 818 | void tcg_prologue_init(TCGContext *s); |
c896fe29 FB |
819 | void tcg_func_start(TCGContext *s); |
820 | ||
5bd2ec3d | 821 | int tcg_gen_code(TCGContext *s, TranslationBlock *tb); |
c896fe29 | 822 | |
b6638662 | 823 | void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); |
a7812ae4 | 824 | |
085272b3 RH |
825 | TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, |
826 | intptr_t, const char *); | |
e1ccc054 | 827 | |
b6638662 RH |
828 | TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name); |
829 | TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name); | |
e1ccc054 | 830 | |
a7812ae4 | 831 | TCGv_i32 tcg_temp_new_internal_i32(int temp_local); |
e1ccc054 RH |
832 | TCGv_i64 tcg_temp_new_internal_i64(int temp_local); |
833 | ||
834 | void tcg_temp_free_i32(TCGv_i32 arg); | |
835 | void tcg_temp_free_i64(TCGv_i64 arg); | |
836 | ||
e1ccc054 RH |
837 | static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, |
838 | const char *name) | |
839 | { | |
085272b3 RH |
840 | TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); |
841 | return temp_tcgv_i32(t); | |
e1ccc054 RH |
842 | } |
843 | ||
a7812ae4 PB |
844 | static inline TCGv_i32 tcg_temp_new_i32(void) |
845 | { | |
846 | return tcg_temp_new_internal_i32(0); | |
847 | } | |
e1ccc054 | 848 | |
a7812ae4 PB |
849 | static inline TCGv_i32 tcg_temp_local_new_i32(void) |
850 | { | |
851 | return tcg_temp_new_internal_i32(1); | |
852 | } | |
a7812ae4 | 853 | |
e1ccc054 RH |
854 | static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, |
855 | const char *name) | |
856 | { | |
085272b3 RH |
857 | TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); |
858 | return temp_tcgv_i64(t); | |
e1ccc054 RH |
859 | } |
860 | ||
a7812ae4 | 861 | static inline TCGv_i64 tcg_temp_new_i64(void) |
641d5fbe | 862 | { |
a7812ae4 | 863 | return tcg_temp_new_internal_i64(0); |
641d5fbe | 864 | } |
e1ccc054 | 865 | |
a7812ae4 | 866 | static inline TCGv_i64 tcg_temp_local_new_i64(void) |
641d5fbe | 867 | { |
a7812ae4 | 868 | return tcg_temp_new_internal_i64(1); |
641d5fbe | 869 | } |
a7812ae4 | 870 | |
27bfd83c PM |
871 | #if defined(CONFIG_DEBUG_TCG) |
872 | /* If you call tcg_clear_temp_count() at the start of a section of | |
873 | * code which is not supposed to leak any TCG temporaries, then | |
874 | * calling tcg_check_temp_count() at the end of the section will | |
875 | * return 1 if the section did in fact leak a temporary. | |
876 | */ | |
877 | void tcg_clear_temp_count(void); | |
878 | int tcg_check_temp_count(void); | |
879 | #else | |
880 | #define tcg_clear_temp_count() do { } while (0) | |
881 | #define tcg_check_temp_count() 0 | |
882 | #endif | |
883 | ||
405cf9ff | 884 | void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf); |
246ae24d | 885 | void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf); |
c896fe29 FB |
886 | |
887 | #define TCG_CT_ALIAS 0x80 | |
888 | #define TCG_CT_IALIAS 0x40 | |
82790a87 | 889 | #define TCG_CT_NEWREG 0x20 /* output requires a new register */ |
c896fe29 FB |
890 | #define TCG_CT_REG 0x01 |
891 | #define TCG_CT_CONST 0x02 /* any constant of register size */ | |
892 | ||
893 | typedef struct TCGArgConstraint { | |
5ff9d6a4 FB |
894 | uint16_t ct; |
895 | uint8_t alias_index; | |
c896fe29 FB |
896 | union { |
897 | TCGRegSet regs; | |
898 | } u; | |
899 | } TCGArgConstraint; | |
900 | ||
901 | #define TCG_MAX_OP_ARGS 16 | |
902 | ||
8399ad59 RH |
903 | /* Bits for TCGOpDef->flags, 8 bits available. */ |
904 | enum { | |
905 | /* Instruction defines the end of a basic block. */ | |
906 | TCG_OPF_BB_END = 0x01, | |
907 | /* Instruction clobbers call registers and potentially update globals. */ | |
908 | TCG_OPF_CALL_CLOBBER = 0x02, | |
3d5c5f87 AJ |
909 | /* Instruction has side effects: it cannot be removed if its outputs |
910 | are not used, and might trigger exceptions. */ | |
8399ad59 RH |
911 | TCG_OPF_SIDE_EFFECTS = 0x04, |
912 | /* Instruction operands are 64-bits (otherwise 32-bits). */ | |
913 | TCG_OPF_64BIT = 0x08, | |
c1a61f6c RH |
914 | /* Instruction is optional and not implemented by the host, or insn |
915 | is generic and should not be implemened by the host. */ | |
25c4d9cc | 916 | TCG_OPF_NOT_PRESENT = 0x10, |
8399ad59 | 917 | }; |
c896fe29 FB |
918 | |
919 | typedef struct TCGOpDef { | |
920 | const char *name; | |
921 | uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; | |
922 | uint8_t flags; | |
c896fe29 FB |
923 | TCGArgConstraint *args_ct; |
924 | int *sorted_args; | |
c68aaa18 SW |
925 | #if defined(CONFIG_DEBUG_TCG) |
926 | int used; | |
927 | #endif | |
c896fe29 | 928 | } TCGOpDef; |
8399ad59 RH |
929 | |
930 | extern TCGOpDef tcg_op_defs[]; | |
2a24374a SW |
931 | extern const size_t tcg_op_defs_max; |
932 | ||
c896fe29 | 933 | typedef struct TCGTargetOpDef { |
a9751609 | 934 | TCGOpcode op; |
c896fe29 FB |
935 | const char *args_ct_str[TCG_MAX_OP_ARGS]; |
936 | } TCGTargetOpDef; | |
937 | ||
c896fe29 FB |
938 | #define tcg_abort() \ |
939 | do {\ | |
940 | fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\ | |
941 | abort();\ | |
942 | } while (0) | |
943 | ||
8b73d49f | 944 | #if UINTPTR_MAX == UINT32_MAX |
dc41aa7d RH |
945 | static inline TCGv_ptr TCGV_NAT_TO_PTR(TCGv_i32 n) { return (TCGv_ptr)n; } |
946 | static inline TCGv_i32 TCGV_PTR_TO_NAT(TCGv_ptr n) { return (TCGv_i32)n; } | |
ebecf363 | 947 | |
8b73d49f | 948 | #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V))) |
ebecf363 PM |
949 | #define tcg_global_reg_new_ptr(R, N) \ |
950 | TCGV_NAT_TO_PTR(tcg_global_reg_new_i32((R), (N))) | |
951 | #define tcg_global_mem_new_ptr(R, O, N) \ | |
952 | TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N))) | |
953 | #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32()) | |
954 | #define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T)) | |
c896fe29 | 955 | #else |
dc41aa7d RH |
956 | static inline TCGv_ptr TCGV_NAT_TO_PTR(TCGv_i64 n) { return (TCGv_ptr)n; } |
957 | static inline TCGv_i64 TCGV_PTR_TO_NAT(TCGv_ptr n) { return (TCGv_i64)n; } | |
ebecf363 | 958 | |
8b73d49f | 959 | #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V))) |
ebecf363 PM |
960 | #define tcg_global_reg_new_ptr(R, N) \ |
961 | TCGV_NAT_TO_PTR(tcg_global_reg_new_i64((R), (N))) | |
962 | #define tcg_global_mem_new_ptr(R, O, N) \ | |
963 | TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N))) | |
964 | #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64()) | |
965 | #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T)) | |
c896fe29 FB |
966 | #endif |
967 | ||
be0f34b5 RH |
968 | bool tcg_op_supported(TCGOpcode op); |
969 | ||
ae8b75dc | 970 | void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); |
a7812ae4 | 971 | |
0c627cdc | 972 | void tcg_op_remove(TCGContext *s, TCGOp *op); |
5a18407f RH |
973 | TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg); |
974 | TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg); | |
975 | ||
c45cb8bb | 976 | void tcg_optimize(TCGContext *s); |
8f2e8c07 | 977 | |
a7812ae4 | 978 | /* only used for debugging purposes */ |
eeacee4d | 979 | void tcg_dump_ops(TCGContext *s); |
a7812ae4 | 980 | |
a7812ae4 PB |
981 | TCGv_i32 tcg_const_i32(int32_t val); |
982 | TCGv_i64 tcg_const_i64(int64_t val); | |
983 | TCGv_i32 tcg_const_local_i32(int32_t val); | |
984 | TCGv_i64 tcg_const_local_i64(int64_t val); | |
985 | ||
42a268c2 RH |
986 | TCGLabel *gen_new_label(void); |
987 | ||
988 | /** | |
989 | * label_arg | |
990 | * @l: label | |
991 | * | |
992 | * Encode a label for storage in the TCG opcode stream. | |
993 | */ | |
994 | ||
995 | static inline TCGArg label_arg(TCGLabel *l) | |
996 | { | |
51e3972c | 997 | return (uintptr_t)l; |
42a268c2 RH |
998 | } |
999 | ||
1000 | /** | |
1001 | * arg_label | |
1002 | * @i: value | |
1003 | * | |
1004 | * The opposite of label_arg. Retrieve a label from the | |
1005 | * encoding of the TCG opcode stream. | |
1006 | */ | |
1007 | ||
51e3972c | 1008 | static inline TCGLabel *arg_label(TCGArg i) |
42a268c2 | 1009 | { |
51e3972c | 1010 | return (TCGLabel *)(uintptr_t)i; |
42a268c2 RH |
1011 | } |
1012 | ||
52a1f64e RH |
1013 | /** |
1014 | * tcg_ptr_byte_diff | |
1015 | * @a, @b: addresses to be differenced | |
1016 | * | |
1017 | * There are many places within the TCG backends where we need a byte | |
1018 | * difference between two pointers. While this can be accomplished | |
1019 | * with local casting, it's easy to get wrong -- especially if one is | |
1020 | * concerned with the signedness of the result. | |
1021 | * | |
1022 | * This version relies on GCC's void pointer arithmetic to get the | |
1023 | * correct result. | |
1024 | */ | |
1025 | ||
1026 | static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b) | |
1027 | { | |
1028 | return a - b; | |
1029 | } | |
1030 | ||
1031 | /** | |
1032 | * tcg_pcrel_diff | |
1033 | * @s: the tcg context | |
1034 | * @target: address of the target | |
1035 | * | |
1036 | * Produce a pc-relative difference, from the current code_ptr | |
1037 | * to the destination address. | |
1038 | */ | |
1039 | ||
1040 | static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target) | |
1041 | { | |
1042 | return tcg_ptr_byte_diff(target, s->code_ptr); | |
1043 | } | |
1044 | ||
1045 | /** | |
1046 | * tcg_current_code_size | |
1047 | * @s: the tcg context | |
1048 | * | |
1049 | * Compute the current code size within the translation block. | |
1050 | * This is used to fill in qemu's data structures for goto_tb. | |
1051 | */ | |
1052 | ||
1053 | static inline size_t tcg_current_code_size(TCGContext *s) | |
1054 | { | |
1055 | return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); | |
1056 | } | |
1057 | ||
59227d5d RH |
1058 | /* Combine the TCGMemOp and mmu_idx parameters into a single value. */ |
1059 | typedef uint32_t TCGMemOpIdx; | |
1060 | ||
1061 | /** | |
1062 | * make_memop_idx | |
1063 | * @op: memory operation | |
1064 | * @idx: mmu index | |
1065 | * | |
1066 | * Encode these values into a single parameter. | |
1067 | */ | |
1068 | static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx) | |
1069 | { | |
1070 | tcg_debug_assert(idx <= 15); | |
1071 | return (op << 4) | idx; | |
1072 | } | |
1073 | ||
1074 | /** | |
1075 | * get_memop | |
1076 | * @oi: combined op/idx parameter | |
1077 | * | |
1078 | * Extract the memory operation from the combined value. | |
1079 | */ | |
1080 | static inline TCGMemOp get_memop(TCGMemOpIdx oi) | |
1081 | { | |
1082 | return oi >> 4; | |
1083 | } | |
1084 | ||
1085 | /** | |
1086 | * get_mmuidx | |
1087 | * @oi: combined op/idx parameter | |
1088 | * | |
1089 | * Extract the mmu index from the combined value. | |
1090 | */ | |
1091 | static inline unsigned get_mmuidx(TCGMemOpIdx oi) | |
1092 | { | |
1093 | return oi & 15; | |
1094 | } | |
1095 | ||
0980011b PM |
1096 | /** |
1097 | * tcg_qemu_tb_exec: | |
819af24b | 1098 | * @env: pointer to CPUArchState for the CPU |
0980011b PM |
1099 | * @tb_ptr: address of generated code for the TB to execute |
1100 | * | |
1101 | * Start executing code from a given translation block. | |
1102 | * Where translation blocks have been linked, execution | |
1103 | * may proceed from the given TB into successive ones. | |
1104 | * Control eventually returns only when some action is needed | |
1105 | * from the top-level loop: either control must pass to a TB | |
1106 | * which has not yet been directly linked, or an asynchronous | |
1107 | * event such as an interrupt needs handling. | |
1108 | * | |
819af24b SF |
1109 | * Return: The return value is the value passed to the corresponding |
1110 | * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. | |
1111 | * The value is either zero or a 4-byte aligned pointer to that TB combined | |
1112 | * with additional information in its two least significant bits. The | |
1113 | * additional information is encoded as follows: | |
0980011b PM |
1114 | * 0, 1: the link between this TB and the next is via the specified |
1115 | * TB index (0 or 1). That is, we left the TB via (the equivalent | |
1116 | * of) "goto_tb <index>". The main loop uses this to determine | |
1117 | * how to link the TB just executed to the next. | |
1118 | * 2: we are using instruction counting code generation, and we | |
1119 | * did not start executing this TB because the instruction counter | |
819af24b | 1120 | * would hit zero midway through it. In this case the pointer |
0980011b PM |
1121 | * returned is the TB we were about to execute, and the caller must |
1122 | * arrange to execute the remaining count of instructions. | |
378df4b2 PM |
1123 | * 3: we stopped because the CPU's exit_request flag was set |
1124 | * (usually meaning that there is an interrupt that needs to be | |
819af24b SF |
1125 | * handled). The pointer returned is the TB we were about to execute |
1126 | * when we noticed the pending exit request. | |
0980011b PM |
1127 | * |
1128 | * If the bottom two bits indicate an exit-via-index then the CPU | |
1129 | * state is correctly synchronised and ready for execution of the next | |
1130 | * TB (and in particular the guest PC is the address to execute next). | |
1131 | * Otherwise, we gave up on execution of this TB before it started, and | |
fee068e4 | 1132 | * the caller must fix up the CPU state by calling the CPU's |
819af24b | 1133 | * synchronize_from_tb() method with the TB pointer we return (falling |
fee068e4 PC |
1134 | * back to calling the CPU's set_pc method with tb->pb if no |
1135 | * synchronize_from_tb() method exists). | |
0980011b PM |
1136 | * |
1137 | * Note that TCG targets may use a different definition of tcg_qemu_tb_exec | |
1138 | * to this default (which just calls the prologue.code emitted by | |
1139 | * tcg_target_qemu_prologue()). | |
1140 | */ | |
1141 | #define TB_EXIT_MASK 3 | |
1142 | #define TB_EXIT_IDX0 0 | |
1143 | #define TB_EXIT_IDX1 1 | |
378df4b2 | 1144 | #define TB_EXIT_REQUESTED 3 |
0980011b | 1145 | |
5a58e884 PB |
1146 | #ifdef HAVE_TCG_QEMU_TB_EXEC |
1147 | uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); | |
1148 | #else | |
ce285b17 | 1149 | # define tcg_qemu_tb_exec(env, tb_ptr) \ |
04d5a1da | 1150 | ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr) |
932a6909 | 1151 | #endif |
813da627 RH |
1152 | |
1153 | void tcg_register_jit(void *buf, size_t buf_size); | |
b76f0d8c | 1154 | |
e58eb534 RH |
1155 | /* |
1156 | * Memory helpers that will be used by TCG generated code. | |
1157 | */ | |
1158 | #ifdef CONFIG_SOFTMMU | |
c8f94df5 RH |
1159 | /* Value zero-extended to tcg register size. */ |
1160 | tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, | |
3972ef6f | 1161 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1162 | tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1163 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1164 | tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1165 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1166 | uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1167 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1168 | tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1169 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1170 | tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1171 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1172 | uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1173 | TCGMemOpIdx oi, uintptr_t retaddr); |
e58eb534 | 1174 | |
c8f94df5 RH |
1175 | /* Value sign-extended to tcg register size. */ |
1176 | tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, | |
3972ef6f | 1177 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1178 | tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1179 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1180 | tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1181 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1182 | tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1183 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1184 | tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1185 | TCGMemOpIdx oi, uintptr_t retaddr); |
c8f94df5 | 1186 | |
e58eb534 | 1187 | void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, |
3972ef6f | 1188 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1189 | void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, |
3972ef6f | 1190 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1191 | void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, |
3972ef6f | 1192 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1193 | void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, |
3972ef6f | 1194 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1195 | void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, |
3972ef6f | 1196 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1197 | void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, |
3972ef6f | 1198 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1199 | void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, |
3972ef6f | 1200 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1201 | |
282dffc8 PD |
1202 | uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, |
1203 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1204 | uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, | |
1205 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1206 | uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr, | |
1207 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1208 | uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, | |
1209 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1210 | uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, | |
1211 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1212 | uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr, | |
1213 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1214 | uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, | |
1215 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1216 | ||
867b3201 RH |
1217 | /* Temporary aliases until backends are converted. */ |
1218 | #ifdef TARGET_WORDS_BIGENDIAN | |
1219 | # define helper_ret_ldsw_mmu helper_be_ldsw_mmu | |
1220 | # define helper_ret_lduw_mmu helper_be_lduw_mmu | |
1221 | # define helper_ret_ldsl_mmu helper_be_ldsl_mmu | |
1222 | # define helper_ret_ldul_mmu helper_be_ldul_mmu | |
282dffc8 | 1223 | # define helper_ret_ldl_mmu helper_be_ldul_mmu |
867b3201 RH |
1224 | # define helper_ret_ldq_mmu helper_be_ldq_mmu |
1225 | # define helper_ret_stw_mmu helper_be_stw_mmu | |
1226 | # define helper_ret_stl_mmu helper_be_stl_mmu | |
1227 | # define helper_ret_stq_mmu helper_be_stq_mmu | |
282dffc8 PD |
1228 | # define helper_ret_ldw_cmmu helper_be_ldw_cmmu |
1229 | # define helper_ret_ldl_cmmu helper_be_ldl_cmmu | |
1230 | # define helper_ret_ldq_cmmu helper_be_ldq_cmmu | |
867b3201 RH |
1231 | #else |
1232 | # define helper_ret_ldsw_mmu helper_le_ldsw_mmu | |
1233 | # define helper_ret_lduw_mmu helper_le_lduw_mmu | |
1234 | # define helper_ret_ldsl_mmu helper_le_ldsl_mmu | |
1235 | # define helper_ret_ldul_mmu helper_le_ldul_mmu | |
282dffc8 | 1236 | # define helper_ret_ldl_mmu helper_le_ldul_mmu |
867b3201 RH |
1237 | # define helper_ret_ldq_mmu helper_le_ldq_mmu |
1238 | # define helper_ret_stw_mmu helper_le_stw_mmu | |
1239 | # define helper_ret_stl_mmu helper_le_stl_mmu | |
1240 | # define helper_ret_stq_mmu helper_le_stq_mmu | |
282dffc8 PD |
1241 | # define helper_ret_ldw_cmmu helper_le_ldw_cmmu |
1242 | # define helper_ret_ldl_cmmu helper_le_ldl_cmmu | |
1243 | # define helper_ret_ldq_cmmu helper_le_ldq_cmmu | |
867b3201 | 1244 | #endif |
e58eb534 | 1245 | |
c482cb11 RH |
1246 | uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, |
1247 | uint32_t cmpv, uint32_t newv, | |
1248 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1249 | uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr, | |
1250 | uint32_t cmpv, uint32_t newv, | |
1251 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1252 | uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr, | |
1253 | uint32_t cmpv, uint32_t newv, | |
1254 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1255 | uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr, | |
1256 | uint64_t cmpv, uint64_t newv, | |
1257 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1258 | uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr, | |
1259 | uint32_t cmpv, uint32_t newv, | |
1260 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1261 | uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr, | |
1262 | uint32_t cmpv, uint32_t newv, | |
1263 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1264 | uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr, | |
1265 | uint64_t cmpv, uint64_t newv, | |
1266 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1267 | ||
1268 | #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ | |
1269 | TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu \ | |
1270 | (CPUArchState *env, target_ulong addr, TYPE val, \ | |
1271 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1272 | ||
df79b996 | 1273 | #ifdef CONFIG_ATOMIC64 |
c482cb11 | 1274 | #define GEN_ATOMIC_HELPER_ALL(NAME) \ |
df79b996 | 1275 | GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ |
c482cb11 | 1276 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ |
c482cb11 | 1277 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ |
df79b996 | 1278 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ |
c482cb11 | 1279 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ |
df79b996 | 1280 | GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ |
c482cb11 | 1281 | GEN_ATOMIC_HELPER(NAME, uint64_t, q_be) |
df79b996 RH |
1282 | #else |
1283 | #define GEN_ATOMIC_HELPER_ALL(NAME) \ | |
1284 | GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ | |
1285 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ | |
1286 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ | |
1287 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ | |
1288 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) | |
1289 | #endif | |
c482cb11 RH |
1290 | |
1291 | GEN_ATOMIC_HELPER_ALL(fetch_add) | |
1292 | GEN_ATOMIC_HELPER_ALL(fetch_sub) | |
1293 | GEN_ATOMIC_HELPER_ALL(fetch_and) | |
1294 | GEN_ATOMIC_HELPER_ALL(fetch_or) | |
1295 | GEN_ATOMIC_HELPER_ALL(fetch_xor) | |
1296 | ||
1297 | GEN_ATOMIC_HELPER_ALL(add_fetch) | |
1298 | GEN_ATOMIC_HELPER_ALL(sub_fetch) | |
1299 | GEN_ATOMIC_HELPER_ALL(and_fetch) | |
1300 | GEN_ATOMIC_HELPER_ALL(or_fetch) | |
1301 | GEN_ATOMIC_HELPER_ALL(xor_fetch) | |
1302 | ||
1303 | GEN_ATOMIC_HELPER_ALL(xchg) | |
1304 | ||
1305 | #undef GEN_ATOMIC_HELPER_ALL | |
1306 | #undef GEN_ATOMIC_HELPER | |
e58eb534 RH |
1307 | #endif /* CONFIG_SOFTMMU */ |
1308 | ||
7ebee43e RH |
1309 | #ifdef CONFIG_ATOMIC128 |
1310 | #include "qemu/int128.h" | |
1311 | ||
1312 | /* These aren't really a "proper" helpers because TCG cannot manage Int128. | |
1313 | However, use the same format as the others, for use by the backends. */ | |
1314 | Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, | |
1315 | Int128 cmpv, Int128 newv, | |
1316 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1317 | Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr, | |
1318 | Int128 cmpv, Int128 newv, | |
1319 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1320 | ||
1321 | Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, | |
1322 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1323 | Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, | |
1324 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1325 | void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val, | |
1326 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1327 | void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val, | |
1328 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1329 | ||
1330 | #endif /* CONFIG_ATOMIC128 */ | |
1331 | ||
e58eb534 | 1332 | #endif /* TCG_H */ |