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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e58eb534 RH |
24 | |
25 | #ifndef TCG_H | |
26 | #define TCG_H | |
27 | ||
f8393946 | 28 | #include "qemu-common.h" |
33c11879 | 29 | #include "cpu.h" |
00f6da6a | 30 | #include "exec/tb-context.h" |
0ec9eabc | 31 | #include "qemu/bitops.h" |
20937143 | 32 | #include "tcg-mo.h" |
78cd7b83 RH |
33 | #include "tcg-target.h" |
34 | ||
00f6da6a PB |
35 | /* XXX: make safe guess about sizes */ |
36 | #define MAX_OP_PER_INSTR 266 | |
37 | ||
38 | #if HOST_LONG_BITS == 32 | |
39 | #define MAX_OPC_PARAM_PER_ARG 2 | |
40 | #else | |
41 | #define MAX_OPC_PARAM_PER_ARG 1 | |
42 | #endif | |
43 | #define MAX_OPC_PARAM_IARGS 5 | |
44 | #define MAX_OPC_PARAM_OARGS 1 | |
45 | #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS) | |
46 | ||
47 | /* A Call op needs up to 4 + 2N parameters on 32-bit archs, | |
48 | * and up to 4 + N parameters on 64-bit archs | |
49 | * (N = number of input arguments + output arguments). */ | |
50 | #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) | |
51 | #define OPC_BUF_SIZE 640 | |
52 | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) | |
53 | ||
6e0b0730 PC |
54 | #define CPU_TEMP_BUF_NLONGS 128 |
55 | ||
78cd7b83 RH |
56 | /* Default target word size to pointer size. */ |
57 | #ifndef TCG_TARGET_REG_BITS | |
58 | # if UINTPTR_MAX == UINT32_MAX | |
59 | # define TCG_TARGET_REG_BITS 32 | |
60 | # elif UINTPTR_MAX == UINT64_MAX | |
61 | # define TCG_TARGET_REG_BITS 64 | |
62 | # else | |
63 | # error Unknown pointer size for tcg target | |
64 | # endif | |
817b838e SW |
65 | #endif |
66 | ||
c896fe29 FB |
67 | #if TCG_TARGET_REG_BITS == 32 |
68 | typedef int32_t tcg_target_long; | |
69 | typedef uint32_t tcg_target_ulong; | |
70 | #define TCG_PRIlx PRIx32 | |
71 | #define TCG_PRIld PRId32 | |
72 | #elif TCG_TARGET_REG_BITS == 64 | |
73 | typedef int64_t tcg_target_long; | |
74 | typedef uint64_t tcg_target_ulong; | |
75 | #define TCG_PRIlx PRIx64 | |
76 | #define TCG_PRIld PRId64 | |
77 | #else | |
78 | #error unsupported | |
79 | #endif | |
80 | ||
8d4e9146 FK |
81 | /* Oversized TCG guests make things like MTTCG hard |
82 | * as we can't use atomics for cputlb updates. | |
83 | */ | |
84 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS | |
85 | #define TCG_OVERSIZED_GUEST 1 | |
86 | #else | |
87 | #define TCG_OVERSIZED_GUEST 0 | |
88 | #endif | |
89 | ||
c896fe29 FB |
90 | #if TCG_TARGET_NB_REGS <= 32 |
91 | typedef uint32_t TCGRegSet; | |
92 | #elif TCG_TARGET_NB_REGS <= 64 | |
93 | typedef uint64_t TCGRegSet; | |
94 | #else | |
95 | #error unsupported | |
96 | #endif | |
97 | ||
25c4d9cc | 98 | #if TCG_TARGET_REG_BITS == 32 |
e6a72734 | 99 | /* Turn some undef macros into false macros. */ |
609ad705 RH |
100 | #define TCG_TARGET_HAS_extrl_i64_i32 0 |
101 | #define TCG_TARGET_HAS_extrh_i64_i32 0 | |
25c4d9cc | 102 | #define TCG_TARGET_HAS_div_i64 0 |
ca675f46 | 103 | #define TCG_TARGET_HAS_rem_i64 0 |
25c4d9cc RH |
104 | #define TCG_TARGET_HAS_div2_i64 0 |
105 | #define TCG_TARGET_HAS_rot_i64 0 | |
106 | #define TCG_TARGET_HAS_ext8s_i64 0 | |
107 | #define TCG_TARGET_HAS_ext16s_i64 0 | |
108 | #define TCG_TARGET_HAS_ext32s_i64 0 | |
109 | #define TCG_TARGET_HAS_ext8u_i64 0 | |
110 | #define TCG_TARGET_HAS_ext16u_i64 0 | |
111 | #define TCG_TARGET_HAS_ext32u_i64 0 | |
112 | #define TCG_TARGET_HAS_bswap16_i64 0 | |
113 | #define TCG_TARGET_HAS_bswap32_i64 0 | |
114 | #define TCG_TARGET_HAS_bswap64_i64 0 | |
115 | #define TCG_TARGET_HAS_neg_i64 0 | |
116 | #define TCG_TARGET_HAS_not_i64 0 | |
117 | #define TCG_TARGET_HAS_andc_i64 0 | |
118 | #define TCG_TARGET_HAS_orc_i64 0 | |
119 | #define TCG_TARGET_HAS_eqv_i64 0 | |
120 | #define TCG_TARGET_HAS_nand_i64 0 | |
121 | #define TCG_TARGET_HAS_nor_i64 0 | |
0e28d006 RH |
122 | #define TCG_TARGET_HAS_clz_i64 0 |
123 | #define TCG_TARGET_HAS_ctz_i64 0 | |
a768e4e9 | 124 | #define TCG_TARGET_HAS_ctpop_i64 0 |
25c4d9cc | 125 | #define TCG_TARGET_HAS_deposit_i64 0 |
7ec8bab3 RH |
126 | #define TCG_TARGET_HAS_extract_i64 0 |
127 | #define TCG_TARGET_HAS_sextract_i64 0 | |
ffc5ea09 | 128 | #define TCG_TARGET_HAS_movcond_i64 0 |
d7156f7c RH |
129 | #define TCG_TARGET_HAS_add2_i64 0 |
130 | #define TCG_TARGET_HAS_sub2_i64 0 | |
131 | #define TCG_TARGET_HAS_mulu2_i64 0 | |
4d3203fd | 132 | #define TCG_TARGET_HAS_muls2_i64 0 |
03271524 RH |
133 | #define TCG_TARGET_HAS_muluh_i64 0 |
134 | #define TCG_TARGET_HAS_mulsh_i64 0 | |
e6a72734 RH |
135 | /* Turn some undef macros into true macros. */ |
136 | #define TCG_TARGET_HAS_add2_i32 1 | |
137 | #define TCG_TARGET_HAS_sub2_i32 1 | |
25c4d9cc RH |
138 | #endif |
139 | ||
a4773324 JK |
140 | #ifndef TCG_TARGET_deposit_i32_valid |
141 | #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 | |
142 | #endif | |
143 | #ifndef TCG_TARGET_deposit_i64_valid | |
144 | #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 | |
145 | #endif | |
7ec8bab3 RH |
146 | #ifndef TCG_TARGET_extract_i32_valid |
147 | #define TCG_TARGET_extract_i32_valid(ofs, len) 1 | |
148 | #endif | |
149 | #ifndef TCG_TARGET_extract_i64_valid | |
150 | #define TCG_TARGET_extract_i64_valid(ofs, len) 1 | |
151 | #endif | |
a4773324 | 152 | |
25c4d9cc RH |
153 | /* Only one of DIV or DIV2 should be defined. */ |
154 | #if defined(TCG_TARGET_HAS_div_i32) | |
155 | #define TCG_TARGET_HAS_div2_i32 0 | |
156 | #elif defined(TCG_TARGET_HAS_div2_i32) | |
157 | #define TCG_TARGET_HAS_div_i32 0 | |
ca675f46 | 158 | #define TCG_TARGET_HAS_rem_i32 0 |
25c4d9cc RH |
159 | #endif |
160 | #if defined(TCG_TARGET_HAS_div_i64) | |
161 | #define TCG_TARGET_HAS_div2_i64 0 | |
162 | #elif defined(TCG_TARGET_HAS_div2_i64) | |
163 | #define TCG_TARGET_HAS_div_i64 0 | |
ca675f46 | 164 | #define TCG_TARGET_HAS_rem_i64 0 |
25c4d9cc RH |
165 | #endif |
166 | ||
df9ebea5 RH |
167 | /* For 32-bit targets, some sort of unsigned widening multiply is required. */ |
168 | #if TCG_TARGET_REG_BITS == 32 \ | |
169 | && !(defined(TCG_TARGET_HAS_mulu2_i32) \ | |
170 | || defined(TCG_TARGET_HAS_muluh_i32)) | |
171 | # error "Missing unsigned widening multiply" | |
172 | #endif | |
173 | ||
9aef40ed RH |
174 | #ifndef TARGET_INSN_START_EXTRA_WORDS |
175 | # define TARGET_INSN_START_WORDS 1 | |
176 | #else | |
177 | # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) | |
178 | #endif | |
179 | ||
a9751609 | 180 | typedef enum TCGOpcode { |
c61aaf7a | 181 | #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, |
c896fe29 FB |
182 | #include "tcg-opc.h" |
183 | #undef DEF | |
184 | NB_OPS, | |
a9751609 | 185 | } TCGOpcode; |
c896fe29 | 186 | |
80a8b9a9 RH |
187 | #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) |
188 | #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) | |
189 | #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) | |
c896fe29 | 190 | |
1813e175 | 191 | #ifndef TCG_TARGET_INSN_UNIT_SIZE |
5053361b RH |
192 | # error "Missing TCG_TARGET_INSN_UNIT_SIZE" |
193 | #elif TCG_TARGET_INSN_UNIT_SIZE == 1 | |
1813e175 RH |
194 | typedef uint8_t tcg_insn_unit; |
195 | #elif TCG_TARGET_INSN_UNIT_SIZE == 2 | |
196 | typedef uint16_t tcg_insn_unit; | |
197 | #elif TCG_TARGET_INSN_UNIT_SIZE == 4 | |
198 | typedef uint32_t tcg_insn_unit; | |
199 | #elif TCG_TARGET_INSN_UNIT_SIZE == 8 | |
200 | typedef uint64_t tcg_insn_unit; | |
201 | #else | |
202 | /* The port better have done this. */ | |
203 | #endif | |
204 | ||
205 | ||
8bff06a0 | 206 | #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS |
1f00b27f SS |
207 | # define tcg_debug_assert(X) do { assert(X); } while (0) |
208 | #elif QEMU_GNUC_PREREQ(4, 5) | |
209 | # define tcg_debug_assert(X) \ | |
210 | do { if (!(X)) { __builtin_unreachable(); } } while (0) | |
211 | #else | |
212 | # define tcg_debug_assert(X) do { (void)(X); } while (0) | |
213 | #endif | |
214 | ||
c896fe29 FB |
215 | typedef struct TCGRelocation { |
216 | struct TCGRelocation *next; | |
217 | int type; | |
1813e175 | 218 | tcg_insn_unit *ptr; |
2ba7fae2 | 219 | intptr_t addend; |
c896fe29 FB |
220 | } TCGRelocation; |
221 | ||
222 | typedef struct TCGLabel { | |
51e3972c RH |
223 | unsigned has_value : 1; |
224 | unsigned id : 31; | |
c896fe29 | 225 | union { |
2ba7fae2 | 226 | uintptr_t value; |
1813e175 | 227 | tcg_insn_unit *value_ptr; |
c896fe29 FB |
228 | TCGRelocation *first_reloc; |
229 | } u; | |
230 | } TCGLabel; | |
231 | ||
232 | typedef struct TCGPool { | |
233 | struct TCGPool *next; | |
c44f945a BS |
234 | int size; |
235 | uint8_t data[0] __attribute__ ((aligned)); | |
c896fe29 FB |
236 | } TCGPool; |
237 | ||
238 | #define TCG_POOL_CHUNK_SIZE 32768 | |
239 | ||
c4071c90 | 240 | #define TCG_MAX_TEMPS 512 |
190ce7fb | 241 | #define TCG_MAX_INSNS 512 |
c896fe29 | 242 | |
b03cce8e FB |
243 | /* when the size of the arguments of a called function is smaller than |
244 | this value, they are statically allocated in the TB stack frame */ | |
245 | #define TCG_STATIC_CALL_ARGS_SIZE 128 | |
246 | ||
c02244a5 RH |
247 | typedef enum TCGType { |
248 | TCG_TYPE_I32, | |
249 | TCG_TYPE_I64, | |
250 | TCG_TYPE_COUNT, /* number of different types */ | |
c896fe29 | 251 | |
3b6dac34 | 252 | /* An alias for the size of the host register. */ |
c896fe29 | 253 | #if TCG_TARGET_REG_BITS == 32 |
3b6dac34 | 254 | TCG_TYPE_REG = TCG_TYPE_I32, |
c02244a5 | 255 | #else |
3b6dac34 | 256 | TCG_TYPE_REG = TCG_TYPE_I64, |
c02244a5 | 257 | #endif |
3b6dac34 | 258 | |
d289837e RH |
259 | /* An alias for the size of the native pointer. */ |
260 | #if UINTPTR_MAX == UINT32_MAX | |
261 | TCG_TYPE_PTR = TCG_TYPE_I32, | |
262 | #else | |
263 | TCG_TYPE_PTR = TCG_TYPE_I64, | |
264 | #endif | |
3b6dac34 RH |
265 | |
266 | /* An alias for the size of the target "long", aka register. */ | |
c02244a5 RH |
267 | #if TARGET_LONG_BITS == 64 |
268 | TCG_TYPE_TL = TCG_TYPE_I64, | |
c896fe29 | 269 | #else |
c02244a5 | 270 | TCG_TYPE_TL = TCG_TYPE_I32, |
c896fe29 | 271 | #endif |
c02244a5 | 272 | } TCGType; |
c896fe29 | 273 | |
6c5f4ead RH |
274 | /* Constants for qemu_ld and qemu_st for the Memory Operation field. */ |
275 | typedef enum TCGMemOp { | |
276 | MO_8 = 0, | |
277 | MO_16 = 1, | |
278 | MO_32 = 2, | |
279 | MO_64 = 3, | |
280 | MO_SIZE = 3, /* Mask for the above. */ | |
281 | ||
282 | MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */ | |
283 | ||
284 | MO_BSWAP = 8, /* Host reverse endian. */ | |
285 | #ifdef HOST_WORDS_BIGENDIAN | |
286 | MO_LE = MO_BSWAP, | |
287 | MO_BE = 0, | |
288 | #else | |
289 | MO_LE = 0, | |
290 | MO_BE = MO_BSWAP, | |
291 | #endif | |
292 | #ifdef TARGET_WORDS_BIGENDIAN | |
293 | MO_TE = MO_BE, | |
294 | #else | |
295 | MO_TE = MO_LE, | |
296 | #endif | |
297 | ||
dfb36305 | 298 | /* MO_UNALN accesses are never checked for alignment. |
1f00b27f SS |
299 | * MO_ALIGN accesses will result in a call to the CPU's |
300 | * do_unaligned_access hook if the guest address is not aligned. | |
301 | * The default depends on whether the target CPU defines ALIGNED_ONLY. | |
85aa8081 | 302 | * |
1f00b27f SS |
303 | * Some architectures (e.g. ARMv8) need the address which is aligned |
304 | * to a size more than the size of the memory access. | |
85aa8081 RH |
305 | * Some architectures (e.g. SPARCv9) need an address which is aligned, |
306 | * but less strictly than the natural alignment. | |
307 | * | |
308 | * MO_ALIGN supposes the alignment size is the size of a memory access. | |
309 | * | |
1f00b27f | 310 | * There are three options: |
1f00b27f | 311 | * - unaligned access permitted (MO_UNALN). |
85aa8081 RH |
312 | * - an alignment to the size of an access (MO_ALIGN); |
313 | * - an alignment to a specified size, which may be more or less than | |
314 | * the access size (MO_ALIGN_x where 'x' is a size in bytes); | |
1f00b27f SS |
315 | */ |
316 | MO_ASHIFT = 4, | |
317 | MO_AMASK = 7 << MO_ASHIFT, | |
dfb36305 RH |
318 | #ifdef ALIGNED_ONLY |
319 | MO_ALIGN = 0, | |
320 | MO_UNALN = MO_AMASK, | |
321 | #else | |
322 | MO_ALIGN = MO_AMASK, | |
323 | MO_UNALN = 0, | |
324 | #endif | |
1f00b27f SS |
325 | MO_ALIGN_2 = 1 << MO_ASHIFT, |
326 | MO_ALIGN_4 = 2 << MO_ASHIFT, | |
327 | MO_ALIGN_8 = 3 << MO_ASHIFT, | |
328 | MO_ALIGN_16 = 4 << MO_ASHIFT, | |
329 | MO_ALIGN_32 = 5 << MO_ASHIFT, | |
330 | MO_ALIGN_64 = 6 << MO_ASHIFT, | |
dfb36305 | 331 | |
6c5f4ead RH |
332 | /* Combinations of the above, for ease of use. */ |
333 | MO_UB = MO_8, | |
334 | MO_UW = MO_16, | |
335 | MO_UL = MO_32, | |
336 | MO_SB = MO_SIGN | MO_8, | |
337 | MO_SW = MO_SIGN | MO_16, | |
338 | MO_SL = MO_SIGN | MO_32, | |
339 | MO_Q = MO_64, | |
340 | ||
341 | MO_LEUW = MO_LE | MO_UW, | |
342 | MO_LEUL = MO_LE | MO_UL, | |
343 | MO_LESW = MO_LE | MO_SW, | |
344 | MO_LESL = MO_LE | MO_SL, | |
345 | MO_LEQ = MO_LE | MO_Q, | |
346 | ||
347 | MO_BEUW = MO_BE | MO_UW, | |
348 | MO_BEUL = MO_BE | MO_UL, | |
349 | MO_BESW = MO_BE | MO_SW, | |
350 | MO_BESL = MO_BE | MO_SL, | |
351 | MO_BEQ = MO_BE | MO_Q, | |
352 | ||
353 | MO_TEUW = MO_TE | MO_UW, | |
354 | MO_TEUL = MO_TE | MO_UL, | |
355 | MO_TESW = MO_TE | MO_SW, | |
356 | MO_TESL = MO_TE | MO_SL, | |
357 | MO_TEQ = MO_TE | MO_Q, | |
358 | ||
359 | MO_SSIZE = MO_SIZE | MO_SIGN, | |
360 | } TCGMemOp; | |
361 | ||
1f00b27f SS |
362 | /** |
363 | * get_alignment_bits | |
364 | * @memop: TCGMemOp value | |
365 | * | |
366 | * Extract the alignment size from the memop. | |
1f00b27f | 367 | */ |
85aa8081 | 368 | static inline unsigned get_alignment_bits(TCGMemOp memop) |
1f00b27f | 369 | { |
85aa8081 | 370 | unsigned a = memop & MO_AMASK; |
1f00b27f SS |
371 | |
372 | if (a == MO_UNALN) { | |
85aa8081 RH |
373 | /* No alignment required. */ |
374 | a = 0; | |
1f00b27f | 375 | } else if (a == MO_ALIGN) { |
85aa8081 RH |
376 | /* A natural alignment requirement. */ |
377 | a = memop & MO_SIZE; | |
1f00b27f | 378 | } else { |
85aa8081 RH |
379 | /* A specific alignment requirement. */ |
380 | a = a >> MO_ASHIFT; | |
1f00b27f SS |
381 | } |
382 | #if defined(CONFIG_SOFTMMU) | |
383 | /* The requested alignment cannot overlap the TLB flags. */ | |
85aa8081 | 384 | tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); |
1f00b27f | 385 | #endif |
85aa8081 | 386 | return a; |
1f00b27f SS |
387 | } |
388 | ||
c896fe29 FB |
389 | typedef tcg_target_ulong TCGArg; |
390 | ||
a40d4701 PM |
391 | /* Define type and accessor macros for TCG variables. |
392 | ||
393 | TCG variables are the inputs and outputs of TCG ops, as described | |
394 | in tcg/README. Target CPU front-end code uses these types to deal | |
395 | with TCG variables as it emits TCG code via the tcg_gen_* functions. | |
396 | They come in several flavours: | |
397 | * TCGv_i32 : 32 bit integer type | |
398 | * TCGv_i64 : 64 bit integer type | |
399 | * TCGv_ptr : a host pointer type | |
400 | * TCGv : an integer type the same size as target_ulong | |
401 | (an alias for either TCGv_i32 or TCGv_i64) | |
402 | The compiler's type checking will complain if you mix them | |
403 | up and pass the wrong sized TCGv to a function. | |
404 | ||
405 | Users of tcg_gen_* don't need to know about any of the internal | |
406 | details of these, and should treat them as opaque types. | |
407 | You won't be able to look inside them in a debugger either. | |
408 | ||
409 | Internal implementation details follow: | |
410 | ||
411 | Note that there is no definition of the structs TCGv_i32_d etc anywhere. | |
412 | This is deliberate, because the values we store in variables of type | |
413 | TCGv_i32 are not really pointers-to-structures. They're just small | |
414 | integers, but keeping them in pointer types like this means that the | |
415 | compiler will complain if you accidentally pass a TCGv_i32 to a | |
416 | function which takes a TCGv_i64, and so on. Only the internals of | |
417 | TCG need to care about the actual contents of the types, and they always | |
418 | box and unbox via the MAKE_TCGV_* and GET_TCGV_* functions. | |
419 | Converting to and from intptr_t rather than int reduces the number | |
420 | of sign-extension instructions that get implied on 64-bit hosts. */ | |
ac56dd48 | 421 | |
b6c73a6d RH |
422 | typedef struct TCGv_i32_d *TCGv_i32; |
423 | typedef struct TCGv_i64_d *TCGv_i64; | |
424 | typedef struct TCGv_ptr_d *TCGv_ptr; | |
1bcea73e | 425 | typedef TCGv_ptr TCGv_env; |
5d4e1a10 LV |
426 | #if TARGET_LONG_BITS == 32 |
427 | #define TCGv TCGv_i32 | |
428 | #elif TARGET_LONG_BITS == 64 | |
429 | #define TCGv TCGv_i64 | |
430 | #else | |
431 | #error Unhandled TARGET_LONG_BITS value | |
432 | #endif | |
ac56dd48 | 433 | |
b6c73a6d RH |
434 | static inline TCGv_i32 QEMU_ARTIFICIAL MAKE_TCGV_I32(intptr_t i) |
435 | { | |
436 | return (TCGv_i32)i; | |
437 | } | |
ac56dd48 | 438 | |
b6c73a6d | 439 | static inline TCGv_i64 QEMU_ARTIFICIAL MAKE_TCGV_I64(intptr_t i) |
ac56dd48 | 440 | { |
b6c73a6d RH |
441 | return (TCGv_i64)i; |
442 | } | |
ac56dd48 | 443 | |
b6c73a6d | 444 | static inline TCGv_ptr QEMU_ARTIFICIAL MAKE_TCGV_PTR(intptr_t i) |
a7812ae4 | 445 | { |
b6c73a6d RH |
446 | return (TCGv_ptr)i; |
447 | } | |
ac56dd48 | 448 | |
b6c73a6d RH |
449 | static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I32(TCGv_i32 t) |
450 | { | |
451 | return (intptr_t)t; | |
452 | } | |
ac56dd48 | 453 | |
b6c73a6d RH |
454 | static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I64(TCGv_i64 t) |
455 | { | |
456 | return (intptr_t)t; | |
457 | } | |
458 | ||
459 | static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t) | |
460 | { | |
461 | return (intptr_t)t; | |
462 | } | |
44e6acb0 | 463 | |
ac56dd48 | 464 | #if TCG_TARGET_REG_BITS == 32 |
b6c73a6d RH |
465 | #define TCGV_LOW(t) MAKE_TCGV_I32(GET_TCGV_I64(t)) |
466 | #define TCGV_HIGH(t) MAKE_TCGV_I32(GET_TCGV_I64(t) + 1) | |
ac56dd48 PB |
467 | #endif |
468 | ||
43e860ef AJ |
469 | #define TCGV_EQUAL_I32(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b)) |
470 | #define TCGV_EQUAL_I64(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b)) | |
c1de788a | 471 | #define TCGV_EQUAL_PTR(a, b) (GET_TCGV_PTR(a) == GET_TCGV_PTR(b)) |
43e860ef | 472 | |
a50f5b91 | 473 | /* Dummy definition to avoid compiler warnings. */ |
a7812ae4 PB |
474 | #define TCGV_UNUSED_I32(x) x = MAKE_TCGV_I32(-1) |
475 | #define TCGV_UNUSED_I64(x) x = MAKE_TCGV_I64(-1) | |
c1de788a | 476 | #define TCGV_UNUSED_PTR(x) x = MAKE_TCGV_PTR(-1) |
a50f5b91 | 477 | |
afcb92be RH |
478 | #define TCGV_IS_UNUSED_I32(x) (GET_TCGV_I32(x) == -1) |
479 | #define TCGV_IS_UNUSED_I64(x) (GET_TCGV_I64(x) == -1) | |
c1de788a | 480 | #define TCGV_IS_UNUSED_PTR(x) (GET_TCGV_PTR(x) == -1) |
afcb92be | 481 | |
c896fe29 | 482 | /* call flags */ |
78505279 AJ |
483 | /* Helper does not read globals (either directly or through an exception). It |
484 | implies TCG_CALL_NO_WRITE_GLOBALS. */ | |
485 | #define TCG_CALL_NO_READ_GLOBALS 0x0010 | |
486 | /* Helper does not write globals */ | |
487 | #define TCG_CALL_NO_WRITE_GLOBALS 0x0020 | |
488 | /* Helper can be safely suppressed if the return value is not used. */ | |
489 | #define TCG_CALL_NO_SIDE_EFFECTS 0x0040 | |
490 | ||
491 | /* convenience version of most used call flags */ | |
492 | #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS | |
493 | #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS | |
494 | #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS | |
495 | #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) | |
496 | #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) | |
497 | ||
39cf05d3 | 498 | /* used to align parameters */ |
39cf05d3 FB |
499 | #define TCG_CALL_DUMMY_ARG ((TCGArg)(-1)) |
500 | ||
a93cf9df SW |
501 | /* Conditions. Note that these are laid out for easy manipulation by |
502 | the functions below: | |
0aed257f RH |
503 | bit 0 is used for inverting; |
504 | bit 1 is signed, | |
505 | bit 2 is unsigned, | |
506 | bit 3 is used with bit 0 for swapping signed/unsigned. */ | |
c896fe29 | 507 | typedef enum { |
0aed257f RH |
508 | /* non-signed */ |
509 | TCG_COND_NEVER = 0 | 0 | 0 | 0, | |
510 | TCG_COND_ALWAYS = 0 | 0 | 0 | 1, | |
511 | TCG_COND_EQ = 8 | 0 | 0 | 0, | |
512 | TCG_COND_NE = 8 | 0 | 0 | 1, | |
513 | /* signed */ | |
514 | TCG_COND_LT = 0 | 0 | 2 | 0, | |
515 | TCG_COND_GE = 0 | 0 | 2 | 1, | |
516 | TCG_COND_LE = 8 | 0 | 2 | 0, | |
517 | TCG_COND_GT = 8 | 0 | 2 | 1, | |
c896fe29 | 518 | /* unsigned */ |
0aed257f RH |
519 | TCG_COND_LTU = 0 | 4 | 0 | 0, |
520 | TCG_COND_GEU = 0 | 4 | 0 | 1, | |
521 | TCG_COND_LEU = 8 | 4 | 0 | 0, | |
522 | TCG_COND_GTU = 8 | 4 | 0 | 1, | |
c896fe29 FB |
523 | } TCGCond; |
524 | ||
1c086220 | 525 | /* Invert the sense of the comparison. */ |
401d466d RH |
526 | static inline TCGCond tcg_invert_cond(TCGCond c) |
527 | { | |
528 | return (TCGCond)(c ^ 1); | |
529 | } | |
530 | ||
1c086220 RH |
531 | /* Swap the operands in a comparison. */ |
532 | static inline TCGCond tcg_swap_cond(TCGCond c) | |
533 | { | |
0aed257f | 534 | return c & 6 ? (TCGCond)(c ^ 9) : c; |
1c086220 RH |
535 | } |
536 | ||
d1e321b8 | 537 | /* Create an "unsigned" version of a "signed" comparison. */ |
ff44c2f3 RH |
538 | static inline TCGCond tcg_unsigned_cond(TCGCond c) |
539 | { | |
0aed257f | 540 | return c & 2 ? (TCGCond)(c ^ 6) : c; |
ff44c2f3 RH |
541 | } |
542 | ||
d1e321b8 | 543 | /* Must a comparison be considered unsigned? */ |
bcc66562 RH |
544 | static inline bool is_unsigned_cond(TCGCond c) |
545 | { | |
0aed257f | 546 | return (c & 4) != 0; |
bcc66562 RH |
547 | } |
548 | ||
d1e321b8 RH |
549 | /* Create a "high" version of a double-word comparison. |
550 | This removes equality from a LTE or GTE comparison. */ | |
551 | static inline TCGCond tcg_high_cond(TCGCond c) | |
552 | { | |
553 | switch (c) { | |
554 | case TCG_COND_GE: | |
555 | case TCG_COND_LE: | |
556 | case TCG_COND_GEU: | |
557 | case TCG_COND_LEU: | |
558 | return (TCGCond)(c ^ 8); | |
559 | default: | |
560 | return c; | |
561 | } | |
562 | } | |
563 | ||
00c8fa9f EC |
564 | typedef enum TCGTempVal { |
565 | TEMP_VAL_DEAD, | |
566 | TEMP_VAL_REG, | |
567 | TEMP_VAL_MEM, | |
568 | TEMP_VAL_CONST, | |
569 | } TCGTempVal; | |
c896fe29 | 570 | |
c896fe29 | 571 | typedef struct TCGTemp { |
b6638662 | 572 | TCGReg reg:8; |
00c8fa9f EC |
573 | TCGTempVal val_type:8; |
574 | TCGType base_type:8; | |
575 | TCGType type:8; | |
c896fe29 | 576 | unsigned int fixed_reg:1; |
b3915dbb RH |
577 | unsigned int indirect_reg:1; |
578 | unsigned int indirect_base:1; | |
c896fe29 FB |
579 | unsigned int mem_coherent:1; |
580 | unsigned int mem_allocated:1; | |
fa477d25 RH |
581 | /* If true, the temp is saved across both basic blocks and |
582 | translation blocks. */ | |
583 | unsigned int temp_global:1; | |
584 | /* If true, the temp is saved across basic blocks but dead | |
585 | at the end of translation blocks. If false, the temp is | |
586 | dead at the end of basic blocks. */ | |
587 | unsigned int temp_local:1; | |
588 | unsigned int temp_allocated:1; | |
00c8fa9f EC |
589 | |
590 | tcg_target_long val; | |
b3a62939 | 591 | struct TCGTemp *mem_base; |
00c8fa9f | 592 | intptr_t mem_offset; |
c896fe29 | 593 | const char *name; |
b83eabea RH |
594 | |
595 | /* Pass-specific information that can be stored for a temporary. | |
596 | One word worth of integer data, and one pointer to data | |
597 | allocated separately. */ | |
598 | uintptr_t state; | |
599 | void *state_ptr; | |
c896fe29 FB |
600 | } TCGTemp; |
601 | ||
c896fe29 FB |
602 | typedef struct TCGContext TCGContext; |
603 | ||
0ec9eabc RH |
604 | typedef struct TCGTempSet { |
605 | unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; | |
606 | } TCGTempSet; | |
607 | ||
a1b3c48d RH |
608 | /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding, |
609 | this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands. | |
610 | There are never more than 2 outputs, which means that we can store all | |
611 | dead + sync data within 16 bits. */ | |
612 | #define DEAD_ARG 4 | |
613 | #define SYNC_ARG 1 | |
614 | typedef uint16_t TCGLifeData; | |
615 | ||
75e8b9b7 RH |
616 | /* The layout here is designed to avoid a bitfield crossing of |
617 | a 32-bit boundary, which would cause GCC to add extra padding. */ | |
c45cb8bb | 618 | typedef struct TCGOp { |
bee158cb RH |
619 | TCGOpcode opc : 8; /* 8 */ |
620 | ||
c45cb8bb | 621 | /* The number of out and in parameter for a call. */ |
75e8b9b7 RH |
622 | unsigned calli : 4; /* 12 */ |
623 | unsigned callo : 2; /* 14 */ | |
624 | unsigned : 2; /* 16 */ | |
c45cb8bb | 625 | |
75e8b9b7 RH |
626 | /* Index of the prev/next op, or 0 for the end of the list. */ |
627 | unsigned prev : 16; /* 32 */ | |
628 | unsigned next : 16; /* 48 */ | |
c45cb8bb | 629 | |
bee158cb RH |
630 | /* Lifetime data of the operands. */ |
631 | unsigned life : 16; /* 64 */ | |
75e8b9b7 RH |
632 | |
633 | /* Arguments for the opcode. */ | |
634 | TCGArg args[MAX_OPC_PARAM]; | |
c45cb8bb RH |
635 | } TCGOp; |
636 | ||
75e8b9b7 RH |
637 | /* Make sure that we don't expand the structure without noticing. */ |
638 | QEMU_BUILD_BUG_ON(sizeof(TCGOp) != 8 + sizeof(TCGArg) * MAX_OPC_PARAM); | |
639 | ||
dcb8e758 RH |
640 | /* Make sure operands fit in the bitfields above. */ |
641 | QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); | |
75e8b9b7 | 642 | QEMU_BUILD_BUG_ON(OPC_BUF_SIZE > (1 << 16)); |
c45cb8bb | 643 | |
c896fe29 FB |
644 | struct TCGContext { |
645 | uint8_t *pool_cur, *pool_end; | |
4055299e | 646 | TCGPool *pool_first, *pool_current, *pool_first_large; |
c896fe29 | 647 | int nb_labels; |
c896fe29 FB |
648 | int nb_globals; |
649 | int nb_temps; | |
5a18407f | 650 | int nb_indirects; |
c896fe29 FB |
651 | |
652 | /* goto_tb support */ | |
1813e175 | 653 | tcg_insn_unit *code_buf; |
f309101c | 654 | uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */ |
a8583393 RH |
655 | uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */ |
656 | uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */ | |
c896fe29 | 657 | |
c896fe29 | 658 | TCGRegSet reserved_regs; |
e2c6d1b4 RH |
659 | intptr_t current_frame_offset; |
660 | intptr_t frame_start; | |
661 | intptr_t frame_end; | |
b3a62939 | 662 | TCGTemp *frame_temp; |
c896fe29 | 663 | |
1813e175 | 664 | tcg_insn_unit *code_ptr; |
c896fe29 | 665 | |
a23a9ec6 FB |
666 | #ifdef CONFIG_PROFILER |
667 | /* profiling info */ | |
668 | int64_t tb_count1; | |
669 | int64_t tb_count; | |
670 | int64_t op_count; /* total insn count */ | |
671 | int op_count_max; /* max insn per TB */ | |
672 | int64_t temp_count; | |
673 | int temp_count_max; | |
a23a9ec6 FB |
674 | int64_t del_op_count; |
675 | int64_t code_in_len; | |
676 | int64_t code_out_len; | |
fca8a500 | 677 | int64_t search_out_len; |
a23a9ec6 FB |
678 | int64_t interm_time; |
679 | int64_t code_time; | |
680 | int64_t la_time; | |
c5cc28ff | 681 | int64_t opt_time; |
a23a9ec6 FB |
682 | int64_t restore_count; |
683 | int64_t restore_time; | |
684 | #endif | |
27bfd83c PM |
685 | |
686 | #ifdef CONFIG_DEBUG_TCG | |
687 | int temps_in_use; | |
0a209d4b | 688 | int goto_tb_issue_mask; |
27bfd83c | 689 | #endif |
b76f0d8c | 690 | |
c45cb8bb | 691 | int gen_next_op_idx; |
8232a46a | 692 | |
1813e175 RH |
693 | /* Code generation. Note that we specifically do not use tcg_insn_unit |
694 | here, because there's too much arithmetic throughout that relies | |
695 | on addition and subtraction working on bytes. Rely on the GCC | |
696 | extension that allows arithmetic on void*. */ | |
1813e175 | 697 | void *code_gen_prologue; |
cedbcb01 | 698 | void *code_gen_epilogue; |
1813e175 | 699 | void *code_gen_buffer; |
0b0d3320 | 700 | size_t code_gen_buffer_size; |
1813e175 | 701 | void *code_gen_ptr; |
57a26946 | 702 | void *data_gen_ptr; |
0b0d3320 | 703 | |
b125f9dc RH |
704 | /* Threshold to flush the translated code buffer. */ |
705 | void *code_gen_highwater; | |
706 | ||
5e5f07e0 EV |
707 | TBContext tb_ctx; |
708 | ||
7c255043 LV |
709 | /* Track which vCPU triggers events */ |
710 | CPUState *cpu; /* *_trans */ | |
711 | TCGv_env tcg_env; /* *_exec */ | |
712 | ||
659ef5cb RH |
713 | /* These structures are private to tcg-target.inc.c. */ |
714 | #ifdef TCG_TARGET_NEED_LDST_LABELS | |
715 | struct TCGLabelQemuLdst *ldst_labels; | |
716 | #endif | |
57a26946 RH |
717 | #ifdef TCG_TARGET_NEED_POOL_LABELS |
718 | struct TCGLabelPoolData *pool_labels; | |
719 | #endif | |
c45cb8bb RH |
720 | |
721 | TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; | |
722 | TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ | |
723 | ||
f8b2f202 RH |
724 | /* Tells which temporary holds a given register. |
725 | It does not take into account fixed registers */ | |
726 | TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; | |
c45cb8bb RH |
727 | |
728 | TCGOp gen_op_buf[OPC_BUF_SIZE]; | |
c45cb8bb | 729 | |
fca8a500 RH |
730 | uint16_t gen_insn_end_off[TCG_MAX_INSNS]; |
731 | target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; | |
c896fe29 FB |
732 | }; |
733 | ||
734 | extern TCGContext tcg_ctx; | |
fdbc2b57 | 735 | extern bool parallel_cpus; |
c896fe29 | 736 | |
1807f4c4 RH |
737 | static inline size_t temp_idx(TCGTemp *ts) |
738 | { | |
739 | ptrdiff_t n = ts - tcg_ctx.temps; | |
740 | tcg_debug_assert(n >= 0 && n < tcg_ctx.nb_temps); | |
741 | return n; | |
742 | } | |
743 | ||
744 | static inline TCGArg temp_arg(TCGTemp *ts) | |
745 | { | |
746 | return temp_idx(ts); | |
747 | } | |
748 | ||
43439139 RH |
749 | static inline TCGTemp *arg_temp(TCGArg a) |
750 | { | |
c6c7d84d | 751 | return a == TCG_CALL_DUMMY_ARG ? NULL : &tcg_ctx.temps[a]; |
43439139 RH |
752 | } |
753 | ||
6349039d RH |
754 | static inline size_t arg_index(TCGArg a) |
755 | { | |
756 | return a; | |
757 | } | |
758 | ||
1d41478f EI |
759 | static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v) |
760 | { | |
75e8b9b7 | 761 | tcg_ctx.gen_op_buf[op_idx].args[arg] = v; |
1d41478f EI |
762 | } |
763 | ||
fe700adb RH |
764 | /* The number of opcodes emitted so far. */ |
765 | static inline int tcg_op_buf_count(void) | |
766 | { | |
c45cb8bb | 767 | return tcg_ctx.gen_next_op_idx; |
fe700adb RH |
768 | } |
769 | ||
770 | /* Test for whether to terminate the TB for using too many opcodes. */ | |
771 | static inline bool tcg_op_buf_full(void) | |
772 | { | |
773 | return tcg_op_buf_count() >= OPC_MAX_SIZE; | |
774 | } | |
775 | ||
c896fe29 FB |
776 | /* pool based memory allocation */ |
777 | ||
7d7500d9 | 778 | /* tb_lock must be held for tcg_malloc_internal. */ |
c896fe29 FB |
779 | void *tcg_malloc_internal(TCGContext *s, int size); |
780 | void tcg_pool_reset(TCGContext *s); | |
6e3b2bfd | 781 | TranslationBlock *tcg_tb_alloc(TCGContext *s); |
c896fe29 | 782 | |
7d7500d9 | 783 | /* Called with tb_lock held. */ |
c896fe29 FB |
784 | static inline void *tcg_malloc(int size) |
785 | { | |
786 | TCGContext *s = &tcg_ctx; | |
787 | uint8_t *ptr, *ptr_end; | |
13aaef67 RH |
788 | |
789 | /* ??? This is a weak placeholder for minimum malloc alignment. */ | |
790 | size = QEMU_ALIGN_UP(size, 8); | |
791 | ||
c896fe29 FB |
792 | ptr = s->pool_cur; |
793 | ptr_end = ptr + size; | |
794 | if (unlikely(ptr_end > s->pool_end)) { | |
795 | return tcg_malloc_internal(&tcg_ctx, size); | |
796 | } else { | |
797 | s->pool_cur = ptr_end; | |
798 | return ptr; | |
799 | } | |
800 | } | |
801 | ||
802 | void tcg_context_init(TCGContext *s); | |
9002ec79 | 803 | void tcg_prologue_init(TCGContext *s); |
c896fe29 FB |
804 | void tcg_func_start(TCGContext *s); |
805 | ||
5bd2ec3d | 806 | int tcg_gen_code(TCGContext *s, TranslationBlock *tb); |
c896fe29 | 807 | |
b6638662 | 808 | void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); |
a7812ae4 | 809 | |
e1ccc054 RH |
810 | int tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *); |
811 | ||
b6638662 RH |
812 | TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name); |
813 | TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name); | |
e1ccc054 | 814 | |
a7812ae4 | 815 | TCGv_i32 tcg_temp_new_internal_i32(int temp_local); |
e1ccc054 RH |
816 | TCGv_i64 tcg_temp_new_internal_i64(int temp_local); |
817 | ||
818 | void tcg_temp_free_i32(TCGv_i32 arg); | |
819 | void tcg_temp_free_i64(TCGv_i64 arg); | |
820 | ||
e1ccc054 RH |
821 | static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, |
822 | const char *name) | |
823 | { | |
824 | int idx = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); | |
825 | return MAKE_TCGV_I32(idx); | |
826 | } | |
827 | ||
a7812ae4 PB |
828 | static inline TCGv_i32 tcg_temp_new_i32(void) |
829 | { | |
830 | return tcg_temp_new_internal_i32(0); | |
831 | } | |
e1ccc054 | 832 | |
a7812ae4 PB |
833 | static inline TCGv_i32 tcg_temp_local_new_i32(void) |
834 | { | |
835 | return tcg_temp_new_internal_i32(1); | |
836 | } | |
a7812ae4 | 837 | |
e1ccc054 RH |
838 | static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, |
839 | const char *name) | |
840 | { | |
841 | int idx = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); | |
842 | return MAKE_TCGV_I64(idx); | |
843 | } | |
844 | ||
a7812ae4 | 845 | static inline TCGv_i64 tcg_temp_new_i64(void) |
641d5fbe | 846 | { |
a7812ae4 | 847 | return tcg_temp_new_internal_i64(0); |
641d5fbe | 848 | } |
e1ccc054 | 849 | |
a7812ae4 | 850 | static inline TCGv_i64 tcg_temp_local_new_i64(void) |
641d5fbe | 851 | { |
a7812ae4 | 852 | return tcg_temp_new_internal_i64(1); |
641d5fbe | 853 | } |
a7812ae4 | 854 | |
27bfd83c PM |
855 | #if defined(CONFIG_DEBUG_TCG) |
856 | /* If you call tcg_clear_temp_count() at the start of a section of | |
857 | * code which is not supposed to leak any TCG temporaries, then | |
858 | * calling tcg_check_temp_count() at the end of the section will | |
859 | * return 1 if the section did in fact leak a temporary. | |
860 | */ | |
861 | void tcg_clear_temp_count(void); | |
862 | int tcg_check_temp_count(void); | |
863 | #else | |
864 | #define tcg_clear_temp_count() do { } while (0) | |
865 | #define tcg_check_temp_count() 0 | |
866 | #endif | |
867 | ||
405cf9ff | 868 | void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf); |
246ae24d | 869 | void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf); |
c896fe29 FB |
870 | |
871 | #define TCG_CT_ALIAS 0x80 | |
872 | #define TCG_CT_IALIAS 0x40 | |
82790a87 | 873 | #define TCG_CT_NEWREG 0x20 /* output requires a new register */ |
c896fe29 FB |
874 | #define TCG_CT_REG 0x01 |
875 | #define TCG_CT_CONST 0x02 /* any constant of register size */ | |
876 | ||
877 | typedef struct TCGArgConstraint { | |
5ff9d6a4 FB |
878 | uint16_t ct; |
879 | uint8_t alias_index; | |
c896fe29 FB |
880 | union { |
881 | TCGRegSet regs; | |
882 | } u; | |
883 | } TCGArgConstraint; | |
884 | ||
885 | #define TCG_MAX_OP_ARGS 16 | |
886 | ||
8399ad59 RH |
887 | /* Bits for TCGOpDef->flags, 8 bits available. */ |
888 | enum { | |
889 | /* Instruction defines the end of a basic block. */ | |
890 | TCG_OPF_BB_END = 0x01, | |
891 | /* Instruction clobbers call registers and potentially update globals. */ | |
892 | TCG_OPF_CALL_CLOBBER = 0x02, | |
3d5c5f87 AJ |
893 | /* Instruction has side effects: it cannot be removed if its outputs |
894 | are not used, and might trigger exceptions. */ | |
8399ad59 RH |
895 | TCG_OPF_SIDE_EFFECTS = 0x04, |
896 | /* Instruction operands are 64-bits (otherwise 32-bits). */ | |
897 | TCG_OPF_64BIT = 0x08, | |
c1a61f6c RH |
898 | /* Instruction is optional and not implemented by the host, or insn |
899 | is generic and should not be implemened by the host. */ | |
25c4d9cc | 900 | TCG_OPF_NOT_PRESENT = 0x10, |
8399ad59 | 901 | }; |
c896fe29 FB |
902 | |
903 | typedef struct TCGOpDef { | |
904 | const char *name; | |
905 | uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; | |
906 | uint8_t flags; | |
c896fe29 FB |
907 | TCGArgConstraint *args_ct; |
908 | int *sorted_args; | |
c68aaa18 SW |
909 | #if defined(CONFIG_DEBUG_TCG) |
910 | int used; | |
911 | #endif | |
c896fe29 | 912 | } TCGOpDef; |
8399ad59 RH |
913 | |
914 | extern TCGOpDef tcg_op_defs[]; | |
2a24374a SW |
915 | extern const size_t tcg_op_defs_max; |
916 | ||
c896fe29 | 917 | typedef struct TCGTargetOpDef { |
a9751609 | 918 | TCGOpcode op; |
c896fe29 FB |
919 | const char *args_ct_str[TCG_MAX_OP_ARGS]; |
920 | } TCGTargetOpDef; | |
921 | ||
c896fe29 FB |
922 | #define tcg_abort() \ |
923 | do {\ | |
924 | fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\ | |
925 | abort();\ | |
926 | } while (0) | |
927 | ||
8b73d49f | 928 | #if UINTPTR_MAX == UINT32_MAX |
ebecf363 PM |
929 | #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I32(n)) |
930 | #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I32(GET_TCGV_PTR(n)) | |
931 | ||
8b73d49f | 932 | #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V))) |
ebecf363 PM |
933 | #define tcg_global_reg_new_ptr(R, N) \ |
934 | TCGV_NAT_TO_PTR(tcg_global_reg_new_i32((R), (N))) | |
935 | #define tcg_global_mem_new_ptr(R, O, N) \ | |
936 | TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N))) | |
937 | #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32()) | |
938 | #define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T)) | |
c896fe29 | 939 | #else |
ebecf363 PM |
940 | #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I64(n)) |
941 | #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I64(GET_TCGV_PTR(n)) | |
942 | ||
8b73d49f | 943 | #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V))) |
ebecf363 PM |
944 | #define tcg_global_reg_new_ptr(R, N) \ |
945 | TCGV_NAT_TO_PTR(tcg_global_reg_new_i64((R), (N))) | |
946 | #define tcg_global_mem_new_ptr(R, O, N) \ | |
947 | TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N))) | |
948 | #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64()) | |
949 | #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T)) | |
c896fe29 FB |
950 | #endif |
951 | ||
be0f34b5 RH |
952 | bool tcg_op_supported(TCGOpcode op); |
953 | ||
960c50e0 | 954 | void tcg_gen_callN(void *func, TCGArg ret, int nargs, TCGArg *args); |
a7812ae4 | 955 | |
0c627cdc | 956 | void tcg_op_remove(TCGContext *s, TCGOp *op); |
5a18407f RH |
957 | TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg); |
958 | TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc, int narg); | |
959 | ||
c45cb8bb | 960 | void tcg_optimize(TCGContext *s); |
8f2e8c07 | 961 | |
a7812ae4 | 962 | /* only used for debugging purposes */ |
eeacee4d | 963 | void tcg_dump_ops(TCGContext *s); |
a7812ae4 | 964 | |
a7812ae4 PB |
965 | TCGv_i32 tcg_const_i32(int32_t val); |
966 | TCGv_i64 tcg_const_i64(int64_t val); | |
967 | TCGv_i32 tcg_const_local_i32(int32_t val); | |
968 | TCGv_i64 tcg_const_local_i64(int64_t val); | |
969 | ||
42a268c2 RH |
970 | TCGLabel *gen_new_label(void); |
971 | ||
972 | /** | |
973 | * label_arg | |
974 | * @l: label | |
975 | * | |
976 | * Encode a label for storage in the TCG opcode stream. | |
977 | */ | |
978 | ||
979 | static inline TCGArg label_arg(TCGLabel *l) | |
980 | { | |
51e3972c | 981 | return (uintptr_t)l; |
42a268c2 RH |
982 | } |
983 | ||
984 | /** | |
985 | * arg_label | |
986 | * @i: value | |
987 | * | |
988 | * The opposite of label_arg. Retrieve a label from the | |
989 | * encoding of the TCG opcode stream. | |
990 | */ | |
991 | ||
51e3972c | 992 | static inline TCGLabel *arg_label(TCGArg i) |
42a268c2 | 993 | { |
51e3972c | 994 | return (TCGLabel *)(uintptr_t)i; |
42a268c2 RH |
995 | } |
996 | ||
52a1f64e RH |
997 | /** |
998 | * tcg_ptr_byte_diff | |
999 | * @a, @b: addresses to be differenced | |
1000 | * | |
1001 | * There are many places within the TCG backends where we need a byte | |
1002 | * difference between two pointers. While this can be accomplished | |
1003 | * with local casting, it's easy to get wrong -- especially if one is | |
1004 | * concerned with the signedness of the result. | |
1005 | * | |
1006 | * This version relies on GCC's void pointer arithmetic to get the | |
1007 | * correct result. | |
1008 | */ | |
1009 | ||
1010 | static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b) | |
1011 | { | |
1012 | return a - b; | |
1013 | } | |
1014 | ||
1015 | /** | |
1016 | * tcg_pcrel_diff | |
1017 | * @s: the tcg context | |
1018 | * @target: address of the target | |
1019 | * | |
1020 | * Produce a pc-relative difference, from the current code_ptr | |
1021 | * to the destination address. | |
1022 | */ | |
1023 | ||
1024 | static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target) | |
1025 | { | |
1026 | return tcg_ptr_byte_diff(target, s->code_ptr); | |
1027 | } | |
1028 | ||
1029 | /** | |
1030 | * tcg_current_code_size | |
1031 | * @s: the tcg context | |
1032 | * | |
1033 | * Compute the current code size within the translation block. | |
1034 | * This is used to fill in qemu's data structures for goto_tb. | |
1035 | */ | |
1036 | ||
1037 | static inline size_t tcg_current_code_size(TCGContext *s) | |
1038 | { | |
1039 | return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); | |
1040 | } | |
1041 | ||
59227d5d RH |
1042 | /* Combine the TCGMemOp and mmu_idx parameters into a single value. */ |
1043 | typedef uint32_t TCGMemOpIdx; | |
1044 | ||
1045 | /** | |
1046 | * make_memop_idx | |
1047 | * @op: memory operation | |
1048 | * @idx: mmu index | |
1049 | * | |
1050 | * Encode these values into a single parameter. | |
1051 | */ | |
1052 | static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx) | |
1053 | { | |
1054 | tcg_debug_assert(idx <= 15); | |
1055 | return (op << 4) | idx; | |
1056 | } | |
1057 | ||
1058 | /** | |
1059 | * get_memop | |
1060 | * @oi: combined op/idx parameter | |
1061 | * | |
1062 | * Extract the memory operation from the combined value. | |
1063 | */ | |
1064 | static inline TCGMemOp get_memop(TCGMemOpIdx oi) | |
1065 | { | |
1066 | return oi >> 4; | |
1067 | } | |
1068 | ||
1069 | /** | |
1070 | * get_mmuidx | |
1071 | * @oi: combined op/idx parameter | |
1072 | * | |
1073 | * Extract the mmu index from the combined value. | |
1074 | */ | |
1075 | static inline unsigned get_mmuidx(TCGMemOpIdx oi) | |
1076 | { | |
1077 | return oi & 15; | |
1078 | } | |
1079 | ||
0980011b PM |
1080 | /** |
1081 | * tcg_qemu_tb_exec: | |
819af24b | 1082 | * @env: pointer to CPUArchState for the CPU |
0980011b PM |
1083 | * @tb_ptr: address of generated code for the TB to execute |
1084 | * | |
1085 | * Start executing code from a given translation block. | |
1086 | * Where translation blocks have been linked, execution | |
1087 | * may proceed from the given TB into successive ones. | |
1088 | * Control eventually returns only when some action is needed | |
1089 | * from the top-level loop: either control must pass to a TB | |
1090 | * which has not yet been directly linked, or an asynchronous | |
1091 | * event such as an interrupt needs handling. | |
1092 | * | |
819af24b SF |
1093 | * Return: The return value is the value passed to the corresponding |
1094 | * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. | |
1095 | * The value is either zero or a 4-byte aligned pointer to that TB combined | |
1096 | * with additional information in its two least significant bits. The | |
1097 | * additional information is encoded as follows: | |
0980011b PM |
1098 | * 0, 1: the link between this TB and the next is via the specified |
1099 | * TB index (0 or 1). That is, we left the TB via (the equivalent | |
1100 | * of) "goto_tb <index>". The main loop uses this to determine | |
1101 | * how to link the TB just executed to the next. | |
1102 | * 2: we are using instruction counting code generation, and we | |
1103 | * did not start executing this TB because the instruction counter | |
819af24b | 1104 | * would hit zero midway through it. In this case the pointer |
0980011b PM |
1105 | * returned is the TB we were about to execute, and the caller must |
1106 | * arrange to execute the remaining count of instructions. | |
378df4b2 PM |
1107 | * 3: we stopped because the CPU's exit_request flag was set |
1108 | * (usually meaning that there is an interrupt that needs to be | |
819af24b SF |
1109 | * handled). The pointer returned is the TB we were about to execute |
1110 | * when we noticed the pending exit request. | |
0980011b PM |
1111 | * |
1112 | * If the bottom two bits indicate an exit-via-index then the CPU | |
1113 | * state is correctly synchronised and ready for execution of the next | |
1114 | * TB (and in particular the guest PC is the address to execute next). | |
1115 | * Otherwise, we gave up on execution of this TB before it started, and | |
fee068e4 | 1116 | * the caller must fix up the CPU state by calling the CPU's |
819af24b | 1117 | * synchronize_from_tb() method with the TB pointer we return (falling |
fee068e4 PC |
1118 | * back to calling the CPU's set_pc method with tb->pb if no |
1119 | * synchronize_from_tb() method exists). | |
0980011b PM |
1120 | * |
1121 | * Note that TCG targets may use a different definition of tcg_qemu_tb_exec | |
1122 | * to this default (which just calls the prologue.code emitted by | |
1123 | * tcg_target_qemu_prologue()). | |
1124 | */ | |
1125 | #define TB_EXIT_MASK 3 | |
1126 | #define TB_EXIT_IDX0 0 | |
1127 | #define TB_EXIT_IDX1 1 | |
378df4b2 | 1128 | #define TB_EXIT_REQUESTED 3 |
0980011b | 1129 | |
5a58e884 PB |
1130 | #ifdef HAVE_TCG_QEMU_TB_EXEC |
1131 | uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr); | |
1132 | #else | |
ce285b17 | 1133 | # define tcg_qemu_tb_exec(env, tb_ptr) \ |
04d5a1da | 1134 | ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr) |
932a6909 | 1135 | #endif |
813da627 RH |
1136 | |
1137 | void tcg_register_jit(void *buf, size_t buf_size); | |
b76f0d8c | 1138 | |
e58eb534 RH |
1139 | /* |
1140 | * Memory helpers that will be used by TCG generated code. | |
1141 | */ | |
1142 | #ifdef CONFIG_SOFTMMU | |
c8f94df5 RH |
1143 | /* Value zero-extended to tcg register size. */ |
1144 | tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, | |
3972ef6f | 1145 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1146 | tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1147 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1148 | tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1149 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1150 | uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1151 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1152 | tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1153 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1154 | tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1155 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1156 | uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1157 | TCGMemOpIdx oi, uintptr_t retaddr); |
e58eb534 | 1158 | |
c8f94df5 RH |
1159 | /* Value sign-extended to tcg register size. */ |
1160 | tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, | |
3972ef6f | 1161 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1162 | tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1163 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1164 | tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1165 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1166 | tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1167 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1168 | tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1169 | TCGMemOpIdx oi, uintptr_t retaddr); |
c8f94df5 | 1170 | |
e58eb534 | 1171 | void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, |
3972ef6f | 1172 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1173 | void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, |
3972ef6f | 1174 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1175 | void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, |
3972ef6f | 1176 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1177 | void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, |
3972ef6f | 1178 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1179 | void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, |
3972ef6f | 1180 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1181 | void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, |
3972ef6f | 1182 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1183 | void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, |
3972ef6f | 1184 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1185 | |
282dffc8 PD |
1186 | uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr, |
1187 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1188 | uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr, | |
1189 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1190 | uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr, | |
1191 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1192 | uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr, | |
1193 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1194 | uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr, | |
1195 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1196 | uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr, | |
1197 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1198 | uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr, | |
1199 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1200 | ||
867b3201 RH |
1201 | /* Temporary aliases until backends are converted. */ |
1202 | #ifdef TARGET_WORDS_BIGENDIAN | |
1203 | # define helper_ret_ldsw_mmu helper_be_ldsw_mmu | |
1204 | # define helper_ret_lduw_mmu helper_be_lduw_mmu | |
1205 | # define helper_ret_ldsl_mmu helper_be_ldsl_mmu | |
1206 | # define helper_ret_ldul_mmu helper_be_ldul_mmu | |
282dffc8 | 1207 | # define helper_ret_ldl_mmu helper_be_ldul_mmu |
867b3201 RH |
1208 | # define helper_ret_ldq_mmu helper_be_ldq_mmu |
1209 | # define helper_ret_stw_mmu helper_be_stw_mmu | |
1210 | # define helper_ret_stl_mmu helper_be_stl_mmu | |
1211 | # define helper_ret_stq_mmu helper_be_stq_mmu | |
282dffc8 PD |
1212 | # define helper_ret_ldw_cmmu helper_be_ldw_cmmu |
1213 | # define helper_ret_ldl_cmmu helper_be_ldl_cmmu | |
1214 | # define helper_ret_ldq_cmmu helper_be_ldq_cmmu | |
867b3201 RH |
1215 | #else |
1216 | # define helper_ret_ldsw_mmu helper_le_ldsw_mmu | |
1217 | # define helper_ret_lduw_mmu helper_le_lduw_mmu | |
1218 | # define helper_ret_ldsl_mmu helper_le_ldsl_mmu | |
1219 | # define helper_ret_ldul_mmu helper_le_ldul_mmu | |
282dffc8 | 1220 | # define helper_ret_ldl_mmu helper_le_ldul_mmu |
867b3201 RH |
1221 | # define helper_ret_ldq_mmu helper_le_ldq_mmu |
1222 | # define helper_ret_stw_mmu helper_le_stw_mmu | |
1223 | # define helper_ret_stl_mmu helper_le_stl_mmu | |
1224 | # define helper_ret_stq_mmu helper_le_stq_mmu | |
282dffc8 PD |
1225 | # define helper_ret_ldw_cmmu helper_le_ldw_cmmu |
1226 | # define helper_ret_ldl_cmmu helper_le_ldl_cmmu | |
1227 | # define helper_ret_ldq_cmmu helper_le_ldq_cmmu | |
867b3201 | 1228 | #endif |
e58eb534 | 1229 | |
c482cb11 RH |
1230 | uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, |
1231 | uint32_t cmpv, uint32_t newv, | |
1232 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1233 | uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr, | |
1234 | uint32_t cmpv, uint32_t newv, | |
1235 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1236 | uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr, | |
1237 | uint32_t cmpv, uint32_t newv, | |
1238 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1239 | uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr, | |
1240 | uint64_t cmpv, uint64_t newv, | |
1241 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1242 | uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr, | |
1243 | uint32_t cmpv, uint32_t newv, | |
1244 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1245 | uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr, | |
1246 | uint32_t cmpv, uint32_t newv, | |
1247 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1248 | uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr, | |
1249 | uint64_t cmpv, uint64_t newv, | |
1250 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1251 | ||
1252 | #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ | |
1253 | TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu \ | |
1254 | (CPUArchState *env, target_ulong addr, TYPE val, \ | |
1255 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1256 | ||
df79b996 | 1257 | #ifdef CONFIG_ATOMIC64 |
c482cb11 | 1258 | #define GEN_ATOMIC_HELPER_ALL(NAME) \ |
df79b996 | 1259 | GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ |
c482cb11 | 1260 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ |
c482cb11 | 1261 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ |
df79b996 | 1262 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ |
c482cb11 | 1263 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ |
df79b996 | 1264 | GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ |
c482cb11 | 1265 | GEN_ATOMIC_HELPER(NAME, uint64_t, q_be) |
df79b996 RH |
1266 | #else |
1267 | #define GEN_ATOMIC_HELPER_ALL(NAME) \ | |
1268 | GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ | |
1269 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ | |
1270 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ | |
1271 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ | |
1272 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) | |
1273 | #endif | |
c482cb11 RH |
1274 | |
1275 | GEN_ATOMIC_HELPER_ALL(fetch_add) | |
1276 | GEN_ATOMIC_HELPER_ALL(fetch_sub) | |
1277 | GEN_ATOMIC_HELPER_ALL(fetch_and) | |
1278 | GEN_ATOMIC_HELPER_ALL(fetch_or) | |
1279 | GEN_ATOMIC_HELPER_ALL(fetch_xor) | |
1280 | ||
1281 | GEN_ATOMIC_HELPER_ALL(add_fetch) | |
1282 | GEN_ATOMIC_HELPER_ALL(sub_fetch) | |
1283 | GEN_ATOMIC_HELPER_ALL(and_fetch) | |
1284 | GEN_ATOMIC_HELPER_ALL(or_fetch) | |
1285 | GEN_ATOMIC_HELPER_ALL(xor_fetch) | |
1286 | ||
1287 | GEN_ATOMIC_HELPER_ALL(xchg) | |
1288 | ||
1289 | #undef GEN_ATOMIC_HELPER_ALL | |
1290 | #undef GEN_ATOMIC_HELPER | |
e58eb534 RH |
1291 | #endif /* CONFIG_SOFTMMU */ |
1292 | ||
7ebee43e RH |
1293 | #ifdef CONFIG_ATOMIC128 |
1294 | #include "qemu/int128.h" | |
1295 | ||
1296 | /* These aren't really a "proper" helpers because TCG cannot manage Int128. | |
1297 | However, use the same format as the others, for use by the backends. */ | |
1298 | Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, | |
1299 | Int128 cmpv, Int128 newv, | |
1300 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1301 | Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr, | |
1302 | Int128 cmpv, Int128 newv, | |
1303 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1304 | ||
1305 | Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, | |
1306 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1307 | Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, | |
1308 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1309 | void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val, | |
1310 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1311 | void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val, | |
1312 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1313 | ||
1314 | #endif /* CONFIG_ATOMIC128 */ | |
1315 | ||
e58eb534 | 1316 | #endif /* TCG_H */ |