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Commit | Line | Data |
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7316329a SW |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2009, 2011 Stefan Weil | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | /* TODO list: | |
26 | * - See TODO comments in code. | |
27 | */ | |
28 | ||
29 | /* Marker for missing code. */ | |
30 | #define TODO() \ | |
31 | do { \ | |
32 | fprintf(stderr, "TODO %s:%u: %s()\n", \ | |
33 | __FILE__, __LINE__, __func__); \ | |
34 | tcg_abort(); \ | |
35 | } while (0) | |
36 | ||
7316329a SW |
37 | /* Bitfield n...m (in 32 bit value). */ |
38 | #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m) | |
39 | ||
63b29fda RH |
40 | static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) |
41 | { | |
42 | switch (op) { | |
43 | case INDEX_op_ld8u_i32: | |
44 | case INDEX_op_ld8s_i32: | |
45 | case INDEX_op_ld16u_i32: | |
46 | case INDEX_op_ld16s_i32: | |
47 | case INDEX_op_ld_i32: | |
48 | case INDEX_op_ld8u_i64: | |
49 | case INDEX_op_ld8s_i64: | |
50 | case INDEX_op_ld16u_i64: | |
51 | case INDEX_op_ld16s_i64: | |
52 | case INDEX_op_ld32u_i64: | |
53 | case INDEX_op_ld32s_i64: | |
54 | case INDEX_op_ld_i64: | |
55 | case INDEX_op_not_i32: | |
56 | case INDEX_op_not_i64: | |
57 | case INDEX_op_neg_i32: | |
58 | case INDEX_op_neg_i64: | |
59 | case INDEX_op_ext8s_i32: | |
60 | case INDEX_op_ext8s_i64: | |
61 | case INDEX_op_ext16s_i32: | |
62 | case INDEX_op_ext16s_i64: | |
63 | case INDEX_op_ext8u_i32: | |
64 | case INDEX_op_ext8u_i64: | |
65 | case INDEX_op_ext16u_i32: | |
66 | case INDEX_op_ext16u_i64: | |
67 | case INDEX_op_ext32s_i64: | |
68 | case INDEX_op_ext32u_i64: | |
69 | case INDEX_op_ext_i32_i64: | |
70 | case INDEX_op_extu_i32_i64: | |
71 | case INDEX_op_bswap16_i32: | |
72 | case INDEX_op_bswap16_i64: | |
73 | case INDEX_op_bswap32_i32: | |
74 | case INDEX_op_bswap32_i64: | |
75 | case INDEX_op_bswap64_i64: | |
76 | return C_O1_I1(r, r); | |
77 | ||
78 | case INDEX_op_st8_i32: | |
79 | case INDEX_op_st16_i32: | |
80 | case INDEX_op_st_i32: | |
81 | case INDEX_op_st8_i64: | |
82 | case INDEX_op_st16_i64: | |
83 | case INDEX_op_st32_i64: | |
84 | case INDEX_op_st_i64: | |
85 | return C_O0_I2(r, r); | |
86 | ||
87 | case INDEX_op_div_i32: | |
88 | case INDEX_op_div_i64: | |
89 | case INDEX_op_divu_i32: | |
90 | case INDEX_op_divu_i64: | |
91 | case INDEX_op_rem_i32: | |
92 | case INDEX_op_rem_i64: | |
93 | case INDEX_op_remu_i32: | |
94 | case INDEX_op_remu_i64: | |
63b29fda RH |
95 | case INDEX_op_add_i32: |
96 | case INDEX_op_add_i64: | |
97 | case INDEX_op_sub_i32: | |
98 | case INDEX_op_sub_i64: | |
99 | case INDEX_op_mul_i32: | |
100 | case INDEX_op_mul_i64: | |
101 | case INDEX_op_and_i32: | |
102 | case INDEX_op_and_i64: | |
103 | case INDEX_op_andc_i32: | |
104 | case INDEX_op_andc_i64: | |
105 | case INDEX_op_eqv_i32: | |
106 | case INDEX_op_eqv_i64: | |
107 | case INDEX_op_nand_i32: | |
108 | case INDEX_op_nand_i64: | |
109 | case INDEX_op_nor_i32: | |
110 | case INDEX_op_nor_i64: | |
111 | case INDEX_op_or_i32: | |
112 | case INDEX_op_or_i64: | |
113 | case INDEX_op_orc_i32: | |
114 | case INDEX_op_orc_i64: | |
115 | case INDEX_op_xor_i32: | |
116 | case INDEX_op_xor_i64: | |
117 | case INDEX_op_shl_i32: | |
118 | case INDEX_op_shl_i64: | |
119 | case INDEX_op_shr_i32: | |
120 | case INDEX_op_shr_i64: | |
121 | case INDEX_op_sar_i32: | |
122 | case INDEX_op_sar_i64: | |
123 | case INDEX_op_rotl_i32: | |
124 | case INDEX_op_rotl_i64: | |
125 | case INDEX_op_rotr_i32: | |
126 | case INDEX_op_rotr_i64: | |
2f74f45e RH |
127 | case INDEX_op_setcond_i32: |
128 | case INDEX_op_setcond_i64: | |
63b29fda RH |
129 | case INDEX_op_deposit_i32: |
130 | case INDEX_op_deposit_i64: | |
79dd3a4f | 131 | return C_O1_I2(r, r, r); |
63b29fda RH |
132 | |
133 | case INDEX_op_brcond_i32: | |
134 | case INDEX_op_brcond_i64: | |
2f74f45e | 135 | return C_O0_I2(r, r); |
7316329a | 136 | |
63b29fda | 137 | #if TCG_TARGET_REG_BITS == 32 |
7316329a | 138 | /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */ |
63b29fda RH |
139 | case INDEX_op_add2_i32: |
140 | case INDEX_op_sub2_i32: | |
141 | return C_O2_I4(r, r, r, r, r, r); | |
142 | case INDEX_op_brcond2_i32: | |
2f74f45e | 143 | return C_O0_I4(r, r, r, r); |
63b29fda RH |
144 | case INDEX_op_mulu2_i32: |
145 | return C_O2_I2(r, r, r, r); | |
146 | case INDEX_op_setcond2_i32: | |
2f74f45e | 147 | return C_O1_I4(r, r, r, r, r); |
63b29fda | 148 | #endif |
f69d277e | 149 | |
63b29fda RH |
150 | case INDEX_op_qemu_ld_i32: |
151 | return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS | |
152 | ? C_O1_I1(r, r) | |
153 | : C_O1_I2(r, r, r)); | |
154 | case INDEX_op_qemu_ld_i64: | |
155 | return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) | |
156 | : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O2_I1(r, r, r) | |
157 | : C_O2_I2(r, r, r, r)); | |
158 | case INDEX_op_qemu_st_i32: | |
159 | return (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS | |
160 | ? C_O0_I2(r, r) | |
161 | : C_O0_I3(r, r, r)); | |
162 | case INDEX_op_qemu_st_i64: | |
163 | return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) | |
164 | : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? C_O0_I3(r, r, r) | |
165 | : C_O0_I4(r, r, r, r)); | |
166 | ||
167 | default: | |
168 | g_assert_not_reached(); | |
f69d277e | 169 | } |
f69d277e RH |
170 | } |
171 | ||
7316329a SW |
172 | static const int tcg_target_reg_alloc_order[] = { |
173 | TCG_REG_R0, | |
174 | TCG_REG_R1, | |
175 | TCG_REG_R2, | |
176 | TCG_REG_R3, | |
7316329a | 177 | TCG_REG_R4, |
7316329a SW |
178 | TCG_REG_R5, |
179 | TCG_REG_R6, | |
180 | TCG_REG_R7, | |
7316329a SW |
181 | TCG_REG_R8, |
182 | TCG_REG_R9, | |
183 | TCG_REG_R10, | |
184 | TCG_REG_R11, | |
185 | TCG_REG_R12, | |
186 | TCG_REG_R13, | |
187 | TCG_REG_R14, | |
188 | TCG_REG_R15, | |
7316329a SW |
189 | }; |
190 | ||
1df3caa9 | 191 | #if MAX_OPC_PARAM_IARGS != 6 |
7316329a SW |
192 | # error Fix needed, number of supported input arguments changed! |
193 | #endif | |
194 | ||
195 | static const int tcg_target_call_iarg_regs[] = { | |
196 | TCG_REG_R0, | |
197 | TCG_REG_R1, | |
198 | TCG_REG_R2, | |
199 | TCG_REG_R3, | |
7316329a | 200 | TCG_REG_R4, |
7316329a | 201 | TCG_REG_R5, |
6673f47d SW |
202 | #if TCG_TARGET_REG_BITS == 32 |
203 | /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */ | |
552672ba | 204 | TCG_REG_R6, |
7316329a | 205 | TCG_REG_R7, |
7316329a | 206 | TCG_REG_R8, |
6673f47d SW |
207 | TCG_REG_R9, |
208 | TCG_REG_R10, | |
1df3caa9 | 209 | TCG_REG_R11, |
7316329a SW |
210 | #endif |
211 | }; | |
212 | ||
213 | static const int tcg_target_call_oarg_regs[] = { | |
214 | TCG_REG_R0, | |
215 | #if TCG_TARGET_REG_BITS == 32 | |
216 | TCG_REG_R1 | |
217 | #endif | |
218 | }; | |
219 | ||
8d8fdbae | 220 | #ifdef CONFIG_DEBUG_TCG |
7316329a SW |
221 | static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
222 | "r00", | |
223 | "r01", | |
224 | "r02", | |
225 | "r03", | |
226 | "r04", | |
227 | "r05", | |
228 | "r06", | |
229 | "r07", | |
7316329a SW |
230 | "r08", |
231 | "r09", | |
232 | "r10", | |
233 | "r11", | |
234 | "r12", | |
235 | "r13", | |
236 | "r14", | |
237 | "r15", | |
7316329a SW |
238 | }; |
239 | #endif | |
240 | ||
6ac17786 | 241 | static bool patch_reloc(tcg_insn_unit *code_ptr, int type, |
2ba7fae2 | 242 | intptr_t value, intptr_t addend) |
7316329a SW |
243 | { |
244 | /* tcg_out_reloc always uses the same type, addend. */ | |
eabb7b91 AJ |
245 | tcg_debug_assert(type == sizeof(tcg_target_long)); |
246 | tcg_debug_assert(addend == 0); | |
247 | tcg_debug_assert(value != 0); | |
a7f96f76 RH |
248 | if (TCG_TARGET_REG_BITS == 32) { |
249 | tcg_patch32(code_ptr, value); | |
250 | } else { | |
251 | tcg_patch64(code_ptr, value); | |
252 | } | |
6ac17786 | 253 | return true; |
7316329a SW |
254 | } |
255 | ||
7316329a SW |
256 | /* Write value (native size). */ |
257 | static void tcg_out_i(TCGContext *s, tcg_target_ulong v) | |
258 | { | |
a7f96f76 RH |
259 | if (TCG_TARGET_REG_BITS == 32) { |
260 | tcg_out32(s, v); | |
261 | } else { | |
262 | tcg_out64(s, v); | |
263 | } | |
7316329a SW |
264 | } |
265 | ||
7316329a SW |
266 | /* Write opcode. */ |
267 | static void tcg_out_op_t(TCGContext *s, TCGOpcode op) | |
268 | { | |
269 | tcg_out8(s, op); | |
270 | tcg_out8(s, 0); | |
271 | } | |
272 | ||
273 | /* Write register. */ | |
274 | static void tcg_out_r(TCGContext *s, TCGArg t0) | |
275 | { | |
eabb7b91 | 276 | tcg_debug_assert(t0 < TCG_TARGET_NB_REGS); |
7316329a SW |
277 | tcg_out8(s, t0); |
278 | } | |
279 | ||
7316329a | 280 | /* Write label. */ |
bec16311 | 281 | static void tci_out_label(TCGContext *s, TCGLabel *label) |
7316329a | 282 | { |
7316329a SW |
283 | if (label->has_value) { |
284 | tcg_out_i(s, label->u.value); | |
eabb7b91 | 285 | tcg_debug_assert(label->u.value); |
7316329a | 286 | } else { |
bec16311 | 287 | tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0); |
3c01ae0e | 288 | s->code_ptr += sizeof(tcg_target_ulong); |
7316329a SW |
289 | } |
290 | } | |
291 | ||
53f40556 RH |
292 | static void stack_bounds_check(TCGReg base, target_long offset) |
293 | { | |
294 | if (base == TCG_REG_CALL_STACK) { | |
295 | tcg_debug_assert(offset < 0); | |
296 | tcg_debug_assert(offset >= -(CPU_TEMP_BUF_NLONGS * sizeof(long))); | |
297 | } | |
298 | } | |
299 | ||
b9dcd21a RH |
300 | static void tcg_out_op_l(TCGContext *s, TCGOpcode op, TCGLabel *l0) |
301 | { | |
302 | uint8_t *old_code_ptr = s->code_ptr; | |
303 | ||
304 | tcg_out_op_t(s, op); | |
305 | tci_out_label(s, l0); | |
306 | ||
307 | old_code_ptr[1] = s->code_ptr - old_code_ptr; | |
308 | } | |
309 | ||
7aa295c5 RH |
310 | static void tcg_out_op_p(TCGContext *s, TCGOpcode op, void *p0) |
311 | { | |
312 | uint8_t *old_code_ptr = s->code_ptr; | |
313 | ||
314 | tcg_out_op_t(s, op); | |
315 | tcg_out_i(s, (uintptr_t)p0); | |
316 | ||
317 | old_code_ptr[1] = s->code_ptr - old_code_ptr; | |
318 | } | |
319 | ||
ffe86eb0 RH |
320 | static void tcg_out_op_rr(TCGContext *s, TCGOpcode op, TCGReg r0, TCGReg r1) |
321 | { | |
322 | uint8_t *old_code_ptr = s->code_ptr; | |
323 | ||
324 | tcg_out_op_t(s, op); | |
325 | tcg_out_r(s, r0); | |
326 | tcg_out_r(s, r1); | |
327 | ||
328 | old_code_ptr[1] = s->code_ptr - old_code_ptr; | |
329 | } | |
330 | ||
549d0396 RH |
331 | static void tcg_out_op_rrr(TCGContext *s, TCGOpcode op, |
332 | TCGReg r0, TCGReg r1, TCGReg r2) | |
333 | { | |
334 | uint8_t *old_code_ptr = s->code_ptr; | |
335 | ||
336 | tcg_out_op_t(s, op); | |
337 | tcg_out_r(s, r0); | |
338 | tcg_out_r(s, r1); | |
339 | tcg_out_r(s, r2); | |
340 | ||
341 | old_code_ptr[1] = s->code_ptr - old_code_ptr; | |
342 | } | |
343 | ||
fe8c47cb RH |
344 | static void tcg_out_op_rrs(TCGContext *s, TCGOpcode op, |
345 | TCGReg r0, TCGReg r1, intptr_t i2) | |
7316329a SW |
346 | { |
347 | uint8_t *old_code_ptr = s->code_ptr; | |
53f40556 | 348 | |
fe8c47cb RH |
349 | tcg_out_op_t(s, op); |
350 | tcg_out_r(s, r0); | |
351 | tcg_out_r(s, r1); | |
352 | tcg_debug_assert(i2 == (int32_t)i2); | |
353 | tcg_out32(s, i2); | |
354 | ||
355 | old_code_ptr[1] = s->code_ptr - old_code_ptr; | |
356 | } | |
357 | ||
358 | static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg val, TCGReg base, | |
359 | intptr_t offset) | |
360 | { | |
361 | stack_bounds_check(base, offset); | |
362 | switch (type) { | |
363 | case TCG_TYPE_I32: | |
364 | tcg_out_op_rrs(s, INDEX_op_ld_i32, val, base, offset); | |
365 | break; | |
7316329a | 366 | #if TCG_TARGET_REG_BITS == 64 |
fe8c47cb RH |
367 | case TCG_TYPE_I64: |
368 | tcg_out_op_rrs(s, INDEX_op_ld_i64, val, base, offset); | |
369 | break; | |
7316329a | 370 | #endif |
fe8c47cb RH |
371 | default: |
372 | g_assert_not_reached(); | |
7316329a | 373 | } |
7316329a SW |
374 | } |
375 | ||
78113e83 | 376 | static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) |
7316329a | 377 | { |
ffe86eb0 RH |
378 | switch (type) { |
379 | case TCG_TYPE_I32: | |
380 | tcg_out_op_rr(s, INDEX_op_mov_i32, ret, arg); | |
381 | break; | |
382 | #if TCG_TARGET_REG_BITS == 64 | |
383 | case TCG_TYPE_I64: | |
384 | tcg_out_op_rr(s, INDEX_op_mov_i64, ret, arg); | |
385 | break; | |
7316329a | 386 | #endif |
ffe86eb0 RH |
387 | default: |
388 | g_assert_not_reached(); | |
389 | } | |
78113e83 | 390 | return true; |
7316329a SW |
391 | } |
392 | ||
393 | static void tcg_out_movi(TCGContext *s, TCGType type, | |
2a534aff | 394 | TCGReg t0, tcg_target_long arg) |
7316329a SW |
395 | { |
396 | uint8_t *old_code_ptr = s->code_ptr; | |
397 | uint32_t arg32 = arg; | |
398 | if (type == TCG_TYPE_I32 || arg == arg32) { | |
1bd1af98 | 399 | tcg_out_op_t(s, INDEX_op_tci_movi_i32); |
7316329a SW |
400 | tcg_out_r(s, t0); |
401 | tcg_out32(s, arg32); | |
402 | } else { | |
eabb7b91 | 403 | tcg_debug_assert(type == TCG_TYPE_I64); |
7316329a | 404 | #if TCG_TARGET_REG_BITS == 64 |
1bd1af98 | 405 | tcg_out_op_t(s, INDEX_op_tci_movi_i64); |
7316329a SW |
406 | tcg_out_r(s, t0); |
407 | tcg_out64(s, arg); | |
408 | #else | |
409 | TODO(); | |
410 | #endif | |
411 | } | |
412 | old_code_ptr[1] = s->code_ptr - old_code_ptr; | |
413 | } | |
414 | ||
2be7d76b | 415 | static inline void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) |
dddbb2e1 | 416 | { |
a3abb292 RH |
417 | uint8_t *old_code_ptr = s->code_ptr; |
418 | tcg_out_op_t(s, INDEX_op_call); | |
2f74f45e | 419 | tcg_out_i(s, (uintptr_t)arg); |
a3abb292 | 420 | old_code_ptr[1] = s->code_ptr - old_code_ptr; |
dddbb2e1 RH |
421 | } |
422 | ||
c764f8cc RH |
423 | #if TCG_TARGET_REG_BITS == 64 |
424 | # define CASE_32_64(x) \ | |
425 | case glue(glue(INDEX_op_, x), _i64): \ | |
426 | case glue(glue(INDEX_op_, x), _i32): | |
427 | # define CASE_64(x) \ | |
428 | case glue(glue(INDEX_op_, x), _i64): | |
429 | #else | |
430 | # define CASE_32_64(x) \ | |
431 | case glue(glue(INDEX_op_, x), _i32): | |
432 | # define CASE_64(x) | |
433 | #endif | |
434 | ||
7316329a SW |
435 | static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, |
436 | const int *const_args) | |
437 | { | |
438 | uint8_t *old_code_ptr = s->code_ptr; | |
439 | ||
7316329a SW |
440 | switch (opc) { |
441 | case INDEX_op_exit_tb: | |
7aa295c5 | 442 | tcg_out_op_p(s, opc, (void *)args[0]); |
7316329a | 443 | break; |
c764f8cc | 444 | |
7316329a | 445 | case INDEX_op_goto_tb: |
1670a2b9 RH |
446 | tcg_debug_assert(s->tb_jmp_insn_offset == 0); |
447 | /* indirect jump method. */ | |
7aa295c5 | 448 | tcg_out_op_p(s, opc, s->tb_jmp_target_addr + args[0]); |
9f754620 | 449 | set_jmp_reset_offset(s, args[0]); |
7316329a | 450 | break; |
88c3e909 | 451 | |
7316329a | 452 | case INDEX_op_br: |
b9dcd21a | 453 | tcg_out_op_l(s, opc, arg_label(args[0])); |
7316329a | 454 | break; |
88c3e909 RH |
455 | |
456 | CASE_32_64(setcond) | |
ae216c97 | 457 | tcg_out_op_t(s, opc); |
7316329a SW |
458 | tcg_out_r(s, args[0]); |
459 | tcg_out_r(s, args[1]); | |
2f74f45e | 460 | tcg_out_r(s, args[2]); |
7316329a | 461 | tcg_out8(s, args[3]); /* condition */ |
ae216c97 | 462 | old_code_ptr[1] = s->code_ptr - old_code_ptr; |
7316329a | 463 | break; |
88c3e909 | 464 | |
7316329a SW |
465 | #if TCG_TARGET_REG_BITS == 32 |
466 | case INDEX_op_setcond2_i32: | |
467 | /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */ | |
ae216c97 | 468 | tcg_out_op_t(s, opc); |
7316329a SW |
469 | tcg_out_r(s, args[0]); |
470 | tcg_out_r(s, args[1]); | |
471 | tcg_out_r(s, args[2]); | |
2f74f45e RH |
472 | tcg_out_r(s, args[3]); |
473 | tcg_out_r(s, args[4]); | |
7316329a | 474 | tcg_out8(s, args[5]); /* condition */ |
ae216c97 | 475 | old_code_ptr[1] = s->code_ptr - old_code_ptr; |
7316329a | 476 | break; |
7316329a | 477 | #endif |
a73605a7 RH |
478 | |
479 | CASE_32_64(ld8u) | |
480 | CASE_32_64(ld8s) | |
481 | CASE_32_64(ld16u) | |
482 | CASE_32_64(ld16s) | |
7316329a | 483 | case INDEX_op_ld_i32: |
a73605a7 RH |
484 | CASE_64(ld32u) |
485 | CASE_64(ld32s) | |
486 | CASE_64(ld) | |
487 | CASE_32_64(st8) | |
488 | CASE_32_64(st16) | |
7316329a | 489 | case INDEX_op_st_i32: |
a73605a7 RH |
490 | CASE_64(st32) |
491 | CASE_64(st) | |
53f40556 | 492 | stack_bounds_check(args[1], args[2]); |
fe8c47cb | 493 | tcg_out_op_rrs(s, opc, args[0], args[1], args[2]); |
7316329a | 494 | break; |
c764f8cc RH |
495 | |
496 | CASE_32_64(add) | |
497 | CASE_32_64(sub) | |
498 | CASE_32_64(mul) | |
499 | CASE_32_64(and) | |
500 | CASE_32_64(or) | |
501 | CASE_32_64(xor) | |
502 | CASE_32_64(andc) /* Optional (TCG_TARGET_HAS_andc_*). */ | |
503 | CASE_32_64(orc) /* Optional (TCG_TARGET_HAS_orc_*). */ | |
504 | CASE_32_64(eqv) /* Optional (TCG_TARGET_HAS_eqv_*). */ | |
505 | CASE_32_64(nand) /* Optional (TCG_TARGET_HAS_nand_*). */ | |
506 | CASE_32_64(nor) /* Optional (TCG_TARGET_HAS_nor_*). */ | |
507 | CASE_32_64(shl) | |
508 | CASE_32_64(shr) | |
509 | CASE_32_64(sar) | |
510 | CASE_32_64(rotl) /* Optional (TCG_TARGET_HAS_rot_*). */ | |
511 | CASE_32_64(rotr) /* Optional (TCG_TARGET_HAS_rot_*). */ | |
512 | CASE_32_64(div) /* Optional (TCG_TARGET_HAS_div_*). */ | |
513 | CASE_32_64(divu) /* Optional (TCG_TARGET_HAS_div_*). */ | |
514 | CASE_32_64(rem) /* Optional (TCG_TARGET_HAS_div_*). */ | |
515 | CASE_32_64(remu) /* Optional (TCG_TARGET_HAS_div_*). */ | |
549d0396 | 516 | tcg_out_op_rrr(s, opc, args[0], args[1], args[2]); |
7316329a | 517 | break; |
da9a5e0b RH |
518 | |
519 | CASE_32_64(deposit) /* Optional (TCG_TARGET_HAS_deposit_*). */ | |
ae216c97 | 520 | tcg_out_op_t(s, opc); |
79dd3a4f RH |
521 | { |
522 | TCGArg pos = args[3], len = args[4]; | |
523 | TCGArg max = opc == INDEX_op_deposit_i32 ? 32 : 64; | |
524 | ||
525 | tcg_debug_assert(pos < max); | |
526 | tcg_debug_assert(pos + len <= max); | |
527 | ||
528 | tcg_out_r(s, args[0]); | |
529 | tcg_out_r(s, args[1]); | |
530 | tcg_out_r(s, args[2]); | |
531 | tcg_out8(s, pos); | |
532 | tcg_out8(s, len); | |
533 | } | |
ae216c97 | 534 | old_code_ptr[1] = s->code_ptr - old_code_ptr; |
e24dc9fe | 535 | break; |
7316329a | 536 | |
88c3e909 | 537 | CASE_32_64(brcond) |
ae216c97 | 538 | tcg_out_op_t(s, opc); |
7316329a | 539 | tcg_out_r(s, args[0]); |
2f74f45e | 540 | tcg_out_r(s, args[1]); |
7316329a | 541 | tcg_out8(s, args[2]); /* condition */ |
bec16311 | 542 | tci_out_label(s, arg_label(args[3])); |
ae216c97 | 543 | old_code_ptr[1] = s->code_ptr - old_code_ptr; |
7316329a | 544 | break; |
1e9ac766 RH |
545 | |
546 | CASE_32_64(neg) /* Optional (TCG_TARGET_HAS_neg_*). */ | |
547 | CASE_32_64(not) /* Optional (TCG_TARGET_HAS_not_*). */ | |
548 | CASE_32_64(ext8s) /* Optional (TCG_TARGET_HAS_ext8s_*). */ | |
549 | CASE_32_64(ext8u) /* Optional (TCG_TARGET_HAS_ext8u_*). */ | |
550 | CASE_32_64(ext16s) /* Optional (TCG_TARGET_HAS_ext16s_*). */ | |
551 | CASE_32_64(ext16u) /* Optional (TCG_TARGET_HAS_ext16u_*). */ | |
552 | CASE_64(ext32s) /* Optional (TCG_TARGET_HAS_ext32s_i64). */ | |
553 | CASE_64(ext32u) /* Optional (TCG_TARGET_HAS_ext32u_i64). */ | |
554 | CASE_64(ext_i32) | |
555 | CASE_64(extu_i32) | |
556 | CASE_32_64(bswap16) /* Optional (TCG_TARGET_HAS_bswap16_*). */ | |
557 | CASE_32_64(bswap32) /* Optional (TCG_TARGET_HAS_bswap32_*). */ | |
558 | CASE_64(bswap64) /* Optional (TCG_TARGET_HAS_bswap64_i64). */ | |
ffe86eb0 | 559 | tcg_out_op_rr(s, opc, args[0], args[1]); |
7316329a | 560 | break; |
c764f8cc | 561 | |
7316329a SW |
562 | #if TCG_TARGET_REG_BITS == 32 |
563 | case INDEX_op_add2_i32: | |
564 | case INDEX_op_sub2_i32: | |
ae216c97 | 565 | tcg_out_op_t(s, opc); |
7316329a SW |
566 | tcg_out_r(s, args[0]); |
567 | tcg_out_r(s, args[1]); | |
568 | tcg_out_r(s, args[2]); | |
569 | tcg_out_r(s, args[3]); | |
570 | tcg_out_r(s, args[4]); | |
571 | tcg_out_r(s, args[5]); | |
ae216c97 | 572 | old_code_ptr[1] = s->code_ptr - old_code_ptr; |
7316329a SW |
573 | break; |
574 | case INDEX_op_brcond2_i32: | |
ae216c97 | 575 | tcg_out_op_t(s, opc); |
7316329a SW |
576 | tcg_out_r(s, args[0]); |
577 | tcg_out_r(s, args[1]); | |
2f74f45e RH |
578 | tcg_out_r(s, args[2]); |
579 | tcg_out_r(s, args[3]); | |
7316329a | 580 | tcg_out8(s, args[4]); /* condition */ |
bec16311 | 581 | tci_out_label(s, arg_label(args[5])); |
ae216c97 | 582 | old_code_ptr[1] = s->code_ptr - old_code_ptr; |
7316329a SW |
583 | break; |
584 | case INDEX_op_mulu2_i32: | |
ae216c97 | 585 | tcg_out_op_t(s, opc); |
7316329a SW |
586 | tcg_out_r(s, args[0]); |
587 | tcg_out_r(s, args[1]); | |
588 | tcg_out_r(s, args[2]); | |
589 | tcg_out_r(s, args[3]); | |
ae216c97 | 590 | old_code_ptr[1] = s->code_ptr - old_code_ptr; |
7316329a SW |
591 | break; |
592 | #endif | |
88c3e909 | 593 | |
76782fab | 594 | case INDEX_op_qemu_ld_i32: |
76782fab | 595 | case INDEX_op_qemu_st_i32: |
ae216c97 | 596 | tcg_out_op_t(s, opc); |
7316329a SW |
597 | tcg_out_r(s, *args++); |
598 | tcg_out_r(s, *args++); | |
76782fab RH |
599 | if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { |
600 | tcg_out_r(s, *args++); | |
601 | } | |
00e338fa | 602 | tcg_out32(s, *args++); |
ae216c97 | 603 | old_code_ptr[1] = s->code_ptr - old_code_ptr; |
7316329a | 604 | break; |
a73605a7 RH |
605 | |
606 | case INDEX_op_qemu_ld_i64: | |
76782fab | 607 | case INDEX_op_qemu_st_i64: |
ae216c97 | 608 | tcg_out_op_t(s, opc); |
7316329a | 609 | tcg_out_r(s, *args++); |
76782fab RH |
610 | if (TCG_TARGET_REG_BITS == 32) { |
611 | tcg_out_r(s, *args++); | |
612 | } | |
7316329a | 613 | tcg_out_r(s, *args++); |
76782fab RH |
614 | if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { |
615 | tcg_out_r(s, *args++); | |
616 | } | |
00e338fa | 617 | tcg_out32(s, *args++); |
ae216c97 | 618 | old_code_ptr[1] = s->code_ptr - old_code_ptr; |
7316329a | 619 | break; |
c764f8cc | 620 | |
a1e69e2f | 621 | case INDEX_op_mb: |
ae216c97 RH |
622 | tcg_out_op_t(s, opc); |
623 | old_code_ptr[1] = s->code_ptr - old_code_ptr; | |
a1e69e2f | 624 | break; |
c764f8cc | 625 | |
96d0ee7f RH |
626 | case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ |
627 | case INDEX_op_mov_i64: | |
96d0ee7f | 628 | case INDEX_op_call: /* Always emitted via tcg_out_call. */ |
7316329a | 629 | default: |
7316329a SW |
630 | tcg_abort(); |
631 | } | |
7316329a SW |
632 | } |
633 | ||
fe8c47cb RH |
634 | static void tcg_out_st(TCGContext *s, TCGType type, TCGReg val, TCGReg base, |
635 | intptr_t offset) | |
7316329a | 636 | { |
fe8c47cb RH |
637 | stack_bounds_check(base, offset); |
638 | switch (type) { | |
639 | case TCG_TYPE_I32: | |
640 | tcg_out_op_rrs(s, INDEX_op_st_i32, val, base, offset); | |
641 | break; | |
7316329a | 642 | #if TCG_TARGET_REG_BITS == 64 |
fe8c47cb RH |
643 | case TCG_TYPE_I64: |
644 | tcg_out_op_rrs(s, INDEX_op_st_i64, val, base, offset); | |
645 | break; | |
7316329a | 646 | #endif |
fe8c47cb RH |
647 | default: |
648 | g_assert_not_reached(); | |
7316329a | 649 | } |
7316329a SW |
650 | } |
651 | ||
59d7c14e RH |
652 | static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, |
653 | TCGReg base, intptr_t ofs) | |
654 | { | |
655 | return false; | |
656 | } | |
657 | ||
7316329a | 658 | /* Test if a constant matches the constraint. */ |
f6c6afc1 | 659 | static int tcg_target_const_match(tcg_target_long val, TCGType type, |
7316329a SW |
660 | const TCGArgConstraint *arg_ct) |
661 | { | |
662 | /* No need to return 0 or 1, 0 or != 0 is good enough. */ | |
663 | return arg_ct->ct & TCG_CT_CONST; | |
664 | } | |
665 | ||
7316329a SW |
666 | static void tcg_target_init(TCGContext *s) |
667 | { | |
668 | #if defined(CONFIG_DEBUG_TCG_INTERPRETER) | |
669 | const char *envval = getenv("DEBUG_TCG"); | |
670 | if (envval) { | |
24537a01 | 671 | qemu_set_log(strtol(envval, NULL, 0)); |
7316329a SW |
672 | } |
673 | #endif | |
674 | ||
675 | /* The current code uses uint8_t for tcg operations. */ | |
eabb7b91 | 676 | tcg_debug_assert(tcg_op_defs_max <= UINT8_MAX); |
7316329a SW |
677 | |
678 | /* Registers available for 32 bit operations. */ | |
f46934df | 679 | tcg_target_available_regs[TCG_TYPE_I32] = BIT(TCG_TARGET_NB_REGS) - 1; |
7316329a | 680 | /* Registers available for 64 bit operations. */ |
f46934df | 681 | tcg_target_available_regs[TCG_TYPE_I64] = BIT(TCG_TARGET_NB_REGS) - 1; |
7316329a | 682 | /* TODO: Which registers should be set here? */ |
f46934df | 683 | tcg_target_call_clobber_regs = BIT(TCG_TARGET_NB_REGS) - 1; |
ee79c356 | 684 | |
ccb1bb66 | 685 | s->reserved_regs = 0; |
7316329a | 686 | tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); |
ee79c356 RH |
687 | |
688 | /* We use negative offsets from "sp" so that we can distinguish | |
689 | stores that might pretend to be call arguments. */ | |
690 | tcg_set_frame(s, TCG_REG_CALL_STACK, | |
691 | -CPU_TEMP_BUF_NLONGS * sizeof(long), | |
7316329a SW |
692 | CPU_TEMP_BUF_NLONGS * sizeof(long)); |
693 | } | |
694 | ||
695 | /* Generate global QEMU prologue and epilogue code. */ | |
4699ca6d | 696 | static inline void tcg_target_qemu_prologue(TCGContext *s) |
7316329a | 697 | { |
7316329a | 698 | } |