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Commit | Line | Data |
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7657f4bf SW |
1 | /* |
2 | * Tiny Code Interpreter for QEMU | |
3 | * | |
3ccdbecf | 4 | * Copyright (c) 2009, 2011, 2016 Stefan Weil |
7657f4bf SW |
5 | * |
6 | * This program is free software: you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation, either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
d38ea87a | 20 | #include "qemu/osdep.h" |
ad3d0e4d | 21 | #include "tcg/tcg.h" |
d2ba8026 | 22 | #include "tcg/tcg-ldst.h" |
7b7d8b2d | 23 | #include <ffi.h> |
7657f4bf | 24 | |
7b7d8b2d RH |
25 | |
26 | /* | |
27 | * Enable TCI assertions only when debugging TCG (and without NDEBUG defined). | |
28 | * Without assertions, the interpreter runs much faster. | |
29 | */ | |
30 | #if defined(CONFIG_DEBUG_TCG) | |
31 | # define tci_assert(cond) assert(cond) | |
7657f4bf | 32 | #else |
7b7d8b2d | 33 | # define tci_assert(cond) ((void)(cond)) |
7657f4bf SW |
34 | #endif |
35 | ||
13e71f08 RH |
36 | __thread uintptr_t tci_tb_ptr; |
37 | ||
5e75150c EC |
38 | static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, |
39 | uint32_t low_index, uint64_t value) | |
7657f4bf | 40 | { |
f6db0d8d | 41 | regs[low_index] = (uint32_t)value; |
7e00a080 | 42 | regs[high_index] = value >> 32; |
7657f4bf | 43 | } |
7657f4bf | 44 | |
7657f4bf SW |
45 | /* Create a 64 bit value from two 32 bit values. */ |
46 | static uint64_t tci_uint64(uint32_t high, uint32_t low) | |
47 | { | |
48 | return ((uint64_t)high << 32) + low; | |
49 | } | |
7657f4bf | 50 | |
cdd9799b RH |
51 | /* |
52 | * Load sets of arguments all at once. The naming convention is: | |
53 | * tci_args_<arguments> | |
54 | * where arguments is a sequence of | |
55 | * | |
79dd3a4f | 56 | * b = immediate (bit position) |
963e9fa2 | 57 | * c = condition (TCGCond) |
b95aa12e RH |
58 | * i = immediate (uint32_t) |
59 | * I = immediate (tcg_target_ulong) | |
f28ca03e | 60 | * l = label or pointer |
9002ffcb | 61 | * m = immediate (MemOpIdx) |
7b7d8b2d | 62 | * n = immediate (call return length) |
cdd9799b RH |
63 | * r = register |
64 | * s = signed ldst offset | |
65 | */ | |
66 | ||
65089889 | 67 | static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0) |
92bc4fad | 68 | { |
65089889 RH |
69 | int diff = sextract32(insn, 12, 20); |
70 | *l0 = diff ? (void *)tb_ptr + diff : NULL; | |
92bc4fad RH |
71 | } |
72 | ||
6eea0434 RH |
73 | static void tci_args_r(uint32_t insn, TCGReg *r0) |
74 | { | |
75 | *r0 = extract32(insn, 8, 4); | |
76 | } | |
77 | ||
65089889 RH |
78 | static void tci_args_nl(uint32_t insn, const void *tb_ptr, |
79 | uint8_t *n0, void **l1) | |
f28ca03e | 80 | { |
65089889 RH |
81 | *n0 = extract32(insn, 8, 4); |
82 | *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr; | |
f28ca03e RH |
83 | } |
84 | ||
65089889 RH |
85 | static void tci_args_rl(uint32_t insn, const void *tb_ptr, |
86 | TCGReg *r0, void **l1) | |
7b7d8b2d | 87 | { |
65089889 RH |
88 | *r0 = extract32(insn, 8, 4); |
89 | *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr; | |
7b7d8b2d RH |
90 | } |
91 | ||
65089889 | 92 | static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1) |
fc8ec9e1 | 93 | { |
65089889 RH |
94 | *r0 = extract32(insn, 8, 4); |
95 | *r1 = extract32(insn, 12, 4); | |
fc8ec9e1 RH |
96 | } |
97 | ||
65089889 | 98 | static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1) |
fc4a62f6 | 99 | { |
65089889 RH |
100 | *r0 = extract32(insn, 8, 4); |
101 | *i1 = sextract32(insn, 12, 20); | |
fc4a62f6 RH |
102 | } |
103 | ||
65089889 | 104 | static void tci_args_rrm(uint32_t insn, TCGReg *r0, |
9002ffcb | 105 | TCGReg *r1, MemOpIdx *m2) |
b95aa12e | 106 | { |
65089889 RH |
107 | *r0 = extract32(insn, 8, 4); |
108 | *r1 = extract32(insn, 12, 4); | |
ab64da79 | 109 | *m2 = extract32(insn, 16, 16); |
b95aa12e RH |
110 | } |
111 | ||
65089889 | 112 | static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2) |
b95aa12e | 113 | { |
65089889 RH |
114 | *r0 = extract32(insn, 8, 4); |
115 | *r1 = extract32(insn, 12, 4); | |
116 | *r2 = extract32(insn, 16, 4); | |
b95aa12e | 117 | } |
b95aa12e | 118 | |
65089889 | 119 | static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2) |
63041ed2 | 120 | { |
65089889 RH |
121 | *r0 = extract32(insn, 8, 4); |
122 | *r1 = extract32(insn, 12, 4); | |
123 | *i2 = sextract32(insn, 16, 16); | |
63041ed2 RH |
124 | } |
125 | ||
0f10d7c5 RH |
126 | static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, |
127 | uint8_t *i2, uint8_t *i3) | |
128 | { | |
129 | *r0 = extract32(insn, 8, 4); | |
130 | *r1 = extract32(insn, 12, 4); | |
131 | *i2 = extract32(insn, 16, 6); | |
132 | *i3 = extract32(insn, 22, 6); | |
133 | } | |
134 | ||
65089889 | 135 | static void tci_args_rrrc(uint32_t insn, |
963e9fa2 RH |
136 | TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) |
137 | { | |
65089889 RH |
138 | *r0 = extract32(insn, 8, 4); |
139 | *r1 = extract32(insn, 12, 4); | |
140 | *r2 = extract32(insn, 16, 4); | |
141 | *c3 = extract32(insn, 20, 4); | |
963e9fa2 RH |
142 | } |
143 | ||
65089889 | 144 | static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, |
79dd3a4f RH |
145 | TCGReg *r2, uint8_t *i3, uint8_t *i4) |
146 | { | |
65089889 RH |
147 | *r0 = extract32(insn, 8, 4); |
148 | *r1 = extract32(insn, 12, 4); | |
149 | *r2 = extract32(insn, 16, 4); | |
150 | *i3 = extract32(insn, 20, 6); | |
151 | *i4 = extract32(insn, 26, 6); | |
79dd3a4f RH |
152 | } |
153 | ||
65089889 RH |
154 | static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, |
155 | TCGReg *r2, TCGReg *r3, TCGReg *r4) | |
63041ed2 | 156 | { |
65089889 RH |
157 | *r0 = extract32(insn, 8, 4); |
158 | *r1 = extract32(insn, 12, 4); | |
159 | *r2 = extract32(insn, 16, 4); | |
160 | *r3 = extract32(insn, 20, 4); | |
161 | *r4 = extract32(insn, 24, 4); | |
63041ed2 RH |
162 | } |
163 | ||
65089889 | 164 | static void tci_args_rrrr(uint32_t insn, |
cbe87131 RH |
165 | TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) |
166 | { | |
65089889 RH |
167 | *r0 = extract32(insn, 8, 4); |
168 | *r1 = extract32(insn, 12, 4); | |
169 | *r2 = extract32(insn, 16, 4); | |
170 | *r3 = extract32(insn, 20, 4); | |
cbe87131 RH |
171 | } |
172 | ||
65089889 | 173 | static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, |
817cadd6 RH |
174 | TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5) |
175 | { | |
65089889 RH |
176 | *r0 = extract32(insn, 8, 4); |
177 | *r1 = extract32(insn, 12, 4); | |
178 | *r2 = extract32(insn, 16, 4); | |
179 | *r3 = extract32(insn, 20, 4); | |
180 | *r4 = extract32(insn, 24, 4); | |
181 | *c5 = extract32(insn, 28, 4); | |
817cadd6 | 182 | } |
120402b5 | 183 | |
65089889 | 184 | static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, |
120402b5 RH |
185 | TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) |
186 | { | |
65089889 RH |
187 | *r0 = extract32(insn, 8, 4); |
188 | *r1 = extract32(insn, 12, 4); | |
189 | *r2 = extract32(insn, 16, 4); | |
190 | *r3 = extract32(insn, 20, 4); | |
191 | *r4 = extract32(insn, 24, 4); | |
192 | *r5 = extract32(insn, 28, 4); | |
120402b5 | 193 | } |
817cadd6 | 194 | |
7657f4bf SW |
195 | static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) |
196 | { | |
197 | bool result = false; | |
198 | int32_t i0 = u0; | |
199 | int32_t i1 = u1; | |
200 | switch (condition) { | |
201 | case TCG_COND_EQ: | |
202 | result = (u0 == u1); | |
203 | break; | |
204 | case TCG_COND_NE: | |
205 | result = (u0 != u1); | |
206 | break; | |
207 | case TCG_COND_LT: | |
208 | result = (i0 < i1); | |
209 | break; | |
210 | case TCG_COND_GE: | |
211 | result = (i0 >= i1); | |
212 | break; | |
213 | case TCG_COND_LE: | |
214 | result = (i0 <= i1); | |
215 | break; | |
216 | case TCG_COND_GT: | |
217 | result = (i0 > i1); | |
218 | break; | |
219 | case TCG_COND_LTU: | |
220 | result = (u0 < u1); | |
221 | break; | |
222 | case TCG_COND_GEU: | |
223 | result = (u0 >= u1); | |
224 | break; | |
225 | case TCG_COND_LEU: | |
226 | result = (u0 <= u1); | |
227 | break; | |
228 | case TCG_COND_GTU: | |
229 | result = (u0 > u1); | |
230 | break; | |
23c5692a RH |
231 | case TCG_COND_TSTEQ: |
232 | result = (u0 & u1) == 0; | |
233 | break; | |
234 | case TCG_COND_TSTNE: | |
235 | result = (u0 & u1) != 0; | |
236 | break; | |
7657f4bf | 237 | default: |
f6996f99 | 238 | g_assert_not_reached(); |
7657f4bf SW |
239 | } |
240 | return result; | |
241 | } | |
242 | ||
243 | static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) | |
244 | { | |
245 | bool result = false; | |
246 | int64_t i0 = u0; | |
247 | int64_t i1 = u1; | |
248 | switch (condition) { | |
249 | case TCG_COND_EQ: | |
250 | result = (u0 == u1); | |
251 | break; | |
252 | case TCG_COND_NE: | |
253 | result = (u0 != u1); | |
254 | break; | |
255 | case TCG_COND_LT: | |
256 | result = (i0 < i1); | |
257 | break; | |
258 | case TCG_COND_GE: | |
259 | result = (i0 >= i1); | |
260 | break; | |
261 | case TCG_COND_LE: | |
262 | result = (i0 <= i1); | |
263 | break; | |
264 | case TCG_COND_GT: | |
265 | result = (i0 > i1); | |
266 | break; | |
267 | case TCG_COND_LTU: | |
268 | result = (u0 < u1); | |
269 | break; | |
270 | case TCG_COND_GEU: | |
271 | result = (u0 >= u1); | |
272 | break; | |
273 | case TCG_COND_LEU: | |
274 | result = (u0 <= u1); | |
275 | break; | |
276 | case TCG_COND_GTU: | |
277 | result = (u0 > u1); | |
278 | break; | |
23c5692a RH |
279 | case TCG_COND_TSTEQ: |
280 | result = (u0 & u1) == 0; | |
281 | break; | |
282 | case TCG_COND_TSTNE: | |
283 | result = (u0 & u1) != 0; | |
284 | break; | |
7657f4bf | 285 | default: |
f6996f99 | 286 | g_assert_not_reached(); |
7657f4bf SW |
287 | } |
288 | return result; | |
289 | } | |
290 | ||
dd7dc93e | 291 | static uint64_t tci_qemu_ld(CPUArchState *env, uint64_t taddr, |
9002ffcb | 292 | MemOpIdx oi, const void *tb_ptr) |
69acc02a | 293 | { |
fe1bee3a | 294 | MemOp mop = get_memop(oi); |
d1b1348c RH |
295 | uintptr_t ra = (uintptr_t)tb_ptr; |
296 | ||
0cadc1ed | 297 | switch (mop & MO_SSIZE) { |
d1b1348c | 298 | case MO_UB: |
0cadc1ed | 299 | return helper_ldub_mmu(env, taddr, oi, ra); |
d1b1348c | 300 | case MO_SB: |
0cadc1ed RH |
301 | return helper_ldsb_mmu(env, taddr, oi, ra); |
302 | case MO_UW: | |
303 | return helper_lduw_mmu(env, taddr, oi, ra); | |
304 | case MO_SW: | |
305 | return helper_ldsw_mmu(env, taddr, oi, ra); | |
306 | case MO_UL: | |
307 | return helper_ldul_mmu(env, taddr, oi, ra); | |
308 | case MO_SL: | |
309 | return helper_ldsl_mmu(env, taddr, oi, ra); | |
310 | case MO_UQ: | |
311 | return helper_ldq_mmu(env, taddr, oi, ra); | |
d1b1348c RH |
312 | default: |
313 | g_assert_not_reached(); | |
314 | } | |
69acc02a RH |
315 | } |
316 | ||
dd7dc93e | 317 | static void tci_qemu_st(CPUArchState *env, uint64_t taddr, uint64_t val, |
9002ffcb | 318 | MemOpIdx oi, const void *tb_ptr) |
69acc02a | 319 | { |
fe1bee3a | 320 | MemOp mop = get_memop(oi); |
d1b1348c RH |
321 | uintptr_t ra = (uintptr_t)tb_ptr; |
322 | ||
0cadc1ed | 323 | switch (mop & MO_SIZE) { |
d1b1348c | 324 | case MO_UB: |
0cadc1ed | 325 | helper_stb_mmu(env, taddr, val, oi, ra); |
d1b1348c | 326 | break; |
0cadc1ed RH |
327 | case MO_UW: |
328 | helper_stw_mmu(env, taddr, val, oi, ra); | |
d1b1348c | 329 | break; |
0cadc1ed RH |
330 | case MO_UL: |
331 | helper_stl_mmu(env, taddr, val, oi, ra); | |
d1b1348c | 332 | break; |
0cadc1ed RH |
333 | case MO_UQ: |
334 | helper_stq_mmu(env, taddr, val, oi, ra); | |
d1b1348c RH |
335 | break; |
336 | default: | |
337 | g_assert_not_reached(); | |
338 | } | |
69acc02a RH |
339 | } |
340 | ||
7f33f5cd RH |
341 | #if TCG_TARGET_REG_BITS == 64 |
342 | # define CASE_32_64(x) \ | |
343 | case glue(glue(INDEX_op_, x), _i64): \ | |
344 | case glue(glue(INDEX_op_, x), _i32): | |
345 | # define CASE_64(x) \ | |
346 | case glue(glue(INDEX_op_, x), _i64): | |
347 | #else | |
348 | # define CASE_32_64(x) \ | |
349 | case glue(glue(INDEX_op_, x), _i32): | |
350 | # define CASE_64(x) | |
351 | #endif | |
352 | ||
7657f4bf | 353 | /* Interpret pseudo code in tb. */ |
c905a368 DB |
354 | /* |
355 | * Disable CFI checks. | |
356 | * One possible operation in the pseudo code is a call to binary code. | |
357 | * Therefore, disable CFI checks in the interpreter function | |
358 | */ | |
db0c51a3 RH |
359 | uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, |
360 | const void *v_tb_ptr) | |
7657f4bf | 361 | { |
65089889 | 362 | const uint32_t *tb_ptr = v_tb_ptr; |
5e75150c | 363 | tcg_target_ulong regs[TCG_TARGET_NB_REGS]; |
7b7d8b2d RH |
364 | uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) |
365 | / sizeof(uint64_t)]; | |
7657f4bf | 366 | |
5e75150c | 367 | regs[TCG_AREG0] = (tcg_target_ulong)env; |
7b7d8b2d | 368 | regs[TCG_REG_CALL_STACK] = (uintptr_t)stack; |
3ccdbecf | 369 | tci_assert(tb_ptr); |
7657f4bf SW |
370 | |
371 | for (;;) { | |
65089889 RH |
372 | uint32_t insn; |
373 | TCGOpcode opc; | |
08096b1a | 374 | TCGReg r0, r1, r2, r3, r4, r5; |
7657f4bf | 375 | tcg_target_ulong t1; |
7657f4bf | 376 | TCGCond condition; |
79dd3a4f | 377 | uint8_t pos, len; |
7657f4bf | 378 | uint32_t tmp32; |
dd7dc93e | 379 | uint64_t tmp64, taddr; |
5a0adf34 | 380 | uint64_t T1, T2; |
9002ffcb | 381 | MemOpIdx oi; |
cdd9799b | 382 | int32_t ofs; |
65089889 | 383 | void *ptr; |
7657f4bf | 384 | |
65089889 RH |
385 | insn = *tb_ptr++; |
386 | opc = extract32(insn, 0, 8); | |
7657f4bf SW |
387 | |
388 | switch (opc) { | |
7657f4bf | 389 | case INDEX_op_call: |
e9709e17 RH |
390 | { |
391 | void *call_slots[MAX_CALL_IARGS]; | |
392 | ffi_cif *cif; | |
393 | void *func; | |
394 | unsigned i, s, n; | |
395 | ||
396 | tci_args_nl(insn, tb_ptr, &len, &ptr); | |
397 | func = ((void **)ptr)[0]; | |
398 | cif = ((void **)ptr)[1]; | |
399 | ||
400 | n = cif->nargs; | |
401 | for (i = s = 0; i < n; ++i) { | |
402 | ffi_type *t = cif->arg_types[i]; | |
403 | call_slots[i] = &stack[s]; | |
404 | s += DIV_ROUND_UP(t->size, 8); | |
7b7d8b2d | 405 | } |
7b7d8b2d | 406 | |
e9709e17 RH |
407 | /* Helper functions may need to access the "return address" */ |
408 | tci_tb_ptr = (uintptr_t)tb_ptr; | |
409 | ffi_call(cif, func, stack, call_slots); | |
65089889 | 410 | } |
7b7d8b2d | 411 | |
7b7d8b2d RH |
412 | switch (len) { |
413 | case 0: /* void */ | |
414 | break; | |
415 | case 1: /* uint32_t */ | |
416 | /* | |
896c76e6 | 417 | * The result winds up "left-aligned" in the stack[0] slot. |
7b7d8b2d RH |
418 | * Note that libffi has an odd special case in that it will |
419 | * always widen an integral result to ffi_arg. | |
420 | */ | |
896c76e6 RH |
421 | if (sizeof(ffi_arg) == 8) { |
422 | regs[TCG_REG_R0] = (uint32_t)stack[0]; | |
423 | } else { | |
7b7d8b2d | 424 | regs[TCG_REG_R0] = *(uint32_t *)stack; |
7b7d8b2d | 425 | } |
896c76e6 | 426 | break; |
7b7d8b2d | 427 | case 2: /* uint64_t */ |
896c76e6 RH |
428 | /* |
429 | * For TCG_TARGET_REG_BITS == 32, the register pair | |
430 | * must stay in host memory order. | |
431 | */ | |
432 | memcpy(®s[TCG_REG_R0], stack, 8); | |
7b7d8b2d | 433 | break; |
e9709e17 RH |
434 | case 3: /* Int128 */ |
435 | memcpy(®s[TCG_REG_R0], stack, 16); | |
436 | break; | |
7b7d8b2d RH |
437 | default: |
438 | g_assert_not_reached(); | |
439 | } | |
7657f4bf | 440 | break; |
7b7d8b2d | 441 | |
7657f4bf | 442 | case INDEX_op_br: |
65089889 | 443 | tci_args_l(insn, tb_ptr, &ptr); |
f28ca03e | 444 | tb_ptr = ptr; |
7657f4bf SW |
445 | continue; |
446 | case INDEX_op_setcond_i32: | |
65089889 | 447 | tci_args_rrrc(insn, &r0, &r1, &r2, &condition); |
963e9fa2 | 448 | regs[r0] = tci_compare32(regs[r1], regs[r2], condition); |
7657f4bf | 449 | break; |
df093c19 RH |
450 | case INDEX_op_movcond_i32: |
451 | tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); | |
452 | tmp32 = tci_compare32(regs[r1], regs[r2], condition); | |
453 | regs[r0] = regs[tmp32 ? r3 : r4]; | |
454 | break; | |
7657f4bf SW |
455 | #if TCG_TARGET_REG_BITS == 32 |
456 | case INDEX_op_setcond2_i32: | |
65089889 | 457 | tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); |
817cadd6 RH |
458 | T1 = tci_uint64(regs[r2], regs[r1]); |
459 | T2 = tci_uint64(regs[r4], regs[r3]); | |
460 | regs[r0] = tci_compare64(T1, T2, condition); | |
7657f4bf SW |
461 | break; |
462 | #elif TCG_TARGET_REG_BITS == 64 | |
463 | case INDEX_op_setcond_i64: | |
65089889 | 464 | tci_args_rrrc(insn, &r0, &r1, &r2, &condition); |
963e9fa2 | 465 | regs[r0] = tci_compare64(regs[r1], regs[r2], condition); |
7657f4bf | 466 | break; |
df093c19 RH |
467 | case INDEX_op_movcond_i64: |
468 | tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); | |
469 | tmp32 = tci_compare64(regs[r1], regs[r2], condition); | |
470 | regs[r0] = regs[tmp32 ? r3 : r4]; | |
471 | break; | |
7657f4bf | 472 | #endif |
9e9acb7b | 473 | CASE_32_64(mov) |
65089889 | 474 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 475 | regs[r0] = regs[r1]; |
7657f4bf | 476 | break; |
65089889 RH |
477 | case INDEX_op_tci_movi: |
478 | tci_args_ri(insn, &r0, &t1); | |
b95aa12e | 479 | regs[r0] = t1; |
7657f4bf | 480 | break; |
65089889 RH |
481 | case INDEX_op_tci_movl: |
482 | tci_args_rl(insn, tb_ptr, &r0, &ptr); | |
483 | regs[r0] = *(tcg_target_ulong *)ptr; | |
484 | break; | |
7657f4bf SW |
485 | |
486 | /* Load/store operations (32 bit). */ | |
487 | ||
7f33f5cd | 488 | CASE_32_64(ld8u) |
65089889 | 489 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
490 | ptr = (void *)(regs[r1] + ofs); |
491 | regs[r0] = *(uint8_t *)ptr; | |
7657f4bf | 492 | break; |
850163eb | 493 | CASE_32_64(ld8s) |
65089889 | 494 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
495 | ptr = (void *)(regs[r1] + ofs); |
496 | regs[r0] = *(int8_t *)ptr; | |
2f160e0f | 497 | break; |
77c38c7c | 498 | CASE_32_64(ld16u) |
65089889 | 499 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
500 | ptr = (void *)(regs[r1] + ofs); |
501 | regs[r0] = *(uint16_t *)ptr; | |
7657f4bf | 502 | break; |
b09d78bf | 503 | CASE_32_64(ld16s) |
65089889 | 504 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
505 | ptr = (void *)(regs[r1] + ofs); |
506 | regs[r0] = *(int16_t *)ptr; | |
7657f4bf SW |
507 | break; |
508 | case INDEX_op_ld_i32: | |
c1d77e94 | 509 | CASE_64(ld32u) |
65089889 | 510 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
511 | ptr = (void *)(regs[r1] + ofs); |
512 | regs[r0] = *(uint32_t *)ptr; | |
7657f4bf | 513 | break; |
ba9a80c1 | 514 | CASE_32_64(st8) |
65089889 | 515 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
516 | ptr = (void *)(regs[r1] + ofs); |
517 | *(uint8_t *)ptr = regs[r0]; | |
7657f4bf | 518 | break; |
90be4dde | 519 | CASE_32_64(st16) |
65089889 | 520 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
521 | ptr = (void *)(regs[r1] + ofs); |
522 | *(uint16_t *)ptr = regs[r0]; | |
7657f4bf SW |
523 | break; |
524 | case INDEX_op_st_i32: | |
b4d5bf0f | 525 | CASE_64(st32) |
65089889 | 526 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
527 | ptr = (void *)(regs[r1] + ofs); |
528 | *(uint32_t *)ptr = regs[r0]; | |
7657f4bf SW |
529 | break; |
530 | ||
dd2bb20e | 531 | /* Arithmetic operations (mixed 32/64 bit). */ |
7657f4bf | 532 | |
dd2bb20e | 533 | CASE_32_64(add) |
65089889 | 534 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 535 | regs[r0] = regs[r1] + regs[r2]; |
7657f4bf | 536 | break; |
dd2bb20e | 537 | CASE_32_64(sub) |
65089889 | 538 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 539 | regs[r0] = regs[r1] - regs[r2]; |
7657f4bf | 540 | break; |
dd2bb20e | 541 | CASE_32_64(mul) |
65089889 | 542 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 543 | regs[r0] = regs[r1] * regs[r2]; |
7657f4bf | 544 | break; |
dd2bb20e | 545 | CASE_32_64(and) |
65089889 | 546 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 547 | regs[r0] = regs[r1] & regs[r2]; |
7657f4bf | 548 | break; |
dd2bb20e | 549 | CASE_32_64(or) |
65089889 | 550 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 551 | regs[r0] = regs[r1] | regs[r2]; |
7657f4bf | 552 | break; |
dd2bb20e | 553 | CASE_32_64(xor) |
65089889 | 554 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 555 | regs[r0] = regs[r1] ^ regs[r2]; |
7657f4bf | 556 | break; |
a81520b9 RH |
557 | #if TCG_TARGET_HAS_andc_i32 || TCG_TARGET_HAS_andc_i64 |
558 | CASE_32_64(andc) | |
559 | tci_args_rrr(insn, &r0, &r1, &r2); | |
560 | regs[r0] = regs[r1] & ~regs[r2]; | |
561 | break; | |
562 | #endif | |
563 | #if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64 | |
564 | CASE_32_64(orc) | |
565 | tci_args_rrr(insn, &r0, &r1, &r2); | |
566 | regs[r0] = regs[r1] | ~regs[r2]; | |
567 | break; | |
568 | #endif | |
569 | #if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64 | |
570 | CASE_32_64(eqv) | |
571 | tci_args_rrr(insn, &r0, &r1, &r2); | |
572 | regs[r0] = ~(regs[r1] ^ regs[r2]); | |
573 | break; | |
574 | #endif | |
575 | #if TCG_TARGET_HAS_nand_i32 || TCG_TARGET_HAS_nand_i64 | |
576 | CASE_32_64(nand) | |
577 | tci_args_rrr(insn, &r0, &r1, &r2); | |
578 | regs[r0] = ~(regs[r1] & regs[r2]); | |
579 | break; | |
580 | #endif | |
581 | #if TCG_TARGET_HAS_nor_i32 || TCG_TARGET_HAS_nor_i64 | |
582 | CASE_32_64(nor) | |
583 | tci_args_rrr(insn, &r0, &r1, &r2); | |
584 | regs[r0] = ~(regs[r1] | regs[r2]); | |
585 | break; | |
586 | #endif | |
dd2bb20e RH |
587 | |
588 | /* Arithmetic operations (32 bit). */ | |
589 | ||
590 | case INDEX_op_div_i32: | |
65089889 | 591 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 592 | regs[r0] = (int32_t)regs[r1] / (int32_t)regs[r2]; |
7657f4bf | 593 | break; |
dd2bb20e | 594 | case INDEX_op_divu_i32: |
65089889 | 595 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 596 | regs[r0] = (uint32_t)regs[r1] / (uint32_t)regs[r2]; |
7657f4bf | 597 | break; |
dd2bb20e | 598 | case INDEX_op_rem_i32: |
65089889 | 599 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 600 | regs[r0] = (int32_t)regs[r1] % (int32_t)regs[r2]; |
7657f4bf | 601 | break; |
dd2bb20e | 602 | case INDEX_op_remu_i32: |
65089889 | 603 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 604 | regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2]; |
7657f4bf | 605 | break; |
5255f48c RH |
606 | #if TCG_TARGET_HAS_clz_i32 |
607 | case INDEX_op_clz_i32: | |
608 | tci_args_rrr(insn, &r0, &r1, &r2); | |
609 | tmp32 = regs[r1]; | |
610 | regs[r0] = tmp32 ? clz32(tmp32) : regs[r2]; | |
611 | break; | |
612 | #endif | |
613 | #if TCG_TARGET_HAS_ctz_i32 | |
614 | case INDEX_op_ctz_i32: | |
615 | tci_args_rrr(insn, &r0, &r1, &r2); | |
616 | tmp32 = regs[r1]; | |
617 | regs[r0] = tmp32 ? ctz32(tmp32) : regs[r2]; | |
618 | break; | |
619 | #endif | |
620 | #if TCG_TARGET_HAS_ctpop_i32 | |
621 | case INDEX_op_ctpop_i32: | |
622 | tci_args_rr(insn, &r0, &r1); | |
623 | regs[r0] = ctpop32(regs[r1]); | |
624 | break; | |
625 | #endif | |
7657f4bf SW |
626 | |
627 | /* Shift/rotate operations (32 bit). */ | |
628 | ||
629 | case INDEX_op_shl_i32: | |
65089889 | 630 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 631 | regs[r0] = (uint32_t)regs[r1] << (regs[r2] & 31); |
7657f4bf SW |
632 | break; |
633 | case INDEX_op_shr_i32: | |
65089889 | 634 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 635 | regs[r0] = (uint32_t)regs[r1] >> (regs[r2] & 31); |
7657f4bf SW |
636 | break; |
637 | case INDEX_op_sar_i32: | |
65089889 | 638 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 639 | regs[r0] = (int32_t)regs[r1] >> (regs[r2] & 31); |
7657f4bf SW |
640 | break; |
641 | #if TCG_TARGET_HAS_rot_i32 | |
642 | case INDEX_op_rotl_i32: | |
65089889 | 643 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 644 | regs[r0] = rol32(regs[r1], regs[r2] & 31); |
7657f4bf SW |
645 | break; |
646 | case INDEX_op_rotr_i32: | |
65089889 | 647 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 648 | regs[r0] = ror32(regs[r1], regs[r2] & 31); |
7657f4bf | 649 | break; |
e24dc9fe SW |
650 | #endif |
651 | #if TCG_TARGET_HAS_deposit_i32 | |
652 | case INDEX_op_deposit_i32: | |
65089889 | 653 | tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); |
79dd3a4f | 654 | regs[r0] = deposit32(regs[r1], pos, len, regs[r2]); |
e24dc9fe | 655 | break; |
0f10d7c5 RH |
656 | #endif |
657 | #if TCG_TARGET_HAS_extract_i32 | |
658 | case INDEX_op_extract_i32: | |
659 | tci_args_rrbb(insn, &r0, &r1, &pos, &len); | |
660 | regs[r0] = extract32(regs[r1], pos, len); | |
661 | break; | |
662 | #endif | |
663 | #if TCG_TARGET_HAS_sextract_i32 | |
664 | case INDEX_op_sextract_i32: | |
665 | tci_args_rrbb(insn, &r0, &r1, &pos, &len); | |
666 | regs[r0] = sextract32(regs[r1], pos, len); | |
667 | break; | |
7657f4bf SW |
668 | #endif |
669 | case INDEX_op_brcond_i32: | |
65089889 | 670 | tci_args_rl(insn, tb_ptr, &r0, &ptr); |
fc8ec9e1 | 671 | if ((uint32_t)regs[r0]) { |
5a0adf34 | 672 | tb_ptr = ptr; |
7657f4bf SW |
673 | } |
674 | break; | |
08096b1a | 675 | #if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_add2_i32 |
7657f4bf | 676 | case INDEX_op_add2_i32: |
65089889 | 677 | tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); |
120402b5 RH |
678 | T1 = tci_uint64(regs[r3], regs[r2]); |
679 | T2 = tci_uint64(regs[r5], regs[r4]); | |
680 | tci_write_reg64(regs, r1, r0, T1 + T2); | |
7657f4bf | 681 | break; |
08096b1a RH |
682 | #endif |
683 | #if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_sub2_i32 | |
7657f4bf | 684 | case INDEX_op_sub2_i32: |
65089889 | 685 | tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); |
120402b5 RH |
686 | T1 = tci_uint64(regs[r3], regs[r2]); |
687 | T2 = tci_uint64(regs[r5], regs[r4]); | |
688 | tci_write_reg64(regs, r1, r0, T1 - T2); | |
7657f4bf | 689 | break; |
08096b1a | 690 | #endif |
f6db0d8d | 691 | #if TCG_TARGET_HAS_mulu2_i32 |
7657f4bf | 692 | case INDEX_op_mulu2_i32: |
65089889 | 693 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); |
f6db0d8d RH |
694 | tmp64 = (uint64_t)(uint32_t)regs[r2] * (uint32_t)regs[r3]; |
695 | tci_write_reg64(regs, r1, r0, tmp64); | |
7657f4bf | 696 | break; |
f6db0d8d RH |
697 | #endif |
698 | #if TCG_TARGET_HAS_muls2_i32 | |
699 | case INDEX_op_muls2_i32: | |
700 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); | |
701 | tmp64 = (int64_t)(int32_t)regs[r2] * (int32_t)regs[r3]; | |
702 | tci_write_reg64(regs, r1, r0, tmp64); | |
703 | break; | |
704 | #endif | |
13a1d640 RH |
705 | #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 |
706 | CASE_32_64(ext8s) | |
65089889 | 707 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 708 | regs[r0] = (int8_t)regs[r1]; |
7657f4bf SW |
709 | break; |
710 | #endif | |
0d57d36a RH |
711 | #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 || \ |
712 | TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 | |
13a1d640 | 713 | CASE_32_64(ext16s) |
65089889 | 714 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 715 | regs[r0] = (int16_t)regs[r1]; |
7657f4bf SW |
716 | break; |
717 | #endif | |
13a1d640 RH |
718 | #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 |
719 | CASE_32_64(ext8u) | |
65089889 | 720 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 721 | regs[r0] = (uint8_t)regs[r1]; |
7657f4bf SW |
722 | break; |
723 | #endif | |
13a1d640 RH |
724 | #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 |
725 | CASE_32_64(ext16u) | |
65089889 | 726 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 727 | regs[r0] = (uint16_t)regs[r1]; |
7657f4bf SW |
728 | break; |
729 | #endif | |
fe2b13bb RH |
730 | #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 |
731 | CASE_32_64(bswap16) | |
65089889 | 732 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 733 | regs[r0] = bswap16(regs[r1]); |
7657f4bf SW |
734 | break; |
735 | #endif | |
fe2b13bb RH |
736 | #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 |
737 | CASE_32_64(bswap32) | |
65089889 | 738 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 739 | regs[r0] = bswap32(regs[r1]); |
7657f4bf SW |
740 | break; |
741 | #endif | |
9e9acb7b RH |
742 | #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 |
743 | CASE_32_64(not) | |
65089889 | 744 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 745 | regs[r0] = ~regs[r1]; |
7657f4bf SW |
746 | break; |
747 | #endif | |
9e9acb7b | 748 | CASE_32_64(neg) |
65089889 | 749 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 750 | regs[r0] = -regs[r1]; |
7657f4bf | 751 | break; |
7657f4bf | 752 | #if TCG_TARGET_REG_BITS == 64 |
7657f4bf SW |
753 | /* Load/store operations (64 bit). */ |
754 | ||
7657f4bf | 755 | case INDEX_op_ld32s_i64: |
65089889 | 756 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
757 | ptr = (void *)(regs[r1] + ofs); |
758 | regs[r0] = *(int32_t *)ptr; | |
7657f4bf SW |
759 | break; |
760 | case INDEX_op_ld_i64: | |
65089889 | 761 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
762 | ptr = (void *)(regs[r1] + ofs); |
763 | regs[r0] = *(uint64_t *)ptr; | |
7657f4bf | 764 | break; |
7657f4bf | 765 | case INDEX_op_st_i64: |
65089889 | 766 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
767 | ptr = (void *)(regs[r1] + ofs); |
768 | *(uint64_t *)ptr = regs[r0]; | |
7657f4bf SW |
769 | break; |
770 | ||
771 | /* Arithmetic operations (64 bit). */ | |
772 | ||
7657f4bf | 773 | case INDEX_op_div_i64: |
65089889 | 774 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 775 | regs[r0] = (int64_t)regs[r1] / (int64_t)regs[r2]; |
ae40c098 | 776 | break; |
7657f4bf | 777 | case INDEX_op_divu_i64: |
65089889 | 778 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 779 | regs[r0] = (uint64_t)regs[r1] / (uint64_t)regs[r2]; |
ae40c098 | 780 | break; |
7657f4bf | 781 | case INDEX_op_rem_i64: |
65089889 | 782 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 783 | regs[r0] = (int64_t)regs[r1] % (int64_t)regs[r2]; |
ae40c098 | 784 | break; |
7657f4bf | 785 | case INDEX_op_remu_i64: |
65089889 | 786 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 787 | regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2]; |
7657f4bf | 788 | break; |
5255f48c RH |
789 | #if TCG_TARGET_HAS_clz_i64 |
790 | case INDEX_op_clz_i64: | |
791 | tci_args_rrr(insn, &r0, &r1, &r2); | |
792 | regs[r0] = regs[r1] ? clz64(regs[r1]) : regs[r2]; | |
793 | break; | |
794 | #endif | |
795 | #if TCG_TARGET_HAS_ctz_i64 | |
796 | case INDEX_op_ctz_i64: | |
797 | tci_args_rrr(insn, &r0, &r1, &r2); | |
798 | regs[r0] = regs[r1] ? ctz64(regs[r1]) : regs[r2]; | |
799 | break; | |
800 | #endif | |
801 | #if TCG_TARGET_HAS_ctpop_i64 | |
802 | case INDEX_op_ctpop_i64: | |
803 | tci_args_rr(insn, &r0, &r1); | |
804 | regs[r0] = ctpop64(regs[r1]); | |
805 | break; | |
806 | #endif | |
f6db0d8d RH |
807 | #if TCG_TARGET_HAS_mulu2_i64 |
808 | case INDEX_op_mulu2_i64: | |
809 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); | |
810 | mulu64(®s[r0], ®s[r1], regs[r2], regs[r3]); | |
811 | break; | |
812 | #endif | |
813 | #if TCG_TARGET_HAS_muls2_i64 | |
814 | case INDEX_op_muls2_i64: | |
815 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); | |
816 | muls64(®s[r0], ®s[r1], regs[r2], regs[r3]); | |
817 | break; | |
818 | #endif | |
08096b1a RH |
819 | #if TCG_TARGET_HAS_add2_i64 |
820 | case INDEX_op_add2_i64: | |
821 | tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); | |
822 | T1 = regs[r2] + regs[r4]; | |
823 | T2 = regs[r3] + regs[r5] + (T1 < regs[r2]); | |
824 | regs[r0] = T1; | |
825 | regs[r1] = T2; | |
826 | break; | |
827 | #endif | |
828 | #if TCG_TARGET_HAS_add2_i64 | |
829 | case INDEX_op_sub2_i64: | |
830 | tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); | |
831 | T1 = regs[r2] - regs[r4]; | |
832 | T2 = regs[r3] - regs[r5] - (regs[r2] < regs[r4]); | |
833 | regs[r0] = T1; | |
834 | regs[r1] = T2; | |
835 | break; | |
836 | #endif | |
7657f4bf SW |
837 | |
838 | /* Shift/rotate operations (64 bit). */ | |
839 | ||
840 | case INDEX_op_shl_i64: | |
65089889 | 841 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 842 | regs[r0] = regs[r1] << (regs[r2] & 63); |
7657f4bf SW |
843 | break; |
844 | case INDEX_op_shr_i64: | |
65089889 | 845 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 846 | regs[r0] = regs[r1] >> (regs[r2] & 63); |
7657f4bf SW |
847 | break; |
848 | case INDEX_op_sar_i64: | |
65089889 | 849 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 850 | regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63); |
7657f4bf SW |
851 | break; |
852 | #if TCG_TARGET_HAS_rot_i64 | |
853 | case INDEX_op_rotl_i64: | |
65089889 | 854 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 855 | regs[r0] = rol64(regs[r1], regs[r2] & 63); |
d285bf78 | 856 | break; |
7657f4bf | 857 | case INDEX_op_rotr_i64: |
65089889 | 858 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 859 | regs[r0] = ror64(regs[r1], regs[r2] & 63); |
7657f4bf | 860 | break; |
e24dc9fe SW |
861 | #endif |
862 | #if TCG_TARGET_HAS_deposit_i64 | |
863 | case INDEX_op_deposit_i64: | |
65089889 | 864 | tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); |
79dd3a4f | 865 | regs[r0] = deposit64(regs[r1], pos, len, regs[r2]); |
e24dc9fe | 866 | break; |
0f10d7c5 RH |
867 | #endif |
868 | #if TCG_TARGET_HAS_extract_i64 | |
869 | case INDEX_op_extract_i64: | |
870 | tci_args_rrbb(insn, &r0, &r1, &pos, &len); | |
871 | regs[r0] = extract64(regs[r1], pos, len); | |
872 | break; | |
873 | #endif | |
874 | #if TCG_TARGET_HAS_sextract_i64 | |
875 | case INDEX_op_sextract_i64: | |
876 | tci_args_rrbb(insn, &r0, &r1, &pos, &len); | |
877 | regs[r0] = sextract64(regs[r1], pos, len); | |
878 | break; | |
7657f4bf SW |
879 | #endif |
880 | case INDEX_op_brcond_i64: | |
65089889 | 881 | tci_args_rl(insn, tb_ptr, &r0, &ptr); |
fc8ec9e1 | 882 | if (regs[r0]) { |
5a0adf34 | 883 | tb_ptr = ptr; |
7657f4bf SW |
884 | } |
885 | break; | |
7657f4bf | 886 | case INDEX_op_ext32s_i64: |
4f2331e5 | 887 | case INDEX_op_ext_i32_i64: |
65089889 | 888 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 889 | regs[r0] = (int32_t)regs[r1]; |
7657f4bf | 890 | break; |
7657f4bf | 891 | case INDEX_op_ext32u_i64: |
4f2331e5 | 892 | case INDEX_op_extu_i32_i64: |
65089889 | 893 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 894 | regs[r0] = (uint32_t)regs[r1]; |
7657f4bf | 895 | break; |
7657f4bf SW |
896 | #if TCG_TARGET_HAS_bswap64_i64 |
897 | case INDEX_op_bswap64_i64: | |
65089889 | 898 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 899 | regs[r0] = bswap64(regs[r1]); |
7657f4bf SW |
900 | break; |
901 | #endif | |
7657f4bf SW |
902 | #endif /* TCG_TARGET_REG_BITS == 64 */ |
903 | ||
904 | /* QEMU specific operations. */ | |
905 | ||
7657f4bf | 906 | case INDEX_op_exit_tb: |
65089889 | 907 | tci_args_l(insn, tb_ptr, &ptr); |
158d3873 RH |
908 | return (uintptr_t)ptr; |
909 | ||
7657f4bf | 910 | case INDEX_op_goto_tb: |
65089889 | 911 | tci_args_l(insn, tb_ptr, &ptr); |
1670a2b9 | 912 | tb_ptr = *(void **)ptr; |
92bc4fad | 913 | break; |
1670a2b9 | 914 | |
6eea0434 RH |
915 | case INDEX_op_goto_ptr: |
916 | tci_args_r(insn, &r0); | |
917 | ptr = (void *)regs[r0]; | |
918 | if (!ptr) { | |
919 | return 0; | |
920 | } | |
921 | tb_ptr = ptr; | |
922 | break; | |
923 | ||
fecccfcc | 924 | case INDEX_op_qemu_ld_a32_i32: |
dd7dc93e RH |
925 | tci_args_rrm(insn, &r0, &r1, &oi); |
926 | taddr = (uint32_t)regs[r1]; | |
927 | goto do_ld_i32; | |
fecccfcc | 928 | case INDEX_op_qemu_ld_a64_i32: |
dd7dc93e | 929 | if (TCG_TARGET_REG_BITS == 64) { |
65089889 | 930 | tci_args_rrm(insn, &r0, &r1, &oi); |
63041ed2 RH |
931 | taddr = regs[r1]; |
932 | } else { | |
ab64da79 | 933 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); |
63041ed2 | 934 | taddr = tci_uint64(regs[r2], regs[r1]); |
ab64da79 | 935 | oi = regs[r3]; |
63041ed2 | 936 | } |
dd7dc93e RH |
937 | do_ld_i32: |
938 | regs[r0] = tci_qemu_ld(env, taddr, oi, tb_ptr); | |
7657f4bf | 939 | break; |
63041ed2 | 940 | |
fecccfcc | 941 | case INDEX_op_qemu_ld_a32_i64: |
dd7dc93e RH |
942 | if (TCG_TARGET_REG_BITS == 64) { |
943 | tci_args_rrm(insn, &r0, &r1, &oi); | |
944 | taddr = (uint32_t)regs[r1]; | |
945 | } else { | |
ab64da79 | 946 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); |
dd7dc93e | 947 | taddr = (uint32_t)regs[r2]; |
ab64da79 | 948 | oi = regs[r3]; |
dd7dc93e RH |
949 | } |
950 | goto do_ld_i64; | |
fecccfcc | 951 | case INDEX_op_qemu_ld_a64_i64: |
63041ed2 | 952 | if (TCG_TARGET_REG_BITS == 64) { |
65089889 | 953 | tci_args_rrm(insn, &r0, &r1, &oi); |
63041ed2 | 954 | taddr = regs[r1]; |
63041ed2 | 955 | } else { |
65089889 | 956 | tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); |
63041ed2 | 957 | taddr = tci_uint64(regs[r3], regs[r2]); |
65089889 | 958 | oi = regs[r4]; |
76782fab | 959 | } |
dd7dc93e | 960 | do_ld_i64: |
69acc02a | 961 | tmp64 = tci_qemu_ld(env, taddr, oi, tb_ptr); |
76782fab | 962 | if (TCG_TARGET_REG_BITS == 32) { |
63041ed2 RH |
963 | tci_write_reg64(regs, r1, r0, tmp64); |
964 | } else { | |
965 | regs[r0] = tmp64; | |
76782fab | 966 | } |
7657f4bf | 967 | break; |
63041ed2 | 968 | |
fecccfcc | 969 | case INDEX_op_qemu_st_a32_i32: |
dd7dc93e RH |
970 | tci_args_rrm(insn, &r0, &r1, &oi); |
971 | taddr = (uint32_t)regs[r1]; | |
972 | goto do_st_i32; | |
fecccfcc | 973 | case INDEX_op_qemu_st_a64_i32: |
dd7dc93e | 974 | if (TCG_TARGET_REG_BITS == 64) { |
65089889 | 975 | tci_args_rrm(insn, &r0, &r1, &oi); |
63041ed2 RH |
976 | taddr = regs[r1]; |
977 | } else { | |
ab64da79 | 978 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); |
63041ed2 | 979 | taddr = tci_uint64(regs[r2], regs[r1]); |
ab64da79 | 980 | oi = regs[r3]; |
63041ed2 | 981 | } |
dd7dc93e RH |
982 | do_st_i32: |
983 | tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr); | |
7657f4bf | 984 | break; |
63041ed2 | 985 | |
fecccfcc | 986 | case INDEX_op_qemu_st_a32_i64: |
dd7dc93e RH |
987 | if (TCG_TARGET_REG_BITS == 64) { |
988 | tci_args_rrm(insn, &r0, &r1, &oi); | |
989 | tmp64 = regs[r0]; | |
990 | taddr = (uint32_t)regs[r1]; | |
991 | } else { | |
ab64da79 | 992 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); |
dd7dc93e RH |
993 | tmp64 = tci_uint64(regs[r1], regs[r0]); |
994 | taddr = (uint32_t)regs[r2]; | |
ab64da79 | 995 | oi = regs[r3]; |
dd7dc93e RH |
996 | } |
997 | goto do_st_i64; | |
fecccfcc | 998 | case INDEX_op_qemu_st_a64_i64: |
63041ed2 | 999 | if (TCG_TARGET_REG_BITS == 64) { |
65089889 | 1000 | tci_args_rrm(insn, &r0, &r1, &oi); |
63041ed2 | 1001 | tmp64 = regs[r0]; |
dd7dc93e | 1002 | taddr = regs[r1]; |
63041ed2 | 1003 | } else { |
dd7dc93e | 1004 | tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); |
63041ed2 | 1005 | tmp64 = tci_uint64(regs[r1], regs[r0]); |
dd7dc93e RH |
1006 | taddr = tci_uint64(regs[r3], regs[r2]); |
1007 | oi = regs[r4]; | |
63041ed2 | 1008 | } |
dd7dc93e | 1009 | do_st_i64: |
69acc02a | 1010 | tci_qemu_st(env, taddr, tmp64, oi, tb_ptr); |
7657f4bf | 1011 | break; |
63041ed2 | 1012 | |
a1e69e2f PK |
1013 | case INDEX_op_mb: |
1014 | /* Ensure ordering for all kinds */ | |
1015 | smp_mb(); | |
1016 | break; | |
7657f4bf | 1017 | default: |
f6996f99 | 1018 | g_assert_not_reached(); |
7657f4bf | 1019 | } |
7657f4bf | 1020 | } |
7657f4bf | 1021 | } |
59964b4f RH |
1022 | |
1023 | /* | |
1024 | * Disassembler that matches the interpreter | |
1025 | */ | |
1026 | ||
1027 | static const char *str_r(TCGReg r) | |
1028 | { | |
1029 | static const char regs[TCG_TARGET_NB_REGS][4] = { | |
1030 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
1031 | "r8", "r9", "r10", "r11", "r12", "r13", "env", "sp" | |
1032 | }; | |
1033 | ||
1034 | QEMU_BUILD_BUG_ON(TCG_AREG0 != TCG_REG_R14); | |
1035 | QEMU_BUILD_BUG_ON(TCG_REG_CALL_STACK != TCG_REG_R15); | |
1036 | ||
1037 | assert((unsigned)r < TCG_TARGET_NB_REGS); | |
1038 | return regs[r]; | |
1039 | } | |
1040 | ||
1041 | static const char *str_c(TCGCond c) | |
1042 | { | |
1043 | static const char cond[16][8] = { | |
1044 | [TCG_COND_NEVER] = "never", | |
1045 | [TCG_COND_ALWAYS] = "always", | |
1046 | [TCG_COND_EQ] = "eq", | |
1047 | [TCG_COND_NE] = "ne", | |
1048 | [TCG_COND_LT] = "lt", | |
1049 | [TCG_COND_GE] = "ge", | |
1050 | [TCG_COND_LE] = "le", | |
1051 | [TCG_COND_GT] = "gt", | |
1052 | [TCG_COND_LTU] = "ltu", | |
1053 | [TCG_COND_GEU] = "geu", | |
1054 | [TCG_COND_LEU] = "leu", | |
1055 | [TCG_COND_GTU] = "gtu", | |
23c5692a RH |
1056 | [TCG_COND_TSTEQ] = "tsteq", |
1057 | [TCG_COND_TSTNE] = "tstne", | |
59964b4f RH |
1058 | }; |
1059 | ||
1060 | assert((unsigned)c < ARRAY_SIZE(cond)); | |
1061 | assert(cond[c][0] != 0); | |
1062 | return cond[c]; | |
1063 | } | |
1064 | ||
1065 | /* Disassemble TCI bytecode. */ | |
1066 | int print_insn_tci(bfd_vma addr, disassemble_info *info) | |
1067 | { | |
65089889 | 1068 | const uint32_t *tb_ptr = (const void *)(uintptr_t)addr; |
59964b4f RH |
1069 | const TCGOpDef *def; |
1070 | const char *op_name; | |
65089889 | 1071 | uint32_t insn; |
59964b4f | 1072 | TCGOpcode op; |
08096b1a | 1073 | TCGReg r0, r1, r2, r3, r4, r5; |
59964b4f RH |
1074 | tcg_target_ulong i1; |
1075 | int32_t s2; | |
1076 | TCGCond c; | |
9002ffcb | 1077 | MemOpIdx oi; |
59964b4f | 1078 | uint8_t pos, len; |
65089889 | 1079 | void *ptr; |
59964b4f | 1080 | |
65089889 RH |
1081 | /* TCI is always the host, so we don't need to load indirect. */ |
1082 | insn = *tb_ptr++; | |
59964b4f | 1083 | |
65089889 | 1084 | info->fprintf_func(info->stream, "%08x ", insn); |
59964b4f | 1085 | |
65089889 | 1086 | op = extract32(insn, 0, 8); |
59964b4f RH |
1087 | def = &tcg_op_defs[op]; |
1088 | op_name = def->name; | |
59964b4f RH |
1089 | |
1090 | switch (op) { | |
1091 | case INDEX_op_br: | |
59964b4f RH |
1092 | case INDEX_op_exit_tb: |
1093 | case INDEX_op_goto_tb: | |
65089889 | 1094 | tci_args_l(insn, tb_ptr, &ptr); |
59964b4f RH |
1095 | info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); |
1096 | break; | |
1097 | ||
6eea0434 RH |
1098 | case INDEX_op_goto_ptr: |
1099 | tci_args_r(insn, &r0); | |
1100 | info->fprintf_func(info->stream, "%-12s %s", op_name, str_r(r0)); | |
1101 | break; | |
1102 | ||
7b7d8b2d | 1103 | case INDEX_op_call: |
65089889 RH |
1104 | tci_args_nl(insn, tb_ptr, &len, &ptr); |
1105 | info->fprintf_func(info->stream, "%-12s %d, %p", op_name, len, ptr); | |
7b7d8b2d RH |
1106 | break; |
1107 | ||
59964b4f RH |
1108 | case INDEX_op_brcond_i32: |
1109 | case INDEX_op_brcond_i64: | |
65089889 | 1110 | tci_args_rl(insn, tb_ptr, &r0, &ptr); |
fc8ec9e1 RH |
1111 | info->fprintf_func(info->stream, "%-12s %s, 0, ne, %p", |
1112 | op_name, str_r(r0), ptr); | |
59964b4f RH |
1113 | break; |
1114 | ||
1115 | case INDEX_op_setcond_i32: | |
1116 | case INDEX_op_setcond_i64: | |
65089889 | 1117 | tci_args_rrrc(insn, &r0, &r1, &r2, &c); |
59964b4f RH |
1118 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", |
1119 | op_name, str_r(r0), str_r(r1), str_r(r2), str_c(c)); | |
1120 | break; | |
1121 | ||
65089889 RH |
1122 | case INDEX_op_tci_movi: |
1123 | tci_args_ri(insn, &r0, &i1); | |
59964b4f RH |
1124 | info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx, |
1125 | op_name, str_r(r0), i1); | |
1126 | break; | |
1127 | ||
65089889 RH |
1128 | case INDEX_op_tci_movl: |
1129 | tci_args_rl(insn, tb_ptr, &r0, &ptr); | |
1130 | info->fprintf_func(info->stream, "%-12s %s, %p", | |
1131 | op_name, str_r(r0), ptr); | |
59964b4f | 1132 | break; |
59964b4f RH |
1133 | |
1134 | case INDEX_op_ld8u_i32: | |
1135 | case INDEX_op_ld8u_i64: | |
1136 | case INDEX_op_ld8s_i32: | |
1137 | case INDEX_op_ld8s_i64: | |
1138 | case INDEX_op_ld16u_i32: | |
1139 | case INDEX_op_ld16u_i64: | |
1140 | case INDEX_op_ld16s_i32: | |
1141 | case INDEX_op_ld16s_i64: | |
1142 | case INDEX_op_ld32u_i64: | |
1143 | case INDEX_op_ld32s_i64: | |
1144 | case INDEX_op_ld_i32: | |
1145 | case INDEX_op_ld_i64: | |
1146 | case INDEX_op_st8_i32: | |
1147 | case INDEX_op_st8_i64: | |
1148 | case INDEX_op_st16_i32: | |
1149 | case INDEX_op_st16_i64: | |
1150 | case INDEX_op_st32_i64: | |
1151 | case INDEX_op_st_i32: | |
1152 | case INDEX_op_st_i64: | |
65089889 | 1153 | tci_args_rrs(insn, &r0, &r1, &s2); |
59964b4f RH |
1154 | info->fprintf_func(info->stream, "%-12s %s, %s, %d", |
1155 | op_name, str_r(r0), str_r(r1), s2); | |
1156 | break; | |
1157 | ||
1158 | case INDEX_op_mov_i32: | |
1159 | case INDEX_op_mov_i64: | |
1160 | case INDEX_op_ext8s_i32: | |
1161 | case INDEX_op_ext8s_i64: | |
1162 | case INDEX_op_ext8u_i32: | |
1163 | case INDEX_op_ext8u_i64: | |
1164 | case INDEX_op_ext16s_i32: | |
1165 | case INDEX_op_ext16s_i64: | |
1166 | case INDEX_op_ext16u_i32: | |
1167 | case INDEX_op_ext32s_i64: | |
1168 | case INDEX_op_ext32u_i64: | |
1169 | case INDEX_op_ext_i32_i64: | |
1170 | case INDEX_op_extu_i32_i64: | |
1171 | case INDEX_op_bswap16_i32: | |
1172 | case INDEX_op_bswap16_i64: | |
1173 | case INDEX_op_bswap32_i32: | |
1174 | case INDEX_op_bswap32_i64: | |
1175 | case INDEX_op_bswap64_i64: | |
1176 | case INDEX_op_not_i32: | |
1177 | case INDEX_op_not_i64: | |
1178 | case INDEX_op_neg_i32: | |
1179 | case INDEX_op_neg_i64: | |
5255f48c RH |
1180 | case INDEX_op_ctpop_i32: |
1181 | case INDEX_op_ctpop_i64: | |
65089889 | 1182 | tci_args_rr(insn, &r0, &r1); |
59964b4f RH |
1183 | info->fprintf_func(info->stream, "%-12s %s, %s", |
1184 | op_name, str_r(r0), str_r(r1)); | |
1185 | break; | |
1186 | ||
1187 | case INDEX_op_add_i32: | |
1188 | case INDEX_op_add_i64: | |
1189 | case INDEX_op_sub_i32: | |
1190 | case INDEX_op_sub_i64: | |
1191 | case INDEX_op_mul_i32: | |
1192 | case INDEX_op_mul_i64: | |
1193 | case INDEX_op_and_i32: | |
1194 | case INDEX_op_and_i64: | |
1195 | case INDEX_op_or_i32: | |
1196 | case INDEX_op_or_i64: | |
1197 | case INDEX_op_xor_i32: | |
1198 | case INDEX_op_xor_i64: | |
a81520b9 RH |
1199 | case INDEX_op_andc_i32: |
1200 | case INDEX_op_andc_i64: | |
1201 | case INDEX_op_orc_i32: | |
1202 | case INDEX_op_orc_i64: | |
1203 | case INDEX_op_eqv_i32: | |
1204 | case INDEX_op_eqv_i64: | |
1205 | case INDEX_op_nand_i32: | |
1206 | case INDEX_op_nand_i64: | |
1207 | case INDEX_op_nor_i32: | |
1208 | case INDEX_op_nor_i64: | |
59964b4f RH |
1209 | case INDEX_op_div_i32: |
1210 | case INDEX_op_div_i64: | |
1211 | case INDEX_op_rem_i32: | |
1212 | case INDEX_op_rem_i64: | |
1213 | case INDEX_op_divu_i32: | |
1214 | case INDEX_op_divu_i64: | |
1215 | case INDEX_op_remu_i32: | |
1216 | case INDEX_op_remu_i64: | |
1217 | case INDEX_op_shl_i32: | |
1218 | case INDEX_op_shl_i64: | |
1219 | case INDEX_op_shr_i32: | |
1220 | case INDEX_op_shr_i64: | |
1221 | case INDEX_op_sar_i32: | |
1222 | case INDEX_op_sar_i64: | |
1223 | case INDEX_op_rotl_i32: | |
1224 | case INDEX_op_rotl_i64: | |
1225 | case INDEX_op_rotr_i32: | |
1226 | case INDEX_op_rotr_i64: | |
5255f48c RH |
1227 | case INDEX_op_clz_i32: |
1228 | case INDEX_op_clz_i64: | |
1229 | case INDEX_op_ctz_i32: | |
1230 | case INDEX_op_ctz_i64: | |
65089889 | 1231 | tci_args_rrr(insn, &r0, &r1, &r2); |
59964b4f RH |
1232 | info->fprintf_func(info->stream, "%-12s %s, %s, %s", |
1233 | op_name, str_r(r0), str_r(r1), str_r(r2)); | |
1234 | break; | |
1235 | ||
1236 | case INDEX_op_deposit_i32: | |
1237 | case INDEX_op_deposit_i64: | |
65089889 | 1238 | tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); |
59964b4f RH |
1239 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %d, %d", |
1240 | op_name, str_r(r0), str_r(r1), str_r(r2), pos, len); | |
1241 | break; | |
1242 | ||
0f10d7c5 RH |
1243 | case INDEX_op_extract_i32: |
1244 | case INDEX_op_extract_i64: | |
1245 | case INDEX_op_sextract_i32: | |
1246 | case INDEX_op_sextract_i64: | |
1247 | tci_args_rrbb(insn, &r0, &r1, &pos, &len); | |
1248 | info->fprintf_func(info->stream, "%-12s %s,%s,%d,%d", | |
1249 | op_name, str_r(r0), str_r(r1), pos, len); | |
1250 | break; | |
1251 | ||
df093c19 RH |
1252 | case INDEX_op_movcond_i32: |
1253 | case INDEX_op_movcond_i64: | |
59964b4f | 1254 | case INDEX_op_setcond2_i32: |
65089889 | 1255 | tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c); |
59964b4f RH |
1256 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s", |
1257 | op_name, str_r(r0), str_r(r1), str_r(r2), | |
1258 | str_r(r3), str_r(r4), str_c(c)); | |
1259 | break; | |
1260 | ||
59964b4f | 1261 | case INDEX_op_mulu2_i32: |
f6db0d8d RH |
1262 | case INDEX_op_mulu2_i64: |
1263 | case INDEX_op_muls2_i32: | |
1264 | case INDEX_op_muls2_i64: | |
65089889 | 1265 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); |
59964b4f RH |
1266 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", |
1267 | op_name, str_r(r0), str_r(r1), | |
1268 | str_r(r2), str_r(r3)); | |
1269 | break; | |
1270 | ||
1271 | case INDEX_op_add2_i32: | |
08096b1a | 1272 | case INDEX_op_add2_i64: |
59964b4f | 1273 | case INDEX_op_sub2_i32: |
08096b1a | 1274 | case INDEX_op_sub2_i64: |
65089889 | 1275 | tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); |
59964b4f RH |
1276 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s", |
1277 | op_name, str_r(r0), str_r(r1), str_r(r2), | |
1278 | str_r(r3), str_r(r4), str_r(r5)); | |
1279 | break; | |
59964b4f | 1280 | |
fecccfcc RH |
1281 | case INDEX_op_qemu_ld_a32_i32: |
1282 | case INDEX_op_qemu_st_a32_i32: | |
1283 | len = 1 + 1; | |
1284 | goto do_qemu_ldst; | |
1285 | case INDEX_op_qemu_ld_a32_i64: | |
1286 | case INDEX_op_qemu_st_a32_i64: | |
1287 | case INDEX_op_qemu_ld_a64_i32: | |
1288 | case INDEX_op_qemu_st_a64_i32: | |
1289 | len = 1 + DIV_ROUND_UP(64, TCG_TARGET_REG_BITS); | |
1290 | goto do_qemu_ldst; | |
1291 | case INDEX_op_qemu_ld_a64_i64: | |
1292 | case INDEX_op_qemu_st_a64_i64: | |
1293 | len = 2 * DIV_ROUND_UP(64, TCG_TARGET_REG_BITS); | |
59964b4f | 1294 | goto do_qemu_ldst; |
59964b4f | 1295 | do_qemu_ldst: |
59964b4f RH |
1296 | switch (len) { |
1297 | case 2: | |
65089889 | 1298 | tci_args_rrm(insn, &r0, &r1, &oi); |
59964b4f RH |
1299 | info->fprintf_func(info->stream, "%-12s %s, %s, %x", |
1300 | op_name, str_r(r0), str_r(r1), oi); | |
1301 | break; | |
1302 | case 3: | |
ab64da79 RH |
1303 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); |
1304 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", | |
1305 | op_name, str_r(r0), str_r(r1), | |
1306 | str_r(r2), str_r(r3)); | |
59964b4f RH |
1307 | break; |
1308 | case 4: | |
65089889 RH |
1309 | tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); |
1310 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s", | |
59964b4f | 1311 | op_name, str_r(r0), str_r(r1), |
65089889 | 1312 | str_r(r2), str_r(r3), str_r(r4)); |
59964b4f RH |
1313 | break; |
1314 | default: | |
1315 | g_assert_not_reached(); | |
1316 | } | |
1317 | break; | |
1318 | ||
65089889 RH |
1319 | case 0: |
1320 | /* tcg_out_nop_fill uses zeros */ | |
1321 | if (insn == 0) { | |
1322 | info->fprintf_func(info->stream, "align"); | |
1323 | break; | |
1324 | } | |
1325 | /* fall through */ | |
1326 | ||
59964b4f RH |
1327 | default: |
1328 | info->fprintf_func(info->stream, "illegal opcode %d", op); | |
1329 | break; | |
1330 | } | |
1331 | ||
65089889 | 1332 | return sizeof(insn); |
59964b4f | 1333 | } |