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Commit | Line | Data |
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7657f4bf SW |
1 | /* |
2 | * Tiny Code Interpreter for QEMU | |
3 | * | |
3ccdbecf | 4 | * Copyright (c) 2009, 2011, 2016 Stefan Weil |
7657f4bf SW |
5 | * |
6 | * This program is free software: you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation, either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
d38ea87a | 20 | #include "qemu/osdep.h" |
ad3d0e4d | 21 | #include "tcg/tcg.h" |
d2ba8026 | 22 | #include "tcg/tcg-ldst.h" |
7b7d8b2d | 23 | #include <ffi.h> |
7657f4bf | 24 | |
7b7d8b2d RH |
25 | |
26 | /* | |
27 | * Enable TCI assertions only when debugging TCG (and without NDEBUG defined). | |
28 | * Without assertions, the interpreter runs much faster. | |
29 | */ | |
30 | #if defined(CONFIG_DEBUG_TCG) | |
31 | # define tci_assert(cond) assert(cond) | |
7657f4bf | 32 | #else |
7b7d8b2d | 33 | # define tci_assert(cond) ((void)(cond)) |
7657f4bf SW |
34 | #endif |
35 | ||
13e71f08 RH |
36 | __thread uintptr_t tci_tb_ptr; |
37 | ||
5e75150c EC |
38 | static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, |
39 | uint32_t low_index, uint64_t value) | |
7657f4bf | 40 | { |
f6db0d8d | 41 | regs[low_index] = (uint32_t)value; |
7e00a080 | 42 | regs[high_index] = value >> 32; |
7657f4bf | 43 | } |
7657f4bf | 44 | |
7657f4bf SW |
45 | /* Create a 64 bit value from two 32 bit values. */ |
46 | static uint64_t tci_uint64(uint32_t high, uint32_t low) | |
47 | { | |
48 | return ((uint64_t)high << 32) + low; | |
49 | } | |
7657f4bf | 50 | |
cdd9799b RH |
51 | /* |
52 | * Load sets of arguments all at once. The naming convention is: | |
53 | * tci_args_<arguments> | |
54 | * where arguments is a sequence of | |
55 | * | |
79dd3a4f | 56 | * b = immediate (bit position) |
963e9fa2 | 57 | * c = condition (TCGCond) |
b95aa12e RH |
58 | * i = immediate (uint32_t) |
59 | * I = immediate (tcg_target_ulong) | |
f28ca03e | 60 | * l = label or pointer |
9002ffcb | 61 | * m = immediate (MemOpIdx) |
7b7d8b2d | 62 | * n = immediate (call return length) |
cdd9799b RH |
63 | * r = register |
64 | * s = signed ldst offset | |
65 | */ | |
66 | ||
65089889 | 67 | static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0) |
92bc4fad | 68 | { |
65089889 RH |
69 | int diff = sextract32(insn, 12, 20); |
70 | *l0 = diff ? (void *)tb_ptr + diff : NULL; | |
92bc4fad RH |
71 | } |
72 | ||
6eea0434 RH |
73 | static void tci_args_r(uint32_t insn, TCGReg *r0) |
74 | { | |
75 | *r0 = extract32(insn, 8, 4); | |
76 | } | |
77 | ||
65089889 RH |
78 | static void tci_args_nl(uint32_t insn, const void *tb_ptr, |
79 | uint8_t *n0, void **l1) | |
f28ca03e | 80 | { |
65089889 RH |
81 | *n0 = extract32(insn, 8, 4); |
82 | *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr; | |
f28ca03e RH |
83 | } |
84 | ||
65089889 RH |
85 | static void tci_args_rl(uint32_t insn, const void *tb_ptr, |
86 | TCGReg *r0, void **l1) | |
7b7d8b2d | 87 | { |
65089889 RH |
88 | *r0 = extract32(insn, 8, 4); |
89 | *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr; | |
7b7d8b2d RH |
90 | } |
91 | ||
65089889 | 92 | static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1) |
fc8ec9e1 | 93 | { |
65089889 RH |
94 | *r0 = extract32(insn, 8, 4); |
95 | *r1 = extract32(insn, 12, 4); | |
fc8ec9e1 RH |
96 | } |
97 | ||
65089889 | 98 | static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1) |
fc4a62f6 | 99 | { |
65089889 RH |
100 | *r0 = extract32(insn, 8, 4); |
101 | *i1 = sextract32(insn, 12, 20); | |
fc4a62f6 RH |
102 | } |
103 | ||
65089889 | 104 | static void tci_args_rrm(uint32_t insn, TCGReg *r0, |
9002ffcb | 105 | TCGReg *r1, MemOpIdx *m2) |
b95aa12e | 106 | { |
65089889 RH |
107 | *r0 = extract32(insn, 8, 4); |
108 | *r1 = extract32(insn, 12, 4); | |
ab64da79 | 109 | *m2 = extract32(insn, 16, 16); |
b95aa12e RH |
110 | } |
111 | ||
65089889 | 112 | static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2) |
b95aa12e | 113 | { |
65089889 RH |
114 | *r0 = extract32(insn, 8, 4); |
115 | *r1 = extract32(insn, 12, 4); | |
116 | *r2 = extract32(insn, 16, 4); | |
b95aa12e | 117 | } |
b95aa12e | 118 | |
65089889 | 119 | static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2) |
63041ed2 | 120 | { |
65089889 RH |
121 | *r0 = extract32(insn, 8, 4); |
122 | *r1 = extract32(insn, 12, 4); | |
123 | *i2 = sextract32(insn, 16, 16); | |
63041ed2 RH |
124 | } |
125 | ||
0f10d7c5 RH |
126 | static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, |
127 | uint8_t *i2, uint8_t *i3) | |
128 | { | |
129 | *r0 = extract32(insn, 8, 4); | |
130 | *r1 = extract32(insn, 12, 4); | |
131 | *i2 = extract32(insn, 16, 6); | |
132 | *i3 = extract32(insn, 22, 6); | |
133 | } | |
134 | ||
65089889 | 135 | static void tci_args_rrrc(uint32_t insn, |
963e9fa2 RH |
136 | TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) |
137 | { | |
65089889 RH |
138 | *r0 = extract32(insn, 8, 4); |
139 | *r1 = extract32(insn, 12, 4); | |
140 | *r2 = extract32(insn, 16, 4); | |
141 | *c3 = extract32(insn, 20, 4); | |
963e9fa2 RH |
142 | } |
143 | ||
65089889 | 144 | static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, |
79dd3a4f RH |
145 | TCGReg *r2, uint8_t *i3, uint8_t *i4) |
146 | { | |
65089889 RH |
147 | *r0 = extract32(insn, 8, 4); |
148 | *r1 = extract32(insn, 12, 4); | |
149 | *r2 = extract32(insn, 16, 4); | |
150 | *i3 = extract32(insn, 20, 6); | |
151 | *i4 = extract32(insn, 26, 6); | |
79dd3a4f RH |
152 | } |
153 | ||
65089889 RH |
154 | static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, |
155 | TCGReg *r2, TCGReg *r3, TCGReg *r4) | |
63041ed2 | 156 | { |
65089889 RH |
157 | *r0 = extract32(insn, 8, 4); |
158 | *r1 = extract32(insn, 12, 4); | |
159 | *r2 = extract32(insn, 16, 4); | |
160 | *r3 = extract32(insn, 20, 4); | |
161 | *r4 = extract32(insn, 24, 4); | |
63041ed2 RH |
162 | } |
163 | ||
65089889 | 164 | static void tci_args_rrrr(uint32_t insn, |
cbe87131 RH |
165 | TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) |
166 | { | |
65089889 RH |
167 | *r0 = extract32(insn, 8, 4); |
168 | *r1 = extract32(insn, 12, 4); | |
169 | *r2 = extract32(insn, 16, 4); | |
170 | *r3 = extract32(insn, 20, 4); | |
cbe87131 RH |
171 | } |
172 | ||
65089889 | 173 | static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, |
817cadd6 RH |
174 | TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5) |
175 | { | |
65089889 RH |
176 | *r0 = extract32(insn, 8, 4); |
177 | *r1 = extract32(insn, 12, 4); | |
178 | *r2 = extract32(insn, 16, 4); | |
179 | *r3 = extract32(insn, 20, 4); | |
180 | *r4 = extract32(insn, 24, 4); | |
181 | *c5 = extract32(insn, 28, 4); | |
817cadd6 | 182 | } |
120402b5 | 183 | |
65089889 | 184 | static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, |
120402b5 RH |
185 | TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) |
186 | { | |
65089889 RH |
187 | *r0 = extract32(insn, 8, 4); |
188 | *r1 = extract32(insn, 12, 4); | |
189 | *r2 = extract32(insn, 16, 4); | |
190 | *r3 = extract32(insn, 20, 4); | |
191 | *r4 = extract32(insn, 24, 4); | |
192 | *r5 = extract32(insn, 28, 4); | |
120402b5 | 193 | } |
817cadd6 | 194 | |
7657f4bf SW |
195 | static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) |
196 | { | |
197 | bool result = false; | |
198 | int32_t i0 = u0; | |
199 | int32_t i1 = u1; | |
200 | switch (condition) { | |
201 | case TCG_COND_EQ: | |
202 | result = (u0 == u1); | |
203 | break; | |
204 | case TCG_COND_NE: | |
205 | result = (u0 != u1); | |
206 | break; | |
207 | case TCG_COND_LT: | |
208 | result = (i0 < i1); | |
209 | break; | |
210 | case TCG_COND_GE: | |
211 | result = (i0 >= i1); | |
212 | break; | |
213 | case TCG_COND_LE: | |
214 | result = (i0 <= i1); | |
215 | break; | |
216 | case TCG_COND_GT: | |
217 | result = (i0 > i1); | |
218 | break; | |
219 | case TCG_COND_LTU: | |
220 | result = (u0 < u1); | |
221 | break; | |
222 | case TCG_COND_GEU: | |
223 | result = (u0 >= u1); | |
224 | break; | |
225 | case TCG_COND_LEU: | |
226 | result = (u0 <= u1); | |
227 | break; | |
228 | case TCG_COND_GTU: | |
229 | result = (u0 > u1); | |
230 | break; | |
231 | default: | |
f6996f99 | 232 | g_assert_not_reached(); |
7657f4bf SW |
233 | } |
234 | return result; | |
235 | } | |
236 | ||
237 | static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) | |
238 | { | |
239 | bool result = false; | |
240 | int64_t i0 = u0; | |
241 | int64_t i1 = u1; | |
242 | switch (condition) { | |
243 | case TCG_COND_EQ: | |
244 | result = (u0 == u1); | |
245 | break; | |
246 | case TCG_COND_NE: | |
247 | result = (u0 != u1); | |
248 | break; | |
249 | case TCG_COND_LT: | |
250 | result = (i0 < i1); | |
251 | break; | |
252 | case TCG_COND_GE: | |
253 | result = (i0 >= i1); | |
254 | break; | |
255 | case TCG_COND_LE: | |
256 | result = (i0 <= i1); | |
257 | break; | |
258 | case TCG_COND_GT: | |
259 | result = (i0 > i1); | |
260 | break; | |
261 | case TCG_COND_LTU: | |
262 | result = (u0 < u1); | |
263 | break; | |
264 | case TCG_COND_GEU: | |
265 | result = (u0 >= u1); | |
266 | break; | |
267 | case TCG_COND_LEU: | |
268 | result = (u0 <= u1); | |
269 | break; | |
270 | case TCG_COND_GTU: | |
271 | result = (u0 > u1); | |
272 | break; | |
273 | default: | |
f6996f99 | 274 | g_assert_not_reached(); |
7657f4bf SW |
275 | } |
276 | return result; | |
277 | } | |
278 | ||
dd7dc93e | 279 | static uint64_t tci_qemu_ld(CPUArchState *env, uint64_t taddr, |
9002ffcb | 280 | MemOpIdx oi, const void *tb_ptr) |
69acc02a | 281 | { |
fe1bee3a | 282 | MemOp mop = get_memop(oi); |
d1b1348c RH |
283 | uintptr_t ra = (uintptr_t)tb_ptr; |
284 | ||
0cadc1ed | 285 | switch (mop & MO_SSIZE) { |
d1b1348c | 286 | case MO_UB: |
0cadc1ed | 287 | return helper_ldub_mmu(env, taddr, oi, ra); |
d1b1348c | 288 | case MO_SB: |
0cadc1ed RH |
289 | return helper_ldsb_mmu(env, taddr, oi, ra); |
290 | case MO_UW: | |
291 | return helper_lduw_mmu(env, taddr, oi, ra); | |
292 | case MO_SW: | |
293 | return helper_ldsw_mmu(env, taddr, oi, ra); | |
294 | case MO_UL: | |
295 | return helper_ldul_mmu(env, taddr, oi, ra); | |
296 | case MO_SL: | |
297 | return helper_ldsl_mmu(env, taddr, oi, ra); | |
298 | case MO_UQ: | |
299 | return helper_ldq_mmu(env, taddr, oi, ra); | |
d1b1348c RH |
300 | default: |
301 | g_assert_not_reached(); | |
302 | } | |
69acc02a RH |
303 | } |
304 | ||
dd7dc93e | 305 | static void tci_qemu_st(CPUArchState *env, uint64_t taddr, uint64_t val, |
9002ffcb | 306 | MemOpIdx oi, const void *tb_ptr) |
69acc02a | 307 | { |
fe1bee3a | 308 | MemOp mop = get_memop(oi); |
d1b1348c RH |
309 | uintptr_t ra = (uintptr_t)tb_ptr; |
310 | ||
0cadc1ed | 311 | switch (mop & MO_SIZE) { |
d1b1348c | 312 | case MO_UB: |
0cadc1ed | 313 | helper_stb_mmu(env, taddr, val, oi, ra); |
d1b1348c | 314 | break; |
0cadc1ed RH |
315 | case MO_UW: |
316 | helper_stw_mmu(env, taddr, val, oi, ra); | |
d1b1348c | 317 | break; |
0cadc1ed RH |
318 | case MO_UL: |
319 | helper_stl_mmu(env, taddr, val, oi, ra); | |
d1b1348c | 320 | break; |
0cadc1ed RH |
321 | case MO_UQ: |
322 | helper_stq_mmu(env, taddr, val, oi, ra); | |
d1b1348c RH |
323 | break; |
324 | default: | |
325 | g_assert_not_reached(); | |
326 | } | |
69acc02a RH |
327 | } |
328 | ||
7f33f5cd RH |
329 | #if TCG_TARGET_REG_BITS == 64 |
330 | # define CASE_32_64(x) \ | |
331 | case glue(glue(INDEX_op_, x), _i64): \ | |
332 | case glue(glue(INDEX_op_, x), _i32): | |
333 | # define CASE_64(x) \ | |
334 | case glue(glue(INDEX_op_, x), _i64): | |
335 | #else | |
336 | # define CASE_32_64(x) \ | |
337 | case glue(glue(INDEX_op_, x), _i32): | |
338 | # define CASE_64(x) | |
339 | #endif | |
340 | ||
7657f4bf | 341 | /* Interpret pseudo code in tb. */ |
c905a368 DB |
342 | /* |
343 | * Disable CFI checks. | |
344 | * One possible operation in the pseudo code is a call to binary code. | |
345 | * Therefore, disable CFI checks in the interpreter function | |
346 | */ | |
db0c51a3 RH |
347 | uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, |
348 | const void *v_tb_ptr) | |
7657f4bf | 349 | { |
65089889 | 350 | const uint32_t *tb_ptr = v_tb_ptr; |
5e75150c | 351 | tcg_target_ulong regs[TCG_TARGET_NB_REGS]; |
7b7d8b2d RH |
352 | uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) |
353 | / sizeof(uint64_t)]; | |
7657f4bf | 354 | |
5e75150c | 355 | regs[TCG_AREG0] = (tcg_target_ulong)env; |
7b7d8b2d | 356 | regs[TCG_REG_CALL_STACK] = (uintptr_t)stack; |
3ccdbecf | 357 | tci_assert(tb_ptr); |
7657f4bf SW |
358 | |
359 | for (;;) { | |
65089889 RH |
360 | uint32_t insn; |
361 | TCGOpcode opc; | |
08096b1a | 362 | TCGReg r0, r1, r2, r3, r4, r5; |
7657f4bf | 363 | tcg_target_ulong t1; |
7657f4bf | 364 | TCGCond condition; |
79dd3a4f | 365 | uint8_t pos, len; |
7657f4bf | 366 | uint32_t tmp32; |
dd7dc93e | 367 | uint64_t tmp64, taddr; |
5a0adf34 | 368 | uint64_t T1, T2; |
9002ffcb | 369 | MemOpIdx oi; |
cdd9799b | 370 | int32_t ofs; |
65089889 | 371 | void *ptr; |
7657f4bf | 372 | |
65089889 RH |
373 | insn = *tb_ptr++; |
374 | opc = extract32(insn, 0, 8); | |
7657f4bf SW |
375 | |
376 | switch (opc) { | |
7657f4bf | 377 | case INDEX_op_call: |
e9709e17 RH |
378 | { |
379 | void *call_slots[MAX_CALL_IARGS]; | |
380 | ffi_cif *cif; | |
381 | void *func; | |
382 | unsigned i, s, n; | |
383 | ||
384 | tci_args_nl(insn, tb_ptr, &len, &ptr); | |
385 | func = ((void **)ptr)[0]; | |
386 | cif = ((void **)ptr)[1]; | |
387 | ||
388 | n = cif->nargs; | |
389 | for (i = s = 0; i < n; ++i) { | |
390 | ffi_type *t = cif->arg_types[i]; | |
391 | call_slots[i] = &stack[s]; | |
392 | s += DIV_ROUND_UP(t->size, 8); | |
7b7d8b2d | 393 | } |
7b7d8b2d | 394 | |
e9709e17 RH |
395 | /* Helper functions may need to access the "return address" */ |
396 | tci_tb_ptr = (uintptr_t)tb_ptr; | |
397 | ffi_call(cif, func, stack, call_slots); | |
65089889 | 398 | } |
7b7d8b2d | 399 | |
7b7d8b2d RH |
400 | switch (len) { |
401 | case 0: /* void */ | |
402 | break; | |
403 | case 1: /* uint32_t */ | |
404 | /* | |
896c76e6 | 405 | * The result winds up "left-aligned" in the stack[0] slot. |
7b7d8b2d RH |
406 | * Note that libffi has an odd special case in that it will |
407 | * always widen an integral result to ffi_arg. | |
408 | */ | |
896c76e6 RH |
409 | if (sizeof(ffi_arg) == 8) { |
410 | regs[TCG_REG_R0] = (uint32_t)stack[0]; | |
411 | } else { | |
7b7d8b2d | 412 | regs[TCG_REG_R0] = *(uint32_t *)stack; |
7b7d8b2d | 413 | } |
896c76e6 | 414 | break; |
7b7d8b2d | 415 | case 2: /* uint64_t */ |
896c76e6 RH |
416 | /* |
417 | * For TCG_TARGET_REG_BITS == 32, the register pair | |
418 | * must stay in host memory order. | |
419 | */ | |
420 | memcpy(®s[TCG_REG_R0], stack, 8); | |
7b7d8b2d | 421 | break; |
e9709e17 RH |
422 | case 3: /* Int128 */ |
423 | memcpy(®s[TCG_REG_R0], stack, 16); | |
424 | break; | |
7b7d8b2d RH |
425 | default: |
426 | g_assert_not_reached(); | |
427 | } | |
7657f4bf | 428 | break; |
7b7d8b2d | 429 | |
7657f4bf | 430 | case INDEX_op_br: |
65089889 | 431 | tci_args_l(insn, tb_ptr, &ptr); |
f28ca03e | 432 | tb_ptr = ptr; |
7657f4bf SW |
433 | continue; |
434 | case INDEX_op_setcond_i32: | |
65089889 | 435 | tci_args_rrrc(insn, &r0, &r1, &r2, &condition); |
963e9fa2 | 436 | regs[r0] = tci_compare32(regs[r1], regs[r2], condition); |
7657f4bf | 437 | break; |
df093c19 RH |
438 | case INDEX_op_movcond_i32: |
439 | tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); | |
440 | tmp32 = tci_compare32(regs[r1], regs[r2], condition); | |
441 | regs[r0] = regs[tmp32 ? r3 : r4]; | |
442 | break; | |
7657f4bf SW |
443 | #if TCG_TARGET_REG_BITS == 32 |
444 | case INDEX_op_setcond2_i32: | |
65089889 | 445 | tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); |
817cadd6 RH |
446 | T1 = tci_uint64(regs[r2], regs[r1]); |
447 | T2 = tci_uint64(regs[r4], regs[r3]); | |
448 | regs[r0] = tci_compare64(T1, T2, condition); | |
7657f4bf SW |
449 | break; |
450 | #elif TCG_TARGET_REG_BITS == 64 | |
451 | case INDEX_op_setcond_i64: | |
65089889 | 452 | tci_args_rrrc(insn, &r0, &r1, &r2, &condition); |
963e9fa2 | 453 | regs[r0] = tci_compare64(regs[r1], regs[r2], condition); |
7657f4bf | 454 | break; |
df093c19 RH |
455 | case INDEX_op_movcond_i64: |
456 | tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); | |
457 | tmp32 = tci_compare64(regs[r1], regs[r2], condition); | |
458 | regs[r0] = regs[tmp32 ? r3 : r4]; | |
459 | break; | |
7657f4bf | 460 | #endif |
9e9acb7b | 461 | CASE_32_64(mov) |
65089889 | 462 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 463 | regs[r0] = regs[r1]; |
7657f4bf | 464 | break; |
65089889 RH |
465 | case INDEX_op_tci_movi: |
466 | tci_args_ri(insn, &r0, &t1); | |
b95aa12e | 467 | regs[r0] = t1; |
7657f4bf | 468 | break; |
65089889 RH |
469 | case INDEX_op_tci_movl: |
470 | tci_args_rl(insn, tb_ptr, &r0, &ptr); | |
471 | regs[r0] = *(tcg_target_ulong *)ptr; | |
472 | break; | |
7657f4bf SW |
473 | |
474 | /* Load/store operations (32 bit). */ | |
475 | ||
7f33f5cd | 476 | CASE_32_64(ld8u) |
65089889 | 477 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
478 | ptr = (void *)(regs[r1] + ofs); |
479 | regs[r0] = *(uint8_t *)ptr; | |
7657f4bf | 480 | break; |
850163eb | 481 | CASE_32_64(ld8s) |
65089889 | 482 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
483 | ptr = (void *)(regs[r1] + ofs); |
484 | regs[r0] = *(int8_t *)ptr; | |
2f160e0f | 485 | break; |
77c38c7c | 486 | CASE_32_64(ld16u) |
65089889 | 487 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
488 | ptr = (void *)(regs[r1] + ofs); |
489 | regs[r0] = *(uint16_t *)ptr; | |
7657f4bf | 490 | break; |
b09d78bf | 491 | CASE_32_64(ld16s) |
65089889 | 492 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
493 | ptr = (void *)(regs[r1] + ofs); |
494 | regs[r0] = *(int16_t *)ptr; | |
7657f4bf SW |
495 | break; |
496 | case INDEX_op_ld_i32: | |
c1d77e94 | 497 | CASE_64(ld32u) |
65089889 | 498 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
499 | ptr = (void *)(regs[r1] + ofs); |
500 | regs[r0] = *(uint32_t *)ptr; | |
7657f4bf | 501 | break; |
ba9a80c1 | 502 | CASE_32_64(st8) |
65089889 | 503 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
504 | ptr = (void *)(regs[r1] + ofs); |
505 | *(uint8_t *)ptr = regs[r0]; | |
7657f4bf | 506 | break; |
90be4dde | 507 | CASE_32_64(st16) |
65089889 | 508 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
509 | ptr = (void *)(regs[r1] + ofs); |
510 | *(uint16_t *)ptr = regs[r0]; | |
7657f4bf SW |
511 | break; |
512 | case INDEX_op_st_i32: | |
b4d5bf0f | 513 | CASE_64(st32) |
65089889 | 514 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
515 | ptr = (void *)(regs[r1] + ofs); |
516 | *(uint32_t *)ptr = regs[r0]; | |
7657f4bf SW |
517 | break; |
518 | ||
dd2bb20e | 519 | /* Arithmetic operations (mixed 32/64 bit). */ |
7657f4bf | 520 | |
dd2bb20e | 521 | CASE_32_64(add) |
65089889 | 522 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 523 | regs[r0] = regs[r1] + regs[r2]; |
7657f4bf | 524 | break; |
dd2bb20e | 525 | CASE_32_64(sub) |
65089889 | 526 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 527 | regs[r0] = regs[r1] - regs[r2]; |
7657f4bf | 528 | break; |
dd2bb20e | 529 | CASE_32_64(mul) |
65089889 | 530 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 531 | regs[r0] = regs[r1] * regs[r2]; |
7657f4bf | 532 | break; |
dd2bb20e | 533 | CASE_32_64(and) |
65089889 | 534 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 535 | regs[r0] = regs[r1] & regs[r2]; |
7657f4bf | 536 | break; |
dd2bb20e | 537 | CASE_32_64(or) |
65089889 | 538 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 539 | regs[r0] = regs[r1] | regs[r2]; |
7657f4bf | 540 | break; |
dd2bb20e | 541 | CASE_32_64(xor) |
65089889 | 542 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 543 | regs[r0] = regs[r1] ^ regs[r2]; |
7657f4bf | 544 | break; |
a81520b9 RH |
545 | #if TCG_TARGET_HAS_andc_i32 || TCG_TARGET_HAS_andc_i64 |
546 | CASE_32_64(andc) | |
547 | tci_args_rrr(insn, &r0, &r1, &r2); | |
548 | regs[r0] = regs[r1] & ~regs[r2]; | |
549 | break; | |
550 | #endif | |
551 | #if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64 | |
552 | CASE_32_64(orc) | |
553 | tci_args_rrr(insn, &r0, &r1, &r2); | |
554 | regs[r0] = regs[r1] | ~regs[r2]; | |
555 | break; | |
556 | #endif | |
557 | #if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64 | |
558 | CASE_32_64(eqv) | |
559 | tci_args_rrr(insn, &r0, &r1, &r2); | |
560 | regs[r0] = ~(regs[r1] ^ regs[r2]); | |
561 | break; | |
562 | #endif | |
563 | #if TCG_TARGET_HAS_nand_i32 || TCG_TARGET_HAS_nand_i64 | |
564 | CASE_32_64(nand) | |
565 | tci_args_rrr(insn, &r0, &r1, &r2); | |
566 | regs[r0] = ~(regs[r1] & regs[r2]); | |
567 | break; | |
568 | #endif | |
569 | #if TCG_TARGET_HAS_nor_i32 || TCG_TARGET_HAS_nor_i64 | |
570 | CASE_32_64(nor) | |
571 | tci_args_rrr(insn, &r0, &r1, &r2); | |
572 | regs[r0] = ~(regs[r1] | regs[r2]); | |
573 | break; | |
574 | #endif | |
dd2bb20e RH |
575 | |
576 | /* Arithmetic operations (32 bit). */ | |
577 | ||
578 | case INDEX_op_div_i32: | |
65089889 | 579 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 580 | regs[r0] = (int32_t)regs[r1] / (int32_t)regs[r2]; |
7657f4bf | 581 | break; |
dd2bb20e | 582 | case INDEX_op_divu_i32: |
65089889 | 583 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 584 | regs[r0] = (uint32_t)regs[r1] / (uint32_t)regs[r2]; |
7657f4bf | 585 | break; |
dd2bb20e | 586 | case INDEX_op_rem_i32: |
65089889 | 587 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 588 | regs[r0] = (int32_t)regs[r1] % (int32_t)regs[r2]; |
7657f4bf | 589 | break; |
dd2bb20e | 590 | case INDEX_op_remu_i32: |
65089889 | 591 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 592 | regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2]; |
7657f4bf | 593 | break; |
5255f48c RH |
594 | #if TCG_TARGET_HAS_clz_i32 |
595 | case INDEX_op_clz_i32: | |
596 | tci_args_rrr(insn, &r0, &r1, &r2); | |
597 | tmp32 = regs[r1]; | |
598 | regs[r0] = tmp32 ? clz32(tmp32) : regs[r2]; | |
599 | break; | |
600 | #endif | |
601 | #if TCG_TARGET_HAS_ctz_i32 | |
602 | case INDEX_op_ctz_i32: | |
603 | tci_args_rrr(insn, &r0, &r1, &r2); | |
604 | tmp32 = regs[r1]; | |
605 | regs[r0] = tmp32 ? ctz32(tmp32) : regs[r2]; | |
606 | break; | |
607 | #endif | |
608 | #if TCG_TARGET_HAS_ctpop_i32 | |
609 | case INDEX_op_ctpop_i32: | |
610 | tci_args_rr(insn, &r0, &r1); | |
611 | regs[r0] = ctpop32(regs[r1]); | |
612 | break; | |
613 | #endif | |
7657f4bf SW |
614 | |
615 | /* Shift/rotate operations (32 bit). */ | |
616 | ||
617 | case INDEX_op_shl_i32: | |
65089889 | 618 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 619 | regs[r0] = (uint32_t)regs[r1] << (regs[r2] & 31); |
7657f4bf SW |
620 | break; |
621 | case INDEX_op_shr_i32: | |
65089889 | 622 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 623 | regs[r0] = (uint32_t)regs[r1] >> (regs[r2] & 31); |
7657f4bf SW |
624 | break; |
625 | case INDEX_op_sar_i32: | |
65089889 | 626 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 627 | regs[r0] = (int32_t)regs[r1] >> (regs[r2] & 31); |
7657f4bf SW |
628 | break; |
629 | #if TCG_TARGET_HAS_rot_i32 | |
630 | case INDEX_op_rotl_i32: | |
65089889 | 631 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 632 | regs[r0] = rol32(regs[r1], regs[r2] & 31); |
7657f4bf SW |
633 | break; |
634 | case INDEX_op_rotr_i32: | |
65089889 | 635 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 636 | regs[r0] = ror32(regs[r1], regs[r2] & 31); |
7657f4bf | 637 | break; |
e24dc9fe SW |
638 | #endif |
639 | #if TCG_TARGET_HAS_deposit_i32 | |
640 | case INDEX_op_deposit_i32: | |
65089889 | 641 | tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); |
79dd3a4f | 642 | regs[r0] = deposit32(regs[r1], pos, len, regs[r2]); |
e24dc9fe | 643 | break; |
0f10d7c5 RH |
644 | #endif |
645 | #if TCG_TARGET_HAS_extract_i32 | |
646 | case INDEX_op_extract_i32: | |
647 | tci_args_rrbb(insn, &r0, &r1, &pos, &len); | |
648 | regs[r0] = extract32(regs[r1], pos, len); | |
649 | break; | |
650 | #endif | |
651 | #if TCG_TARGET_HAS_sextract_i32 | |
652 | case INDEX_op_sextract_i32: | |
653 | tci_args_rrbb(insn, &r0, &r1, &pos, &len); | |
654 | regs[r0] = sextract32(regs[r1], pos, len); | |
655 | break; | |
7657f4bf SW |
656 | #endif |
657 | case INDEX_op_brcond_i32: | |
65089889 | 658 | tci_args_rl(insn, tb_ptr, &r0, &ptr); |
fc8ec9e1 | 659 | if ((uint32_t)regs[r0]) { |
5a0adf34 | 660 | tb_ptr = ptr; |
7657f4bf SW |
661 | } |
662 | break; | |
08096b1a | 663 | #if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_add2_i32 |
7657f4bf | 664 | case INDEX_op_add2_i32: |
65089889 | 665 | tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); |
120402b5 RH |
666 | T1 = tci_uint64(regs[r3], regs[r2]); |
667 | T2 = tci_uint64(regs[r5], regs[r4]); | |
668 | tci_write_reg64(regs, r1, r0, T1 + T2); | |
7657f4bf | 669 | break; |
08096b1a RH |
670 | #endif |
671 | #if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_sub2_i32 | |
7657f4bf | 672 | case INDEX_op_sub2_i32: |
65089889 | 673 | tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); |
120402b5 RH |
674 | T1 = tci_uint64(regs[r3], regs[r2]); |
675 | T2 = tci_uint64(regs[r5], regs[r4]); | |
676 | tci_write_reg64(regs, r1, r0, T1 - T2); | |
7657f4bf | 677 | break; |
08096b1a | 678 | #endif |
f6db0d8d | 679 | #if TCG_TARGET_HAS_mulu2_i32 |
7657f4bf | 680 | case INDEX_op_mulu2_i32: |
65089889 | 681 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); |
f6db0d8d RH |
682 | tmp64 = (uint64_t)(uint32_t)regs[r2] * (uint32_t)regs[r3]; |
683 | tci_write_reg64(regs, r1, r0, tmp64); | |
7657f4bf | 684 | break; |
f6db0d8d RH |
685 | #endif |
686 | #if TCG_TARGET_HAS_muls2_i32 | |
687 | case INDEX_op_muls2_i32: | |
688 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); | |
689 | tmp64 = (int64_t)(int32_t)regs[r2] * (int32_t)regs[r3]; | |
690 | tci_write_reg64(regs, r1, r0, tmp64); | |
691 | break; | |
692 | #endif | |
13a1d640 RH |
693 | #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 |
694 | CASE_32_64(ext8s) | |
65089889 | 695 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 696 | regs[r0] = (int8_t)regs[r1]; |
7657f4bf SW |
697 | break; |
698 | #endif | |
0d57d36a RH |
699 | #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 || \ |
700 | TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 | |
13a1d640 | 701 | CASE_32_64(ext16s) |
65089889 | 702 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 703 | regs[r0] = (int16_t)regs[r1]; |
7657f4bf SW |
704 | break; |
705 | #endif | |
13a1d640 RH |
706 | #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 |
707 | CASE_32_64(ext8u) | |
65089889 | 708 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 709 | regs[r0] = (uint8_t)regs[r1]; |
7657f4bf SW |
710 | break; |
711 | #endif | |
13a1d640 RH |
712 | #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 |
713 | CASE_32_64(ext16u) | |
65089889 | 714 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 715 | regs[r0] = (uint16_t)regs[r1]; |
7657f4bf SW |
716 | break; |
717 | #endif | |
fe2b13bb RH |
718 | #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 |
719 | CASE_32_64(bswap16) | |
65089889 | 720 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 721 | regs[r0] = bswap16(regs[r1]); |
7657f4bf SW |
722 | break; |
723 | #endif | |
fe2b13bb RH |
724 | #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 |
725 | CASE_32_64(bswap32) | |
65089889 | 726 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 727 | regs[r0] = bswap32(regs[r1]); |
7657f4bf SW |
728 | break; |
729 | #endif | |
9e9acb7b RH |
730 | #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 |
731 | CASE_32_64(not) | |
65089889 | 732 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 733 | regs[r0] = ~regs[r1]; |
7657f4bf SW |
734 | break; |
735 | #endif | |
9e9acb7b RH |
736 | #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 |
737 | CASE_32_64(neg) | |
65089889 | 738 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 739 | regs[r0] = -regs[r1]; |
7657f4bf SW |
740 | break; |
741 | #endif | |
742 | #if TCG_TARGET_REG_BITS == 64 | |
7657f4bf SW |
743 | /* Load/store operations (64 bit). */ |
744 | ||
7657f4bf | 745 | case INDEX_op_ld32s_i64: |
65089889 | 746 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
747 | ptr = (void *)(regs[r1] + ofs); |
748 | regs[r0] = *(int32_t *)ptr; | |
7657f4bf SW |
749 | break; |
750 | case INDEX_op_ld_i64: | |
65089889 | 751 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
752 | ptr = (void *)(regs[r1] + ofs); |
753 | regs[r0] = *(uint64_t *)ptr; | |
7657f4bf | 754 | break; |
7657f4bf | 755 | case INDEX_op_st_i64: |
65089889 | 756 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
757 | ptr = (void *)(regs[r1] + ofs); |
758 | *(uint64_t *)ptr = regs[r0]; | |
7657f4bf SW |
759 | break; |
760 | ||
761 | /* Arithmetic operations (64 bit). */ | |
762 | ||
7657f4bf | 763 | case INDEX_op_div_i64: |
65089889 | 764 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 765 | regs[r0] = (int64_t)regs[r1] / (int64_t)regs[r2]; |
ae40c098 | 766 | break; |
7657f4bf | 767 | case INDEX_op_divu_i64: |
65089889 | 768 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 769 | regs[r0] = (uint64_t)regs[r1] / (uint64_t)regs[r2]; |
ae40c098 | 770 | break; |
7657f4bf | 771 | case INDEX_op_rem_i64: |
65089889 | 772 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 773 | regs[r0] = (int64_t)regs[r1] % (int64_t)regs[r2]; |
ae40c098 | 774 | break; |
7657f4bf | 775 | case INDEX_op_remu_i64: |
65089889 | 776 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 777 | regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2]; |
7657f4bf | 778 | break; |
5255f48c RH |
779 | #if TCG_TARGET_HAS_clz_i64 |
780 | case INDEX_op_clz_i64: | |
781 | tci_args_rrr(insn, &r0, &r1, &r2); | |
782 | regs[r0] = regs[r1] ? clz64(regs[r1]) : regs[r2]; | |
783 | break; | |
784 | #endif | |
785 | #if TCG_TARGET_HAS_ctz_i64 | |
786 | case INDEX_op_ctz_i64: | |
787 | tci_args_rrr(insn, &r0, &r1, &r2); | |
788 | regs[r0] = regs[r1] ? ctz64(regs[r1]) : regs[r2]; | |
789 | break; | |
790 | #endif | |
791 | #if TCG_TARGET_HAS_ctpop_i64 | |
792 | case INDEX_op_ctpop_i64: | |
793 | tci_args_rr(insn, &r0, &r1); | |
794 | regs[r0] = ctpop64(regs[r1]); | |
795 | break; | |
796 | #endif | |
f6db0d8d RH |
797 | #if TCG_TARGET_HAS_mulu2_i64 |
798 | case INDEX_op_mulu2_i64: | |
799 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); | |
800 | mulu64(®s[r0], ®s[r1], regs[r2], regs[r3]); | |
801 | break; | |
802 | #endif | |
803 | #if TCG_TARGET_HAS_muls2_i64 | |
804 | case INDEX_op_muls2_i64: | |
805 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); | |
806 | muls64(®s[r0], ®s[r1], regs[r2], regs[r3]); | |
807 | break; | |
808 | #endif | |
08096b1a RH |
809 | #if TCG_TARGET_HAS_add2_i64 |
810 | case INDEX_op_add2_i64: | |
811 | tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); | |
812 | T1 = regs[r2] + regs[r4]; | |
813 | T2 = regs[r3] + regs[r5] + (T1 < regs[r2]); | |
814 | regs[r0] = T1; | |
815 | regs[r1] = T2; | |
816 | break; | |
817 | #endif | |
818 | #if TCG_TARGET_HAS_add2_i64 | |
819 | case INDEX_op_sub2_i64: | |
820 | tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); | |
821 | T1 = regs[r2] - regs[r4]; | |
822 | T2 = regs[r3] - regs[r5] - (regs[r2] < regs[r4]); | |
823 | regs[r0] = T1; | |
824 | regs[r1] = T2; | |
825 | break; | |
826 | #endif | |
7657f4bf SW |
827 | |
828 | /* Shift/rotate operations (64 bit). */ | |
829 | ||
830 | case INDEX_op_shl_i64: | |
65089889 | 831 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 832 | regs[r0] = regs[r1] << (regs[r2] & 63); |
7657f4bf SW |
833 | break; |
834 | case INDEX_op_shr_i64: | |
65089889 | 835 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 836 | regs[r0] = regs[r1] >> (regs[r2] & 63); |
7657f4bf SW |
837 | break; |
838 | case INDEX_op_sar_i64: | |
65089889 | 839 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 840 | regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63); |
7657f4bf SW |
841 | break; |
842 | #if TCG_TARGET_HAS_rot_i64 | |
843 | case INDEX_op_rotl_i64: | |
65089889 | 844 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 845 | regs[r0] = rol64(regs[r1], regs[r2] & 63); |
d285bf78 | 846 | break; |
7657f4bf | 847 | case INDEX_op_rotr_i64: |
65089889 | 848 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 849 | regs[r0] = ror64(regs[r1], regs[r2] & 63); |
7657f4bf | 850 | break; |
e24dc9fe SW |
851 | #endif |
852 | #if TCG_TARGET_HAS_deposit_i64 | |
853 | case INDEX_op_deposit_i64: | |
65089889 | 854 | tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); |
79dd3a4f | 855 | regs[r0] = deposit64(regs[r1], pos, len, regs[r2]); |
e24dc9fe | 856 | break; |
0f10d7c5 RH |
857 | #endif |
858 | #if TCG_TARGET_HAS_extract_i64 | |
859 | case INDEX_op_extract_i64: | |
860 | tci_args_rrbb(insn, &r0, &r1, &pos, &len); | |
861 | regs[r0] = extract64(regs[r1], pos, len); | |
862 | break; | |
863 | #endif | |
864 | #if TCG_TARGET_HAS_sextract_i64 | |
865 | case INDEX_op_sextract_i64: | |
866 | tci_args_rrbb(insn, &r0, &r1, &pos, &len); | |
867 | regs[r0] = sextract64(regs[r1], pos, len); | |
868 | break; | |
7657f4bf SW |
869 | #endif |
870 | case INDEX_op_brcond_i64: | |
65089889 | 871 | tci_args_rl(insn, tb_ptr, &r0, &ptr); |
fc8ec9e1 | 872 | if (regs[r0]) { |
5a0adf34 | 873 | tb_ptr = ptr; |
7657f4bf SW |
874 | } |
875 | break; | |
7657f4bf | 876 | case INDEX_op_ext32s_i64: |
4f2331e5 | 877 | case INDEX_op_ext_i32_i64: |
65089889 | 878 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 879 | regs[r0] = (int32_t)regs[r1]; |
7657f4bf | 880 | break; |
7657f4bf | 881 | case INDEX_op_ext32u_i64: |
4f2331e5 | 882 | case INDEX_op_extu_i32_i64: |
65089889 | 883 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 884 | regs[r0] = (uint32_t)regs[r1]; |
7657f4bf | 885 | break; |
7657f4bf SW |
886 | #if TCG_TARGET_HAS_bswap64_i64 |
887 | case INDEX_op_bswap64_i64: | |
65089889 | 888 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 889 | regs[r0] = bswap64(regs[r1]); |
7657f4bf SW |
890 | break; |
891 | #endif | |
7657f4bf SW |
892 | #endif /* TCG_TARGET_REG_BITS == 64 */ |
893 | ||
894 | /* QEMU specific operations. */ | |
895 | ||
7657f4bf | 896 | case INDEX_op_exit_tb: |
65089889 | 897 | tci_args_l(insn, tb_ptr, &ptr); |
158d3873 RH |
898 | return (uintptr_t)ptr; |
899 | ||
7657f4bf | 900 | case INDEX_op_goto_tb: |
65089889 | 901 | tci_args_l(insn, tb_ptr, &ptr); |
1670a2b9 | 902 | tb_ptr = *(void **)ptr; |
92bc4fad | 903 | break; |
1670a2b9 | 904 | |
6eea0434 RH |
905 | case INDEX_op_goto_ptr: |
906 | tci_args_r(insn, &r0); | |
907 | ptr = (void *)regs[r0]; | |
908 | if (!ptr) { | |
909 | return 0; | |
910 | } | |
911 | tb_ptr = ptr; | |
912 | break; | |
913 | ||
fecccfcc | 914 | case INDEX_op_qemu_ld_a32_i32: |
dd7dc93e RH |
915 | tci_args_rrm(insn, &r0, &r1, &oi); |
916 | taddr = (uint32_t)regs[r1]; | |
917 | goto do_ld_i32; | |
fecccfcc | 918 | case INDEX_op_qemu_ld_a64_i32: |
dd7dc93e | 919 | if (TCG_TARGET_REG_BITS == 64) { |
65089889 | 920 | tci_args_rrm(insn, &r0, &r1, &oi); |
63041ed2 RH |
921 | taddr = regs[r1]; |
922 | } else { | |
ab64da79 | 923 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); |
63041ed2 | 924 | taddr = tci_uint64(regs[r2], regs[r1]); |
ab64da79 | 925 | oi = regs[r3]; |
63041ed2 | 926 | } |
dd7dc93e RH |
927 | do_ld_i32: |
928 | regs[r0] = tci_qemu_ld(env, taddr, oi, tb_ptr); | |
7657f4bf | 929 | break; |
63041ed2 | 930 | |
fecccfcc | 931 | case INDEX_op_qemu_ld_a32_i64: |
dd7dc93e RH |
932 | if (TCG_TARGET_REG_BITS == 64) { |
933 | tci_args_rrm(insn, &r0, &r1, &oi); | |
934 | taddr = (uint32_t)regs[r1]; | |
935 | } else { | |
ab64da79 | 936 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); |
dd7dc93e | 937 | taddr = (uint32_t)regs[r2]; |
ab64da79 | 938 | oi = regs[r3]; |
dd7dc93e RH |
939 | } |
940 | goto do_ld_i64; | |
fecccfcc | 941 | case INDEX_op_qemu_ld_a64_i64: |
63041ed2 | 942 | if (TCG_TARGET_REG_BITS == 64) { |
65089889 | 943 | tci_args_rrm(insn, &r0, &r1, &oi); |
63041ed2 | 944 | taddr = regs[r1]; |
63041ed2 | 945 | } else { |
65089889 | 946 | tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); |
63041ed2 | 947 | taddr = tci_uint64(regs[r3], regs[r2]); |
65089889 | 948 | oi = regs[r4]; |
76782fab | 949 | } |
dd7dc93e | 950 | do_ld_i64: |
69acc02a | 951 | tmp64 = tci_qemu_ld(env, taddr, oi, tb_ptr); |
76782fab | 952 | if (TCG_TARGET_REG_BITS == 32) { |
63041ed2 RH |
953 | tci_write_reg64(regs, r1, r0, tmp64); |
954 | } else { | |
955 | regs[r0] = tmp64; | |
76782fab | 956 | } |
7657f4bf | 957 | break; |
63041ed2 | 958 | |
fecccfcc | 959 | case INDEX_op_qemu_st_a32_i32: |
dd7dc93e RH |
960 | tci_args_rrm(insn, &r0, &r1, &oi); |
961 | taddr = (uint32_t)regs[r1]; | |
962 | goto do_st_i32; | |
fecccfcc | 963 | case INDEX_op_qemu_st_a64_i32: |
dd7dc93e | 964 | if (TCG_TARGET_REG_BITS == 64) { |
65089889 | 965 | tci_args_rrm(insn, &r0, &r1, &oi); |
63041ed2 RH |
966 | taddr = regs[r1]; |
967 | } else { | |
ab64da79 | 968 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); |
63041ed2 | 969 | taddr = tci_uint64(regs[r2], regs[r1]); |
ab64da79 | 970 | oi = regs[r3]; |
63041ed2 | 971 | } |
dd7dc93e RH |
972 | do_st_i32: |
973 | tci_qemu_st(env, taddr, regs[r0], oi, tb_ptr); | |
7657f4bf | 974 | break; |
63041ed2 | 975 | |
fecccfcc | 976 | case INDEX_op_qemu_st_a32_i64: |
dd7dc93e RH |
977 | if (TCG_TARGET_REG_BITS == 64) { |
978 | tci_args_rrm(insn, &r0, &r1, &oi); | |
979 | tmp64 = regs[r0]; | |
980 | taddr = (uint32_t)regs[r1]; | |
981 | } else { | |
ab64da79 | 982 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); |
dd7dc93e RH |
983 | tmp64 = tci_uint64(regs[r1], regs[r0]); |
984 | taddr = (uint32_t)regs[r2]; | |
ab64da79 | 985 | oi = regs[r3]; |
dd7dc93e RH |
986 | } |
987 | goto do_st_i64; | |
fecccfcc | 988 | case INDEX_op_qemu_st_a64_i64: |
63041ed2 | 989 | if (TCG_TARGET_REG_BITS == 64) { |
65089889 | 990 | tci_args_rrm(insn, &r0, &r1, &oi); |
63041ed2 | 991 | tmp64 = regs[r0]; |
dd7dc93e | 992 | taddr = regs[r1]; |
63041ed2 | 993 | } else { |
dd7dc93e | 994 | tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); |
63041ed2 | 995 | tmp64 = tci_uint64(regs[r1], regs[r0]); |
dd7dc93e RH |
996 | taddr = tci_uint64(regs[r3], regs[r2]); |
997 | oi = regs[r4]; | |
63041ed2 | 998 | } |
dd7dc93e | 999 | do_st_i64: |
69acc02a | 1000 | tci_qemu_st(env, taddr, tmp64, oi, tb_ptr); |
7657f4bf | 1001 | break; |
63041ed2 | 1002 | |
a1e69e2f PK |
1003 | case INDEX_op_mb: |
1004 | /* Ensure ordering for all kinds */ | |
1005 | smp_mb(); | |
1006 | break; | |
7657f4bf | 1007 | default: |
f6996f99 | 1008 | g_assert_not_reached(); |
7657f4bf | 1009 | } |
7657f4bf | 1010 | } |
7657f4bf | 1011 | } |
59964b4f RH |
1012 | |
1013 | /* | |
1014 | * Disassembler that matches the interpreter | |
1015 | */ | |
1016 | ||
1017 | static const char *str_r(TCGReg r) | |
1018 | { | |
1019 | static const char regs[TCG_TARGET_NB_REGS][4] = { | |
1020 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
1021 | "r8", "r9", "r10", "r11", "r12", "r13", "env", "sp" | |
1022 | }; | |
1023 | ||
1024 | QEMU_BUILD_BUG_ON(TCG_AREG0 != TCG_REG_R14); | |
1025 | QEMU_BUILD_BUG_ON(TCG_REG_CALL_STACK != TCG_REG_R15); | |
1026 | ||
1027 | assert((unsigned)r < TCG_TARGET_NB_REGS); | |
1028 | return regs[r]; | |
1029 | } | |
1030 | ||
1031 | static const char *str_c(TCGCond c) | |
1032 | { | |
1033 | static const char cond[16][8] = { | |
1034 | [TCG_COND_NEVER] = "never", | |
1035 | [TCG_COND_ALWAYS] = "always", | |
1036 | [TCG_COND_EQ] = "eq", | |
1037 | [TCG_COND_NE] = "ne", | |
1038 | [TCG_COND_LT] = "lt", | |
1039 | [TCG_COND_GE] = "ge", | |
1040 | [TCG_COND_LE] = "le", | |
1041 | [TCG_COND_GT] = "gt", | |
1042 | [TCG_COND_LTU] = "ltu", | |
1043 | [TCG_COND_GEU] = "geu", | |
1044 | [TCG_COND_LEU] = "leu", | |
1045 | [TCG_COND_GTU] = "gtu", | |
1046 | }; | |
1047 | ||
1048 | assert((unsigned)c < ARRAY_SIZE(cond)); | |
1049 | assert(cond[c][0] != 0); | |
1050 | return cond[c]; | |
1051 | } | |
1052 | ||
1053 | /* Disassemble TCI bytecode. */ | |
1054 | int print_insn_tci(bfd_vma addr, disassemble_info *info) | |
1055 | { | |
65089889 | 1056 | const uint32_t *tb_ptr = (const void *)(uintptr_t)addr; |
59964b4f RH |
1057 | const TCGOpDef *def; |
1058 | const char *op_name; | |
65089889 | 1059 | uint32_t insn; |
59964b4f | 1060 | TCGOpcode op; |
08096b1a | 1061 | TCGReg r0, r1, r2, r3, r4, r5; |
59964b4f RH |
1062 | tcg_target_ulong i1; |
1063 | int32_t s2; | |
1064 | TCGCond c; | |
9002ffcb | 1065 | MemOpIdx oi; |
59964b4f | 1066 | uint8_t pos, len; |
65089889 | 1067 | void *ptr; |
59964b4f | 1068 | |
65089889 RH |
1069 | /* TCI is always the host, so we don't need to load indirect. */ |
1070 | insn = *tb_ptr++; | |
59964b4f | 1071 | |
65089889 | 1072 | info->fprintf_func(info->stream, "%08x ", insn); |
59964b4f | 1073 | |
65089889 | 1074 | op = extract32(insn, 0, 8); |
59964b4f RH |
1075 | def = &tcg_op_defs[op]; |
1076 | op_name = def->name; | |
59964b4f RH |
1077 | |
1078 | switch (op) { | |
1079 | case INDEX_op_br: | |
59964b4f RH |
1080 | case INDEX_op_exit_tb: |
1081 | case INDEX_op_goto_tb: | |
65089889 | 1082 | tci_args_l(insn, tb_ptr, &ptr); |
59964b4f RH |
1083 | info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); |
1084 | break; | |
1085 | ||
6eea0434 RH |
1086 | case INDEX_op_goto_ptr: |
1087 | tci_args_r(insn, &r0); | |
1088 | info->fprintf_func(info->stream, "%-12s %s", op_name, str_r(r0)); | |
1089 | break; | |
1090 | ||
7b7d8b2d | 1091 | case INDEX_op_call: |
65089889 RH |
1092 | tci_args_nl(insn, tb_ptr, &len, &ptr); |
1093 | info->fprintf_func(info->stream, "%-12s %d, %p", op_name, len, ptr); | |
7b7d8b2d RH |
1094 | break; |
1095 | ||
59964b4f RH |
1096 | case INDEX_op_brcond_i32: |
1097 | case INDEX_op_brcond_i64: | |
65089889 | 1098 | tci_args_rl(insn, tb_ptr, &r0, &ptr); |
fc8ec9e1 RH |
1099 | info->fprintf_func(info->stream, "%-12s %s, 0, ne, %p", |
1100 | op_name, str_r(r0), ptr); | |
59964b4f RH |
1101 | break; |
1102 | ||
1103 | case INDEX_op_setcond_i32: | |
1104 | case INDEX_op_setcond_i64: | |
65089889 | 1105 | tci_args_rrrc(insn, &r0, &r1, &r2, &c); |
59964b4f RH |
1106 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", |
1107 | op_name, str_r(r0), str_r(r1), str_r(r2), str_c(c)); | |
1108 | break; | |
1109 | ||
65089889 RH |
1110 | case INDEX_op_tci_movi: |
1111 | tci_args_ri(insn, &r0, &i1); | |
59964b4f RH |
1112 | info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx, |
1113 | op_name, str_r(r0), i1); | |
1114 | break; | |
1115 | ||
65089889 RH |
1116 | case INDEX_op_tci_movl: |
1117 | tci_args_rl(insn, tb_ptr, &r0, &ptr); | |
1118 | info->fprintf_func(info->stream, "%-12s %s, %p", | |
1119 | op_name, str_r(r0), ptr); | |
59964b4f | 1120 | break; |
59964b4f RH |
1121 | |
1122 | case INDEX_op_ld8u_i32: | |
1123 | case INDEX_op_ld8u_i64: | |
1124 | case INDEX_op_ld8s_i32: | |
1125 | case INDEX_op_ld8s_i64: | |
1126 | case INDEX_op_ld16u_i32: | |
1127 | case INDEX_op_ld16u_i64: | |
1128 | case INDEX_op_ld16s_i32: | |
1129 | case INDEX_op_ld16s_i64: | |
1130 | case INDEX_op_ld32u_i64: | |
1131 | case INDEX_op_ld32s_i64: | |
1132 | case INDEX_op_ld_i32: | |
1133 | case INDEX_op_ld_i64: | |
1134 | case INDEX_op_st8_i32: | |
1135 | case INDEX_op_st8_i64: | |
1136 | case INDEX_op_st16_i32: | |
1137 | case INDEX_op_st16_i64: | |
1138 | case INDEX_op_st32_i64: | |
1139 | case INDEX_op_st_i32: | |
1140 | case INDEX_op_st_i64: | |
65089889 | 1141 | tci_args_rrs(insn, &r0, &r1, &s2); |
59964b4f RH |
1142 | info->fprintf_func(info->stream, "%-12s %s, %s, %d", |
1143 | op_name, str_r(r0), str_r(r1), s2); | |
1144 | break; | |
1145 | ||
1146 | case INDEX_op_mov_i32: | |
1147 | case INDEX_op_mov_i64: | |
1148 | case INDEX_op_ext8s_i32: | |
1149 | case INDEX_op_ext8s_i64: | |
1150 | case INDEX_op_ext8u_i32: | |
1151 | case INDEX_op_ext8u_i64: | |
1152 | case INDEX_op_ext16s_i32: | |
1153 | case INDEX_op_ext16s_i64: | |
1154 | case INDEX_op_ext16u_i32: | |
1155 | case INDEX_op_ext32s_i64: | |
1156 | case INDEX_op_ext32u_i64: | |
1157 | case INDEX_op_ext_i32_i64: | |
1158 | case INDEX_op_extu_i32_i64: | |
1159 | case INDEX_op_bswap16_i32: | |
1160 | case INDEX_op_bswap16_i64: | |
1161 | case INDEX_op_bswap32_i32: | |
1162 | case INDEX_op_bswap32_i64: | |
1163 | case INDEX_op_bswap64_i64: | |
1164 | case INDEX_op_not_i32: | |
1165 | case INDEX_op_not_i64: | |
1166 | case INDEX_op_neg_i32: | |
1167 | case INDEX_op_neg_i64: | |
5255f48c RH |
1168 | case INDEX_op_ctpop_i32: |
1169 | case INDEX_op_ctpop_i64: | |
65089889 | 1170 | tci_args_rr(insn, &r0, &r1); |
59964b4f RH |
1171 | info->fprintf_func(info->stream, "%-12s %s, %s", |
1172 | op_name, str_r(r0), str_r(r1)); | |
1173 | break; | |
1174 | ||
1175 | case INDEX_op_add_i32: | |
1176 | case INDEX_op_add_i64: | |
1177 | case INDEX_op_sub_i32: | |
1178 | case INDEX_op_sub_i64: | |
1179 | case INDEX_op_mul_i32: | |
1180 | case INDEX_op_mul_i64: | |
1181 | case INDEX_op_and_i32: | |
1182 | case INDEX_op_and_i64: | |
1183 | case INDEX_op_or_i32: | |
1184 | case INDEX_op_or_i64: | |
1185 | case INDEX_op_xor_i32: | |
1186 | case INDEX_op_xor_i64: | |
a81520b9 RH |
1187 | case INDEX_op_andc_i32: |
1188 | case INDEX_op_andc_i64: | |
1189 | case INDEX_op_orc_i32: | |
1190 | case INDEX_op_orc_i64: | |
1191 | case INDEX_op_eqv_i32: | |
1192 | case INDEX_op_eqv_i64: | |
1193 | case INDEX_op_nand_i32: | |
1194 | case INDEX_op_nand_i64: | |
1195 | case INDEX_op_nor_i32: | |
1196 | case INDEX_op_nor_i64: | |
59964b4f RH |
1197 | case INDEX_op_div_i32: |
1198 | case INDEX_op_div_i64: | |
1199 | case INDEX_op_rem_i32: | |
1200 | case INDEX_op_rem_i64: | |
1201 | case INDEX_op_divu_i32: | |
1202 | case INDEX_op_divu_i64: | |
1203 | case INDEX_op_remu_i32: | |
1204 | case INDEX_op_remu_i64: | |
1205 | case INDEX_op_shl_i32: | |
1206 | case INDEX_op_shl_i64: | |
1207 | case INDEX_op_shr_i32: | |
1208 | case INDEX_op_shr_i64: | |
1209 | case INDEX_op_sar_i32: | |
1210 | case INDEX_op_sar_i64: | |
1211 | case INDEX_op_rotl_i32: | |
1212 | case INDEX_op_rotl_i64: | |
1213 | case INDEX_op_rotr_i32: | |
1214 | case INDEX_op_rotr_i64: | |
5255f48c RH |
1215 | case INDEX_op_clz_i32: |
1216 | case INDEX_op_clz_i64: | |
1217 | case INDEX_op_ctz_i32: | |
1218 | case INDEX_op_ctz_i64: | |
65089889 | 1219 | tci_args_rrr(insn, &r0, &r1, &r2); |
59964b4f RH |
1220 | info->fprintf_func(info->stream, "%-12s %s, %s, %s", |
1221 | op_name, str_r(r0), str_r(r1), str_r(r2)); | |
1222 | break; | |
1223 | ||
1224 | case INDEX_op_deposit_i32: | |
1225 | case INDEX_op_deposit_i64: | |
65089889 | 1226 | tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); |
59964b4f RH |
1227 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %d, %d", |
1228 | op_name, str_r(r0), str_r(r1), str_r(r2), pos, len); | |
1229 | break; | |
1230 | ||
0f10d7c5 RH |
1231 | case INDEX_op_extract_i32: |
1232 | case INDEX_op_extract_i64: | |
1233 | case INDEX_op_sextract_i32: | |
1234 | case INDEX_op_sextract_i64: | |
1235 | tci_args_rrbb(insn, &r0, &r1, &pos, &len); | |
1236 | info->fprintf_func(info->stream, "%-12s %s,%s,%d,%d", | |
1237 | op_name, str_r(r0), str_r(r1), pos, len); | |
1238 | break; | |
1239 | ||
df093c19 RH |
1240 | case INDEX_op_movcond_i32: |
1241 | case INDEX_op_movcond_i64: | |
59964b4f | 1242 | case INDEX_op_setcond2_i32: |
65089889 | 1243 | tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c); |
59964b4f RH |
1244 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s", |
1245 | op_name, str_r(r0), str_r(r1), str_r(r2), | |
1246 | str_r(r3), str_r(r4), str_c(c)); | |
1247 | break; | |
1248 | ||
59964b4f | 1249 | case INDEX_op_mulu2_i32: |
f6db0d8d RH |
1250 | case INDEX_op_mulu2_i64: |
1251 | case INDEX_op_muls2_i32: | |
1252 | case INDEX_op_muls2_i64: | |
65089889 | 1253 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); |
59964b4f RH |
1254 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", |
1255 | op_name, str_r(r0), str_r(r1), | |
1256 | str_r(r2), str_r(r3)); | |
1257 | break; | |
1258 | ||
1259 | case INDEX_op_add2_i32: | |
08096b1a | 1260 | case INDEX_op_add2_i64: |
59964b4f | 1261 | case INDEX_op_sub2_i32: |
08096b1a | 1262 | case INDEX_op_sub2_i64: |
65089889 | 1263 | tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); |
59964b4f RH |
1264 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s", |
1265 | op_name, str_r(r0), str_r(r1), str_r(r2), | |
1266 | str_r(r3), str_r(r4), str_r(r5)); | |
1267 | break; | |
59964b4f | 1268 | |
fecccfcc RH |
1269 | case INDEX_op_qemu_ld_a32_i32: |
1270 | case INDEX_op_qemu_st_a32_i32: | |
1271 | len = 1 + 1; | |
1272 | goto do_qemu_ldst; | |
1273 | case INDEX_op_qemu_ld_a32_i64: | |
1274 | case INDEX_op_qemu_st_a32_i64: | |
1275 | case INDEX_op_qemu_ld_a64_i32: | |
1276 | case INDEX_op_qemu_st_a64_i32: | |
1277 | len = 1 + DIV_ROUND_UP(64, TCG_TARGET_REG_BITS); | |
1278 | goto do_qemu_ldst; | |
1279 | case INDEX_op_qemu_ld_a64_i64: | |
1280 | case INDEX_op_qemu_st_a64_i64: | |
1281 | len = 2 * DIV_ROUND_UP(64, TCG_TARGET_REG_BITS); | |
59964b4f | 1282 | goto do_qemu_ldst; |
59964b4f | 1283 | do_qemu_ldst: |
59964b4f RH |
1284 | switch (len) { |
1285 | case 2: | |
65089889 | 1286 | tci_args_rrm(insn, &r0, &r1, &oi); |
59964b4f RH |
1287 | info->fprintf_func(info->stream, "%-12s %s, %s, %x", |
1288 | op_name, str_r(r0), str_r(r1), oi); | |
1289 | break; | |
1290 | case 3: | |
ab64da79 RH |
1291 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); |
1292 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", | |
1293 | op_name, str_r(r0), str_r(r1), | |
1294 | str_r(r2), str_r(r3)); | |
59964b4f RH |
1295 | break; |
1296 | case 4: | |
65089889 RH |
1297 | tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); |
1298 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s", | |
59964b4f | 1299 | op_name, str_r(r0), str_r(r1), |
65089889 | 1300 | str_r(r2), str_r(r3), str_r(r4)); |
59964b4f RH |
1301 | break; |
1302 | default: | |
1303 | g_assert_not_reached(); | |
1304 | } | |
1305 | break; | |
1306 | ||
65089889 RH |
1307 | case 0: |
1308 | /* tcg_out_nop_fill uses zeros */ | |
1309 | if (insn == 0) { | |
1310 | info->fprintf_func(info->stream, "align"); | |
1311 | break; | |
1312 | } | |
1313 | /* fall through */ | |
1314 | ||
59964b4f RH |
1315 | default: |
1316 | info->fprintf_func(info->stream, "illegal opcode %d", op); | |
1317 | break; | |
1318 | } | |
1319 | ||
65089889 | 1320 | return sizeof(insn); |
59964b4f | 1321 | } |