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Commit | Line | Data |
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7657f4bf SW |
1 | /* |
2 | * Tiny Code Interpreter for QEMU | |
3 | * | |
3ccdbecf | 4 | * Copyright (c) 2009, 2011, 2016 Stefan Weil |
7657f4bf SW |
5 | * |
6 | * This program is free software: you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation, either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
18 | */ | |
19 | ||
d38ea87a | 20 | #include "qemu/osdep.h" |
7657f4bf | 21 | #include "qemu-common.h" |
65603e2f | 22 | #include "tcg/tcg.h" /* MAX_OPC_PARAM_IARGS */ |
f08b6170 | 23 | #include "exec/cpu_ldst.h" |
dcb32f1d | 24 | #include "tcg/tcg-op.h" |
d2ba8026 | 25 | #include "tcg/tcg-ldst.h" |
c905a368 | 26 | #include "qemu/compiler.h" |
7b7d8b2d | 27 | #include <ffi.h> |
7657f4bf | 28 | |
7b7d8b2d RH |
29 | |
30 | /* | |
31 | * Enable TCI assertions only when debugging TCG (and without NDEBUG defined). | |
32 | * Without assertions, the interpreter runs much faster. | |
33 | */ | |
34 | #if defined(CONFIG_DEBUG_TCG) | |
35 | # define tci_assert(cond) assert(cond) | |
7657f4bf | 36 | #else |
7b7d8b2d | 37 | # define tci_assert(cond) ((void)(cond)) |
7657f4bf SW |
38 | #endif |
39 | ||
13e71f08 RH |
40 | __thread uintptr_t tci_tb_ptr; |
41 | ||
5e75150c EC |
42 | static void tci_write_reg64(tcg_target_ulong *regs, uint32_t high_index, |
43 | uint32_t low_index, uint64_t value) | |
7657f4bf | 44 | { |
f6db0d8d | 45 | regs[low_index] = (uint32_t)value; |
7e00a080 | 46 | regs[high_index] = value >> 32; |
7657f4bf | 47 | } |
7657f4bf | 48 | |
7657f4bf SW |
49 | /* Create a 64 bit value from two 32 bit values. */ |
50 | static uint64_t tci_uint64(uint32_t high, uint32_t low) | |
51 | { | |
52 | return ((uint64_t)high << 32) + low; | |
53 | } | |
7657f4bf | 54 | |
cdd9799b RH |
55 | /* |
56 | * Load sets of arguments all at once. The naming convention is: | |
57 | * tci_args_<arguments> | |
58 | * where arguments is a sequence of | |
59 | * | |
79dd3a4f | 60 | * b = immediate (bit position) |
963e9fa2 | 61 | * c = condition (TCGCond) |
b95aa12e RH |
62 | * i = immediate (uint32_t) |
63 | * I = immediate (tcg_target_ulong) | |
f28ca03e | 64 | * l = label or pointer |
9002ffcb | 65 | * m = immediate (MemOpIdx) |
7b7d8b2d | 66 | * n = immediate (call return length) |
cdd9799b RH |
67 | * r = register |
68 | * s = signed ldst offset | |
69 | */ | |
70 | ||
65089889 | 71 | static void tci_args_l(uint32_t insn, const void *tb_ptr, void **l0) |
92bc4fad | 72 | { |
65089889 RH |
73 | int diff = sextract32(insn, 12, 20); |
74 | *l0 = diff ? (void *)tb_ptr + diff : NULL; | |
92bc4fad RH |
75 | } |
76 | ||
6eea0434 RH |
77 | static void tci_args_r(uint32_t insn, TCGReg *r0) |
78 | { | |
79 | *r0 = extract32(insn, 8, 4); | |
80 | } | |
81 | ||
65089889 RH |
82 | static void tci_args_nl(uint32_t insn, const void *tb_ptr, |
83 | uint8_t *n0, void **l1) | |
f28ca03e | 84 | { |
65089889 RH |
85 | *n0 = extract32(insn, 8, 4); |
86 | *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr; | |
f28ca03e RH |
87 | } |
88 | ||
65089889 RH |
89 | static void tci_args_rl(uint32_t insn, const void *tb_ptr, |
90 | TCGReg *r0, void **l1) | |
7b7d8b2d | 91 | { |
65089889 RH |
92 | *r0 = extract32(insn, 8, 4); |
93 | *l1 = sextract32(insn, 12, 20) + (void *)tb_ptr; | |
7b7d8b2d RH |
94 | } |
95 | ||
65089889 | 96 | static void tci_args_rr(uint32_t insn, TCGReg *r0, TCGReg *r1) |
fc8ec9e1 | 97 | { |
65089889 RH |
98 | *r0 = extract32(insn, 8, 4); |
99 | *r1 = extract32(insn, 12, 4); | |
fc8ec9e1 RH |
100 | } |
101 | ||
65089889 | 102 | static void tci_args_ri(uint32_t insn, TCGReg *r0, tcg_target_ulong *i1) |
fc4a62f6 | 103 | { |
65089889 RH |
104 | *r0 = extract32(insn, 8, 4); |
105 | *i1 = sextract32(insn, 12, 20); | |
fc4a62f6 RH |
106 | } |
107 | ||
65089889 | 108 | static void tci_args_rrm(uint32_t insn, TCGReg *r0, |
9002ffcb | 109 | TCGReg *r1, MemOpIdx *m2) |
b95aa12e | 110 | { |
65089889 RH |
111 | *r0 = extract32(insn, 8, 4); |
112 | *r1 = extract32(insn, 12, 4); | |
113 | *m2 = extract32(insn, 20, 12); | |
b95aa12e RH |
114 | } |
115 | ||
65089889 | 116 | static void tci_args_rrr(uint32_t insn, TCGReg *r0, TCGReg *r1, TCGReg *r2) |
b95aa12e | 117 | { |
65089889 RH |
118 | *r0 = extract32(insn, 8, 4); |
119 | *r1 = extract32(insn, 12, 4); | |
120 | *r2 = extract32(insn, 16, 4); | |
b95aa12e | 121 | } |
b95aa12e | 122 | |
65089889 | 123 | static void tci_args_rrs(uint32_t insn, TCGReg *r0, TCGReg *r1, int32_t *i2) |
63041ed2 | 124 | { |
65089889 RH |
125 | *r0 = extract32(insn, 8, 4); |
126 | *r1 = extract32(insn, 12, 4); | |
127 | *i2 = sextract32(insn, 16, 16); | |
63041ed2 RH |
128 | } |
129 | ||
0f10d7c5 RH |
130 | static void tci_args_rrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, |
131 | uint8_t *i2, uint8_t *i3) | |
132 | { | |
133 | *r0 = extract32(insn, 8, 4); | |
134 | *r1 = extract32(insn, 12, 4); | |
135 | *i2 = extract32(insn, 16, 6); | |
136 | *i3 = extract32(insn, 22, 6); | |
137 | } | |
138 | ||
65089889 | 139 | static void tci_args_rrrc(uint32_t insn, |
963e9fa2 RH |
140 | TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGCond *c3) |
141 | { | |
65089889 RH |
142 | *r0 = extract32(insn, 8, 4); |
143 | *r1 = extract32(insn, 12, 4); | |
144 | *r2 = extract32(insn, 16, 4); | |
145 | *c3 = extract32(insn, 20, 4); | |
963e9fa2 RH |
146 | } |
147 | ||
65089889 | 148 | static void tci_args_rrrm(uint32_t insn, |
9002ffcb | 149 | TCGReg *r0, TCGReg *r1, TCGReg *r2, MemOpIdx *m3) |
63041ed2 | 150 | { |
65089889 RH |
151 | *r0 = extract32(insn, 8, 4); |
152 | *r1 = extract32(insn, 12, 4); | |
153 | *r2 = extract32(insn, 16, 4); | |
154 | *m3 = extract32(insn, 20, 12); | |
63041ed2 RH |
155 | } |
156 | ||
65089889 | 157 | static void tci_args_rrrbb(uint32_t insn, TCGReg *r0, TCGReg *r1, |
79dd3a4f RH |
158 | TCGReg *r2, uint8_t *i3, uint8_t *i4) |
159 | { | |
65089889 RH |
160 | *r0 = extract32(insn, 8, 4); |
161 | *r1 = extract32(insn, 12, 4); | |
162 | *r2 = extract32(insn, 16, 4); | |
163 | *i3 = extract32(insn, 20, 6); | |
164 | *i4 = extract32(insn, 26, 6); | |
79dd3a4f RH |
165 | } |
166 | ||
65089889 RH |
167 | static void tci_args_rrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, |
168 | TCGReg *r2, TCGReg *r3, TCGReg *r4) | |
63041ed2 | 169 | { |
65089889 RH |
170 | *r0 = extract32(insn, 8, 4); |
171 | *r1 = extract32(insn, 12, 4); | |
172 | *r2 = extract32(insn, 16, 4); | |
173 | *r3 = extract32(insn, 20, 4); | |
174 | *r4 = extract32(insn, 24, 4); | |
63041ed2 RH |
175 | } |
176 | ||
65089889 | 177 | static void tci_args_rrrr(uint32_t insn, |
cbe87131 RH |
178 | TCGReg *r0, TCGReg *r1, TCGReg *r2, TCGReg *r3) |
179 | { | |
65089889 RH |
180 | *r0 = extract32(insn, 8, 4); |
181 | *r1 = extract32(insn, 12, 4); | |
182 | *r2 = extract32(insn, 16, 4); | |
183 | *r3 = extract32(insn, 20, 4); | |
cbe87131 RH |
184 | } |
185 | ||
65089889 | 186 | static void tci_args_rrrrrc(uint32_t insn, TCGReg *r0, TCGReg *r1, |
817cadd6 RH |
187 | TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGCond *c5) |
188 | { | |
65089889 RH |
189 | *r0 = extract32(insn, 8, 4); |
190 | *r1 = extract32(insn, 12, 4); | |
191 | *r2 = extract32(insn, 16, 4); | |
192 | *r3 = extract32(insn, 20, 4); | |
193 | *r4 = extract32(insn, 24, 4); | |
194 | *c5 = extract32(insn, 28, 4); | |
817cadd6 | 195 | } |
120402b5 | 196 | |
65089889 | 197 | static void tci_args_rrrrrr(uint32_t insn, TCGReg *r0, TCGReg *r1, |
120402b5 RH |
198 | TCGReg *r2, TCGReg *r3, TCGReg *r4, TCGReg *r5) |
199 | { | |
65089889 RH |
200 | *r0 = extract32(insn, 8, 4); |
201 | *r1 = extract32(insn, 12, 4); | |
202 | *r2 = extract32(insn, 16, 4); | |
203 | *r3 = extract32(insn, 20, 4); | |
204 | *r4 = extract32(insn, 24, 4); | |
205 | *r5 = extract32(insn, 28, 4); | |
120402b5 | 206 | } |
817cadd6 | 207 | |
7657f4bf SW |
208 | static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition) |
209 | { | |
210 | bool result = false; | |
211 | int32_t i0 = u0; | |
212 | int32_t i1 = u1; | |
213 | switch (condition) { | |
214 | case TCG_COND_EQ: | |
215 | result = (u0 == u1); | |
216 | break; | |
217 | case TCG_COND_NE: | |
218 | result = (u0 != u1); | |
219 | break; | |
220 | case TCG_COND_LT: | |
221 | result = (i0 < i1); | |
222 | break; | |
223 | case TCG_COND_GE: | |
224 | result = (i0 >= i1); | |
225 | break; | |
226 | case TCG_COND_LE: | |
227 | result = (i0 <= i1); | |
228 | break; | |
229 | case TCG_COND_GT: | |
230 | result = (i0 > i1); | |
231 | break; | |
232 | case TCG_COND_LTU: | |
233 | result = (u0 < u1); | |
234 | break; | |
235 | case TCG_COND_GEU: | |
236 | result = (u0 >= u1); | |
237 | break; | |
238 | case TCG_COND_LEU: | |
239 | result = (u0 <= u1); | |
240 | break; | |
241 | case TCG_COND_GTU: | |
242 | result = (u0 > u1); | |
243 | break; | |
244 | default: | |
f6996f99 | 245 | g_assert_not_reached(); |
7657f4bf SW |
246 | } |
247 | return result; | |
248 | } | |
249 | ||
250 | static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition) | |
251 | { | |
252 | bool result = false; | |
253 | int64_t i0 = u0; | |
254 | int64_t i1 = u1; | |
255 | switch (condition) { | |
256 | case TCG_COND_EQ: | |
257 | result = (u0 == u1); | |
258 | break; | |
259 | case TCG_COND_NE: | |
260 | result = (u0 != u1); | |
261 | break; | |
262 | case TCG_COND_LT: | |
263 | result = (i0 < i1); | |
264 | break; | |
265 | case TCG_COND_GE: | |
266 | result = (i0 >= i1); | |
267 | break; | |
268 | case TCG_COND_LE: | |
269 | result = (i0 <= i1); | |
270 | break; | |
271 | case TCG_COND_GT: | |
272 | result = (i0 > i1); | |
273 | break; | |
274 | case TCG_COND_LTU: | |
275 | result = (u0 < u1); | |
276 | break; | |
277 | case TCG_COND_GEU: | |
278 | result = (u0 >= u1); | |
279 | break; | |
280 | case TCG_COND_LEU: | |
281 | result = (u0 <= u1); | |
282 | break; | |
283 | case TCG_COND_GTU: | |
284 | result = (u0 > u1); | |
285 | break; | |
286 | default: | |
f6996f99 | 287 | g_assert_not_reached(); |
7657f4bf SW |
288 | } |
289 | return result; | |
290 | } | |
291 | ||
69acc02a | 292 | static uint64_t tci_qemu_ld(CPUArchState *env, target_ulong taddr, |
9002ffcb | 293 | MemOpIdx oi, const void *tb_ptr) |
69acc02a RH |
294 | { |
295 | MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE); | |
d1b1348c RH |
296 | uintptr_t ra = (uintptr_t)tb_ptr; |
297 | ||
2fc6f16c | 298 | #ifdef CONFIG_SOFTMMU |
d1b1348c RH |
299 | switch (mop) { |
300 | case MO_UB: | |
301 | return helper_ret_ldub_mmu(env, taddr, oi, ra); | |
302 | case MO_SB: | |
303 | return helper_ret_ldsb_mmu(env, taddr, oi, ra); | |
304 | case MO_LEUW: | |
305 | return helper_le_lduw_mmu(env, taddr, oi, ra); | |
306 | case MO_LESW: | |
307 | return helper_le_ldsw_mmu(env, taddr, oi, ra); | |
308 | case MO_LEUL: | |
309 | return helper_le_ldul_mmu(env, taddr, oi, ra); | |
310 | case MO_LESL: | |
311 | return helper_le_ldsl_mmu(env, taddr, oi, ra); | |
312 | case MO_LEQ: | |
313 | return helper_le_ldq_mmu(env, taddr, oi, ra); | |
314 | case MO_BEUW: | |
315 | return helper_be_lduw_mmu(env, taddr, oi, ra); | |
316 | case MO_BESW: | |
317 | return helper_be_ldsw_mmu(env, taddr, oi, ra); | |
318 | case MO_BEUL: | |
319 | return helper_be_ldul_mmu(env, taddr, oi, ra); | |
320 | case MO_BESL: | |
321 | return helper_be_ldsl_mmu(env, taddr, oi, ra); | |
322 | case MO_BEQ: | |
323 | return helper_be_ldq_mmu(env, taddr, oi, ra); | |
324 | default: | |
325 | g_assert_not_reached(); | |
326 | } | |
327 | #else | |
328 | void *haddr = g2h(env_cpu(env), taddr); | |
329 | uint64_t ret; | |
330 | ||
2fc6f16c | 331 | set_helper_retaddr(ra); |
69acc02a RH |
332 | switch (mop) { |
333 | case MO_UB: | |
d1b1348c RH |
334 | ret = ldub_p(haddr); |
335 | break; | |
69acc02a | 336 | case MO_SB: |
d1b1348c RH |
337 | ret = ldsb_p(haddr); |
338 | break; | |
69acc02a | 339 | case MO_LEUW: |
d1b1348c RH |
340 | ret = lduw_le_p(haddr); |
341 | break; | |
69acc02a | 342 | case MO_LESW: |
d1b1348c RH |
343 | ret = ldsw_le_p(haddr); |
344 | break; | |
69acc02a | 345 | case MO_LEUL: |
d1b1348c RH |
346 | ret = (uint32_t)ldl_le_p(haddr); |
347 | break; | |
69acc02a | 348 | case MO_LESL: |
d1b1348c RH |
349 | ret = (int32_t)ldl_le_p(haddr); |
350 | break; | |
69acc02a | 351 | case MO_LEQ: |
d1b1348c RH |
352 | ret = ldq_le_p(haddr); |
353 | break; | |
69acc02a | 354 | case MO_BEUW: |
d1b1348c RH |
355 | ret = lduw_be_p(haddr); |
356 | break; | |
69acc02a | 357 | case MO_BESW: |
d1b1348c RH |
358 | ret = ldsw_be_p(haddr); |
359 | break; | |
69acc02a | 360 | case MO_BEUL: |
d1b1348c RH |
361 | ret = (uint32_t)ldl_be_p(haddr); |
362 | break; | |
69acc02a | 363 | case MO_BESL: |
d1b1348c RH |
364 | ret = (int32_t)ldl_be_p(haddr); |
365 | break; | |
69acc02a | 366 | case MO_BEQ: |
d1b1348c RH |
367 | ret = ldq_be_p(haddr); |
368 | break; | |
69acc02a RH |
369 | default: |
370 | g_assert_not_reached(); | |
371 | } | |
2fc6f16c | 372 | clear_helper_retaddr(); |
d1b1348c RH |
373 | return ret; |
374 | #endif | |
69acc02a RH |
375 | } |
376 | ||
377 | static void tci_qemu_st(CPUArchState *env, target_ulong taddr, uint64_t val, | |
9002ffcb | 378 | MemOpIdx oi, const void *tb_ptr) |
69acc02a RH |
379 | { |
380 | MemOp mop = get_memop(oi) & (MO_BSWAP | MO_SSIZE); | |
d1b1348c RH |
381 | uintptr_t ra = (uintptr_t)tb_ptr; |
382 | ||
2fc6f16c | 383 | #ifdef CONFIG_SOFTMMU |
d1b1348c RH |
384 | switch (mop) { |
385 | case MO_UB: | |
386 | helper_ret_stb_mmu(env, taddr, val, oi, ra); | |
387 | break; | |
388 | case MO_LEUW: | |
389 | helper_le_stw_mmu(env, taddr, val, oi, ra); | |
390 | break; | |
391 | case MO_LEUL: | |
392 | helper_le_stl_mmu(env, taddr, val, oi, ra); | |
393 | break; | |
394 | case MO_LEQ: | |
395 | helper_le_stq_mmu(env, taddr, val, oi, ra); | |
396 | break; | |
397 | case MO_BEUW: | |
398 | helper_be_stw_mmu(env, taddr, val, oi, ra); | |
399 | break; | |
400 | case MO_BEUL: | |
401 | helper_be_stl_mmu(env, taddr, val, oi, ra); | |
402 | break; | |
403 | case MO_BEQ: | |
404 | helper_be_stq_mmu(env, taddr, val, oi, ra); | |
405 | break; | |
406 | default: | |
407 | g_assert_not_reached(); | |
408 | } | |
409 | #else | |
410 | void *haddr = g2h(env_cpu(env), taddr); | |
411 | ||
2fc6f16c | 412 | set_helper_retaddr(ra); |
69acc02a RH |
413 | switch (mop) { |
414 | case MO_UB: | |
d1b1348c | 415 | stb_p(haddr, val); |
69acc02a RH |
416 | break; |
417 | case MO_LEUW: | |
d1b1348c | 418 | stw_le_p(haddr, val); |
69acc02a RH |
419 | break; |
420 | case MO_LEUL: | |
d1b1348c | 421 | stl_le_p(haddr, val); |
69acc02a RH |
422 | break; |
423 | case MO_LEQ: | |
d1b1348c | 424 | stq_le_p(haddr, val); |
69acc02a RH |
425 | break; |
426 | case MO_BEUW: | |
d1b1348c | 427 | stw_be_p(haddr, val); |
69acc02a RH |
428 | break; |
429 | case MO_BEUL: | |
d1b1348c | 430 | stl_be_p(haddr, val); |
69acc02a RH |
431 | break; |
432 | case MO_BEQ: | |
d1b1348c | 433 | stq_be_p(haddr, val); |
69acc02a RH |
434 | break; |
435 | default: | |
436 | g_assert_not_reached(); | |
437 | } | |
2fc6f16c | 438 | clear_helper_retaddr(); |
d1b1348c | 439 | #endif |
69acc02a RH |
440 | } |
441 | ||
7f33f5cd RH |
442 | #if TCG_TARGET_REG_BITS == 64 |
443 | # define CASE_32_64(x) \ | |
444 | case glue(glue(INDEX_op_, x), _i64): \ | |
445 | case glue(glue(INDEX_op_, x), _i32): | |
446 | # define CASE_64(x) \ | |
447 | case glue(glue(INDEX_op_, x), _i64): | |
448 | #else | |
449 | # define CASE_32_64(x) \ | |
450 | case glue(glue(INDEX_op_, x), _i32): | |
451 | # define CASE_64(x) | |
452 | #endif | |
453 | ||
7657f4bf | 454 | /* Interpret pseudo code in tb. */ |
c905a368 DB |
455 | /* |
456 | * Disable CFI checks. | |
457 | * One possible operation in the pseudo code is a call to binary code. | |
458 | * Therefore, disable CFI checks in the interpreter function | |
459 | */ | |
db0c51a3 RH |
460 | uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, |
461 | const void *v_tb_ptr) | |
7657f4bf | 462 | { |
65089889 | 463 | const uint32_t *tb_ptr = v_tb_ptr; |
5e75150c | 464 | tcg_target_ulong regs[TCG_TARGET_NB_REGS]; |
7b7d8b2d RH |
465 | uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) |
466 | / sizeof(uint64_t)]; | |
467 | void *call_slots[TCG_STATIC_CALL_ARGS_SIZE / sizeof(uint64_t)]; | |
7657f4bf | 468 | |
5e75150c | 469 | regs[TCG_AREG0] = (tcg_target_ulong)env; |
7b7d8b2d RH |
470 | regs[TCG_REG_CALL_STACK] = (uintptr_t)stack; |
471 | /* Other call_slots entries initialized at first use (see below). */ | |
472 | call_slots[0] = NULL; | |
3ccdbecf | 473 | tci_assert(tb_ptr); |
7657f4bf SW |
474 | |
475 | for (;;) { | |
65089889 RH |
476 | uint32_t insn; |
477 | TCGOpcode opc; | |
08096b1a | 478 | TCGReg r0, r1, r2, r3, r4, r5; |
7657f4bf | 479 | tcg_target_ulong t1; |
7657f4bf SW |
480 | TCGCond condition; |
481 | target_ulong taddr; | |
79dd3a4f | 482 | uint8_t pos, len; |
7657f4bf SW |
483 | uint32_t tmp32; |
484 | uint64_t tmp64; | |
5a0adf34 | 485 | uint64_t T1, T2; |
9002ffcb | 486 | MemOpIdx oi; |
cdd9799b | 487 | int32_t ofs; |
65089889 | 488 | void *ptr; |
7657f4bf | 489 | |
65089889 RH |
490 | insn = *tb_ptr++; |
491 | opc = extract32(insn, 0, 8); | |
7657f4bf SW |
492 | |
493 | switch (opc) { | |
7657f4bf | 494 | case INDEX_op_call: |
7b7d8b2d RH |
495 | /* |
496 | * Set up the ffi_avalue array once, delayed until now | |
497 | * because many TB's do not make any calls. In tcg_gen_callN, | |
498 | * we arranged for every real argument to be "left-aligned" | |
499 | * in each 64-bit slot. | |
500 | */ | |
501 | if (unlikely(call_slots[0] == NULL)) { | |
502 | for (int i = 0; i < ARRAY_SIZE(call_slots); ++i) { | |
503 | call_slots[i] = &stack[i]; | |
504 | } | |
505 | } | |
506 | ||
65089889 | 507 | tci_args_nl(insn, tb_ptr, &len, &ptr); |
7b7d8b2d RH |
508 | |
509 | /* Helper functions may need to access the "return address" */ | |
13e71f08 | 510 | tci_tb_ptr = (uintptr_t)tb_ptr; |
7b7d8b2d | 511 | |
65089889 RH |
512 | { |
513 | void **pptr = ptr; | |
514 | ffi_call(pptr[1], pptr[0], stack, call_slots); | |
515 | } | |
7b7d8b2d RH |
516 | |
517 | /* Any result winds up "left-aligned" in the stack[0] slot. */ | |
518 | switch (len) { | |
519 | case 0: /* void */ | |
520 | break; | |
521 | case 1: /* uint32_t */ | |
522 | /* | |
523 | * Note that libffi has an odd special case in that it will | |
524 | * always widen an integral result to ffi_arg. | |
525 | */ | |
526 | if (sizeof(ffi_arg) == 4) { | |
527 | regs[TCG_REG_R0] = *(uint32_t *)stack; | |
528 | break; | |
529 | } | |
530 | /* fall through */ | |
531 | case 2: /* uint64_t */ | |
532 | if (TCG_TARGET_REG_BITS == 32) { | |
533 | tci_write_reg64(regs, TCG_REG_R1, TCG_REG_R0, stack[0]); | |
534 | } else { | |
535 | regs[TCG_REG_R0] = stack[0]; | |
536 | } | |
537 | break; | |
538 | default: | |
539 | g_assert_not_reached(); | |
540 | } | |
7657f4bf | 541 | break; |
7b7d8b2d | 542 | |
7657f4bf | 543 | case INDEX_op_br: |
65089889 | 544 | tci_args_l(insn, tb_ptr, &ptr); |
f28ca03e | 545 | tb_ptr = ptr; |
7657f4bf SW |
546 | continue; |
547 | case INDEX_op_setcond_i32: | |
65089889 | 548 | tci_args_rrrc(insn, &r0, &r1, &r2, &condition); |
963e9fa2 | 549 | regs[r0] = tci_compare32(regs[r1], regs[r2], condition); |
7657f4bf | 550 | break; |
df093c19 RH |
551 | case INDEX_op_movcond_i32: |
552 | tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); | |
553 | tmp32 = tci_compare32(regs[r1], regs[r2], condition); | |
554 | regs[r0] = regs[tmp32 ? r3 : r4]; | |
555 | break; | |
7657f4bf SW |
556 | #if TCG_TARGET_REG_BITS == 32 |
557 | case INDEX_op_setcond2_i32: | |
65089889 | 558 | tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); |
817cadd6 RH |
559 | T1 = tci_uint64(regs[r2], regs[r1]); |
560 | T2 = tci_uint64(regs[r4], regs[r3]); | |
561 | regs[r0] = tci_compare64(T1, T2, condition); | |
7657f4bf SW |
562 | break; |
563 | #elif TCG_TARGET_REG_BITS == 64 | |
564 | case INDEX_op_setcond_i64: | |
65089889 | 565 | tci_args_rrrc(insn, &r0, &r1, &r2, &condition); |
963e9fa2 | 566 | regs[r0] = tci_compare64(regs[r1], regs[r2], condition); |
7657f4bf | 567 | break; |
df093c19 RH |
568 | case INDEX_op_movcond_i64: |
569 | tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &condition); | |
570 | tmp32 = tci_compare64(regs[r1], regs[r2], condition); | |
571 | regs[r0] = regs[tmp32 ? r3 : r4]; | |
572 | break; | |
7657f4bf | 573 | #endif |
9e9acb7b | 574 | CASE_32_64(mov) |
65089889 | 575 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 576 | regs[r0] = regs[r1]; |
7657f4bf | 577 | break; |
65089889 RH |
578 | case INDEX_op_tci_movi: |
579 | tci_args_ri(insn, &r0, &t1); | |
b95aa12e | 580 | regs[r0] = t1; |
7657f4bf | 581 | break; |
65089889 RH |
582 | case INDEX_op_tci_movl: |
583 | tci_args_rl(insn, tb_ptr, &r0, &ptr); | |
584 | regs[r0] = *(tcg_target_ulong *)ptr; | |
585 | break; | |
7657f4bf SW |
586 | |
587 | /* Load/store operations (32 bit). */ | |
588 | ||
7f33f5cd | 589 | CASE_32_64(ld8u) |
65089889 | 590 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
591 | ptr = (void *)(regs[r1] + ofs); |
592 | regs[r0] = *(uint8_t *)ptr; | |
7657f4bf | 593 | break; |
850163eb | 594 | CASE_32_64(ld8s) |
65089889 | 595 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
596 | ptr = (void *)(regs[r1] + ofs); |
597 | regs[r0] = *(int8_t *)ptr; | |
2f160e0f | 598 | break; |
77c38c7c | 599 | CASE_32_64(ld16u) |
65089889 | 600 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
601 | ptr = (void *)(regs[r1] + ofs); |
602 | regs[r0] = *(uint16_t *)ptr; | |
7657f4bf | 603 | break; |
b09d78bf | 604 | CASE_32_64(ld16s) |
65089889 | 605 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
606 | ptr = (void *)(regs[r1] + ofs); |
607 | regs[r0] = *(int16_t *)ptr; | |
7657f4bf SW |
608 | break; |
609 | case INDEX_op_ld_i32: | |
c1d77e94 | 610 | CASE_64(ld32u) |
65089889 | 611 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
612 | ptr = (void *)(regs[r1] + ofs); |
613 | regs[r0] = *(uint32_t *)ptr; | |
7657f4bf | 614 | break; |
ba9a80c1 | 615 | CASE_32_64(st8) |
65089889 | 616 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
617 | ptr = (void *)(regs[r1] + ofs); |
618 | *(uint8_t *)ptr = regs[r0]; | |
7657f4bf | 619 | break; |
90be4dde | 620 | CASE_32_64(st16) |
65089889 | 621 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
622 | ptr = (void *)(regs[r1] + ofs); |
623 | *(uint16_t *)ptr = regs[r0]; | |
7657f4bf SW |
624 | break; |
625 | case INDEX_op_st_i32: | |
b4d5bf0f | 626 | CASE_64(st32) |
65089889 | 627 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
628 | ptr = (void *)(regs[r1] + ofs); |
629 | *(uint32_t *)ptr = regs[r0]; | |
7657f4bf SW |
630 | break; |
631 | ||
dd2bb20e | 632 | /* Arithmetic operations (mixed 32/64 bit). */ |
7657f4bf | 633 | |
dd2bb20e | 634 | CASE_32_64(add) |
65089889 | 635 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 636 | regs[r0] = regs[r1] + regs[r2]; |
7657f4bf | 637 | break; |
dd2bb20e | 638 | CASE_32_64(sub) |
65089889 | 639 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 640 | regs[r0] = regs[r1] - regs[r2]; |
7657f4bf | 641 | break; |
dd2bb20e | 642 | CASE_32_64(mul) |
65089889 | 643 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 644 | regs[r0] = regs[r1] * regs[r2]; |
7657f4bf | 645 | break; |
dd2bb20e | 646 | CASE_32_64(and) |
65089889 | 647 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 648 | regs[r0] = regs[r1] & regs[r2]; |
7657f4bf | 649 | break; |
dd2bb20e | 650 | CASE_32_64(or) |
65089889 | 651 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 652 | regs[r0] = regs[r1] | regs[r2]; |
7657f4bf | 653 | break; |
dd2bb20e | 654 | CASE_32_64(xor) |
65089889 | 655 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 656 | regs[r0] = regs[r1] ^ regs[r2]; |
7657f4bf | 657 | break; |
a81520b9 RH |
658 | #if TCG_TARGET_HAS_andc_i32 || TCG_TARGET_HAS_andc_i64 |
659 | CASE_32_64(andc) | |
660 | tci_args_rrr(insn, &r0, &r1, &r2); | |
661 | regs[r0] = regs[r1] & ~regs[r2]; | |
662 | break; | |
663 | #endif | |
664 | #if TCG_TARGET_HAS_orc_i32 || TCG_TARGET_HAS_orc_i64 | |
665 | CASE_32_64(orc) | |
666 | tci_args_rrr(insn, &r0, &r1, &r2); | |
667 | regs[r0] = regs[r1] | ~regs[r2]; | |
668 | break; | |
669 | #endif | |
670 | #if TCG_TARGET_HAS_eqv_i32 || TCG_TARGET_HAS_eqv_i64 | |
671 | CASE_32_64(eqv) | |
672 | tci_args_rrr(insn, &r0, &r1, &r2); | |
673 | regs[r0] = ~(regs[r1] ^ regs[r2]); | |
674 | break; | |
675 | #endif | |
676 | #if TCG_TARGET_HAS_nand_i32 || TCG_TARGET_HAS_nand_i64 | |
677 | CASE_32_64(nand) | |
678 | tci_args_rrr(insn, &r0, &r1, &r2); | |
679 | regs[r0] = ~(regs[r1] & regs[r2]); | |
680 | break; | |
681 | #endif | |
682 | #if TCG_TARGET_HAS_nor_i32 || TCG_TARGET_HAS_nor_i64 | |
683 | CASE_32_64(nor) | |
684 | tci_args_rrr(insn, &r0, &r1, &r2); | |
685 | regs[r0] = ~(regs[r1] | regs[r2]); | |
686 | break; | |
687 | #endif | |
dd2bb20e RH |
688 | |
689 | /* Arithmetic operations (32 bit). */ | |
690 | ||
691 | case INDEX_op_div_i32: | |
65089889 | 692 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 693 | regs[r0] = (int32_t)regs[r1] / (int32_t)regs[r2]; |
7657f4bf | 694 | break; |
dd2bb20e | 695 | case INDEX_op_divu_i32: |
65089889 | 696 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 697 | regs[r0] = (uint32_t)regs[r1] / (uint32_t)regs[r2]; |
7657f4bf | 698 | break; |
dd2bb20e | 699 | case INDEX_op_rem_i32: |
65089889 | 700 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 701 | regs[r0] = (int32_t)regs[r1] % (int32_t)regs[r2]; |
7657f4bf | 702 | break; |
dd2bb20e | 703 | case INDEX_op_remu_i32: |
65089889 | 704 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 705 | regs[r0] = (uint32_t)regs[r1] % (uint32_t)regs[r2]; |
7657f4bf | 706 | break; |
5255f48c RH |
707 | #if TCG_TARGET_HAS_clz_i32 |
708 | case INDEX_op_clz_i32: | |
709 | tci_args_rrr(insn, &r0, &r1, &r2); | |
710 | tmp32 = regs[r1]; | |
711 | regs[r0] = tmp32 ? clz32(tmp32) : regs[r2]; | |
712 | break; | |
713 | #endif | |
714 | #if TCG_TARGET_HAS_ctz_i32 | |
715 | case INDEX_op_ctz_i32: | |
716 | tci_args_rrr(insn, &r0, &r1, &r2); | |
717 | tmp32 = regs[r1]; | |
718 | regs[r0] = tmp32 ? ctz32(tmp32) : regs[r2]; | |
719 | break; | |
720 | #endif | |
721 | #if TCG_TARGET_HAS_ctpop_i32 | |
722 | case INDEX_op_ctpop_i32: | |
723 | tci_args_rr(insn, &r0, &r1); | |
724 | regs[r0] = ctpop32(regs[r1]); | |
725 | break; | |
726 | #endif | |
7657f4bf SW |
727 | |
728 | /* Shift/rotate operations (32 bit). */ | |
729 | ||
730 | case INDEX_op_shl_i32: | |
65089889 | 731 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 732 | regs[r0] = (uint32_t)regs[r1] << (regs[r2] & 31); |
7657f4bf SW |
733 | break; |
734 | case INDEX_op_shr_i32: | |
65089889 | 735 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 736 | regs[r0] = (uint32_t)regs[r1] >> (regs[r2] & 31); |
7657f4bf SW |
737 | break; |
738 | case INDEX_op_sar_i32: | |
65089889 | 739 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 740 | regs[r0] = (int32_t)regs[r1] >> (regs[r2] & 31); |
7657f4bf SW |
741 | break; |
742 | #if TCG_TARGET_HAS_rot_i32 | |
743 | case INDEX_op_rotl_i32: | |
65089889 | 744 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 745 | regs[r0] = rol32(regs[r1], regs[r2] & 31); |
7657f4bf SW |
746 | break; |
747 | case INDEX_op_rotr_i32: | |
65089889 | 748 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 749 | regs[r0] = ror32(regs[r1], regs[r2] & 31); |
7657f4bf | 750 | break; |
e24dc9fe SW |
751 | #endif |
752 | #if TCG_TARGET_HAS_deposit_i32 | |
753 | case INDEX_op_deposit_i32: | |
65089889 | 754 | tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); |
79dd3a4f | 755 | regs[r0] = deposit32(regs[r1], pos, len, regs[r2]); |
e24dc9fe | 756 | break; |
0f10d7c5 RH |
757 | #endif |
758 | #if TCG_TARGET_HAS_extract_i32 | |
759 | case INDEX_op_extract_i32: | |
760 | tci_args_rrbb(insn, &r0, &r1, &pos, &len); | |
761 | regs[r0] = extract32(regs[r1], pos, len); | |
762 | break; | |
763 | #endif | |
764 | #if TCG_TARGET_HAS_sextract_i32 | |
765 | case INDEX_op_sextract_i32: | |
766 | tci_args_rrbb(insn, &r0, &r1, &pos, &len); | |
767 | regs[r0] = sextract32(regs[r1], pos, len); | |
768 | break; | |
7657f4bf SW |
769 | #endif |
770 | case INDEX_op_brcond_i32: | |
65089889 | 771 | tci_args_rl(insn, tb_ptr, &r0, &ptr); |
fc8ec9e1 | 772 | if ((uint32_t)regs[r0]) { |
5a0adf34 | 773 | tb_ptr = ptr; |
7657f4bf SW |
774 | } |
775 | break; | |
08096b1a | 776 | #if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_add2_i32 |
7657f4bf | 777 | case INDEX_op_add2_i32: |
65089889 | 778 | tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); |
120402b5 RH |
779 | T1 = tci_uint64(regs[r3], regs[r2]); |
780 | T2 = tci_uint64(regs[r5], regs[r4]); | |
781 | tci_write_reg64(regs, r1, r0, T1 + T2); | |
7657f4bf | 782 | break; |
08096b1a RH |
783 | #endif |
784 | #if TCG_TARGET_REG_BITS == 32 || TCG_TARGET_HAS_sub2_i32 | |
7657f4bf | 785 | case INDEX_op_sub2_i32: |
65089889 | 786 | tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); |
120402b5 RH |
787 | T1 = tci_uint64(regs[r3], regs[r2]); |
788 | T2 = tci_uint64(regs[r5], regs[r4]); | |
789 | tci_write_reg64(regs, r1, r0, T1 - T2); | |
7657f4bf | 790 | break; |
08096b1a | 791 | #endif |
f6db0d8d | 792 | #if TCG_TARGET_HAS_mulu2_i32 |
7657f4bf | 793 | case INDEX_op_mulu2_i32: |
65089889 | 794 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); |
f6db0d8d RH |
795 | tmp64 = (uint64_t)(uint32_t)regs[r2] * (uint32_t)regs[r3]; |
796 | tci_write_reg64(regs, r1, r0, tmp64); | |
7657f4bf | 797 | break; |
f6db0d8d RH |
798 | #endif |
799 | #if TCG_TARGET_HAS_muls2_i32 | |
800 | case INDEX_op_muls2_i32: | |
801 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); | |
802 | tmp64 = (int64_t)(int32_t)regs[r2] * (int32_t)regs[r3]; | |
803 | tci_write_reg64(regs, r1, r0, tmp64); | |
804 | break; | |
805 | #endif | |
13a1d640 RH |
806 | #if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64 |
807 | CASE_32_64(ext8s) | |
65089889 | 808 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 809 | regs[r0] = (int8_t)regs[r1]; |
7657f4bf SW |
810 | break; |
811 | #endif | |
0d57d36a RH |
812 | #if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64 || \ |
813 | TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 | |
13a1d640 | 814 | CASE_32_64(ext16s) |
65089889 | 815 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 816 | regs[r0] = (int16_t)regs[r1]; |
7657f4bf SW |
817 | break; |
818 | #endif | |
13a1d640 RH |
819 | #if TCG_TARGET_HAS_ext8u_i32 || TCG_TARGET_HAS_ext8u_i64 |
820 | CASE_32_64(ext8u) | |
65089889 | 821 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 822 | regs[r0] = (uint8_t)regs[r1]; |
7657f4bf SW |
823 | break; |
824 | #endif | |
13a1d640 RH |
825 | #if TCG_TARGET_HAS_ext16u_i32 || TCG_TARGET_HAS_ext16u_i64 |
826 | CASE_32_64(ext16u) | |
65089889 | 827 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 828 | regs[r0] = (uint16_t)regs[r1]; |
7657f4bf SW |
829 | break; |
830 | #endif | |
fe2b13bb RH |
831 | #if TCG_TARGET_HAS_bswap16_i32 || TCG_TARGET_HAS_bswap16_i64 |
832 | CASE_32_64(bswap16) | |
65089889 | 833 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 834 | regs[r0] = bswap16(regs[r1]); |
7657f4bf SW |
835 | break; |
836 | #endif | |
fe2b13bb RH |
837 | #if TCG_TARGET_HAS_bswap32_i32 || TCG_TARGET_HAS_bswap32_i64 |
838 | CASE_32_64(bswap32) | |
65089889 | 839 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 840 | regs[r0] = bswap32(regs[r1]); |
7657f4bf SW |
841 | break; |
842 | #endif | |
9e9acb7b RH |
843 | #if TCG_TARGET_HAS_not_i32 || TCG_TARGET_HAS_not_i64 |
844 | CASE_32_64(not) | |
65089889 | 845 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 846 | regs[r0] = ~regs[r1]; |
7657f4bf SW |
847 | break; |
848 | #endif | |
9e9acb7b RH |
849 | #if TCG_TARGET_HAS_neg_i32 || TCG_TARGET_HAS_neg_i64 |
850 | CASE_32_64(neg) | |
65089889 | 851 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 852 | regs[r0] = -regs[r1]; |
7657f4bf SW |
853 | break; |
854 | #endif | |
855 | #if TCG_TARGET_REG_BITS == 64 | |
7657f4bf SW |
856 | /* Load/store operations (64 bit). */ |
857 | ||
7657f4bf | 858 | case INDEX_op_ld32s_i64: |
65089889 | 859 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
860 | ptr = (void *)(regs[r1] + ofs); |
861 | regs[r0] = *(int32_t *)ptr; | |
7657f4bf SW |
862 | break; |
863 | case INDEX_op_ld_i64: | |
65089889 | 864 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
865 | ptr = (void *)(regs[r1] + ofs); |
866 | regs[r0] = *(uint64_t *)ptr; | |
7657f4bf | 867 | break; |
7657f4bf | 868 | case INDEX_op_st_i64: |
65089889 | 869 | tci_args_rrs(insn, &r0, &r1, &ofs); |
cdd9799b RH |
870 | ptr = (void *)(regs[r1] + ofs); |
871 | *(uint64_t *)ptr = regs[r0]; | |
7657f4bf SW |
872 | break; |
873 | ||
874 | /* Arithmetic operations (64 bit). */ | |
875 | ||
7657f4bf | 876 | case INDEX_op_div_i64: |
65089889 | 877 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 878 | regs[r0] = (int64_t)regs[r1] / (int64_t)regs[r2]; |
ae40c098 | 879 | break; |
7657f4bf | 880 | case INDEX_op_divu_i64: |
65089889 | 881 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 882 | regs[r0] = (uint64_t)regs[r1] / (uint64_t)regs[r2]; |
ae40c098 | 883 | break; |
7657f4bf | 884 | case INDEX_op_rem_i64: |
65089889 | 885 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 886 | regs[r0] = (int64_t)regs[r1] % (int64_t)regs[r2]; |
ae40c098 | 887 | break; |
7657f4bf | 888 | case INDEX_op_remu_i64: |
65089889 | 889 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 890 | regs[r0] = (uint64_t)regs[r1] % (uint64_t)regs[r2]; |
7657f4bf | 891 | break; |
5255f48c RH |
892 | #if TCG_TARGET_HAS_clz_i64 |
893 | case INDEX_op_clz_i64: | |
894 | tci_args_rrr(insn, &r0, &r1, &r2); | |
895 | regs[r0] = regs[r1] ? clz64(regs[r1]) : regs[r2]; | |
896 | break; | |
897 | #endif | |
898 | #if TCG_TARGET_HAS_ctz_i64 | |
899 | case INDEX_op_ctz_i64: | |
900 | tci_args_rrr(insn, &r0, &r1, &r2); | |
901 | regs[r0] = regs[r1] ? ctz64(regs[r1]) : regs[r2]; | |
902 | break; | |
903 | #endif | |
904 | #if TCG_TARGET_HAS_ctpop_i64 | |
905 | case INDEX_op_ctpop_i64: | |
906 | tci_args_rr(insn, &r0, &r1); | |
907 | regs[r0] = ctpop64(regs[r1]); | |
908 | break; | |
909 | #endif | |
f6db0d8d RH |
910 | #if TCG_TARGET_HAS_mulu2_i64 |
911 | case INDEX_op_mulu2_i64: | |
912 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); | |
913 | mulu64(®s[r0], ®s[r1], regs[r2], regs[r3]); | |
914 | break; | |
915 | #endif | |
916 | #if TCG_TARGET_HAS_muls2_i64 | |
917 | case INDEX_op_muls2_i64: | |
918 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); | |
919 | muls64(®s[r0], ®s[r1], regs[r2], regs[r3]); | |
920 | break; | |
921 | #endif | |
08096b1a RH |
922 | #if TCG_TARGET_HAS_add2_i64 |
923 | case INDEX_op_add2_i64: | |
924 | tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); | |
925 | T1 = regs[r2] + regs[r4]; | |
926 | T2 = regs[r3] + regs[r5] + (T1 < regs[r2]); | |
927 | regs[r0] = T1; | |
928 | regs[r1] = T2; | |
929 | break; | |
930 | #endif | |
931 | #if TCG_TARGET_HAS_add2_i64 | |
932 | case INDEX_op_sub2_i64: | |
933 | tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); | |
934 | T1 = regs[r2] - regs[r4]; | |
935 | T2 = regs[r3] - regs[r5] - (regs[r2] < regs[r4]); | |
936 | regs[r0] = T1; | |
937 | regs[r1] = T2; | |
938 | break; | |
939 | #endif | |
7657f4bf SW |
940 | |
941 | /* Shift/rotate operations (64 bit). */ | |
942 | ||
943 | case INDEX_op_shl_i64: | |
65089889 | 944 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 945 | regs[r0] = regs[r1] << (regs[r2] & 63); |
7657f4bf SW |
946 | break; |
947 | case INDEX_op_shr_i64: | |
65089889 | 948 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 949 | regs[r0] = regs[r1] >> (regs[r2] & 63); |
7657f4bf SW |
950 | break; |
951 | case INDEX_op_sar_i64: | |
65089889 | 952 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 953 | regs[r0] = (int64_t)regs[r1] >> (regs[r2] & 63); |
7657f4bf SW |
954 | break; |
955 | #if TCG_TARGET_HAS_rot_i64 | |
956 | case INDEX_op_rotl_i64: | |
65089889 | 957 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 958 | regs[r0] = rol64(regs[r1], regs[r2] & 63); |
d285bf78 | 959 | break; |
7657f4bf | 960 | case INDEX_op_rotr_i64: |
65089889 | 961 | tci_args_rrr(insn, &r0, &r1, &r2); |
e85e4b8f | 962 | regs[r0] = ror64(regs[r1], regs[r2] & 63); |
7657f4bf | 963 | break; |
e24dc9fe SW |
964 | #endif |
965 | #if TCG_TARGET_HAS_deposit_i64 | |
966 | case INDEX_op_deposit_i64: | |
65089889 | 967 | tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); |
79dd3a4f | 968 | regs[r0] = deposit64(regs[r1], pos, len, regs[r2]); |
e24dc9fe | 969 | break; |
0f10d7c5 RH |
970 | #endif |
971 | #if TCG_TARGET_HAS_extract_i64 | |
972 | case INDEX_op_extract_i64: | |
973 | tci_args_rrbb(insn, &r0, &r1, &pos, &len); | |
974 | regs[r0] = extract64(regs[r1], pos, len); | |
975 | break; | |
976 | #endif | |
977 | #if TCG_TARGET_HAS_sextract_i64 | |
978 | case INDEX_op_sextract_i64: | |
979 | tci_args_rrbb(insn, &r0, &r1, &pos, &len); | |
980 | regs[r0] = sextract64(regs[r1], pos, len); | |
981 | break; | |
7657f4bf SW |
982 | #endif |
983 | case INDEX_op_brcond_i64: | |
65089889 | 984 | tci_args_rl(insn, tb_ptr, &r0, &ptr); |
fc8ec9e1 | 985 | if (regs[r0]) { |
5a0adf34 | 986 | tb_ptr = ptr; |
7657f4bf SW |
987 | } |
988 | break; | |
7657f4bf | 989 | case INDEX_op_ext32s_i64: |
4f2331e5 | 990 | case INDEX_op_ext_i32_i64: |
65089889 | 991 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 992 | regs[r0] = (int32_t)regs[r1]; |
7657f4bf | 993 | break; |
7657f4bf | 994 | case INDEX_op_ext32u_i64: |
4f2331e5 | 995 | case INDEX_op_extu_i32_i64: |
65089889 | 996 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 997 | regs[r0] = (uint32_t)regs[r1]; |
7657f4bf | 998 | break; |
7657f4bf SW |
999 | #if TCG_TARGET_HAS_bswap64_i64 |
1000 | case INDEX_op_bswap64_i64: | |
65089889 | 1001 | tci_args_rr(insn, &r0, &r1); |
fc4a62f6 | 1002 | regs[r0] = bswap64(regs[r1]); |
7657f4bf SW |
1003 | break; |
1004 | #endif | |
7657f4bf SW |
1005 | #endif /* TCG_TARGET_REG_BITS == 64 */ |
1006 | ||
1007 | /* QEMU specific operations. */ | |
1008 | ||
7657f4bf | 1009 | case INDEX_op_exit_tb: |
65089889 | 1010 | tci_args_l(insn, tb_ptr, &ptr); |
158d3873 RH |
1011 | return (uintptr_t)ptr; |
1012 | ||
7657f4bf | 1013 | case INDEX_op_goto_tb: |
65089889 | 1014 | tci_args_l(insn, tb_ptr, &ptr); |
1670a2b9 | 1015 | tb_ptr = *(void **)ptr; |
92bc4fad | 1016 | break; |
1670a2b9 | 1017 | |
6eea0434 RH |
1018 | case INDEX_op_goto_ptr: |
1019 | tci_args_r(insn, &r0); | |
1020 | ptr = (void *)regs[r0]; | |
1021 | if (!ptr) { | |
1022 | return 0; | |
1023 | } | |
1024 | tb_ptr = ptr; | |
1025 | break; | |
1026 | ||
76782fab | 1027 | case INDEX_op_qemu_ld_i32: |
63041ed2 | 1028 | if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { |
65089889 | 1029 | tci_args_rrm(insn, &r0, &r1, &oi); |
63041ed2 RH |
1030 | taddr = regs[r1]; |
1031 | } else { | |
65089889 | 1032 | tci_args_rrrm(insn, &r0, &r1, &r2, &oi); |
63041ed2 RH |
1033 | taddr = tci_uint64(regs[r2], regs[r1]); |
1034 | } | |
69acc02a | 1035 | tmp32 = tci_qemu_ld(env, taddr, oi, tb_ptr); |
63041ed2 | 1036 | regs[r0] = tmp32; |
7657f4bf | 1037 | break; |
63041ed2 | 1038 | |
76782fab | 1039 | case INDEX_op_qemu_ld_i64: |
63041ed2 | 1040 | if (TCG_TARGET_REG_BITS == 64) { |
65089889 | 1041 | tci_args_rrm(insn, &r0, &r1, &oi); |
63041ed2 RH |
1042 | taddr = regs[r1]; |
1043 | } else if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { | |
65089889 | 1044 | tci_args_rrrm(insn, &r0, &r1, &r2, &oi); |
63041ed2 RH |
1045 | taddr = regs[r2]; |
1046 | } else { | |
65089889 | 1047 | tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); |
63041ed2 | 1048 | taddr = tci_uint64(regs[r3], regs[r2]); |
65089889 | 1049 | oi = regs[r4]; |
76782fab | 1050 | } |
69acc02a | 1051 | tmp64 = tci_qemu_ld(env, taddr, oi, tb_ptr); |
76782fab | 1052 | if (TCG_TARGET_REG_BITS == 32) { |
63041ed2 RH |
1053 | tci_write_reg64(regs, r1, r0, tmp64); |
1054 | } else { | |
1055 | regs[r0] = tmp64; | |
76782fab | 1056 | } |
7657f4bf | 1057 | break; |
63041ed2 | 1058 | |
76782fab | 1059 | case INDEX_op_qemu_st_i32: |
63041ed2 | 1060 | if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { |
65089889 | 1061 | tci_args_rrm(insn, &r0, &r1, &oi); |
63041ed2 RH |
1062 | taddr = regs[r1]; |
1063 | } else { | |
65089889 | 1064 | tci_args_rrrm(insn, &r0, &r1, &r2, &oi); |
63041ed2 RH |
1065 | taddr = tci_uint64(regs[r2], regs[r1]); |
1066 | } | |
1067 | tmp32 = regs[r0]; | |
69acc02a | 1068 | tci_qemu_st(env, taddr, tmp32, oi, tb_ptr); |
7657f4bf | 1069 | break; |
63041ed2 | 1070 | |
76782fab | 1071 | case INDEX_op_qemu_st_i64: |
63041ed2 | 1072 | if (TCG_TARGET_REG_BITS == 64) { |
65089889 | 1073 | tci_args_rrm(insn, &r0, &r1, &oi); |
63041ed2 RH |
1074 | taddr = regs[r1]; |
1075 | tmp64 = regs[r0]; | |
1076 | } else { | |
1077 | if (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS) { | |
65089889 | 1078 | tci_args_rrrm(insn, &r0, &r1, &r2, &oi); |
63041ed2 RH |
1079 | taddr = regs[r2]; |
1080 | } else { | |
65089889 | 1081 | tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); |
63041ed2 | 1082 | taddr = tci_uint64(regs[r3], regs[r2]); |
65089889 | 1083 | oi = regs[r4]; |
63041ed2 RH |
1084 | } |
1085 | tmp64 = tci_uint64(regs[r1], regs[r0]); | |
1086 | } | |
69acc02a | 1087 | tci_qemu_st(env, taddr, tmp64, oi, tb_ptr); |
7657f4bf | 1088 | break; |
63041ed2 | 1089 | |
a1e69e2f PK |
1090 | case INDEX_op_mb: |
1091 | /* Ensure ordering for all kinds */ | |
1092 | smp_mb(); | |
1093 | break; | |
7657f4bf | 1094 | default: |
f6996f99 | 1095 | g_assert_not_reached(); |
7657f4bf | 1096 | } |
7657f4bf | 1097 | } |
7657f4bf | 1098 | } |
59964b4f RH |
1099 | |
1100 | /* | |
1101 | * Disassembler that matches the interpreter | |
1102 | */ | |
1103 | ||
1104 | static const char *str_r(TCGReg r) | |
1105 | { | |
1106 | static const char regs[TCG_TARGET_NB_REGS][4] = { | |
1107 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
1108 | "r8", "r9", "r10", "r11", "r12", "r13", "env", "sp" | |
1109 | }; | |
1110 | ||
1111 | QEMU_BUILD_BUG_ON(TCG_AREG0 != TCG_REG_R14); | |
1112 | QEMU_BUILD_BUG_ON(TCG_REG_CALL_STACK != TCG_REG_R15); | |
1113 | ||
1114 | assert((unsigned)r < TCG_TARGET_NB_REGS); | |
1115 | return regs[r]; | |
1116 | } | |
1117 | ||
1118 | static const char *str_c(TCGCond c) | |
1119 | { | |
1120 | static const char cond[16][8] = { | |
1121 | [TCG_COND_NEVER] = "never", | |
1122 | [TCG_COND_ALWAYS] = "always", | |
1123 | [TCG_COND_EQ] = "eq", | |
1124 | [TCG_COND_NE] = "ne", | |
1125 | [TCG_COND_LT] = "lt", | |
1126 | [TCG_COND_GE] = "ge", | |
1127 | [TCG_COND_LE] = "le", | |
1128 | [TCG_COND_GT] = "gt", | |
1129 | [TCG_COND_LTU] = "ltu", | |
1130 | [TCG_COND_GEU] = "geu", | |
1131 | [TCG_COND_LEU] = "leu", | |
1132 | [TCG_COND_GTU] = "gtu", | |
1133 | }; | |
1134 | ||
1135 | assert((unsigned)c < ARRAY_SIZE(cond)); | |
1136 | assert(cond[c][0] != 0); | |
1137 | return cond[c]; | |
1138 | } | |
1139 | ||
1140 | /* Disassemble TCI bytecode. */ | |
1141 | int print_insn_tci(bfd_vma addr, disassemble_info *info) | |
1142 | { | |
65089889 | 1143 | const uint32_t *tb_ptr = (const void *)(uintptr_t)addr; |
59964b4f RH |
1144 | const TCGOpDef *def; |
1145 | const char *op_name; | |
65089889 | 1146 | uint32_t insn; |
59964b4f | 1147 | TCGOpcode op; |
08096b1a | 1148 | TCGReg r0, r1, r2, r3, r4, r5; |
59964b4f RH |
1149 | tcg_target_ulong i1; |
1150 | int32_t s2; | |
1151 | TCGCond c; | |
9002ffcb | 1152 | MemOpIdx oi; |
59964b4f | 1153 | uint8_t pos, len; |
65089889 | 1154 | void *ptr; |
59964b4f | 1155 | |
65089889 RH |
1156 | /* TCI is always the host, so we don't need to load indirect. */ |
1157 | insn = *tb_ptr++; | |
59964b4f | 1158 | |
65089889 | 1159 | info->fprintf_func(info->stream, "%08x ", insn); |
59964b4f | 1160 | |
65089889 | 1161 | op = extract32(insn, 0, 8); |
59964b4f RH |
1162 | def = &tcg_op_defs[op]; |
1163 | op_name = def->name; | |
59964b4f RH |
1164 | |
1165 | switch (op) { | |
1166 | case INDEX_op_br: | |
59964b4f RH |
1167 | case INDEX_op_exit_tb: |
1168 | case INDEX_op_goto_tb: | |
65089889 | 1169 | tci_args_l(insn, tb_ptr, &ptr); |
59964b4f RH |
1170 | info->fprintf_func(info->stream, "%-12s %p", op_name, ptr); |
1171 | break; | |
1172 | ||
6eea0434 RH |
1173 | case INDEX_op_goto_ptr: |
1174 | tci_args_r(insn, &r0); | |
1175 | info->fprintf_func(info->stream, "%-12s %s", op_name, str_r(r0)); | |
1176 | break; | |
1177 | ||
7b7d8b2d | 1178 | case INDEX_op_call: |
65089889 RH |
1179 | tci_args_nl(insn, tb_ptr, &len, &ptr); |
1180 | info->fprintf_func(info->stream, "%-12s %d, %p", op_name, len, ptr); | |
7b7d8b2d RH |
1181 | break; |
1182 | ||
59964b4f RH |
1183 | case INDEX_op_brcond_i32: |
1184 | case INDEX_op_brcond_i64: | |
65089889 | 1185 | tci_args_rl(insn, tb_ptr, &r0, &ptr); |
fc8ec9e1 RH |
1186 | info->fprintf_func(info->stream, "%-12s %s, 0, ne, %p", |
1187 | op_name, str_r(r0), ptr); | |
59964b4f RH |
1188 | break; |
1189 | ||
1190 | case INDEX_op_setcond_i32: | |
1191 | case INDEX_op_setcond_i64: | |
65089889 | 1192 | tci_args_rrrc(insn, &r0, &r1, &r2, &c); |
59964b4f RH |
1193 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", |
1194 | op_name, str_r(r0), str_r(r1), str_r(r2), str_c(c)); | |
1195 | break; | |
1196 | ||
65089889 RH |
1197 | case INDEX_op_tci_movi: |
1198 | tci_args_ri(insn, &r0, &i1); | |
59964b4f RH |
1199 | info->fprintf_func(info->stream, "%-12s %s, 0x%" TCG_PRIlx, |
1200 | op_name, str_r(r0), i1); | |
1201 | break; | |
1202 | ||
65089889 RH |
1203 | case INDEX_op_tci_movl: |
1204 | tci_args_rl(insn, tb_ptr, &r0, &ptr); | |
1205 | info->fprintf_func(info->stream, "%-12s %s, %p", | |
1206 | op_name, str_r(r0), ptr); | |
59964b4f | 1207 | break; |
59964b4f RH |
1208 | |
1209 | case INDEX_op_ld8u_i32: | |
1210 | case INDEX_op_ld8u_i64: | |
1211 | case INDEX_op_ld8s_i32: | |
1212 | case INDEX_op_ld8s_i64: | |
1213 | case INDEX_op_ld16u_i32: | |
1214 | case INDEX_op_ld16u_i64: | |
1215 | case INDEX_op_ld16s_i32: | |
1216 | case INDEX_op_ld16s_i64: | |
1217 | case INDEX_op_ld32u_i64: | |
1218 | case INDEX_op_ld32s_i64: | |
1219 | case INDEX_op_ld_i32: | |
1220 | case INDEX_op_ld_i64: | |
1221 | case INDEX_op_st8_i32: | |
1222 | case INDEX_op_st8_i64: | |
1223 | case INDEX_op_st16_i32: | |
1224 | case INDEX_op_st16_i64: | |
1225 | case INDEX_op_st32_i64: | |
1226 | case INDEX_op_st_i32: | |
1227 | case INDEX_op_st_i64: | |
65089889 | 1228 | tci_args_rrs(insn, &r0, &r1, &s2); |
59964b4f RH |
1229 | info->fprintf_func(info->stream, "%-12s %s, %s, %d", |
1230 | op_name, str_r(r0), str_r(r1), s2); | |
1231 | break; | |
1232 | ||
1233 | case INDEX_op_mov_i32: | |
1234 | case INDEX_op_mov_i64: | |
1235 | case INDEX_op_ext8s_i32: | |
1236 | case INDEX_op_ext8s_i64: | |
1237 | case INDEX_op_ext8u_i32: | |
1238 | case INDEX_op_ext8u_i64: | |
1239 | case INDEX_op_ext16s_i32: | |
1240 | case INDEX_op_ext16s_i64: | |
1241 | case INDEX_op_ext16u_i32: | |
1242 | case INDEX_op_ext32s_i64: | |
1243 | case INDEX_op_ext32u_i64: | |
1244 | case INDEX_op_ext_i32_i64: | |
1245 | case INDEX_op_extu_i32_i64: | |
1246 | case INDEX_op_bswap16_i32: | |
1247 | case INDEX_op_bswap16_i64: | |
1248 | case INDEX_op_bswap32_i32: | |
1249 | case INDEX_op_bswap32_i64: | |
1250 | case INDEX_op_bswap64_i64: | |
1251 | case INDEX_op_not_i32: | |
1252 | case INDEX_op_not_i64: | |
1253 | case INDEX_op_neg_i32: | |
1254 | case INDEX_op_neg_i64: | |
5255f48c RH |
1255 | case INDEX_op_ctpop_i32: |
1256 | case INDEX_op_ctpop_i64: | |
65089889 | 1257 | tci_args_rr(insn, &r0, &r1); |
59964b4f RH |
1258 | info->fprintf_func(info->stream, "%-12s %s, %s", |
1259 | op_name, str_r(r0), str_r(r1)); | |
1260 | break; | |
1261 | ||
1262 | case INDEX_op_add_i32: | |
1263 | case INDEX_op_add_i64: | |
1264 | case INDEX_op_sub_i32: | |
1265 | case INDEX_op_sub_i64: | |
1266 | case INDEX_op_mul_i32: | |
1267 | case INDEX_op_mul_i64: | |
1268 | case INDEX_op_and_i32: | |
1269 | case INDEX_op_and_i64: | |
1270 | case INDEX_op_or_i32: | |
1271 | case INDEX_op_or_i64: | |
1272 | case INDEX_op_xor_i32: | |
1273 | case INDEX_op_xor_i64: | |
a81520b9 RH |
1274 | case INDEX_op_andc_i32: |
1275 | case INDEX_op_andc_i64: | |
1276 | case INDEX_op_orc_i32: | |
1277 | case INDEX_op_orc_i64: | |
1278 | case INDEX_op_eqv_i32: | |
1279 | case INDEX_op_eqv_i64: | |
1280 | case INDEX_op_nand_i32: | |
1281 | case INDEX_op_nand_i64: | |
1282 | case INDEX_op_nor_i32: | |
1283 | case INDEX_op_nor_i64: | |
59964b4f RH |
1284 | case INDEX_op_div_i32: |
1285 | case INDEX_op_div_i64: | |
1286 | case INDEX_op_rem_i32: | |
1287 | case INDEX_op_rem_i64: | |
1288 | case INDEX_op_divu_i32: | |
1289 | case INDEX_op_divu_i64: | |
1290 | case INDEX_op_remu_i32: | |
1291 | case INDEX_op_remu_i64: | |
1292 | case INDEX_op_shl_i32: | |
1293 | case INDEX_op_shl_i64: | |
1294 | case INDEX_op_shr_i32: | |
1295 | case INDEX_op_shr_i64: | |
1296 | case INDEX_op_sar_i32: | |
1297 | case INDEX_op_sar_i64: | |
1298 | case INDEX_op_rotl_i32: | |
1299 | case INDEX_op_rotl_i64: | |
1300 | case INDEX_op_rotr_i32: | |
1301 | case INDEX_op_rotr_i64: | |
5255f48c RH |
1302 | case INDEX_op_clz_i32: |
1303 | case INDEX_op_clz_i64: | |
1304 | case INDEX_op_ctz_i32: | |
1305 | case INDEX_op_ctz_i64: | |
65089889 | 1306 | tci_args_rrr(insn, &r0, &r1, &r2); |
59964b4f RH |
1307 | info->fprintf_func(info->stream, "%-12s %s, %s, %s", |
1308 | op_name, str_r(r0), str_r(r1), str_r(r2)); | |
1309 | break; | |
1310 | ||
1311 | case INDEX_op_deposit_i32: | |
1312 | case INDEX_op_deposit_i64: | |
65089889 | 1313 | tci_args_rrrbb(insn, &r0, &r1, &r2, &pos, &len); |
59964b4f RH |
1314 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %d, %d", |
1315 | op_name, str_r(r0), str_r(r1), str_r(r2), pos, len); | |
1316 | break; | |
1317 | ||
0f10d7c5 RH |
1318 | case INDEX_op_extract_i32: |
1319 | case INDEX_op_extract_i64: | |
1320 | case INDEX_op_sextract_i32: | |
1321 | case INDEX_op_sextract_i64: | |
1322 | tci_args_rrbb(insn, &r0, &r1, &pos, &len); | |
1323 | info->fprintf_func(info->stream, "%-12s %s,%s,%d,%d", | |
1324 | op_name, str_r(r0), str_r(r1), pos, len); | |
1325 | break; | |
1326 | ||
df093c19 RH |
1327 | case INDEX_op_movcond_i32: |
1328 | case INDEX_op_movcond_i64: | |
59964b4f | 1329 | case INDEX_op_setcond2_i32: |
65089889 | 1330 | tci_args_rrrrrc(insn, &r0, &r1, &r2, &r3, &r4, &c); |
59964b4f RH |
1331 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s", |
1332 | op_name, str_r(r0), str_r(r1), str_r(r2), | |
1333 | str_r(r3), str_r(r4), str_c(c)); | |
1334 | break; | |
1335 | ||
59964b4f | 1336 | case INDEX_op_mulu2_i32: |
f6db0d8d RH |
1337 | case INDEX_op_mulu2_i64: |
1338 | case INDEX_op_muls2_i32: | |
1339 | case INDEX_op_muls2_i64: | |
65089889 | 1340 | tci_args_rrrr(insn, &r0, &r1, &r2, &r3); |
59964b4f RH |
1341 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s", |
1342 | op_name, str_r(r0), str_r(r1), | |
1343 | str_r(r2), str_r(r3)); | |
1344 | break; | |
1345 | ||
1346 | case INDEX_op_add2_i32: | |
08096b1a | 1347 | case INDEX_op_add2_i64: |
59964b4f | 1348 | case INDEX_op_sub2_i32: |
08096b1a | 1349 | case INDEX_op_sub2_i64: |
65089889 | 1350 | tci_args_rrrrrr(insn, &r0, &r1, &r2, &r3, &r4, &r5); |
59964b4f RH |
1351 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s, %s", |
1352 | op_name, str_r(r0), str_r(r1), str_r(r2), | |
1353 | str_r(r3), str_r(r4), str_r(r5)); | |
1354 | break; | |
59964b4f RH |
1355 | |
1356 | case INDEX_op_qemu_ld_i64: | |
1357 | case INDEX_op_qemu_st_i64: | |
1358 | len = DIV_ROUND_UP(64, TCG_TARGET_REG_BITS); | |
1359 | goto do_qemu_ldst; | |
1360 | case INDEX_op_qemu_ld_i32: | |
1361 | case INDEX_op_qemu_st_i32: | |
1362 | len = 1; | |
1363 | do_qemu_ldst: | |
1364 | len += DIV_ROUND_UP(TARGET_LONG_BITS, TCG_TARGET_REG_BITS); | |
1365 | switch (len) { | |
1366 | case 2: | |
65089889 | 1367 | tci_args_rrm(insn, &r0, &r1, &oi); |
59964b4f RH |
1368 | info->fprintf_func(info->stream, "%-12s %s, %s, %x", |
1369 | op_name, str_r(r0), str_r(r1), oi); | |
1370 | break; | |
1371 | case 3: | |
65089889 | 1372 | tci_args_rrrm(insn, &r0, &r1, &r2, &oi); |
59964b4f RH |
1373 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %x", |
1374 | op_name, str_r(r0), str_r(r1), str_r(r2), oi); | |
1375 | break; | |
1376 | case 4: | |
65089889 RH |
1377 | tci_args_rrrrr(insn, &r0, &r1, &r2, &r3, &r4); |
1378 | info->fprintf_func(info->stream, "%-12s %s, %s, %s, %s, %s", | |
59964b4f | 1379 | op_name, str_r(r0), str_r(r1), |
65089889 | 1380 | str_r(r2), str_r(r3), str_r(r4)); |
59964b4f RH |
1381 | break; |
1382 | default: | |
1383 | g_assert_not_reached(); | |
1384 | } | |
1385 | break; | |
1386 | ||
65089889 RH |
1387 | case 0: |
1388 | /* tcg_out_nop_fill uses zeros */ | |
1389 | if (insn == 0) { | |
1390 | info->fprintf_func(info->stream, "align"); | |
1391 | break; | |
1392 | } | |
1393 | /* fall through */ | |
1394 | ||
59964b4f RH |
1395 | default: |
1396 | info->fprintf_func(info->stream, "illegal opcode %d", op); | |
1397 | break; | |
1398 | } | |
1399 | ||
65089889 | 1400 | return sizeof(insn); |
59964b4f | 1401 | } |