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iotests: Add test for potentially damaging repairs
[mirror_qemu.git] / tests / ahci-test.c
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1cd1031d
JS		 1/*
2 * AHCI test cases
3 *
4 * Copyright (c) 2014 John Snow <jsnow@redhat.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#include <stdint.h>
26#include <string.h>
27#include <stdio.h>
8840a843 28#include <getopt.h>
1cd1031d
JS		 29#include <glib.h>
30
31#include "libqtest.h"
32#include "libqos/pci-pc.h"
33#include "libqos/malloc-pc.h"
34
35#include "qemu-common.h"
36#include "qemu/host-utils.h"
37
38#include "hw/pci/pci_ids.h"
39#include "hw/pci/pci_regs.h"
40
41/* Test-specific defines. */
42#define TEST_IMAGE_SIZE (64 * 1024 * 1024)
43
44/*** Supplementary PCI Config Space IDs & Masks ***/
45#define PCI_DEVICE_ID_INTEL_Q35_AHCI (0x2922)
8840a843
JS		 46#define PCI_MSI_FLAGS_RESERVED (0xFF00)
47#define PCI_PM_CTRL_RESERVED (0xFC)
48#define PCI_BCC(REG32) ((REG32) >> 24)
49#define PCI_PI(REG32) (((REG32) >> 8) & 0xFF)
50#define PCI_SCC(REG32) (((REG32) >> 16) & 0xFF)
51
52/*** Recognized AHCI Device Types ***/
53#define AHCI_INTEL_ICH9 (PCI_DEVICE_ID_INTEL_Q35_AHCI << 16 | \
54 PCI_VENDOR_ID_INTEL)
1cd1031d 55
c2f3029f
JS		 56/*** AHCI/HBA Register Offsets and Bitmasks ***/
57#define AHCI_CAP (0)
58#define AHCI_CAP_NP (0x1F)
59#define AHCI_CAP_SXS (0x20)
60#define AHCI_CAP_EMS (0x40)
61#define AHCI_CAP_CCCS (0x80)
62#define AHCI_CAP_NCS (0x1F00)
63#define AHCI_CAP_PSC (0x2000)
64#define AHCI_CAP_SSC (0x4000)
65#define AHCI_CAP_PMD (0x8000)
66#define AHCI_CAP_FBSS (0x10000)
67#define AHCI_CAP_SPM (0x20000)
68#define AHCI_CAP_SAM (0x40000)
69#define AHCI_CAP_RESERVED (0x80000)
70#define AHCI_CAP_ISS (0xF00000)
71#define AHCI_CAP_SCLO (0x1000000)
72#define AHCI_CAP_SAL (0x2000000)
73#define AHCI_CAP_SALP (0x4000000)
74#define AHCI_CAP_SSS (0x8000000)
75#define AHCI_CAP_SMPS (0x10000000)
76#define AHCI_CAP_SSNTF (0x20000000)
77#define AHCI_CAP_SNCQ (0x40000000)
78#define AHCI_CAP_S64A (0x80000000)
79
80#define AHCI_GHC (1)
81#define AHCI_GHC_HR (0x01)
82#define AHCI_GHC_IE (0x02)
83#define AHCI_GHC_MRSM (0x04)
84#define AHCI_GHC_RESERVED (0x7FFFFFF8)
85#define AHCI_GHC_AE (0x80000000)
86
87#define AHCI_IS (2)
88#define AHCI_PI (3)
89#define AHCI_VS (4)
90
91#define AHCI_CCCCTL (5)
92#define AHCI_CCCCTL_EN (0x01)
93#define AHCI_CCCCTL_RESERVED (0x06)
94#define AHCI_CCCCTL_CC (0xFF00)
95#define AHCI_CCCCTL_TV (0xFFFF0000)
96
97#define AHCI_CCCPORTS (6)
98#define AHCI_EMLOC (7)
99
100#define AHCI_EMCTL (8)
101#define AHCI_EMCTL_STSMR (0x01)
102#define AHCI_EMCTL_CTLTM (0x100)
103#define AHCI_EMCTL_CTLRST (0x200)
104#define AHCI_EMCTL_RESERVED (0xF0F0FCFE)
105
106#define AHCI_CAP2 (9)
107#define AHCI_CAP2_BOH (0x01)
108#define AHCI_CAP2_NVMP (0x02)
109#define AHCI_CAP2_APST (0x04)
110#define AHCI_CAP2_RESERVED (0xFFFFFFF8)
111
112#define AHCI_BOHC (10)
113#define AHCI_RESERVED (11)
114#define AHCI_NVMHCI (24)
115#define AHCI_VENDOR (40)
116#define AHCI_PORTS (64)
117
118/*** Port Memory Offsets & Bitmasks ***/
119#define AHCI_PX_CLB (0)
120#define AHCI_PX_CLB_RESERVED (0x1FF)
121
122#define AHCI_PX_CLBU (1)
123
124#define AHCI_PX_FB (2)
125#define AHCI_PX_FB_RESERVED (0xFF)
126
127#define AHCI_PX_FBU (3)
128
129#define AHCI_PX_IS (4)
130#define AHCI_PX_IS_DHRS (0x1)
131#define AHCI_PX_IS_PSS (0x2)
132#define AHCI_PX_IS_DSS (0x4)
133#define AHCI_PX_IS_SDBS (0x8)
134#define AHCI_PX_IS_UFS (0x10)
135#define AHCI_PX_IS_DPS (0x20)
136#define AHCI_PX_IS_PCS (0x40)
137#define AHCI_PX_IS_DMPS (0x80)
138#define AHCI_PX_IS_RESERVED (0x23FFF00)
139#define AHCI_PX_IS_PRCS (0x400000)
140#define AHCI_PX_IS_IPMS (0x800000)
141#define AHCI_PX_IS_OFS (0x1000000)
142#define AHCI_PX_IS_INFS (0x4000000)
143#define AHCI_PX_IS_IFS (0x8000000)
144#define AHCI_PX_IS_HBDS (0x10000000)
145#define AHCI_PX_IS_HBFS (0x20000000)
146#define AHCI_PX_IS_TFES (0x40000000)
147#define AHCI_PX_IS_CPDS (0x80000000)
148
149#define AHCI_PX_IE (5)
150#define AHCI_PX_IE_DHRE (0x1)
151#define AHCI_PX_IE_PSE (0x2)
152#define AHCI_PX_IE_DSE (0x4)
153#define AHCI_PX_IE_SDBE (0x8)
154#define AHCI_PX_IE_UFE (0x10)
155#define AHCI_PX_IE_DPE (0x20)
156#define AHCI_PX_IE_PCE (0x40)
157#define AHCI_PX_IE_DMPE (0x80)
158#define AHCI_PX_IE_RESERVED (0x23FFF00)
159#define AHCI_PX_IE_PRCE (0x400000)
160#define AHCI_PX_IE_IPME (0x800000)
161#define AHCI_PX_IE_OFE (0x1000000)
162#define AHCI_PX_IE_INFE (0x4000000)
163#define AHCI_PX_IE_IFE (0x8000000)
164#define AHCI_PX_IE_HBDE (0x10000000)
165#define AHCI_PX_IE_HBFE (0x20000000)
166#define AHCI_PX_IE_TFEE (0x40000000)
167#define AHCI_PX_IE_CPDE (0x80000000)
168
169#define AHCI_PX_CMD (6)
170#define AHCI_PX_CMD_ST (0x1)
171#define AHCI_PX_CMD_SUD (0x2)
172#define AHCI_PX_CMD_POD (0x4)
173#define AHCI_PX_CMD_CLO (0x8)
174#define AHCI_PX_CMD_FRE (0x10)
175#define AHCI_PX_CMD_RESERVED (0xE0)
176#define AHCI_PX_CMD_CCS (0x1F00)
177#define AHCI_PX_CMD_MPSS (0x2000)
178#define AHCI_PX_CMD_FR (0x4000)
179#define AHCI_PX_CMD_CR (0x8000)
180#define AHCI_PX_CMD_CPS (0x10000)
181#define AHCI_PX_CMD_PMA (0x20000)
182#define AHCI_PX_CMD_HPCP (0x40000)
183#define AHCI_PX_CMD_MPSP (0x80000)
184#define AHCI_PX_CMD_CPD (0x100000)
185#define AHCI_PX_CMD_ESP (0x200000)
186#define AHCI_PX_CMD_FBSCP (0x400000)
187#define AHCI_PX_CMD_APSTE (0x800000)
188#define AHCI_PX_CMD_ATAPI (0x1000000)
189#define AHCI_PX_CMD_DLAE (0x2000000)
190#define AHCI_PX_CMD_ALPE (0x4000000)
191#define AHCI_PX_CMD_ASP (0x8000000)
192#define AHCI_PX_CMD_ICC (0xF0000000)
193
194#define AHCI_PX_RES1 (7)
195
196#define AHCI_PX_TFD (8)
197#define AHCI_PX_TFD_STS (0xFF)
198#define AHCI_PX_TFD_STS_ERR (0x01)
199#define AHCI_PX_TFD_STS_CS1 (0x06)
200#define AHCI_PX_TFD_STS_DRQ (0x08)
201#define AHCI_PX_TFD_STS_CS2 (0x70)
202#define AHCI_PX_TFD_STS_BSY (0x80)
203#define AHCI_PX_TFD_ERR (0xFF00)
204#define AHCI_PX_TFD_RESERVED (0xFFFF0000)
205
206#define AHCI_PX_SIG (9)
207#define AHCI_PX_SIG_SECTOR_COUNT (0xFF)
208#define AHCI_PX_SIG_LBA_LOW (0xFF00)
209#define AHCI_PX_SIG_LBA_MID (0xFF0000)
210#define AHCI_PX_SIG_LBA_HIGH (0xFF000000)
211
212#define AHCI_PX_SSTS (10)
213#define AHCI_PX_SSTS_DET (0x0F)
214#define AHCI_PX_SSTS_SPD (0xF0)
215#define AHCI_PX_SSTS_IPM (0xF00)
216#define AHCI_PX_SSTS_RESERVED (0xFFFFF000)
217#define SSTS_DET_NO_DEVICE (0x00)
218#define SSTS_DET_PRESENT (0x01)
219#define SSTS_DET_ESTABLISHED (0x03)
220#define SSTS_DET_OFFLINE (0x04)
221
222#define AHCI_PX_SCTL (11)
223
224#define AHCI_PX_SERR (12)
225#define AHCI_PX_SERR_ERR (0xFFFF)
226#define AHCI_PX_SERR_DIAG (0xFFFF0000)
227#define AHCI_PX_SERR_DIAG_X (0x04000000)
228
229#define AHCI_PX_SACT (13)
230#define AHCI_PX_CI (14)
231#define AHCI_PX_SNTF (15)
232
233#define AHCI_PX_FBS (16)
234#define AHCI_PX_FBS_EN (0x1)
235#define AHCI_PX_FBS_DEC (0x2)
236#define AHCI_PX_FBS_SDE (0x4)
237#define AHCI_PX_FBS_DEV (0xF00)
238#define AHCI_PX_FBS_ADO (0xF000)
239#define AHCI_PX_FBS_DWE (0xF0000)
240#define AHCI_PX_FBS_RESERVED (0xFFF000F8)
241
242#define AHCI_PX_RES2 (17)
243#define AHCI_PX_VS (28)
244
245#define HBA_DATA_REGION_SIZE (256)
246#define HBA_PORT_DATA_SIZE (128)
247#define HBA_PORT_NUM_REG (HBA_PORT_DATA_SIZE/4)
248
249#define AHCI_VERSION_0_95 (0x00000905)
250#define AHCI_VERSION_1_0 (0x00010000)
251#define AHCI_VERSION_1_1 (0x00010100)
252#define AHCI_VERSION_1_2 (0x00010200)
253#define AHCI_VERSION_1_3 (0x00010300)
254
0fa781e3
JS		 255/*** Structures ***/
256
257/**
258 * Generic FIS structure.
259 */
260typedef struct FIS {
261 uint8_t fis_type;
262 uint8_t flags;
263 char data[0];
264} __attribute__((__packed__)) FIS;
265
266/**
267 * Register device-to-host FIS structure.
268 */
269typedef struct RegD2HFIS {
270 /* DW0 */
271 uint8_t fis_type;
272 uint8_t flags;
273 uint8_t status;
274 uint8_t error;
275 /* DW1 */
276 uint8_t lba_low;
277 uint8_t lba_mid;
278 uint8_t lba_high;
279 uint8_t device;
280 /* DW2 */
281 uint8_t lba3;
282 uint8_t lba4;
283 uint8_t lba5;
284 uint8_t res1;
285 /* DW3 */
286 uint16_t count;
287 uint8_t res2;
288 uint8_t res3;
289 /* DW4 */
290 uint16_t res4;
291 uint16_t res5;
292} __attribute__((__packed__)) RegD2HFIS;
293
294/**
295 * Register host-to-device FIS structure.
296 */
297typedef struct RegH2DFIS {
298 /* DW0 */
299 uint8_t fis_type;
300 uint8_t flags;
301 uint8_t command;
302 uint8_t feature_low;
303 /* DW1 */
304 uint8_t lba_low;
305 uint8_t lba_mid;
306 uint8_t lba_high;
307 uint8_t device;
308 /* DW2 */
309 uint8_t lba3;
310 uint8_t lba4;
311 uint8_t lba5;
312 uint8_t feature_high;
313 /* DW3 */
314 uint16_t count;
315 uint8_t icc;
316 uint8_t control;
317 /* DW4 */
318 uint32_t aux;
319} __attribute__((__packed__)) RegH2DFIS;
320
321/**
322 * Command List entry structure.
323 * The command list contains between 1-32 of these structures.
324 */
325typedef struct AHCICommand {
326 uint8_t b1;
327 uint8_t b2;
328 uint16_t prdtl; /* Phys Region Desc. Table Length */
329 uint32_t prdbc; /* Phys Region Desc. Byte Count */
330 uint32_t ctba; /* Command Table Descriptor Base Address */
331 uint32_t ctbau; /* '' Upper */
332 uint32_t res[4];
333} __attribute__((__packed__)) AHCICommand;
334
335/**
336 * Physical Region Descriptor; pointed to by the Command List Header,
337 * struct ahci_command.
338 */
339typedef struct PRD {
340 uint32_t dba; /* Data Base Address */
341 uint32_t dbau; /* Data Base Address Upper */
342 uint32_t res; /* Reserved */
343 uint32_t dbc; /* Data Byte Count (0-indexed) & Interrupt Flag (bit 2^31) */
344} PRD;
345
c2f3029f
JS		 346typedef struct HBACap {
347 uint32_t cap;
348 uint32_t cap2;
349} HBACap;
350
1cd1031d
JS		 351/*** Globals ***/
352static QGuestAllocator *guest_malloc;
353static QPCIBus *pcibus;
c2f3029f 354static uint64_t barsize;
1cd1031d 355static char tmp_path[] = "/tmp/qtest.XXXXXX";
8840a843
JS		 356static bool ahci_pedantic;
357static uint32_t ahci_fingerprint;
358
359/*** Macro Utilities ***/
c2f3029f
JS		 360#define BITANY(data, mask) (((data) & (mask)) != 0)
361#define BITSET(data, mask) (((data) & (mask)) == (mask))
362#define BITCLR(data, mask) (((data) & (mask)) == 0)
8840a843
JS		 363#define ASSERT_BIT_SET(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
364#define ASSERT_BIT_CLEAR(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
1cd1031d 365
c2f3029f
JS		 366/*** IO macros for the AHCI memory registers. ***/
367#define AHCI_READ(OFST) qpci_io_readl(ahci, hba_base + (OFST))
368#define AHCI_WRITE(OFST, VAL) qpci_io_writel(ahci, hba_base + (OFST), (VAL))
369#define AHCI_RREG(regno) AHCI_READ(4 * (regno))
370#define AHCI_WREG(regno, val) AHCI_WRITE(4 * (regno), (val))
dbc180e5
JS		 371#define AHCI_SET(regno, mask) AHCI_WREG((regno), AHCI_RREG(regno) | (mask))
372#define AHCI_CLR(regno, mask) AHCI_WREG((regno), AHCI_RREG(regno) & ~(mask))
c2f3029f
JS		 373
374/*** IO macros for port-specific offsets inside of AHCI memory. ***/
375#define PX_OFST(port, regno) (HBA_PORT_NUM_REG * (port) + AHCI_PORTS + (regno))
376#define PX_RREG(port, regno) AHCI_RREG(PX_OFST((port), (regno)))
377#define PX_WREG(port, regno, val) AHCI_WREG(PX_OFST((port), (regno)), (val))
dbc180e5
JS		 378#define PX_SET(port, reg, mask) PX_WREG((port), (reg), \
379 PX_RREG((port), (reg)) | (mask));
380#define PX_CLR(port, reg, mask) PX_WREG((port), (reg), \
381 PX_RREG((port), (reg)) & ~(mask));
c2f3029f 382
0fa781e3
JS		 383/* For calculating how big the PRD table needs to be: */
384#define CMD_TBL_SIZ(n) ((0x80 + ((n) * sizeof(PRD)) + 0x7F) & ~0x7F)
385
386
1cd1031d
JS		 387/*** Function Declarations ***/
388static QPCIDevice *get_ahci_device(void);
96d6d3ba 389static QPCIDevice *start_ahci_device(QPCIDevice *dev, void **hba_base);
1cd1031d 390static void free_ahci_device(QPCIDevice *dev);
c2f3029f
JS		 391static void ahci_test_port_spec(QPCIDevice *ahci, void *hba_base,
392 HBACap *hcap, uint8_t port);
8840a843
JS		 393static void ahci_test_pci_spec(QPCIDevice *ahci);
394static void ahci_test_pci_caps(QPCIDevice *ahci, uint16_t header,
395 uint8_t offset);
396static void ahci_test_satacap(QPCIDevice *ahci, uint8_t offset);
397static void ahci_test_msicap(QPCIDevice *ahci, uint8_t offset);
398static void ahci_test_pmcap(QPCIDevice *ahci, uint8_t offset);
1cd1031d
JS		 399
400/*** Utilities ***/
401
0fa781e3
JS		 402static void string_bswap16(uint16_t *s, size_t bytes)
403{
404 g_assert_cmphex((bytes & 1), ==, 0);
405 bytes /= 2;
406
407 while (bytes--) {
408 *s = bswap16(*s);
409 s++;
410 }
411}
412
1cd1031d
JS		 413/**
414 * Locate, verify, and return a handle to the AHCI device.
415 */
416static QPCIDevice *get_ahci_device(void)
417{
418 QPCIDevice *ahci;
1cd1031d
JS		 419
420 pcibus = qpci_init_pc();
421
422 /* Find the AHCI PCI device and verify it's the right one. */
423 ahci = qpci_device_find(pcibus, QPCI_DEVFN(0x1F, 0x02));
424 g_assert(ahci != NULL);
425
8840a843 426 ahci_fingerprint = qpci_config_readl(ahci, PCI_VENDOR_ID);
1cd1031d 427
8840a843
JS		 428 switch (ahci_fingerprint) {
429 case AHCI_INTEL_ICH9:
430 break;
431 default:
432 /* Unknown device. */
433 g_assert_not_reached();
434 }
1cd1031d
JS		 435
436 return ahci;
437}
438
439static void free_ahci_device(QPCIDevice *ahci)
440{
441 /* libqos doesn't have a function for this, so free it manually */
442 g_free(ahci);
443
444 if (pcibus) {
445 qpci_free_pc(pcibus);
446 pcibus = NULL;
447 }
c2f3029f
JS		 448
449 /* Clear our cached barsize information. */
450 barsize = 0;
1cd1031d
JS		 451}
452
453/*** Test Setup & Teardown ***/
454
455/**
456 * Launch QEMU with the given command line,
457 * and then set up interrupts and our guest malloc interface.
458 */
459static void qtest_boot(const char *cmdline_fmt, ...)
460{
461 va_list ap;
462 char *cmdline;
463
464 va_start(ap, cmdline_fmt);
465 cmdline = g_strdup_vprintf(cmdline_fmt, ap);
466 va_end(ap);
467
468 qtest_start(cmdline);
469 qtest_irq_intercept_in(global_qtest, "ioapic");
470 guest_malloc = pc_alloc_init();
471
472 g_free(cmdline);
473}
474
475/**
476 * Tear down the QEMU instance.
477 */
478static void qtest_shutdown(void)
479{
480 g_free(guest_malloc);
481 guest_malloc = NULL;
482 qtest_end();
483}
484
485/**
486 * Start a Q35 machine and bookmark a handle to the AHCI device.
487 */
488static QPCIDevice *ahci_boot(void)
489{
490 qtest_boot("-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s"
491 " -M q35 "
492 "-device ide-hd,drive=drive0 "
493 "-global ide-hd.ver=%s",
494 tmp_path, "testdisk", "version");
495
496 /* Verify that we have an AHCI device present. */
497 return get_ahci_device();
498}
499
500/**
501 * Clean up the PCI device, then terminate the QEMU instance.
502 */
503static void ahci_shutdown(QPCIDevice *ahci)
504{
505 free_ahci_device(ahci);
506 qtest_shutdown();
507}
508
96d6d3ba
JS		 509/*** Logical Device Initialization ***/
510
511/**
512 * Start the PCI device and sanity-check default operation.
513 */
514static void ahci_pci_enable(QPCIDevice *ahci, void **hba_base)
515{
516 uint8_t reg;
517
518 start_ahci_device(ahci, hba_base);
519
520 switch (ahci_fingerprint) {
521 case AHCI_INTEL_ICH9:
522 /* ICH9 has a register at PCI 0x92 that
523 * acts as a master port enabler mask. */
524 reg = qpci_config_readb(ahci, 0x92);
525 reg |= 0x3F;
526 qpci_config_writeb(ahci, 0x92, reg);
0fa781e3 527 /* 0...0111111b -- bit significant, ports 0-5 enabled. */
96d6d3ba
JS		 528 ASSERT_BIT_SET(qpci_config_readb(ahci, 0x92), 0x3F);
529 break;
530 }
531
532}
533
534/**
535 * Map BAR5/ABAR, and engage the PCI device.
536 */
537static QPCIDevice *start_ahci_device(QPCIDevice *ahci, void **hba_base)
538{
539 /* Map AHCI's ABAR (BAR5) */
c2f3029f 540 *hba_base = qpci_iomap(ahci, 5, &barsize);
96d6d3ba
JS		 541
542 /* turns on pci.cmd.iose, pci.cmd.mse and pci.cmd.bme */
543 qpci_device_enable(ahci);
544
545 return ahci;
546}
547
dbc180e5
JS		 548/**
549 * Test and initialize the AHCI's HBA memory areas.
550 * Initialize and start any ports with devices attached.
551 * Bring the HBA into the idle state.
552 */
553static void ahci_hba_enable(QPCIDevice *ahci, void *hba_base)
554{
555 /* Bits of interest in this section:
556 * GHC.AE Global Host Control / AHCI Enable
557 * PxCMD.ST Port Command: Start
558 * PxCMD.SUD "Spin Up Device"
559 * PxCMD.POD "Power On Device"
560 * PxCMD.FRE "FIS Receive Enable"
561 * PxCMD.FR "FIS Receive Running"
562 * PxCMD.CR "Command List Running"
563 */
564
565 g_assert(ahci != NULL);
566 g_assert(hba_base != NULL);
567
568 uint32_t reg, ports_impl, clb, fb;
569 uint16_t i;
570 uint8_t num_cmd_slots;
571
572 g_assert(hba_base != 0);
573
574 /* Set GHC.AE to 1 */
575 AHCI_SET(AHCI_GHC, AHCI_GHC_AE);
576 reg = AHCI_RREG(AHCI_GHC);
577 ASSERT_BIT_SET(reg, AHCI_GHC_AE);
578
579 /* Read CAP.NCS, how many command slots do we have? */
580 reg = AHCI_RREG(AHCI_CAP);
581 num_cmd_slots = ((reg & AHCI_CAP_NCS) >> ctzl(AHCI_CAP_NCS)) + 1;
582 g_test_message("Number of Command Slots: %u", num_cmd_slots);
583
584 /* Determine which ports are implemented. */
585 ports_impl = AHCI_RREG(AHCI_PI);
586
587 for (i = 0; ports_impl; ports_impl >>= 1, ++i) {
588 if (!(ports_impl & 0x01)) {
589 continue;
590 }
591
592 g_test_message("Initializing port %u", i);
593
594 reg = PX_RREG(i, AHCI_PX_CMD);
595 if (BITCLR(reg, AHCI_PX_CMD_ST | AHCI_PX_CMD_CR |
596 AHCI_PX_CMD_FRE | AHCI_PX_CMD_FR)) {
597 g_test_message("port is idle");
598 } else {
599 g_test_message("port needs to be idled");
600 PX_CLR(i, AHCI_PX_CMD, (AHCI_PX_CMD_ST | AHCI_PX_CMD_FRE));
601 /* The port has 500ms to disengage. */
602 usleep(500000);
603 reg = PX_RREG(i, AHCI_PX_CMD);
604 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
605 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
606 g_test_message("port is now idle");
607 /* The spec does allow for possibly needing a PORT RESET
608 * or HBA reset if we fail to idle the port. */
609 }
610
611 /* Allocate Memory for the Command List Buffer & FIS Buffer */
612 /* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */
613 clb = guest_alloc(guest_malloc, num_cmd_slots * 0x20);
614 g_test_message("CLB: 0x%08x", clb);
615 PX_WREG(i, AHCI_PX_CLB, clb);
616 g_assert_cmphex(clb, ==, PX_RREG(i, AHCI_PX_CLB));
617
618 /* PxFB space ... 0x100, as in 4.2.1 p 35 */
619 fb = guest_alloc(guest_malloc, 0x100);
620 g_test_message("FB: 0x%08x", fb);
621 PX_WREG(i, AHCI_PX_FB, fb);
622 g_assert_cmphex(fb, ==, PX_RREG(i, AHCI_PX_FB));
623
624 /* Clear PxSERR, PxIS, then IS.IPS[x] by writing '1's. */
625 PX_WREG(i, AHCI_PX_SERR, 0xFFFFFFFF);
626 PX_WREG(i, AHCI_PX_IS, 0xFFFFFFFF);
627 AHCI_WREG(AHCI_IS, (1 << i));
628
629 /* Verify Interrupts Cleared */
630 reg = PX_RREG(i, AHCI_PX_SERR);
631 g_assert_cmphex(reg, ==, 0);
632
633 reg = PX_RREG(i, AHCI_PX_IS);
634 g_assert_cmphex(reg, ==, 0);
635
636 reg = AHCI_RREG(AHCI_IS);
637 ASSERT_BIT_CLEAR(reg, (1 << i));
638
639 /* Enable All Interrupts: */
640 PX_WREG(i, AHCI_PX_IE, 0xFFFFFFFF);
641 reg = PX_RREG(i, AHCI_PX_IE);
642 g_assert_cmphex(reg, ==, ~((uint32_t)AHCI_PX_IE_RESERVED));
643
644 /* Enable the FIS Receive Engine. */
645 PX_SET(i, AHCI_PX_CMD, AHCI_PX_CMD_FRE);
646 reg = PX_RREG(i, AHCI_PX_CMD);
647 ASSERT_BIT_SET(reg, AHCI_PX_CMD_FR);
648
649 /* AHCI 1.3 spec: if !STS.BSY, !STS.DRQ and PxSSTS.DET indicates
650 * physical presence, a device is present and may be started. However,
651 * PxSERR.DIAG.X /may/ need to be cleared a priori. */
652 reg = PX_RREG(i, AHCI_PX_SERR);
653 if (BITSET(reg, AHCI_PX_SERR_DIAG_X)) {
654 PX_SET(i, AHCI_PX_SERR, AHCI_PX_SERR_DIAG_X);
655 }
656
657 reg = PX_RREG(i, AHCI_PX_TFD);
658 if (BITCLR(reg, AHCI_PX_TFD_STS_BSY | AHCI_PX_TFD_STS_DRQ)) {
659 reg = PX_RREG(i, AHCI_PX_SSTS);
660 if ((reg & AHCI_PX_SSTS_DET) == SSTS_DET_ESTABLISHED) {
661 /* Device Found: set PxCMD.ST := 1 */
662 PX_SET(i, AHCI_PX_CMD, AHCI_PX_CMD_ST);
663 ASSERT_BIT_SET(PX_RREG(i, AHCI_PX_CMD), AHCI_PX_CMD_CR);
664 g_test_message("Started Device %u", i);
665 } else if ((reg & AHCI_PX_SSTS_DET)) {
666 /* Device present, but in some unknown state. */
667 g_assert_not_reached();
668 }
669 }
670 }
671
672 /* Enable GHC.IE */
673 AHCI_SET(AHCI_GHC, AHCI_GHC_IE);
674 reg = AHCI_RREG(AHCI_GHC);
675 ASSERT_BIT_SET(reg, AHCI_GHC_IE);
676
677 /* TODO: The device should now be idling and waiting for commands.
678 * In the future, a small test-case to inspect the Register D2H FIS
679 * and clear the initial interrupts might be good. */
680}
681
8840a843
JS		 682/*** Specification Adherence Tests ***/
683
684/**
685 * Implementation for test_pci_spec. Ensures PCI configuration space is sane.
686 */
687static void ahci_test_pci_spec(QPCIDevice *ahci)
688{
689 uint8_t datab;
690 uint16_t data;
691 uint32_t datal;
692
693 /* Most of these bits should start cleared until we turn them on. */
694 data = qpci_config_readw(ahci, PCI_COMMAND);
695 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY);
696 ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER);
697 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL); /* Reserved */
698 ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE); /* Reserved */
699 ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY);
700 ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT); /* Reserved */
701 ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR);
702 ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK);
703 ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE);
704 ASSERT_BIT_CLEAR(data, 0xF800); /* Reserved */
705
706 data = qpci_config_readw(ahci, PCI_STATUS);
707 ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04); /* Reserved */
708 ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT);
709 ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST); /* must be set */
710 ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF); /* Reserved */
711 ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY);
712 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT);
713 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT);
714 ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT);
715 ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR);
716 ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY);
717
718 /* RID occupies the low byte, CCs occupy the high three. */
719 datal = qpci_config_readl(ahci, PCI_CLASS_REVISION);
720 if (ahci_pedantic) {
721 /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00,
722 * Though in practice this is likely seldom true. */
723 ASSERT_BIT_CLEAR(datal, 0xFF);
724 }
725
726 /* BCC *must* equal 0x01. */
727 g_assert_cmphex(PCI_BCC(datal), ==, 0x01);
728 if (PCI_SCC(datal) == 0x01) {
729 /* IDE */
730 ASSERT_BIT_SET(0x80000000, datal);
731 ASSERT_BIT_CLEAR(0x60000000, datal);
732 } else if (PCI_SCC(datal) == 0x04) {
733 /* RAID */
734 g_assert_cmphex(PCI_PI(datal), ==, 0);
735 } else if (PCI_SCC(datal) == 0x06) {
736 /* AHCI */
737 g_assert_cmphex(PCI_PI(datal), ==, 0x01);
738 } else {
739 g_assert_not_reached();
740 }
741
742 datab = qpci_config_readb(ahci, PCI_CACHE_LINE_SIZE);
743 g_assert_cmphex(datab, ==, 0);
744
745 datab = qpci_config_readb(ahci, PCI_LATENCY_TIMER);
746 g_assert_cmphex(datab, ==, 0);
747
748 /* Only the bottom 7 bits must be off. */
749 datab = qpci_config_readb(ahci, PCI_HEADER_TYPE);
750 ASSERT_BIT_CLEAR(datab, 0x7F);
751
752 /* BIST is optional, but the low 7 bits must always start off regardless. */
753 datab = qpci_config_readb(ahci, PCI_BIST);
754 ASSERT_BIT_CLEAR(datab, 0x7F);
755
756 /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */
757 datal = qpci_config_readl(ahci, PCI_BASE_ADDRESS_5);
758 g_assert_cmphex(datal, ==, 0);
759
760 qpci_config_writel(ahci, PCI_BASE_ADDRESS_5, 0xFFFFFFFF);
761 datal = qpci_config_readl(ahci, PCI_BASE_ADDRESS_5);
762 /* ABAR must be 32-bit, memory mapped, non-prefetchable and
763 * must be >= 512 bytes. To that end, bits 0-8 must be off. */
764 ASSERT_BIT_CLEAR(datal, 0xFF);
765
766 /* Capability list MUST be present, */
767 datal = qpci_config_readl(ahci, PCI_CAPABILITY_LIST);
768 /* But these bits are reserved. */
769 ASSERT_BIT_CLEAR(datal, ~0xFF);
770 g_assert_cmphex(datal, !=, 0);
771
772 /* Check specification adherence for capability extenstions. */
773 data = qpci_config_readw(ahci, datal);
774
775 switch (ahci_fingerprint) {
776 case AHCI_INTEL_ICH9:
777 /* Intel ICH9 Family Datasheet 14.1.19 p.550 */
778 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI);
779 break;
780 default:
781 /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */
782 g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM);
783 }
784
785 ahci_test_pci_caps(ahci, data, (uint8_t)datal);
786
787 /* Reserved. */
788 datal = qpci_config_readl(ahci, PCI_CAPABILITY_LIST + 4);
789 g_assert_cmphex(datal, ==, 0);
790
791 /* IPIN might vary, but ILINE must be off. */
792 datab = qpci_config_readb(ahci, PCI_INTERRUPT_LINE);
793 g_assert_cmphex(datab, ==, 0);
794}
795
796/**
797 * Test PCI capabilities for AHCI specification adherence.
798 */
799static void ahci_test_pci_caps(QPCIDevice *ahci, uint16_t header,
800 uint8_t offset)
801{
802 uint8_t cid = header & 0xFF;
803 uint8_t next = header >> 8;
804
805 g_test_message("CID: %02x; next: %02x", cid, next);
806
807 switch (cid) {
808 case PCI_CAP_ID_PM:
809 ahci_test_pmcap(ahci, offset);
810 break;
811 case PCI_CAP_ID_MSI:
812 ahci_test_msicap(ahci, offset);
813 break;
814 case PCI_CAP_ID_SATA:
815 ahci_test_satacap(ahci, offset);
816 break;
817
818 default:
819 g_test_message("Unknown CAP 0x%02x", cid);
820 }
821
822 if (next) {
823 ahci_test_pci_caps(ahci, qpci_config_readw(ahci, next), next);
824 }
825}
826
827/**
828 * Test SATA PCI capabilitity for AHCI specification adherence.
829 */
830static void ahci_test_satacap(QPCIDevice *ahci, uint8_t offset)
831{
832 uint16_t dataw;
833 uint32_t datal;
834
835 g_test_message("Verifying SATACAP");
836
837 /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */
838 dataw = qpci_config_readw(ahci, offset + 2);
839 g_assert_cmphex(dataw, ==, 0x10);
840
841 /* Grab the SATACR1 register. */
842 datal = qpci_config_readw(ahci, offset + 4);
843
844 switch (datal & 0x0F) {
845 case 0x04: /* BAR0 */
846 case 0x05: /* BAR1 */
847 case 0x06:
848 case 0x07:
849 case 0x08:
850 case 0x09: /* BAR5 */
851 case 0x0F: /* Immediately following SATACR1 in PCI config space. */
852 break;
853 default:
854 /* Invalid BARLOC for the Index Data Pair. */
855 g_assert_not_reached();
856 }
857
858 /* Reserved. */
859 g_assert_cmphex((datal >> 24), ==, 0x00);
860}
861
862/**
863 * Test MSI PCI capability for AHCI specification adherence.
864 */
865static void ahci_test_msicap(QPCIDevice *ahci, uint8_t offset)
866{
867 uint16_t dataw;
868 uint32_t datal;
869
870 g_test_message("Verifying MSICAP");
871
872 dataw = qpci_config_readw(ahci, offset + PCI_MSI_FLAGS);
873 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE);
874 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE);
875 ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED);
876
877 datal = qpci_config_readl(ahci, offset + PCI_MSI_ADDRESS_LO);
878 g_assert_cmphex(datal, ==, 0);
879
880 if (dataw & PCI_MSI_FLAGS_64BIT) {
881 g_test_message("MSICAP is 64bit");
882 datal = qpci_config_readl(ahci, offset + PCI_MSI_ADDRESS_HI);
883 g_assert_cmphex(datal, ==, 0);
884 dataw = qpci_config_readw(ahci, offset + PCI_MSI_DATA_64);
885 g_assert_cmphex(dataw, ==, 0);
886 } else {
887 g_test_message("MSICAP is 32bit");
888 dataw = qpci_config_readw(ahci, offset + PCI_MSI_DATA_32);
889 g_assert_cmphex(dataw, ==, 0);
890 }
891}
892
893/**
894 * Test Power Management PCI capability for AHCI specification adherence.
895 */
896static void ahci_test_pmcap(QPCIDevice *ahci, uint8_t offset)
897{
898 uint16_t dataw;
899
900 g_test_message("Verifying PMCAP");
901
902 dataw = qpci_config_readw(ahci, offset + PCI_PM_PMC);
903 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK);
904 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED);
905 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1);
906 ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2);
907
908 dataw = qpci_config_readw(ahci, offset + PCI_PM_CTRL);
909 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK);
910 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED);
911 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK);
912 ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK);
913}
914
c2f3029f
JS		 915static void ahci_test_hba_spec(QPCIDevice *ahci, void *hba_base)
916{
917 HBACap hcap;
918 unsigned i;
919 uint32_t cap, cap2, reg;
920 uint32_t ports;
921 uint8_t nports_impl;
922 uint8_t maxports;
923
924 g_assert(ahci != 0);
925 g_assert(hba_base != 0);
926
927 /*
928 * Note that the AHCI spec does expect the BIOS to set up a few things:
929 * CAP.SSS - Support for staggered spin-up (t/f)
930 * CAP.SMPS - Support for mechanical presence switches (t/f)
931 * PI - Ports Implemented (1-32)
932 * PxCMD.HPCP - Hot Plug Capable Port
933 * PxCMD.MPSP - Mechanical Presence Switch Present
934 * PxCMD.CPD - Cold Presence Detection support
935 *
936 * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97:
937 * Foreach Port Implemented:
938 * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0
939 * -PxCLB/U and PxFB/U are set to valid regions in memory
940 * -PxSUD is set to 1.
941 * -PxSSTS.DET is polled for presence; if detected, we continue:
942 * -PxSERR is cleared with 1's.
943 * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero,
944 * the device is ready.
945 */
946
947 /* 1 CAP - Capabilities Register */
948 cap = AHCI_RREG(AHCI_CAP);
949 ASSERT_BIT_CLEAR(cap, AHCI_CAP_RESERVED);
950
951 /* 2 GHC - Global Host Control */
952 reg = AHCI_RREG(AHCI_GHC);
953 ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR);
954 ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE);
955 ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM);
956 if (BITSET(cap, AHCI_CAP_SAM)) {
957 g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only.");
958 ASSERT_BIT_SET(reg, AHCI_GHC_AE);
959 } else {
960 g_test_message("Supports AHCI/Legacy mix.");
961 ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE);
962 }
963
964 /* 3 IS - Interrupt Status */
965 reg = AHCI_RREG(AHCI_IS);
966 g_assert_cmphex(reg, ==, 0);
967
968 /* 4 PI - Ports Implemented */
969 ports = AHCI_RREG(AHCI_PI);
970 /* Ports Implemented must be non-zero. */
971 g_assert_cmphex(ports, !=, 0);
972 /* Ports Implemented must be <= Number of Ports. */
973 nports_impl = ctpopl(ports);
974 g_assert_cmpuint(((AHCI_CAP_NP & cap) + 1), >=, nports_impl);
975
976 g_assert_cmphex(barsize, >, 0);
977 /* Ports must be within the proper range. Given a mapping of SIZE,
978 * 256 bytes are used for global HBA control, and the rest is used
979 * for ports data, at 0x80 bytes each. */
980 maxports = (barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE;
981 /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */
982 g_assert_cmphex((reg >> maxports), ==, 0);
983
984 /* 5 AHCI Version */
985 reg = AHCI_RREG(AHCI_VS);
986 switch (reg) {
987 case AHCI_VERSION_0_95:
988 case AHCI_VERSION_1_0:
989 case AHCI_VERSION_1_1:
990 case AHCI_VERSION_1_2:
991 case AHCI_VERSION_1_3:
992 break;
993 default:
994 g_assert_not_reached();
995 }
996
997 /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */
998 reg = AHCI_RREG(AHCI_CCCCTL);
999 if (BITSET(cap, AHCI_CAP_CCCS)) {
1000 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN);
1001 ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED);
1002 ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC);
1003 ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV);
1004 } else {
1005 g_assert_cmphex(reg, ==, 0);
1006 }
1007
1008 /* 7 CCC_PORTS */
1009 reg = AHCI_RREG(AHCI_CCCPORTS);
1010 /* Must be zeroes initially regardless of CAP.CCCS */
1011 g_assert_cmphex(reg, ==, 0);
1012
1013 /* 8 EM_LOC */
1014 reg = AHCI_RREG(AHCI_EMLOC);
1015 if (BITCLR(cap, AHCI_CAP_EMS)) {
1016 g_assert_cmphex(reg, ==, 0);
1017 }
1018
1019 /* 9 EM_CTL */
1020 reg = AHCI_RREG(AHCI_EMCTL);
1021 if (BITSET(cap, AHCI_CAP_EMS)) {
1022 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR);
1023 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM);
1024 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST);
1025 ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED);
1026 } else {
1027 g_assert_cmphex(reg, ==, 0);
1028 }
1029
1030 /* 10 CAP2 -- Capabilities Extended */
1031 cap2 = AHCI_RREG(AHCI_CAP2);
1032 ASSERT_BIT_CLEAR(cap2, AHCI_CAP2_RESERVED);
1033
1034 /* 11 BOHC -- Bios/OS Handoff Control */
1035 reg = AHCI_RREG(AHCI_BOHC);
1036 g_assert_cmphex(reg, ==, 0);
1037
1038 /* 12 -- 23: Reserved */
1039 g_test_message("Verifying HBA reserved area is empty.");
1040 for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) {
1041 reg = AHCI_RREG(i);
1042 g_assert_cmphex(reg, ==, 0);
1043 }
1044
1045 /* 24 -- 39: NVMHCI */
1046 if (BITCLR(cap2, AHCI_CAP2_NVMP)) {
1047 g_test_message("Verifying HBA/NVMHCI area is empty.");
1048 for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) {
1049 reg = AHCI_RREG(i);
1050 g_assert_cmphex(reg, ==, 0);
1051 }
1052 }
1053
1054 /* 40 -- 63: Vendor */
1055 g_test_message("Verifying HBA/Vendor area is empty.");
1056 for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) {
1057 reg = AHCI_RREG(i);
1058 g_assert_cmphex(reg, ==, 0);
1059 }
1060
1061 /* 64 -- XX: Port Space */
1062 hcap.cap = cap;
1063 hcap.cap2 = cap2;
1064 for (i = 0; ports || (i < maxports); ports >>= 1, ++i) {
1065 if (BITSET(ports, 0x1)) {
1066 g_test_message("Testing port %u for spec", i);
1067 ahci_test_port_spec(ahci, hba_base, &hcap, i);
1068 } else {
1069 uint16_t j;
1070 uint16_t low = AHCI_PORTS + (32 * i);
1071 uint16_t high = AHCI_PORTS + (32 * (i + 1));
1072 g_test_message("Asserting unimplemented port %u "
1073 "(reg [%u-%u]) is empty.",
1074 i, low, high - 1);
1075 for (j = low; j < high; ++j) {
1076 reg = AHCI_RREG(j);
1077 g_assert_cmphex(reg, ==, 0);
1078 }
1079 }
1080 }
1081}
1082
1083/**
1084 * Test the memory space for one port for specification adherence.
1085 */
1086static void ahci_test_port_spec(QPCIDevice *ahci, void *hba_base,
1087 HBACap *hcap, uint8_t port)
1088{
1089 uint32_t reg;
1090 unsigned i;
1091
1092 /* (0) CLB */
1093 reg = PX_RREG(port, AHCI_PX_CLB);
1094 ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED);
1095
1096 /* (1) CLBU */
1097 if (BITCLR(hcap->cap, AHCI_CAP_S64A)) {
1098 reg = PX_RREG(port, AHCI_PX_CLBU);
1099 g_assert_cmphex(reg, ==, 0);
1100 }
1101
1102 /* (2) FB */
1103 reg = PX_RREG(port, AHCI_PX_FB);
1104 ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED);
1105
1106 /* (3) FBU */
1107 if (BITCLR(hcap->cap, AHCI_CAP_S64A)) {
1108 reg = PX_RREG(port, AHCI_PX_FBU);
1109 g_assert_cmphex(reg, ==, 0);
1110 }
1111
1112 /* (4) IS */
1113 reg = PX_RREG(port, AHCI_PX_IS);
1114 g_assert_cmphex(reg, ==, 0);
1115
1116 /* (5) IE */
1117 reg = PX_RREG(port, AHCI_PX_IE);
1118 g_assert_cmphex(reg, ==, 0);
1119
1120 /* (6) CMD */
1121 reg = PX_RREG(port, AHCI_PX_CMD);
1122 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE);
1123 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED);
1124 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS);
1125 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
1126 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
1127 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA); /* And RW only if CAP.SPM */
1128 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE); /* RW only if CAP2.APST */
1129 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI);
1130 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE);
1131 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE); /* RW only if CAP.SALP */
1132 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP); /* RW only if CAP.SALP */
1133 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC);
1134 /* If CPDetect support does not exist, CPState must be off. */
1135 if (BITCLR(reg, AHCI_PX_CMD_CPD)) {
1136 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS);
1137 }
1138 /* If MPSPresence is not set, MPSState must be off. */
1139 if (BITCLR(reg, AHCI_PX_CMD_MPSP)) {
1140 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
1141 }
1142 /* If we do not support MPS, MPSS and MPSP must be off. */
1143 if (BITCLR(hcap->cap, AHCI_CAP_SMPS)) {
1144 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS);
1145 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP);
1146 }
1147 /* If, via CPD or MPSP we detect a drive, HPCP must be on. */
1148 if (BITANY(reg, AHCI_PX_CMD_CPD || AHCI_PX_CMD_MPSP)) {
1149 ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP);
1150 }
1151 /* HPCP and ESP cannot both be active. */
1152 g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP));
1153 /* If CAP.FBSS is not set, FBSCP must not be set. */
1154 if (BITCLR(hcap->cap, AHCI_CAP_FBSS)) {
1155 ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP);
1156 }
1157
1158 /* (7) RESERVED */
1159 reg = PX_RREG(port, AHCI_PX_RES1);
1160 g_assert_cmphex(reg, ==, 0);
1161
1162 /* (8) TFD */
1163 reg = PX_RREG(port, AHCI_PX_TFD);
1164 /* At boot, prior to an FIS being received, the TFD register should be 0x7F,
1165 * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */
1166 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR);
1167 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1);
1168 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ);
1169 ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2);
1170 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY);
1171 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
1172 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED);
1173
1174 /* (9) SIG */
1175 /* Though AHCI specifies the boot value should be 0xFFFFFFFF,
1176 * Even when GHC.ST is zero, the AHCI HBA may receive the initial
1177 * D2H register FIS and update the signature asynchronously,
1178 * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */
1179
1180 /* (10) SSTS / SCR0: SStatus */
1181 reg = PX_RREG(port, AHCI_PX_SSTS);
1182 ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED);
1183 /* Even though the register should be 0 at boot, it is asynchronous and
1184 * prone to change, so we cannot test any well known value. */
1185
1186 /* (11) SCTL / SCR2: SControl */
1187 reg = PX_RREG(port, AHCI_PX_SCTL);
1188 g_assert_cmphex(reg, ==, 0);
1189
1190 /* (12) SERR / SCR1: SError */
1191 reg = PX_RREG(port, AHCI_PX_SERR);
1192 g_assert_cmphex(reg, ==, 0);
1193
1194 /* (13) SACT / SCR3: SActive */
1195 reg = PX_RREG(port, AHCI_PX_SACT);
1196 g_assert_cmphex(reg, ==, 0);
1197
1198 /* (14) CI */
1199 reg = PX_RREG(port, AHCI_PX_CI);
1200 g_assert_cmphex(reg, ==, 0);
1201
1202 /* (15) SNTF */
1203 reg = PX_RREG(port, AHCI_PX_SNTF);
1204 g_assert_cmphex(reg, ==, 0);
1205
1206 /* (16) FBS */
1207 reg = PX_RREG(port, AHCI_PX_FBS);
1208 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN);
1209 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC);
1210 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE);
1211 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV);
1212 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE);
1213 ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED);
1214 if (BITSET(hcap->cap, AHCI_CAP_FBSS)) {
1215 /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */
1216 g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2);
1217 }
1218
1219 /* [17 -- 27] RESERVED */
1220 for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) {
1221 reg = PX_RREG(port, i);
1222 g_assert_cmphex(reg, ==, 0);
1223 }
1224
1225 /* [28 -- 31] Vendor-Specific */
1226 for (i = AHCI_PX_VS; i < 32; ++i) {
1227 reg = PX_RREG(port, i);
1228 if (reg) {
1229 g_test_message("INFO: Vendor register %u non-empty", i);
1230 }
1231 }
1232}
1233
0fa781e3
JS		 1234/**
1235 * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
1236 * device we see, then read and check the response.
1237 */
1238static void ahci_test_identify(QPCIDevice *ahci, void *hba_base)
1239{
1240 RegD2HFIS *d2h = g_malloc0(0x20);
1241 RegD2HFIS *pio = g_malloc0(0x20);
1242 RegH2DFIS fis;
1243 AHCICommand cmd;
1244 PRD prd;
1245 uint32_t ports, reg, clb, table, fb, data_ptr;
1246 uint16_t buff[256];
1247 unsigned i;
1248 int rc;
1249
1250 g_assert(ahci != NULL);
1251 g_assert(hba_base != NULL);
1252
1253 /* We need to:
1254 * (1) Create a Command Table Buffer and update the Command List Slot #0
1255 * to point to this buffer.
1256 * (2) Construct an FIS host-to-device command structure, and write it to
1257 * the top of the command table buffer.
1258 * (3) Create a data buffer for the IDENTIFY response to be sent to
1259 * (4) Create a Physical Region Descriptor that points to the data buffer,
1260 * and write it to the bottom (offset 0x80) of the command table.
1261 * (5) Now, PxCLB points to the command list, command 0 points to
1262 * our table, and our table contains an FIS instruction and a
1263 * PRD that points to our rx buffer.
1264 * (6) We inform the HBA via PxCI that there is a command ready in slot #0.
1265 */
1266
1267 /* Pick the first implemented and running port */
1268 ports = AHCI_RREG(AHCI_PI);
1269 for (i = 0; i < 32; ports >>= 1, ++i) {
1270 if (ports == 0) {
1271 i = 32;
1272 }
1273
1274 if (!(ports & 0x01)) {
1275 continue;
1276 }
1277
1278 reg = PX_RREG(i, AHCI_PX_CMD);
1279 if (BITSET(reg, AHCI_PX_CMD_ST)) {
1280 break;
1281 }
1282 }
1283 g_assert_cmphex(i, <, 32);
1284 g_test_message("Selected port %u for test", i);
1285
1286 /* Clear out this port's interrupts (ignore the init register d2h fis) */
1287 reg = PX_RREG(i, AHCI_PX_IS);
1288 PX_WREG(i, AHCI_PX_IS, reg);
1289 g_assert_cmphex(PX_RREG(i, AHCI_PX_IS), ==, 0);
1290
1291 /* Wipe the FIS-Recieve Buffer */
1292 fb = PX_RREG(i, AHCI_PX_FB);
1293 g_assert_cmphex(fb, !=, 0);
1294 qmemset(fb, 0x00, 0x100);
1295
1296 /* Create a Command Table buffer. 0x80 is the smallest with a PRDTL of 0. */
1297 /* We need at least one PRD, so round up to the nearest 0x80 multiple. */
1298 table = guest_alloc(guest_malloc, CMD_TBL_SIZ(1));
1299 g_assert(table);
1300 ASSERT_BIT_CLEAR(table, 0x7F);
1301
1302 /* Create a data buffer ... where we will dump the IDENTIFY data to. */
1303 data_ptr = guest_alloc(guest_malloc, 512);
1304 g_assert(data_ptr);
1305
1306 /* Grab the Command List Buffer pointer */
1307 clb = PX_RREG(i, AHCI_PX_CLB);
1308 g_assert(clb);
1309
1310 /* Copy the existing Command #0 structure from the CLB into local memory,
1311 * and build a new command #0. */
1312 memread(clb, &cmd, sizeof(cmd));
1313 cmd.b1 = 5; /* reg_h2d_fis is 5 double-words long */
1314 cmd.b2 = 0x04; /* clear PxTFD.STS.BSY when done */
1315 cmd.prdtl = cpu_to_le16(1); /* One PRD table entry. */
1316 cmd.prdbc = 0;
1317 cmd.ctba = cpu_to_le32(table);
1318 cmd.ctbau = 0;
1319
1320 /* Construct our PRD, noting that DBC is 0-indexed. */
1321 prd.dba = cpu_to_le32(data_ptr);
1322 prd.dbau = 0;
1323 prd.res = 0;
1324 /* 511+1 bytes, request DPS interrupt */
1325 prd.dbc = cpu_to_le32(511 | 0x80000000);
1326
1327 /* Construct our Command FIS, Based on http://wiki.osdev.org/AHCI */
1328 memset(&fis, 0x00, sizeof(fis));
1329 fis.fis_type = 0x27; /* Register Host-to-Device FIS */
1330 fis.command = 0xEC; /* IDENTIFY */
1331 fis.device = 0;
1332 fis.flags = 0x80; /* Indicate this is a command FIS */
1333
1334 /* We've committed nothing yet, no interrupts should be posted yet. */
1335 g_assert_cmphex(PX_RREG(i, AHCI_PX_IS), ==, 0);
1336
1337 /* Commit the Command FIS to the Command Table */
1338 memwrite(table, &fis, sizeof(fis));
1339
1340 /* Commit the PRD entry to the Command Table */
1341 memwrite(table + 0x80, &prd, sizeof(prd));
1342
1343 /* Commit Command #0, pointing to the Table, to the Command List Buffer. */
1344 memwrite(clb, &cmd, sizeof(cmd));
1345
1346 /* Everything is in place, but we haven't given the go-ahead yet. */
1347 g_assert_cmphex(PX_RREG(i, AHCI_PX_IS), ==, 0);
1348
1349 /* Issue Command #0 via PxCI */
1350 PX_WREG(i, AHCI_PX_CI, (1 << 0));
1351 while (BITSET(PX_RREG(i, AHCI_PX_TFD), AHCI_PX_TFD_STS_BSY)) {
1352 usleep(50);
1353 }
1354
1355 /* Check for expected interrupts */
1356 reg = PX_RREG(i, AHCI_PX_IS);
1357 ASSERT_BIT_SET(reg, AHCI_PX_IS_DHRS);
1358 ASSERT_BIT_SET(reg, AHCI_PX_IS_PSS);
1359 /* BUG: we expect AHCI_PX_IS_DPS to be set. */
1360 ASSERT_BIT_CLEAR(reg, AHCI_PX_IS_DPS);
1361
1362 /* Clear expected interrupts and assert all interrupts now cleared. */
1363 PX_WREG(i, AHCI_PX_IS, AHCI_PX_IS_DHRS | AHCI_PX_IS_PSS | AHCI_PX_IS_DPS);
1364 g_assert_cmphex(PX_RREG(i, AHCI_PX_IS), ==, 0);
1365
1366 /* Check for errors. */
1367 reg = PX_RREG(i, AHCI_PX_SERR);
1368 g_assert_cmphex(reg, ==, 0);
1369 reg = PX_RREG(i, AHCI_PX_TFD);
1370 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR);
1371 ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
1372
1373 /* Investigate CMD #0, assert that we read 512 bytes */
1374 memread(clb, &cmd, sizeof(cmd));
1375 g_assert_cmphex(512, ==, le32_to_cpu(cmd.prdbc));
1376
1377 /* Investigate FIS responses */
1378 memread(fb + 0x20, pio, 0x20);
1379 memread(fb + 0x40, d2h, 0x20);
1380 g_assert_cmphex(pio->fis_type, ==, 0x5f);
1381 g_assert_cmphex(d2h->fis_type, ==, 0x34);
1382 g_assert_cmphex(pio->flags, ==, d2h->flags);
1383 g_assert_cmphex(pio->status, ==, d2h->status);
1384 g_assert_cmphex(pio->error, ==, d2h->error);
1385
1386 reg = PX_RREG(i, AHCI_PX_TFD);
1387 g_assert_cmphex((reg & AHCI_PX_TFD_ERR), ==, pio->error);
1388 g_assert_cmphex((reg & AHCI_PX_TFD_STS), ==, pio->status);
1389 /* The PIO Setup FIS contains a "bytes read" field, which is a
1390 * 16-bit value. The Physical Region Descriptor Byte Count is
1391 * 32-bit, but for small transfers using one PRD, it should match. */
1392 g_assert_cmphex(le16_to_cpu(pio->res4), ==, le32_to_cpu(cmd.prdbc));
1393
1394 /* Last, but not least: Investigate the IDENTIFY response data. */
1395 memread(data_ptr, &buff, 512);
1396
1397 /* Check serial number/version in the buffer */
1398 /* NB: IDENTIFY strings are packed in 16bit little endian chunks.
1399 * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
1400 * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
1401 * as a consequence, only needs to unchunk the data on LE machines. */
1402 string_bswap16(&buff[10], 20);
1403 rc = memcmp(&buff[10], "testdisk ", 20);
1404 g_assert_cmphex(rc, ==, 0);
1405
1406 string_bswap16(&buff[23], 8);
1407 rc = memcmp(&buff[23], "version ", 8);
1408 g_assert_cmphex(rc, ==, 0);
1409
1410 g_free(d2h);
1411 g_free(pio);
1412}
1413
1cd1031d
JS		 1414/******************************************************************************/
1415/* Test Interfaces */
1416/******************************************************************************/
1417
1418/**
1419 * Basic sanity test to boot a machine, find an AHCI device, and shutdown.
1420 */
1421static void test_sanity(void)
1422{
1423 QPCIDevice *ahci;
1424 ahci = ahci_boot();
1425 ahci_shutdown(ahci);
1426}
1427
8840a843
JS		 1428/**
1429 * Ensure that the PCI configuration space for the AHCI device is in-line with
1430 * the AHCI 1.3 specification for initial values.
1431 */
1432static void test_pci_spec(void)
1433{
1434 QPCIDevice *ahci;
1435 ahci = ahci_boot();
1436 ahci_test_pci_spec(ahci);
1437 ahci_shutdown(ahci);
1438}
1439
96d6d3ba
JS		 1440/**
1441 * Engage the PCI AHCI device and sanity check the response.
1442 * Perform additional PCI config space bringup for the HBA.
1443 */
1444static void test_pci_enable(void)
1445{
1446 QPCIDevice *ahci;
1447 void *hba_base;
1448 ahci = ahci_boot();
1449 ahci_pci_enable(ahci, &hba_base);
1450 ahci_shutdown(ahci);
1451}
1452
c2f3029f
JS		 1453/**
1454 * Investigate the memory mapped regions of the HBA,
1455 * and test them for AHCI specification adherence.
1456 */
1457static void test_hba_spec(void)
1458{
1459 QPCIDevice *ahci;
1460 void *hba_base;
1461
1462 ahci = ahci_boot();
1463 ahci_pci_enable(ahci, &hba_base);
1464 ahci_test_hba_spec(ahci, hba_base);
1465 ahci_shutdown(ahci);
1466}
1467
dbc180e5
JS		 1468/**
1469 * Engage the HBA functionality of the AHCI PCI device,
1470 * and bring it into a functional idle state.
1471 */
1472static void test_hba_enable(void)
1473{
1474 QPCIDevice *ahci;
1475 void *hba_base;
1476
1477 ahci = ahci_boot();
1478 ahci_pci_enable(ahci, &hba_base);
1479 ahci_hba_enable(ahci, hba_base);
1480 ahci_shutdown(ahci);
1481}
1482
0fa781e3
JS		 1483/**
1484 * Bring up the device and issue an IDENTIFY command.
1485 * Inspect the state of the HBA device and the data returned.
1486 */
1487static void test_identify(void)
1488{
1489 QPCIDevice *ahci;
1490 void *hba_base;
1491
1492 ahci = ahci_boot();
1493 ahci_pci_enable(ahci, &hba_base);
1494 ahci_hba_enable(ahci, hba_base);
1495 ahci_test_identify(ahci, hba_base);
1496 ahci_shutdown(ahci);
1497}
1498
1cd1031d
JS		 1499/******************************************************************************/
1500
1501int main(int argc, char **argv)
1502{
1503 const char *arch;
1504 int fd;
1505 int ret;
8840a843
JS		 1506 int c;
1507
1508 static struct option long_options[] = {
1509 {"pedantic", no_argument, 0, 'p' },
1510 {0, 0, 0, 0},
1511 };
1cd1031d
JS		 1512
1513 /* Should be first to utilize g_test functionality, So we can see errors. */
1514 g_test_init(&argc, &argv, NULL);
1515
8840a843
JS		 1516 while (1) {
1517 c = getopt_long(argc, argv, "", long_options, NULL);
1518 if (c == -1) {
1519 break;
1520 }
1521 switch (c) {
1522 case -1:
1523 break;
1524 case 'p':
1525 ahci_pedantic = 1;
1526 break;
1527 default:
1528 fprintf(stderr, "Unrecognized ahci_test option.\n");
1529 g_assert_not_reached();
1530 }
1531 }
1532
1cd1031d
JS		 1533 /* Check architecture */
1534 arch = qtest_get_arch();
1535 if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
1536 g_test_message("Skipping test for non-x86");
1537 return 0;
1538 }
1539
1540 /* Create a temporary raw image */
1541 fd = mkstemp(tmp_path);
1542 g_assert(fd >= 0);
1543 ret = ftruncate(fd, TEST_IMAGE_SIZE);
1544 g_assert(ret == 0);
1545 close(fd);
1546
1547 /* Run the tests */
1548 qtest_add_func("/ahci/sanity", test_sanity);
8840a843 1549 qtest_add_func("/ahci/pci_spec", test_pci_spec);
96d6d3ba 1550 qtest_add_func("/ahci/pci_enable", test_pci_enable);
c2f3029f 1551 qtest_add_func("/ahci/hba_spec", test_hba_spec);
dbc180e5 1552 qtest_add_func("/ahci/hba_enable", test_hba_enable);
0fa781e3 1553 qtest_add_func("/ahci/identify", test_identify);
1cd1031d
JS		 1554
1555 ret = g_test_run();
1556
1557 /* Cleanup */
1558 unlink(tmp_path);
1559
1560 return ret;
1561}
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