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1cd1031d JS |
1 | /* |
2 | * AHCI test cases | |
3 | * | |
4 | * Copyright (c) 2014 John Snow <jsnow@redhat.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
53239262 | 25 | #include "qemu/osdep.h" |
8840a843 | 26 | #include <getopt.h> |
1cd1031d JS |
27 | |
28 | #include "libqtest.h" | |
90e5add6 | 29 | #include "libqos/libqos-pc.h" |
90fc5e09 | 30 | #include "libqos/ahci.h" |
1cd1031d | 31 | #include "libqos/pci-pc.h" |
1cd1031d JS |
32 | |
33 | #include "qemu-common.h" | |
34 | #include "qemu/host-utils.h" | |
35 | ||
36 | #include "hw/pci/pci_ids.h" | |
37 | #include "hw/pci/pci_regs.h" | |
38 | ||
917158dc JS |
39 | /* Test images sizes in MB */ |
40 | #define TEST_IMAGE_SIZE_MB_LARGE (200 * 1024) | |
41 | #define TEST_IMAGE_SIZE_MB_SMALL 64 | |
1cd1031d | 42 | |
1cd1031d | 43 | /*** Globals ***/ |
1cd1031d | 44 | static char tmp_path[] = "/tmp/qtest.XXXXXX"; |
cf5aa89e | 45 | static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX"; |
6d9e7295 | 46 | static char mig_socket[] = "/tmp/qtest-migration.XXXXXX"; |
8840a843 | 47 | static bool ahci_pedantic; |
b236b610 | 48 | static const char *imgfmt; |
917158dc | 49 | static unsigned test_image_size_mb; |
8840a843 | 50 | |
1cd1031d | 51 | /*** Function Declarations ***/ |
8d5eeced | 52 | static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port); |
6100ddb0 JS |
53 | static void ahci_test_pci_spec(AHCIQState *ahci); |
54 | static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header, | |
8840a843 | 55 | uint8_t offset); |
6100ddb0 JS |
56 | static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset); |
57 | static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset); | |
58 | static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset); | |
1cd1031d JS |
59 | |
60 | /*** Utilities ***/ | |
61 | ||
917158dc JS |
62 | static uint64_t mb_to_sectors(uint64_t image_size_mb) |
63 | { | |
64 | return (image_size_mb * 1024 * 1024) / AHCI_SECTOR_SIZE; | |
65 | } | |
66 | ||
0fa781e3 JS |
67 | static void string_bswap16(uint16_t *s, size_t bytes) |
68 | { | |
69 | g_assert_cmphex((bytes & 1), ==, 0); | |
70 | bytes /= 2; | |
71 | ||
72 | while (bytes--) { | |
73 | *s = bswap16(*s); | |
74 | s++; | |
75 | } | |
76 | } | |
77 | ||
278128ab JS |
78 | /** |
79 | * Verify that the transfer did not corrupt our state at all. | |
80 | */ | |
e7c8526b | 81 | static void verify_state(AHCIQState *ahci, uint64_t hba_old) |
278128ab JS |
82 | { |
83 | int i, j; | |
84 | uint32_t ahci_fingerprint; | |
85 | uint64_t hba_base; | |
278128ab JS |
86 | AHCICommandHeader cmd; |
87 | ||
88 | ahci_fingerprint = qpci_config_readl(ahci->dev, PCI_VENDOR_ID); | |
89 | g_assert_cmphex(ahci_fingerprint, ==, ahci->fingerprint); | |
90 | ||
91 | /* If we haven't initialized, this is as much as can be validated. */ | |
e7c8526b | 92 | if (!ahci->enabled) { |
278128ab JS |
93 | return; |
94 | } | |
95 | ||
96 | hba_base = (uint64_t)qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5); | |
e7c8526b | 97 | g_assert_cmphex(hba_base, ==, hba_old); |
278128ab JS |
98 | |
99 | g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP), ==, ahci->cap); | |
100 | g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP2), ==, ahci->cap2); | |
101 | ||
102 | for (i = 0; i < 32; i++) { | |
103 | g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_FB), ==, | |
104 | ahci->port[i].fb); | |
105 | g_assert_cmphex(ahci_px_rreg(ahci, i, AHCI_PX_CLB), ==, | |
106 | ahci->port[i].clb); | |
107 | for (j = 0; j < 32; j++) { | |
108 | ahci_get_command_header(ahci, i, j, &cmd); | |
109 | g_assert_cmphex(cmd.prdtl, ==, ahci->port[i].prdtl[j]); | |
110 | g_assert_cmphex(cmd.ctba, ==, ahci->port[i].ctba[j]); | |
111 | } | |
112 | } | |
113 | } | |
114 | ||
115 | static void ahci_migrate(AHCIQState *from, AHCIQState *to, const char *uri) | |
116 | { | |
117 | QOSState *tmp = to->parent; | |
118 | QPCIDevice *dev = to->dev; | |
6d9e7295 | 119 | char *uri_local = NULL; |
e7c8526b | 120 | uint64_t hba_old; |
6d9e7295 | 121 | |
278128ab | 122 | if (uri == NULL) { |
6d9e7295 JS |
123 | uri_local = g_strdup_printf("%s%s", "unix:", mig_socket); |
124 | uri = uri_local; | |
278128ab JS |
125 | } |
126 | ||
e7c8526b DG |
127 | hba_old = (uint64_t)qpci_config_readl(from->dev, PCI_BASE_ADDRESS_5); |
128 | ||
278128ab JS |
129 | /* context will be 'to' after completion. */ |
130 | migrate(from->parent, to->parent, uri); | |
131 | ||
132 | /* We'd like for the AHCIState objects to still point | |
133 | * to information specific to its specific parent | |
134 | * instance, but otherwise just inherit the new data. */ | |
135 | memcpy(to, from, sizeof(AHCIQState)); | |
136 | to->parent = tmp; | |
137 | to->dev = dev; | |
138 | ||
139 | tmp = from->parent; | |
140 | dev = from->dev; | |
141 | memset(from, 0x00, sizeof(AHCIQState)); | |
142 | from->parent = tmp; | |
143 | from->dev = dev; | |
144 | ||
e7c8526b | 145 | verify_state(to, hba_old); |
6d9e7295 | 146 | g_free(uri_local); |
278128ab JS |
147 | } |
148 | ||
1cd1031d JS |
149 | /*** Test Setup & Teardown ***/ |
150 | ||
151 | /** | |
dd0029c0 | 152 | * Start a Q35 machine and bookmark a handle to the AHCI device. |
1cd1031d | 153 | */ |
debaaa11 | 154 | static AHCIQState *ahci_vboot(const char *cli, va_list ap) |
1cd1031d | 155 | { |
dd0029c0 | 156 | AHCIQState *s; |
1cd1031d | 157 | |
dd0029c0 | 158 | s = g_malloc0(sizeof(AHCIQState)); |
debaaa11 | 159 | s->parent = qtest_pc_vboot(cli, ap); |
259342d3 | 160 | alloc_set_flags(s->parent->alloc, ALLOC_LEAK_ASSERT); |
1cd1031d | 161 | |
dd0029c0 | 162 | /* Verify that we have an AHCI device present. */ |
8d5eeced | 163 | s->dev = get_ahci_device(&s->fingerprint); |
1cd1031d | 164 | |
dd0029c0 | 165 | return s; |
1cd1031d JS |
166 | } |
167 | ||
debaaa11 JS |
168 | /** |
169 | * Start a Q35 machine and bookmark a handle to the AHCI device. | |
170 | */ | |
171 | static AHCIQState *ahci_boot(const char *cli, ...) | |
172 | { | |
173 | AHCIQState *s; | |
174 | va_list ap; | |
175 | ||
176 | if (cli) { | |
177 | va_start(ap, cli); | |
178 | s = ahci_vboot(cli, ap); | |
179 | va_end(ap); | |
180 | } else { | |
181 | cli = "-drive if=none,id=drive0,file=%s,cache=writeback,serial=%s" | |
b236b610 | 182 | ",format=%s" |
debaaa11 JS |
183 | " -M q35 " |
184 | "-device ide-hd,drive=drive0 " | |
185 | "-global ide-hd.ver=%s"; | |
b236b610 | 186 | s = ahci_boot(cli, tmp_path, "testdisk", imgfmt, "version"); |
debaaa11 JS |
187 | } |
188 | ||
189 | return s; | |
190 | } | |
191 | ||
1cd1031d JS |
192 | /** |
193 | * Clean up the PCI device, then terminate the QEMU instance. | |
194 | */ | |
dd0029c0 | 195 | static void ahci_shutdown(AHCIQState *ahci) |
1cd1031d | 196 | { |
dd0029c0 | 197 | QOSState *qs = ahci->parent; |
278128ab JS |
198 | |
199 | set_context(qs); | |
259342d3 | 200 | ahci_clean_mem(ahci); |
dd0029c0 JS |
201 | free_ahci_device(ahci->dev); |
202 | g_free(ahci); | |
203 | qtest_shutdown(qs); | |
1cd1031d JS |
204 | } |
205 | ||
d63b4017 JS |
206 | /** |
207 | * Boot and fully enable the HBA device. | |
208 | * @see ahci_boot, ahci_pci_enable and ahci_hba_enable. | |
209 | */ | |
debaaa11 | 210 | static AHCIQState *ahci_boot_and_enable(const char *cli, ...) |
d63b4017 JS |
211 | { |
212 | AHCIQState *ahci; | |
debaaa11 | 213 | va_list ap; |
34475239 JS |
214 | uint16_t buff[256]; |
215 | uint8_t port; | |
d0b282a5 | 216 | uint8_t hello; |
debaaa11 JS |
217 | |
218 | if (cli) { | |
219 | va_start(ap, cli); | |
220 | ahci = ahci_vboot(cli, ap); | |
221 | va_end(ap); | |
222 | } else { | |
223 | ahci = ahci_boot(NULL); | |
224 | } | |
d63b4017 JS |
225 | |
226 | ahci_pci_enable(ahci); | |
227 | ahci_hba_enable(ahci); | |
34475239 JS |
228 | /* Initialize test device */ |
229 | port = ahci_port_select(ahci); | |
230 | ahci_port_clear(ahci, port); | |
d0b282a5 JS |
231 | if (is_atapi(ahci, port)) { |
232 | hello = CMD_PACKET_ID; | |
233 | } else { | |
234 | hello = CMD_IDENTIFY; | |
235 | } | |
236 | ahci_io(ahci, port, hello, &buff, sizeof(buff), 0); | |
d63b4017 JS |
237 | |
238 | return ahci; | |
239 | } | |
240 | ||
8840a843 JS |
241 | /*** Specification Adherence Tests ***/ |
242 | ||
243 | /** | |
244 | * Implementation for test_pci_spec. Ensures PCI configuration space is sane. | |
245 | */ | |
6100ddb0 | 246 | static void ahci_test_pci_spec(AHCIQState *ahci) |
8840a843 JS |
247 | { |
248 | uint8_t datab; | |
249 | uint16_t data; | |
250 | uint32_t datal; | |
251 | ||
252 | /* Most of these bits should start cleared until we turn them on. */ | |
6100ddb0 | 253 | data = qpci_config_readw(ahci->dev, PCI_COMMAND); |
8840a843 JS |
254 | ASSERT_BIT_CLEAR(data, PCI_COMMAND_MEMORY); |
255 | ASSERT_BIT_CLEAR(data, PCI_COMMAND_MASTER); | |
256 | ASSERT_BIT_CLEAR(data, PCI_COMMAND_SPECIAL); /* Reserved */ | |
257 | ASSERT_BIT_CLEAR(data, PCI_COMMAND_VGA_PALETTE); /* Reserved */ | |
258 | ASSERT_BIT_CLEAR(data, PCI_COMMAND_PARITY); | |
259 | ASSERT_BIT_CLEAR(data, PCI_COMMAND_WAIT); /* Reserved */ | |
260 | ASSERT_BIT_CLEAR(data, PCI_COMMAND_SERR); | |
261 | ASSERT_BIT_CLEAR(data, PCI_COMMAND_FAST_BACK); | |
262 | ASSERT_BIT_CLEAR(data, PCI_COMMAND_INTX_DISABLE); | |
263 | ASSERT_BIT_CLEAR(data, 0xF800); /* Reserved */ | |
264 | ||
6100ddb0 | 265 | data = qpci_config_readw(ahci->dev, PCI_STATUS); |
8840a843 JS |
266 | ASSERT_BIT_CLEAR(data, 0x01 | 0x02 | 0x04); /* Reserved */ |
267 | ASSERT_BIT_CLEAR(data, PCI_STATUS_INTERRUPT); | |
268 | ASSERT_BIT_SET(data, PCI_STATUS_CAP_LIST); /* must be set */ | |
269 | ASSERT_BIT_CLEAR(data, PCI_STATUS_UDF); /* Reserved */ | |
270 | ASSERT_BIT_CLEAR(data, PCI_STATUS_PARITY); | |
271 | ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_TARGET_ABORT); | |
272 | ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_TARGET_ABORT); | |
273 | ASSERT_BIT_CLEAR(data, PCI_STATUS_REC_MASTER_ABORT); | |
274 | ASSERT_BIT_CLEAR(data, PCI_STATUS_SIG_SYSTEM_ERROR); | |
275 | ASSERT_BIT_CLEAR(data, PCI_STATUS_DETECTED_PARITY); | |
276 | ||
277 | /* RID occupies the low byte, CCs occupy the high three. */ | |
6100ddb0 | 278 | datal = qpci_config_readl(ahci->dev, PCI_CLASS_REVISION); |
8840a843 JS |
279 | if (ahci_pedantic) { |
280 | /* AHCI 1.3 specifies that at-boot, the RID should reset to 0x00, | |
281 | * Though in practice this is likely seldom true. */ | |
282 | ASSERT_BIT_CLEAR(datal, 0xFF); | |
283 | } | |
284 | ||
285 | /* BCC *must* equal 0x01. */ | |
286 | g_assert_cmphex(PCI_BCC(datal), ==, 0x01); | |
287 | if (PCI_SCC(datal) == 0x01) { | |
288 | /* IDE */ | |
289 | ASSERT_BIT_SET(0x80000000, datal); | |
290 | ASSERT_BIT_CLEAR(0x60000000, datal); | |
291 | } else if (PCI_SCC(datal) == 0x04) { | |
292 | /* RAID */ | |
293 | g_assert_cmphex(PCI_PI(datal), ==, 0); | |
294 | } else if (PCI_SCC(datal) == 0x06) { | |
295 | /* AHCI */ | |
296 | g_assert_cmphex(PCI_PI(datal), ==, 0x01); | |
297 | } else { | |
298 | g_assert_not_reached(); | |
299 | } | |
300 | ||
6100ddb0 | 301 | datab = qpci_config_readb(ahci->dev, PCI_CACHE_LINE_SIZE); |
8840a843 JS |
302 | g_assert_cmphex(datab, ==, 0); |
303 | ||
6100ddb0 | 304 | datab = qpci_config_readb(ahci->dev, PCI_LATENCY_TIMER); |
8840a843 JS |
305 | g_assert_cmphex(datab, ==, 0); |
306 | ||
307 | /* Only the bottom 7 bits must be off. */ | |
6100ddb0 | 308 | datab = qpci_config_readb(ahci->dev, PCI_HEADER_TYPE); |
8840a843 JS |
309 | ASSERT_BIT_CLEAR(datab, 0x7F); |
310 | ||
311 | /* BIST is optional, but the low 7 bits must always start off regardless. */ | |
6100ddb0 | 312 | datab = qpci_config_readb(ahci->dev, PCI_BIST); |
8840a843 JS |
313 | ASSERT_BIT_CLEAR(datab, 0x7F); |
314 | ||
315 | /* BARS 0-4 do not have a boot spec, but ABAR/BAR5 must be clean. */ | |
6100ddb0 | 316 | datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5); |
8840a843 JS |
317 | g_assert_cmphex(datal, ==, 0); |
318 | ||
6100ddb0 JS |
319 | qpci_config_writel(ahci->dev, PCI_BASE_ADDRESS_5, 0xFFFFFFFF); |
320 | datal = qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5); | |
8840a843 JS |
321 | /* ABAR must be 32-bit, memory mapped, non-prefetchable and |
322 | * must be >= 512 bytes. To that end, bits 0-8 must be off. */ | |
323 | ASSERT_BIT_CLEAR(datal, 0xFF); | |
324 | ||
325 | /* Capability list MUST be present, */ | |
6100ddb0 | 326 | datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST); |
8840a843 JS |
327 | /* But these bits are reserved. */ |
328 | ASSERT_BIT_CLEAR(datal, ~0xFF); | |
329 | g_assert_cmphex(datal, !=, 0); | |
330 | ||
331 | /* Check specification adherence for capability extenstions. */ | |
6100ddb0 | 332 | data = qpci_config_readw(ahci->dev, datal); |
8840a843 | 333 | |
8d5eeced | 334 | switch (ahci->fingerprint) { |
8840a843 JS |
335 | case AHCI_INTEL_ICH9: |
336 | /* Intel ICH9 Family Datasheet 14.1.19 p.550 */ | |
337 | g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_MSI); | |
338 | break; | |
339 | default: | |
340 | /* AHCI 1.3, Section 2.1.14 -- CAP must point to PMCAP. */ | |
341 | g_assert_cmphex((data & 0xFF), ==, PCI_CAP_ID_PM); | |
342 | } | |
343 | ||
344 | ahci_test_pci_caps(ahci, data, (uint8_t)datal); | |
345 | ||
346 | /* Reserved. */ | |
6100ddb0 | 347 | datal = qpci_config_readl(ahci->dev, PCI_CAPABILITY_LIST + 4); |
8840a843 JS |
348 | g_assert_cmphex(datal, ==, 0); |
349 | ||
350 | /* IPIN might vary, but ILINE must be off. */ | |
6100ddb0 | 351 | datab = qpci_config_readb(ahci->dev, PCI_INTERRUPT_LINE); |
8840a843 JS |
352 | g_assert_cmphex(datab, ==, 0); |
353 | } | |
354 | ||
355 | /** | |
356 | * Test PCI capabilities for AHCI specification adherence. | |
357 | */ | |
6100ddb0 | 358 | static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header, |
8840a843 JS |
359 | uint8_t offset) |
360 | { | |
361 | uint8_t cid = header & 0xFF; | |
362 | uint8_t next = header >> 8; | |
363 | ||
364 | g_test_message("CID: %02x; next: %02x", cid, next); | |
365 | ||
366 | switch (cid) { | |
367 | case PCI_CAP_ID_PM: | |
368 | ahci_test_pmcap(ahci, offset); | |
369 | break; | |
370 | case PCI_CAP_ID_MSI: | |
371 | ahci_test_msicap(ahci, offset); | |
372 | break; | |
373 | case PCI_CAP_ID_SATA: | |
374 | ahci_test_satacap(ahci, offset); | |
375 | break; | |
376 | ||
377 | default: | |
378 | g_test_message("Unknown CAP 0x%02x", cid); | |
379 | } | |
380 | ||
381 | if (next) { | |
6100ddb0 | 382 | ahci_test_pci_caps(ahci, qpci_config_readw(ahci->dev, next), next); |
8840a843 JS |
383 | } |
384 | } | |
385 | ||
386 | /** | |
387 | * Test SATA PCI capabilitity for AHCI specification adherence. | |
388 | */ | |
6100ddb0 | 389 | static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset) |
8840a843 JS |
390 | { |
391 | uint16_t dataw; | |
392 | uint32_t datal; | |
393 | ||
394 | g_test_message("Verifying SATACAP"); | |
395 | ||
396 | /* Assert that the SATACAP version is 1.0, And reserved bits are empty. */ | |
6100ddb0 | 397 | dataw = qpci_config_readw(ahci->dev, offset + 2); |
8840a843 JS |
398 | g_assert_cmphex(dataw, ==, 0x10); |
399 | ||
400 | /* Grab the SATACR1 register. */ | |
6100ddb0 | 401 | datal = qpci_config_readw(ahci->dev, offset + 4); |
8840a843 JS |
402 | |
403 | switch (datal & 0x0F) { | |
404 | case 0x04: /* BAR0 */ | |
405 | case 0x05: /* BAR1 */ | |
406 | case 0x06: | |
407 | case 0x07: | |
408 | case 0x08: | |
409 | case 0x09: /* BAR5 */ | |
410 | case 0x0F: /* Immediately following SATACR1 in PCI config space. */ | |
411 | break; | |
412 | default: | |
413 | /* Invalid BARLOC for the Index Data Pair. */ | |
414 | g_assert_not_reached(); | |
415 | } | |
416 | ||
417 | /* Reserved. */ | |
418 | g_assert_cmphex((datal >> 24), ==, 0x00); | |
419 | } | |
420 | ||
421 | /** | |
422 | * Test MSI PCI capability for AHCI specification adherence. | |
423 | */ | |
6100ddb0 | 424 | static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset) |
8840a843 JS |
425 | { |
426 | uint16_t dataw; | |
427 | uint32_t datal; | |
428 | ||
429 | g_test_message("Verifying MSICAP"); | |
430 | ||
6100ddb0 | 431 | dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_FLAGS); |
8840a843 JS |
432 | ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_ENABLE); |
433 | ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_QSIZE); | |
434 | ASSERT_BIT_CLEAR(dataw, PCI_MSI_FLAGS_RESERVED); | |
435 | ||
6100ddb0 | 436 | datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_LO); |
8840a843 JS |
437 | g_assert_cmphex(datal, ==, 0); |
438 | ||
439 | if (dataw & PCI_MSI_FLAGS_64BIT) { | |
440 | g_test_message("MSICAP is 64bit"); | |
6100ddb0 | 441 | datal = qpci_config_readl(ahci->dev, offset + PCI_MSI_ADDRESS_HI); |
8840a843 | 442 | g_assert_cmphex(datal, ==, 0); |
6100ddb0 | 443 | dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_64); |
8840a843 JS |
444 | g_assert_cmphex(dataw, ==, 0); |
445 | } else { | |
446 | g_test_message("MSICAP is 32bit"); | |
6100ddb0 | 447 | dataw = qpci_config_readw(ahci->dev, offset + PCI_MSI_DATA_32); |
8840a843 JS |
448 | g_assert_cmphex(dataw, ==, 0); |
449 | } | |
450 | } | |
451 | ||
452 | /** | |
453 | * Test Power Management PCI capability for AHCI specification adherence. | |
454 | */ | |
6100ddb0 | 455 | static void ahci_test_pmcap(AHCIQState *ahci, uint8_t offset) |
8840a843 JS |
456 | { |
457 | uint16_t dataw; | |
458 | ||
459 | g_test_message("Verifying PMCAP"); | |
460 | ||
6100ddb0 | 461 | dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_PMC); |
8840a843 JS |
462 | ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_PME_CLOCK); |
463 | ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_RESERVED); | |
464 | ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D1); | |
465 | ASSERT_BIT_CLEAR(dataw, PCI_PM_CAP_D2); | |
466 | ||
6100ddb0 | 467 | dataw = qpci_config_readw(ahci->dev, offset + PCI_PM_CTRL); |
8840a843 JS |
468 | ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_STATE_MASK); |
469 | ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_RESERVED); | |
470 | ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SEL_MASK); | |
471 | ASSERT_BIT_CLEAR(dataw, PCI_PM_CTRL_DATA_SCALE_MASK); | |
472 | } | |
473 | ||
6100ddb0 | 474 | static void ahci_test_hba_spec(AHCIQState *ahci) |
c2f3029f | 475 | { |
c2f3029f | 476 | unsigned i; |
8d5eeced | 477 | uint32_t reg; |
c2f3029f JS |
478 | uint32_t ports; |
479 | uint8_t nports_impl; | |
480 | uint8_t maxports; | |
481 | ||
6100ddb0 | 482 | g_assert(ahci != NULL); |
c2f3029f JS |
483 | |
484 | /* | |
485 | * Note that the AHCI spec does expect the BIOS to set up a few things: | |
486 | * CAP.SSS - Support for staggered spin-up (t/f) | |
487 | * CAP.SMPS - Support for mechanical presence switches (t/f) | |
488 | * PI - Ports Implemented (1-32) | |
489 | * PxCMD.HPCP - Hot Plug Capable Port | |
490 | * PxCMD.MPSP - Mechanical Presence Switch Present | |
491 | * PxCMD.CPD - Cold Presence Detection support | |
492 | * | |
493 | * Additional items are touched if CAP.SSS is on, see AHCI 10.1.1 p.97: | |
494 | * Foreach Port Implemented: | |
495 | * -PxCMD.ST, PxCMD.CR, PxCMD.FRE, PxCMD.FR, PxSCTL.DET are 0 | |
496 | * -PxCLB/U and PxFB/U are set to valid regions in memory | |
497 | * -PxSUD is set to 1. | |
498 | * -PxSSTS.DET is polled for presence; if detected, we continue: | |
499 | * -PxSERR is cleared with 1's. | |
500 | * -If PxTFD.STS.BSY, PxTFD.STS.DRQ, and PxTFD.STS.ERR are all zero, | |
501 | * the device is ready. | |
502 | */ | |
503 | ||
504 | /* 1 CAP - Capabilities Register */ | |
1a8bba4d | 505 | ahci->cap = ahci_rreg(ahci, AHCI_CAP); |
8d5eeced | 506 | ASSERT_BIT_CLEAR(ahci->cap, AHCI_CAP_RESERVED); |
c2f3029f JS |
507 | |
508 | /* 2 GHC - Global Host Control */ | |
1a8bba4d | 509 | reg = ahci_rreg(ahci, AHCI_GHC); |
c2f3029f JS |
510 | ASSERT_BIT_CLEAR(reg, AHCI_GHC_HR); |
511 | ASSERT_BIT_CLEAR(reg, AHCI_GHC_IE); | |
512 | ASSERT_BIT_CLEAR(reg, AHCI_GHC_MRSM); | |
8d5eeced | 513 | if (BITSET(ahci->cap, AHCI_CAP_SAM)) { |
c2f3029f JS |
514 | g_test_message("Supports AHCI-Only Mode: GHC_AE is Read-Only."); |
515 | ASSERT_BIT_SET(reg, AHCI_GHC_AE); | |
516 | } else { | |
517 | g_test_message("Supports AHCI/Legacy mix."); | |
518 | ASSERT_BIT_CLEAR(reg, AHCI_GHC_AE); | |
519 | } | |
520 | ||
521 | /* 3 IS - Interrupt Status */ | |
1a8bba4d | 522 | reg = ahci_rreg(ahci, AHCI_IS); |
c2f3029f JS |
523 | g_assert_cmphex(reg, ==, 0); |
524 | ||
525 | /* 4 PI - Ports Implemented */ | |
1a8bba4d | 526 | ports = ahci_rreg(ahci, AHCI_PI); |
c2f3029f JS |
527 | /* Ports Implemented must be non-zero. */ |
528 | g_assert_cmphex(ports, !=, 0); | |
529 | /* Ports Implemented must be <= Number of Ports. */ | |
530 | nports_impl = ctpopl(ports); | |
8d5eeced | 531 | g_assert_cmpuint(((AHCI_CAP_NP & ahci->cap) + 1), >=, nports_impl); |
c2f3029f | 532 | |
c2f3029f JS |
533 | /* Ports must be within the proper range. Given a mapping of SIZE, |
534 | * 256 bytes are used for global HBA control, and the rest is used | |
535 | * for ports data, at 0x80 bytes each. */ | |
8d5eeced JS |
536 | g_assert_cmphex(ahci->barsize, >, 0); |
537 | maxports = (ahci->barsize - HBA_DATA_REGION_SIZE) / HBA_PORT_DATA_SIZE; | |
c2f3029f JS |
538 | /* e.g, 30 ports for 4K of memory. (4096 - 256) / 128 = 30 */ |
539 | g_assert_cmphex((reg >> maxports), ==, 0); | |
540 | ||
541 | /* 5 AHCI Version */ | |
1a8bba4d | 542 | reg = ahci_rreg(ahci, AHCI_VS); |
c2f3029f JS |
543 | switch (reg) { |
544 | case AHCI_VERSION_0_95: | |
545 | case AHCI_VERSION_1_0: | |
546 | case AHCI_VERSION_1_1: | |
547 | case AHCI_VERSION_1_2: | |
548 | case AHCI_VERSION_1_3: | |
549 | break; | |
550 | default: | |
551 | g_assert_not_reached(); | |
552 | } | |
553 | ||
554 | /* 6 Command Completion Coalescing Control: depends on CAP.CCCS. */ | |
1a8bba4d | 555 | reg = ahci_rreg(ahci, AHCI_CCCCTL); |
8d5eeced | 556 | if (BITSET(ahci->cap, AHCI_CAP_CCCS)) { |
c2f3029f JS |
557 | ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_EN); |
558 | ASSERT_BIT_CLEAR(reg, AHCI_CCCCTL_RESERVED); | |
559 | ASSERT_BIT_SET(reg, AHCI_CCCCTL_CC); | |
560 | ASSERT_BIT_SET(reg, AHCI_CCCCTL_TV); | |
561 | } else { | |
562 | g_assert_cmphex(reg, ==, 0); | |
563 | } | |
564 | ||
565 | /* 7 CCC_PORTS */ | |
1a8bba4d | 566 | reg = ahci_rreg(ahci, AHCI_CCCPORTS); |
c2f3029f JS |
567 | /* Must be zeroes initially regardless of CAP.CCCS */ |
568 | g_assert_cmphex(reg, ==, 0); | |
569 | ||
570 | /* 8 EM_LOC */ | |
1a8bba4d | 571 | reg = ahci_rreg(ahci, AHCI_EMLOC); |
8d5eeced | 572 | if (BITCLR(ahci->cap, AHCI_CAP_EMS)) { |
c2f3029f JS |
573 | g_assert_cmphex(reg, ==, 0); |
574 | } | |
575 | ||
576 | /* 9 EM_CTL */ | |
1a8bba4d | 577 | reg = ahci_rreg(ahci, AHCI_EMCTL); |
8d5eeced | 578 | if (BITSET(ahci->cap, AHCI_CAP_EMS)) { |
c2f3029f JS |
579 | ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_STSMR); |
580 | ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLTM); | |
581 | ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_CTLRST); | |
582 | ASSERT_BIT_CLEAR(reg, AHCI_EMCTL_RESERVED); | |
583 | } else { | |
584 | g_assert_cmphex(reg, ==, 0); | |
585 | } | |
586 | ||
587 | /* 10 CAP2 -- Capabilities Extended */ | |
1a8bba4d | 588 | ahci->cap2 = ahci_rreg(ahci, AHCI_CAP2); |
8d5eeced | 589 | ASSERT_BIT_CLEAR(ahci->cap2, AHCI_CAP2_RESERVED); |
c2f3029f JS |
590 | |
591 | /* 11 BOHC -- Bios/OS Handoff Control */ | |
1a8bba4d | 592 | reg = ahci_rreg(ahci, AHCI_BOHC); |
c2f3029f JS |
593 | g_assert_cmphex(reg, ==, 0); |
594 | ||
595 | /* 12 -- 23: Reserved */ | |
596 | g_test_message("Verifying HBA reserved area is empty."); | |
597 | for (i = AHCI_RESERVED; i < AHCI_NVMHCI; ++i) { | |
1a8bba4d | 598 | reg = ahci_rreg(ahci, i); |
c2f3029f JS |
599 | g_assert_cmphex(reg, ==, 0); |
600 | } | |
601 | ||
602 | /* 24 -- 39: NVMHCI */ | |
8d5eeced | 603 | if (BITCLR(ahci->cap2, AHCI_CAP2_NVMP)) { |
c2f3029f JS |
604 | g_test_message("Verifying HBA/NVMHCI area is empty."); |
605 | for (i = AHCI_NVMHCI; i < AHCI_VENDOR; ++i) { | |
1a8bba4d | 606 | reg = ahci_rreg(ahci, i); |
c2f3029f JS |
607 | g_assert_cmphex(reg, ==, 0); |
608 | } | |
609 | } | |
610 | ||
611 | /* 40 -- 63: Vendor */ | |
612 | g_test_message("Verifying HBA/Vendor area is empty."); | |
613 | for (i = AHCI_VENDOR; i < AHCI_PORTS; ++i) { | |
1a8bba4d | 614 | reg = ahci_rreg(ahci, i); |
c2f3029f JS |
615 | g_assert_cmphex(reg, ==, 0); |
616 | } | |
617 | ||
618 | /* 64 -- XX: Port Space */ | |
c2f3029f JS |
619 | for (i = 0; ports || (i < maxports); ports >>= 1, ++i) { |
620 | if (BITSET(ports, 0x1)) { | |
621 | g_test_message("Testing port %u for spec", i); | |
8d5eeced | 622 | ahci_test_port_spec(ahci, i); |
c2f3029f JS |
623 | } else { |
624 | uint16_t j; | |
625 | uint16_t low = AHCI_PORTS + (32 * i); | |
626 | uint16_t high = AHCI_PORTS + (32 * (i + 1)); | |
627 | g_test_message("Asserting unimplemented port %u " | |
628 | "(reg [%u-%u]) is empty.", | |
629 | i, low, high - 1); | |
630 | for (j = low; j < high; ++j) { | |
1a8bba4d | 631 | reg = ahci_rreg(ahci, j); |
c2f3029f JS |
632 | g_assert_cmphex(reg, ==, 0); |
633 | } | |
634 | } | |
635 | } | |
636 | } | |
637 | ||
638 | /** | |
639 | * Test the memory space for one port for specification adherence. | |
640 | */ | |
8d5eeced | 641 | static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port) |
c2f3029f JS |
642 | { |
643 | uint32_t reg; | |
644 | unsigned i; | |
645 | ||
646 | /* (0) CLB */ | |
1a8bba4d | 647 | reg = ahci_px_rreg(ahci, port, AHCI_PX_CLB); |
c2f3029f JS |
648 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CLB_RESERVED); |
649 | ||
650 | /* (1) CLBU */ | |
8d5eeced | 651 | if (BITCLR(ahci->cap, AHCI_CAP_S64A)) { |
1a8bba4d | 652 | reg = ahci_px_rreg(ahci, port, AHCI_PX_CLBU); |
c2f3029f JS |
653 | g_assert_cmphex(reg, ==, 0); |
654 | } | |
655 | ||
656 | /* (2) FB */ | |
1a8bba4d | 657 | reg = ahci_px_rreg(ahci, port, AHCI_PX_FB); |
c2f3029f JS |
658 | ASSERT_BIT_CLEAR(reg, AHCI_PX_FB_RESERVED); |
659 | ||
660 | /* (3) FBU */ | |
8d5eeced | 661 | if (BITCLR(ahci->cap, AHCI_CAP_S64A)) { |
1a8bba4d | 662 | reg = ahci_px_rreg(ahci, port, AHCI_PX_FBU); |
c2f3029f JS |
663 | g_assert_cmphex(reg, ==, 0); |
664 | } | |
665 | ||
666 | /* (4) IS */ | |
1a8bba4d | 667 | reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); |
c2f3029f JS |
668 | g_assert_cmphex(reg, ==, 0); |
669 | ||
670 | /* (5) IE */ | |
1a8bba4d | 671 | reg = ahci_px_rreg(ahci, port, AHCI_PX_IE); |
c2f3029f JS |
672 | g_assert_cmphex(reg, ==, 0); |
673 | ||
674 | /* (6) CMD */ | |
1a8bba4d | 675 | reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD); |
c2f3029f JS |
676 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FRE); |
677 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_RESERVED); | |
678 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CCS); | |
679 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR); | |
680 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR); | |
681 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_PMA); /* And RW only if CAP.SPM */ | |
682 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_APSTE); /* RW only if CAP2.APST */ | |
683 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ATAPI); | |
684 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_DLAE); | |
685 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ALPE); /* RW only if CAP.SALP */ | |
686 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ASP); /* RW only if CAP.SALP */ | |
687 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_ICC); | |
688 | /* If CPDetect support does not exist, CPState must be off. */ | |
689 | if (BITCLR(reg, AHCI_PX_CMD_CPD)) { | |
690 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CPS); | |
691 | } | |
692 | /* If MPSPresence is not set, MPSState must be off. */ | |
693 | if (BITCLR(reg, AHCI_PX_CMD_MPSP)) { | |
694 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS); | |
695 | } | |
696 | /* If we do not support MPS, MPSS and MPSP must be off. */ | |
8d5eeced | 697 | if (BITCLR(ahci->cap, AHCI_CAP_SMPS)) { |
c2f3029f JS |
698 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSS); |
699 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_MPSP); | |
700 | } | |
701 | /* If, via CPD or MPSP we detect a drive, HPCP must be on. */ | |
7e7d49d6 | 702 | if (BITANY(reg, AHCI_PX_CMD_CPD | AHCI_PX_CMD_MPSP)) { |
c2f3029f JS |
703 | ASSERT_BIT_SET(reg, AHCI_PX_CMD_HPCP); |
704 | } | |
705 | /* HPCP and ESP cannot both be active. */ | |
706 | g_assert(!BITSET(reg, AHCI_PX_CMD_HPCP | AHCI_PX_CMD_ESP)); | |
707 | /* If CAP.FBSS is not set, FBSCP must not be set. */ | |
8d5eeced | 708 | if (BITCLR(ahci->cap, AHCI_CAP_FBSS)) { |
c2f3029f JS |
709 | ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FBSCP); |
710 | } | |
711 | ||
712 | /* (7) RESERVED */ | |
1a8bba4d | 713 | reg = ahci_px_rreg(ahci, port, AHCI_PX_RES1); |
c2f3029f JS |
714 | g_assert_cmphex(reg, ==, 0); |
715 | ||
716 | /* (8) TFD */ | |
1a8bba4d | 717 | reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); |
c2f3029f JS |
718 | /* At boot, prior to an FIS being received, the TFD register should be 0x7F, |
719 | * which breaks down as follows, as seen in AHCI 1.3 sec 3.3.8, p. 27. */ | |
720 | ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR); | |
721 | ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS1); | |
722 | ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_DRQ); | |
723 | ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_CS2); | |
724 | ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY); | |
725 | ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR); | |
726 | ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_RESERVED); | |
727 | ||
728 | /* (9) SIG */ | |
729 | /* Though AHCI specifies the boot value should be 0xFFFFFFFF, | |
730 | * Even when GHC.ST is zero, the AHCI HBA may receive the initial | |
731 | * D2H register FIS and update the signature asynchronously, | |
732 | * so we cannot expect a value here. AHCI 1.3, sec 3.3.9, pp 27-28 */ | |
733 | ||
734 | /* (10) SSTS / SCR0: SStatus */ | |
1a8bba4d | 735 | reg = ahci_px_rreg(ahci, port, AHCI_PX_SSTS); |
c2f3029f JS |
736 | ASSERT_BIT_CLEAR(reg, AHCI_PX_SSTS_RESERVED); |
737 | /* Even though the register should be 0 at boot, it is asynchronous and | |
738 | * prone to change, so we cannot test any well known value. */ | |
739 | ||
740 | /* (11) SCTL / SCR2: SControl */ | |
1a8bba4d | 741 | reg = ahci_px_rreg(ahci, port, AHCI_PX_SCTL); |
c2f3029f JS |
742 | g_assert_cmphex(reg, ==, 0); |
743 | ||
744 | /* (12) SERR / SCR1: SError */ | |
1a8bba4d | 745 | reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR); |
c2f3029f JS |
746 | g_assert_cmphex(reg, ==, 0); |
747 | ||
748 | /* (13) SACT / SCR3: SActive */ | |
1a8bba4d | 749 | reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT); |
c2f3029f JS |
750 | g_assert_cmphex(reg, ==, 0); |
751 | ||
752 | /* (14) CI */ | |
1a8bba4d | 753 | reg = ahci_px_rreg(ahci, port, AHCI_PX_CI); |
c2f3029f JS |
754 | g_assert_cmphex(reg, ==, 0); |
755 | ||
756 | /* (15) SNTF */ | |
1a8bba4d | 757 | reg = ahci_px_rreg(ahci, port, AHCI_PX_SNTF); |
c2f3029f JS |
758 | g_assert_cmphex(reg, ==, 0); |
759 | ||
760 | /* (16) FBS */ | |
1a8bba4d | 761 | reg = ahci_px_rreg(ahci, port, AHCI_PX_FBS); |
c2f3029f JS |
762 | ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_EN); |
763 | ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEC); | |
764 | ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_SDE); | |
765 | ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DEV); | |
766 | ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_DWE); | |
767 | ASSERT_BIT_CLEAR(reg, AHCI_PX_FBS_RESERVED); | |
8d5eeced | 768 | if (BITSET(ahci->cap, AHCI_CAP_FBSS)) { |
c2f3029f JS |
769 | /* if Port-Multiplier FIS-based switching avail, ADO must >= 2 */ |
770 | g_assert((reg & AHCI_PX_FBS_ADO) >> ctzl(AHCI_PX_FBS_ADO) >= 2); | |
771 | } | |
772 | ||
773 | /* [17 -- 27] RESERVED */ | |
774 | for (i = AHCI_PX_RES2; i < AHCI_PX_VS; ++i) { | |
1a8bba4d | 775 | reg = ahci_px_rreg(ahci, port, i); |
c2f3029f JS |
776 | g_assert_cmphex(reg, ==, 0); |
777 | } | |
778 | ||
779 | /* [28 -- 31] Vendor-Specific */ | |
780 | for (i = AHCI_PX_VS; i < 32; ++i) { | |
1a8bba4d | 781 | reg = ahci_px_rreg(ahci, port, i); |
c2f3029f JS |
782 | if (reg) { |
783 | g_test_message("INFO: Vendor register %u non-empty", i); | |
784 | } | |
785 | } | |
786 | } | |
787 | ||
0fa781e3 JS |
788 | /** |
789 | * Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first | |
790 | * device we see, then read and check the response. | |
791 | */ | |
6100ddb0 | 792 | static void ahci_test_identify(AHCIQState *ahci) |
0fa781e3 | 793 | { |
0fa781e3 | 794 | uint16_t buff[256]; |
ae029620 | 795 | unsigned px; |
0fa781e3 | 796 | int rc; |
122482a3 | 797 | uint16_t sect_size; |
ae029620 | 798 | const size_t buffsize = 512; |
0fa781e3 JS |
799 | |
800 | g_assert(ahci != NULL); | |
0fa781e3 | 801 | |
ae029620 JS |
802 | /** |
803 | * This serves as a bit of a tutorial on AHCI device programming: | |
804 | * | |
805 | * (1) Create a data buffer for the IDENTIFY response to be sent to | |
806 | * (2) Create a Command Table buffer, where we will store the | |
807 | * command and PRDT (Physical Region Descriptor Table) | |
64a5a272 | 808 | * (3) Construct an FIS host-to-device command structure, and write it to |
ae029620 JS |
809 | * the top of the Command Table buffer. |
810 | * (4) Create one or more Physical Region Descriptors (PRDs) that describe | |
811 | * a location in memory where data may be stored/retrieved. | |
812 | * (5) Write these PRDTs to the bottom (offset 0x80) of the Command Table. | |
813 | * (6) Each AHCI port has up to 32 command slots. Each slot contains a | |
814 | * header that points to a Command Table buffer. Pick an unused slot | |
815 | * and update it to point to the Command Table we have built. | |
816 | * (7) Now: Command #n points to our Command Table, and our Command Table | |
817 | * contains the FIS (that describes our command) and the PRDTL, which | |
818 | * describes our buffer. | |
819 | * (8) We inform the HBA via PxCI (Command Issue) that the command in slot | |
820 | * #n is ready for processing. | |
0fa781e3 JS |
821 | */ |
822 | ||
823 | /* Pick the first implemented and running port */ | |
ae029620 JS |
824 | px = ahci_port_select(ahci); |
825 | g_test_message("Selected port %u for test", px); | |
0fa781e3 | 826 | |
e83fd96b | 827 | /* Clear out the FIS Receive area and any pending interrupts. */ |
ae029620 | 828 | ahci_port_clear(ahci, px); |
0fa781e3 | 829 | |
ae029620 | 830 | /* "Read" 512 bytes using CMD_IDENTIFY into the host buffer. */ |
727be1a7 | 831 | ahci_io(ahci, px, CMD_IDENTIFY, &buff, buffsize, 0); |
0fa781e3 JS |
832 | |
833 | /* Check serial number/version in the buffer */ | |
834 | /* NB: IDENTIFY strings are packed in 16bit little endian chunks. | |
835 | * Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to | |
836 | * unchunk this data. By contrast, ide-test copies 2 bytes at a time, and | |
837 | * as a consequence, only needs to unchunk the data on LE machines. */ | |
838 | string_bswap16(&buff[10], 20); | |
839 | rc = memcmp(&buff[10], "testdisk ", 20); | |
840 | g_assert_cmphex(rc, ==, 0); | |
841 | ||
842 | string_bswap16(&buff[23], 8); | |
843 | rc = memcmp(&buff[23], "version ", 8); | |
844 | g_assert_cmphex(rc, ==, 0); | |
122482a3 JS |
845 | |
846 | sect_size = le16_to_cpu(*((uint16_t *)(&buff[5]))); | |
727be1a7 | 847 | g_assert_cmphex(sect_size, ==, AHCI_SECTOR_SIZE); |
0fa781e3 JS |
848 | } |
849 | ||
bda39dc2 | 850 | static void ahci_test_io_rw_simple(AHCIQState *ahci, unsigned bufsize, |
727be1a7 JS |
851 | uint64_t sector, uint8_t read_cmd, |
852 | uint8_t write_cmd) | |
81705ee4 JS |
853 | { |
854 | uint64_t ptr; | |
855 | uint8_t port; | |
81705ee4 JS |
856 | unsigned char *tx = g_malloc(bufsize); |
857 | unsigned char *rx = g_malloc0(bufsize); | |
858 | ||
859 | g_assert(ahci != NULL); | |
860 | ||
861 | /* Pick the first running port and clear it. */ | |
862 | port = ahci_port_select(ahci); | |
863 | ahci_port_clear(ahci, port); | |
864 | ||
865 | /*** Create pattern and transfer to guest ***/ | |
866 | /* Data buffer in the guest */ | |
867 | ptr = ahci_alloc(ahci, bufsize); | |
868 | g_assert(ptr); | |
869 | ||
d6c403ed | 870 | /* Write some indicative pattern to our buffer. */ |
54fced03 | 871 | generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE); |
91d0374a | 872 | bufwrite(ptr, tx, bufsize); |
81705ee4 JS |
873 | |
874 | /* Write this buffer to disk, then read it back to the DMA buffer. */ | |
727be1a7 | 875 | ahci_guest_io(ahci, port, write_cmd, ptr, bufsize, sector); |
81705ee4 | 876 | qmemset(ptr, 0x00, bufsize); |
727be1a7 | 877 | ahci_guest_io(ahci, port, read_cmd, ptr, bufsize, sector); |
81705ee4 JS |
878 | |
879 | /*** Read back the Data ***/ | |
91d0374a | 880 | bufread(ptr, rx, bufsize); |
81705ee4 JS |
881 | g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0); |
882 | ||
883 | ahci_free(ahci, ptr); | |
884 | g_free(tx); | |
885 | g_free(rx); | |
886 | } | |
887 | ||
0d3e9d1f | 888 | static uint8_t ahci_test_nondata(AHCIQState *ahci, uint8_t ide_cmd) |
4e217074 | 889 | { |
0d3e9d1f | 890 | uint8_t port; |
4e217074 JS |
891 | |
892 | /* Sanitize */ | |
0d3e9d1f JS |
893 | port = ahci_port_select(ahci); |
894 | ahci_port_clear(ahci, port); | |
4e217074 | 895 | |
b1b66c3b | 896 | ahci_io(ahci, port, ide_cmd, NULL, 0, 0); |
0d3e9d1f JS |
897 | |
898 | return port; | |
4e217074 JS |
899 | } |
900 | ||
901 | static void ahci_test_flush(AHCIQState *ahci) | |
902 | { | |
903 | ahci_test_nondata(ahci, CMD_FLUSH_CACHE); | |
904 | } | |
905 | ||
0d3e9d1f JS |
906 | static void ahci_test_max(AHCIQState *ahci) |
907 | { | |
908 | RegD2HFIS *d2h = g_malloc0(0x20); | |
909 | uint64_t nsect; | |
910 | uint8_t port; | |
911 | uint8_t cmd; | |
917158dc | 912 | uint64_t config_sect = mb_to_sectors(test_image_size_mb) - 1; |
0d3e9d1f JS |
913 | |
914 | if (config_sect > 0xFFFFFF) { | |
915 | cmd = CMD_READ_MAX_EXT; | |
916 | } else { | |
917 | cmd = CMD_READ_MAX; | |
918 | } | |
919 | ||
920 | port = ahci_test_nondata(ahci, cmd); | |
921 | memread(ahci->port[port].fb + 0x40, d2h, 0x20); | |
922 | nsect = (uint64_t)d2h->lba_hi[2] << 40 | | |
923 | (uint64_t)d2h->lba_hi[1] << 32 | | |
924 | (uint64_t)d2h->lba_hi[0] << 24 | | |
925 | (uint64_t)d2h->lba_lo[2] << 16 | | |
926 | (uint64_t)d2h->lba_lo[1] << 8 | | |
927 | (uint64_t)d2h->lba_lo[0]; | |
928 | ||
929 | g_assert_cmphex(nsect, ==, config_sect); | |
930 | g_free(d2h); | |
931 | } | |
932 | ||
4e217074 | 933 | |
1cd1031d JS |
934 | /******************************************************************************/ |
935 | /* Test Interfaces */ | |
936 | /******************************************************************************/ | |
937 | ||
938 | /** | |
939 | * Basic sanity test to boot a machine, find an AHCI device, and shutdown. | |
940 | */ | |
941 | static void test_sanity(void) | |
942 | { | |
dd0029c0 | 943 | AHCIQState *ahci; |
debaaa11 | 944 | ahci = ahci_boot(NULL); |
1cd1031d JS |
945 | ahci_shutdown(ahci); |
946 | } | |
947 | ||
8840a843 JS |
948 | /** |
949 | * Ensure that the PCI configuration space for the AHCI device is in-line with | |
950 | * the AHCI 1.3 specification for initial values. | |
951 | */ | |
952 | static void test_pci_spec(void) | |
953 | { | |
dd0029c0 | 954 | AHCIQState *ahci; |
debaaa11 | 955 | ahci = ahci_boot(NULL); |
6100ddb0 | 956 | ahci_test_pci_spec(ahci); |
8840a843 JS |
957 | ahci_shutdown(ahci); |
958 | } | |
959 | ||
96d6d3ba JS |
960 | /** |
961 | * Engage the PCI AHCI device and sanity check the response. | |
962 | * Perform additional PCI config space bringup for the HBA. | |
963 | */ | |
964 | static void test_pci_enable(void) | |
965 | { | |
dd0029c0 | 966 | AHCIQState *ahci; |
debaaa11 | 967 | ahci = ahci_boot(NULL); |
6100ddb0 | 968 | ahci_pci_enable(ahci); |
96d6d3ba JS |
969 | ahci_shutdown(ahci); |
970 | } | |
971 | ||
c2f3029f JS |
972 | /** |
973 | * Investigate the memory mapped regions of the HBA, | |
974 | * and test them for AHCI specification adherence. | |
975 | */ | |
976 | static void test_hba_spec(void) | |
977 | { | |
dd0029c0 | 978 | AHCIQState *ahci; |
c2f3029f | 979 | |
debaaa11 | 980 | ahci = ahci_boot(NULL); |
6100ddb0 JS |
981 | ahci_pci_enable(ahci); |
982 | ahci_test_hba_spec(ahci); | |
c2f3029f JS |
983 | ahci_shutdown(ahci); |
984 | } | |
985 | ||
dbc180e5 JS |
986 | /** |
987 | * Engage the HBA functionality of the AHCI PCI device, | |
988 | * and bring it into a functional idle state. | |
989 | */ | |
990 | static void test_hba_enable(void) | |
991 | { | |
dd0029c0 | 992 | AHCIQState *ahci; |
dbc180e5 | 993 | |
debaaa11 | 994 | ahci = ahci_boot(NULL); |
6100ddb0 JS |
995 | ahci_pci_enable(ahci); |
996 | ahci_hba_enable(ahci); | |
dbc180e5 JS |
997 | ahci_shutdown(ahci); |
998 | } | |
999 | ||
0fa781e3 JS |
1000 | /** |
1001 | * Bring up the device and issue an IDENTIFY command. | |
1002 | * Inspect the state of the HBA device and the data returned. | |
1003 | */ | |
1004 | static void test_identify(void) | |
1005 | { | |
dd0029c0 | 1006 | AHCIQState *ahci; |
0fa781e3 | 1007 | |
debaaa11 | 1008 | ahci = ahci_boot_and_enable(NULL); |
6100ddb0 | 1009 | ahci_test_identify(ahci); |
0fa781e3 JS |
1010 | ahci_shutdown(ahci); |
1011 | } | |
1012 | ||
e0c59cc7 JS |
1013 | /** |
1014 | * Fragmented DMA test: Perform a standard 4K DMA read/write | |
1015 | * test, but make sure the physical regions are fragmented to | |
1016 | * be very small, each just 32 bytes, to see how AHCI performs | |
1017 | * with chunks defined to be much less than a sector. | |
1018 | */ | |
1019 | static void test_dma_fragmented(void) | |
1020 | { | |
1021 | AHCIQState *ahci; | |
1022 | AHCICommand *cmd; | |
1023 | uint8_t px; | |
1024 | size_t bufsize = 4096; | |
1025 | unsigned char *tx = g_malloc(bufsize); | |
1026 | unsigned char *rx = g_malloc0(bufsize); | |
e0c59cc7 JS |
1027 | uint64_t ptr; |
1028 | ||
debaaa11 | 1029 | ahci = ahci_boot_and_enable(NULL); |
e0c59cc7 JS |
1030 | px = ahci_port_select(ahci); |
1031 | ahci_port_clear(ahci, px); | |
1032 | ||
1033 | /* create pattern */ | |
54fced03 | 1034 | generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE); |
e0c59cc7 JS |
1035 | |
1036 | /* Create a DMA buffer in guest memory, and write our pattern to it. */ | |
1037 | ptr = guest_alloc(ahci->parent->alloc, bufsize); | |
1038 | g_assert(ptr); | |
91d0374a | 1039 | bufwrite(ptr, tx, bufsize); |
e0c59cc7 JS |
1040 | |
1041 | cmd = ahci_command_create(CMD_WRITE_DMA); | |
1042 | ahci_command_adjust(cmd, 0, ptr, bufsize, 32); | |
1043 | ahci_command_commit(ahci, cmd, px); | |
1044 | ahci_command_issue(ahci, cmd); | |
1045 | ahci_command_verify(ahci, cmd); | |
248de4a8 | 1046 | ahci_command_free(cmd); |
e0c59cc7 JS |
1047 | |
1048 | cmd = ahci_command_create(CMD_READ_DMA); | |
1049 | ahci_command_adjust(cmd, 0, ptr, bufsize, 32); | |
1050 | ahci_command_commit(ahci, cmd, px); | |
1051 | ahci_command_issue(ahci, cmd); | |
1052 | ahci_command_verify(ahci, cmd); | |
248de4a8 | 1053 | ahci_command_free(cmd); |
e0c59cc7 JS |
1054 | |
1055 | /* Read back the guest's receive buffer into local memory */ | |
91d0374a | 1056 | bufread(ptr, rx, bufsize); |
e0c59cc7 JS |
1057 | guest_free(ahci->parent->alloc, ptr); |
1058 | ||
1059 | g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0); | |
1060 | ||
1061 | ahci_shutdown(ahci); | |
1062 | ||
1063 | g_free(rx); | |
1064 | g_free(tx); | |
1065 | } | |
1066 | ||
2dd7e10d EY |
1067 | /* |
1068 | * Write sector 1 with random data to make AHCI storage dirty | |
1069 | * Needed for flush tests so that flushes actually go though the block layer | |
1070 | */ | |
1071 | static void make_dirty(AHCIQState* ahci, uint8_t port) | |
1072 | { | |
1073 | uint64_t ptr; | |
1074 | unsigned bufsize = 512; | |
1075 | ||
1076 | ptr = ahci_alloc(ahci, bufsize); | |
1077 | g_assert(ptr); | |
1078 | ||
1079 | ahci_guest_io(ahci, port, CMD_WRITE_DMA, ptr, bufsize, 1); | |
1080 | ahci_free(ahci, ptr); | |
1081 | } | |
1082 | ||
4e217074 JS |
1083 | static void test_flush(void) |
1084 | { | |
1085 | AHCIQState *ahci; | |
2dd7e10d | 1086 | uint8_t port; |
4e217074 | 1087 | |
debaaa11 | 1088 | ahci = ahci_boot_and_enable(NULL); |
2dd7e10d EY |
1089 | |
1090 | port = ahci_port_select(ahci); | |
1091 | ahci_port_clear(ahci, port); | |
1092 | ||
1093 | make_dirty(ahci, port); | |
1094 | ||
4e217074 JS |
1095 | ahci_test_flush(ahci); |
1096 | ahci_shutdown(ahci); | |
1097 | } | |
1098 | ||
cf5aa89e JS |
1099 | static void test_flush_retry(void) |
1100 | { | |
1101 | AHCIQState *ahci; | |
1102 | AHCICommand *cmd; | |
1103 | uint8_t port; | |
cf5aa89e JS |
1104 | |
1105 | prepare_blkdebug_script(debug_path, "flush_to_disk"); | |
1106 | ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0," | |
b236b610 | 1107 | "format=%s,cache=writeback," |
cf5aa89e JS |
1108 | "rerror=stop,werror=stop " |
1109 | "-M q35 " | |
1110 | "-device ide-hd,drive=drive0 ", | |
1111 | debug_path, | |
b236b610 | 1112 | tmp_path, imgfmt); |
cf5aa89e | 1113 | |
cf5aa89e JS |
1114 | port = ahci_port_select(ahci); |
1115 | ahci_port_clear(ahci, port); | |
cf5aa89e | 1116 | |
2dd7e10d EY |
1117 | /* Issue write so that flush actually goes to disk */ |
1118 | make_dirty(ahci, port); | |
1119 | ||
1120 | /* Issue Flush Command and wait for error */ | |
b682d3a7 JS |
1121 | cmd = ahci_guest_io_halt(ahci, port, CMD_FLUSH_CACHE, 0, 0, 0); |
1122 | ahci_guest_io_resume(ahci, cmd); | |
1123 | ||
cf5aa89e JS |
1124 | ahci_shutdown(ahci); |
1125 | } | |
1126 | ||
278128ab JS |
1127 | /** |
1128 | * Basic sanity test to boot a machine, find an AHCI device, and shutdown. | |
1129 | */ | |
1130 | static void test_migrate_sanity(void) | |
1131 | { | |
1132 | AHCIQState *src, *dst; | |
6d9e7295 | 1133 | char *uri = g_strdup_printf("unix:%s", mig_socket); |
278128ab JS |
1134 | |
1135 | src = ahci_boot("-m 1024 -M q35 " | |
b236b610 | 1136 | "-drive if=ide,file=%s,format=%s ", tmp_path, imgfmt); |
278128ab | 1137 | dst = ahci_boot("-m 1024 -M q35 " |
b236b610 JS |
1138 | "-drive if=ide,file=%s,format=%s " |
1139 | "-incoming %s", tmp_path, imgfmt, uri); | |
278128ab JS |
1140 | |
1141 | ahci_migrate(src, dst, uri); | |
1142 | ||
1143 | ahci_shutdown(src); | |
1144 | ahci_shutdown(dst); | |
6d9e7295 | 1145 | g_free(uri); |
278128ab JS |
1146 | } |
1147 | ||
88e21f94 | 1148 | /** |
07a1ee79 | 1149 | * Simple migration test: Write a pattern, migrate, then read. |
88e21f94 | 1150 | */ |
07a1ee79 | 1151 | static void ahci_migrate_simple(uint8_t cmd_read, uint8_t cmd_write) |
88e21f94 JS |
1152 | { |
1153 | AHCIQState *src, *dst; | |
1154 | uint8_t px; | |
1155 | size_t bufsize = 4096; | |
1156 | unsigned char *tx = g_malloc(bufsize); | |
1157 | unsigned char *rx = g_malloc0(bufsize); | |
6d9e7295 | 1158 | char *uri = g_strdup_printf("unix:%s", mig_socket); |
88e21f94 JS |
1159 | |
1160 | src = ahci_boot_and_enable("-m 1024 -M q35 " | |
b236b610 JS |
1161 | "-drive if=ide,format=%s,file=%s ", |
1162 | imgfmt, tmp_path); | |
88e21f94 | 1163 | dst = ahci_boot("-m 1024 -M q35 " |
b236b610 JS |
1164 | "-drive if=ide,format=%s,file=%s " |
1165 | "-incoming %s", imgfmt, tmp_path, uri); | |
88e21f94 JS |
1166 | |
1167 | set_context(src->parent); | |
1168 | ||
1169 | /* initialize */ | |
1170 | px = ahci_port_select(src); | |
1171 | ahci_port_clear(src, px); | |
1172 | ||
1173 | /* create pattern */ | |
d7531638 | 1174 | generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE); |
88e21f94 JS |
1175 | |
1176 | /* Write, migrate, then read. */ | |
07a1ee79 | 1177 | ahci_io(src, px, cmd_write, tx, bufsize, 0); |
88e21f94 | 1178 | ahci_migrate(src, dst, uri); |
07a1ee79 | 1179 | ahci_io(dst, px, cmd_read, rx, bufsize, 0); |
88e21f94 JS |
1180 | |
1181 | /* Verify pattern */ | |
1182 | g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0); | |
1183 | ||
1184 | ahci_shutdown(src); | |
1185 | ahci_shutdown(dst); | |
1186 | g_free(rx); | |
1187 | g_free(tx); | |
6d9e7295 | 1188 | g_free(uri); |
88e21f94 JS |
1189 | } |
1190 | ||
07a1ee79 JS |
1191 | static void test_migrate_dma(void) |
1192 | { | |
1193 | ahci_migrate_simple(CMD_READ_DMA, CMD_WRITE_DMA); | |
1194 | } | |
1195 | ||
1196 | static void test_migrate_ncq(void) | |
1197 | { | |
1198 | ahci_migrate_simple(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED); | |
1199 | } | |
1200 | ||
189d1b61 | 1201 | /** |
7f6cf5ee | 1202 | * Halted IO Error Test |
189d1b61 JS |
1203 | * |
1204 | * Simulate an error on first write, Try to write a pattern, | |
1205 | * Confirm the VM has stopped, resume the VM, verify command | |
1206 | * has completed, then read back the data and verify. | |
1207 | */ | |
7f6cf5ee | 1208 | static void ahci_halted_io_test(uint8_t cmd_read, uint8_t cmd_write) |
189d1b61 JS |
1209 | { |
1210 | AHCIQState *ahci; | |
1211 | uint8_t port; | |
1212 | size_t bufsize = 4096; | |
1213 | unsigned char *tx = g_malloc(bufsize); | |
1214 | unsigned char *rx = g_malloc0(bufsize); | |
189d1b61 JS |
1215 | uint64_t ptr; |
1216 | AHCICommand *cmd; | |
1217 | ||
1218 | prepare_blkdebug_script(debug_path, "write_aio"); | |
1219 | ||
1220 | ahci = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0," | |
b236b610 | 1221 | "format=%s,cache=writeback," |
189d1b61 JS |
1222 | "rerror=stop,werror=stop " |
1223 | "-M q35 " | |
1224 | "-device ide-hd,drive=drive0 ", | |
1225 | debug_path, | |
b236b610 | 1226 | tmp_path, imgfmt); |
189d1b61 JS |
1227 | |
1228 | /* Initialize and prepare */ | |
1229 | port = ahci_port_select(ahci); | |
1230 | ahci_port_clear(ahci, port); | |
1231 | ||
189d1b61 | 1232 | /* create DMA source buffer and write pattern */ |
d7531638 | 1233 | generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE); |
189d1b61 JS |
1234 | ptr = ahci_alloc(ahci, bufsize); |
1235 | g_assert(ptr); | |
1236 | memwrite(ptr, tx, bufsize); | |
1237 | ||
1238 | /* Attempt to write (and fail) */ | |
7f6cf5ee | 1239 | cmd = ahci_guest_io_halt(ahci, port, cmd_write, |
189d1b61 JS |
1240 | ptr, bufsize, 0); |
1241 | ||
1242 | /* Attempt to resume the command */ | |
1243 | ahci_guest_io_resume(ahci, cmd); | |
1244 | ahci_free(ahci, ptr); | |
1245 | ||
1246 | /* Read back and verify */ | |
7f6cf5ee | 1247 | ahci_io(ahci, port, cmd_read, rx, bufsize, 0); |
189d1b61 JS |
1248 | g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0); |
1249 | ||
1250 | /* Cleanup and go home */ | |
1251 | ahci_shutdown(ahci); | |
1252 | g_free(rx); | |
1253 | g_free(tx); | |
1254 | } | |
1255 | ||
7f6cf5ee JS |
1256 | static void test_halted_dma(void) |
1257 | { | |
1258 | ahci_halted_io_test(CMD_READ_DMA, CMD_WRITE_DMA); | |
1259 | } | |
1260 | ||
1261 | static void test_halted_ncq(void) | |
1262 | { | |
1263 | ahci_halted_io_test(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED); | |
1264 | } | |
1265 | ||
5d1cf091 | 1266 | /** |
8146d7dc | 1267 | * IO Error Migration Test |
5d1cf091 JS |
1268 | * |
1269 | * Simulate an error on first write, Try to write a pattern, | |
1270 | * Confirm the VM has stopped, migrate, resume the VM, | |
1271 | * verify command has completed, then read back the data and verify. | |
1272 | */ | |
8146d7dc | 1273 | static void ahci_migrate_halted_io(uint8_t cmd_read, uint8_t cmd_write) |
5d1cf091 JS |
1274 | { |
1275 | AHCIQState *src, *dst; | |
1276 | uint8_t port; | |
1277 | size_t bufsize = 4096; | |
1278 | unsigned char *tx = g_malloc(bufsize); | |
1279 | unsigned char *rx = g_malloc0(bufsize); | |
5d1cf091 JS |
1280 | uint64_t ptr; |
1281 | AHCICommand *cmd; | |
6d9e7295 | 1282 | char *uri = g_strdup_printf("unix:%s", mig_socket); |
5d1cf091 JS |
1283 | |
1284 | prepare_blkdebug_script(debug_path, "write_aio"); | |
1285 | ||
1286 | src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0," | |
b236b610 | 1287 | "format=%s,cache=writeback," |
5d1cf091 JS |
1288 | "rerror=stop,werror=stop " |
1289 | "-M q35 " | |
1290 | "-device ide-hd,drive=drive0 ", | |
1291 | debug_path, | |
b236b610 | 1292 | tmp_path, imgfmt); |
5d1cf091 JS |
1293 | |
1294 | dst = ahci_boot("-drive file=%s,if=none,id=drive0," | |
b236b610 | 1295 | "format=%s,cache=writeback," |
5d1cf091 JS |
1296 | "rerror=stop,werror=stop " |
1297 | "-M q35 " | |
1298 | "-device ide-hd,drive=drive0 " | |
1299 | "-incoming %s", | |
b236b610 | 1300 | tmp_path, imgfmt, uri); |
5d1cf091 JS |
1301 | |
1302 | set_context(src->parent); | |
1303 | ||
1304 | /* Initialize and prepare */ | |
1305 | port = ahci_port_select(src); | |
1306 | ahci_port_clear(src, port); | |
d7531638 | 1307 | generate_pattern(tx, bufsize, AHCI_SECTOR_SIZE); |
5d1cf091 JS |
1308 | |
1309 | /* create DMA source buffer and write pattern */ | |
1310 | ptr = ahci_alloc(src, bufsize); | |
1311 | g_assert(ptr); | |
1312 | memwrite(ptr, tx, bufsize); | |
1313 | ||
1314 | /* Write, trigger the VM to stop, migrate, then resume. */ | |
8146d7dc | 1315 | cmd = ahci_guest_io_halt(src, port, cmd_write, |
5d1cf091 JS |
1316 | ptr, bufsize, 0); |
1317 | ahci_migrate(src, dst, uri); | |
1318 | ahci_guest_io_resume(dst, cmd); | |
1319 | ahci_free(dst, ptr); | |
1320 | ||
1321 | /* Read back */ | |
8146d7dc | 1322 | ahci_io(dst, port, cmd_read, rx, bufsize, 0); |
5d1cf091 JS |
1323 | |
1324 | /* Verify TX and RX are identical */ | |
1325 | g_assert_cmphex(memcmp(tx, rx, bufsize), ==, 0); | |
1326 | ||
1327 | /* Cleanup and go home. */ | |
1328 | ahci_shutdown(src); | |
1329 | ahci_shutdown(dst); | |
1330 | g_free(rx); | |
1331 | g_free(tx); | |
6d9e7295 | 1332 | g_free(uri); |
5d1cf091 JS |
1333 | } |
1334 | ||
8146d7dc JS |
1335 | static void test_migrate_halted_dma(void) |
1336 | { | |
1337 | ahci_migrate_halted_io(CMD_READ_DMA, CMD_WRITE_DMA); | |
1338 | } | |
1339 | ||
1340 | static void test_migrate_halted_ncq(void) | |
1341 | { | |
1342 | ahci_migrate_halted_io(READ_FPDMA_QUEUED, WRITE_FPDMA_QUEUED); | |
1343 | } | |
1344 | ||
a606ce50 JS |
1345 | /** |
1346 | * Migration test: Try to flush, migrate, then resume. | |
1347 | */ | |
1348 | static void test_flush_migrate(void) | |
1349 | { | |
1350 | AHCIQState *src, *dst; | |
1351 | AHCICommand *cmd; | |
1352 | uint8_t px; | |
1353 | const char *s; | |
6d9e7295 | 1354 | char *uri = g_strdup_printf("unix:%s", mig_socket); |
a606ce50 JS |
1355 | |
1356 | prepare_blkdebug_script(debug_path, "flush_to_disk"); | |
1357 | ||
1358 | src = ahci_boot_and_enable("-drive file=blkdebug:%s:%s,if=none,id=drive0," | |
b236b610 JS |
1359 | "cache=writeback,rerror=stop,werror=stop," |
1360 | "format=%s " | |
a606ce50 JS |
1361 | "-M q35 " |
1362 | "-device ide-hd,drive=drive0 ", | |
b236b610 | 1363 | debug_path, tmp_path, imgfmt); |
a606ce50 | 1364 | dst = ahci_boot("-drive file=%s,if=none,id=drive0," |
b236b610 JS |
1365 | "cache=writeback,rerror=stop,werror=stop," |
1366 | "format=%s " | |
a606ce50 JS |
1367 | "-M q35 " |
1368 | "-device ide-hd,drive=drive0 " | |
b236b610 | 1369 | "-incoming %s", tmp_path, imgfmt, uri); |
a606ce50 JS |
1370 | |
1371 | set_context(src->parent); | |
1372 | ||
a606ce50 JS |
1373 | px = ahci_port_select(src); |
1374 | ahci_port_clear(src, px); | |
2dd7e10d EY |
1375 | |
1376 | /* Dirty device so that flush reaches disk */ | |
1377 | make_dirty(src, px); | |
1378 | ||
1379 | /* Issue Flush Command */ | |
a606ce50 JS |
1380 | cmd = ahci_command_create(CMD_FLUSH_CACHE); |
1381 | ahci_command_commit(src, cmd, px); | |
1382 | ahci_command_issue_async(src, cmd); | |
1383 | qmp_eventwait("STOP"); | |
1384 | ||
1385 | /* Migrate over */ | |
1386 | ahci_migrate(src, dst, uri); | |
1387 | ||
1388 | /* Complete the command */ | |
1389 | s = "{'execute':'cont' }"; | |
1390 | qmp_async(s); | |
1391 | qmp_eventwait("RESUME"); | |
1392 | ahci_command_wait(dst, cmd); | |
1393 | ahci_command_verify(dst, cmd); | |
1394 | ||
1395 | ahci_command_free(cmd); | |
1396 | ahci_shutdown(src); | |
1397 | ahci_shutdown(dst); | |
6d9e7295 | 1398 | g_free(uri); |
a606ce50 JS |
1399 | } |
1400 | ||
0d3e9d1f JS |
1401 | static void test_max(void) |
1402 | { | |
1403 | AHCIQState *ahci; | |
1404 | ||
1405 | ahci = ahci_boot_and_enable(NULL); | |
1406 | ahci_test_max(ahci); | |
1407 | ahci_shutdown(ahci); | |
1408 | } | |
1409 | ||
d31a3ebc JS |
1410 | static void test_reset(void) |
1411 | { | |
1412 | AHCIQState *ahci; | |
1413 | int i; | |
1414 | ||
1415 | ahci = ahci_boot(NULL); | |
1416 | ahci_test_pci_spec(ahci); | |
1417 | ahci_pci_enable(ahci); | |
1418 | ||
1419 | for (i = 0; i < 2; i++) { | |
1420 | ahci_test_hba_spec(ahci); | |
1421 | ahci_hba_enable(ahci); | |
1422 | ahci_test_identify(ahci); | |
1423 | ahci_test_io_rw_simple(ahci, 4096, 0, | |
1424 | CMD_READ_DMA_EXT, | |
1425 | CMD_WRITE_DMA_EXT); | |
1426 | ahci_set(ahci, AHCI_GHC, AHCI_GHC_HR); | |
1427 | ahci_clean_mem(ahci); | |
1428 | } | |
1429 | ||
1430 | ahci_shutdown(ahci); | |
1431 | } | |
1432 | ||
26ad0045 JS |
1433 | static void test_ncq_simple(void) |
1434 | { | |
1435 | AHCIQState *ahci; | |
1436 | ||
1437 | ahci = ahci_boot_and_enable(NULL); | |
1438 | ahci_test_io_rw_simple(ahci, 4096, 0, | |
1439 | READ_FPDMA_QUEUED, | |
1440 | WRITE_FPDMA_QUEUED); | |
1441 | ahci_shutdown(ahci); | |
1442 | } | |
1443 | ||
e8109694 JS |
1444 | static int prepare_iso(size_t size, unsigned char **buf, char **name) |
1445 | { | |
1446 | char cdrom_path[] = "/tmp/qtest.iso.XXXXXX"; | |
1447 | unsigned char *patt; | |
1448 | ssize_t ret; | |
1449 | int fd = mkstemp(cdrom_path); | |
1450 | ||
1451 | g_assert(buf); | |
1452 | g_assert(name); | |
1453 | patt = g_malloc(size); | |
1454 | ||
1455 | /* Generate a pattern and build a CDROM image to read from */ | |
1456 | generate_pattern(patt, size, ATAPI_SECTOR_SIZE); | |
1457 | ret = write(fd, patt, size); | |
1458 | g_assert(ret == size); | |
1459 | ||
1460 | *name = g_strdup(cdrom_path); | |
1461 | *buf = patt; | |
1462 | return fd; | |
1463 | } | |
1464 | ||
1465 | static void remove_iso(int fd, char *name) | |
1466 | { | |
1467 | unlink(name); | |
1468 | g_free(name); | |
1469 | close(fd); | |
1470 | } | |
1471 | ||
1472 | static int ahci_cb_cmp_buff(AHCIQState *ahci, AHCICommand *cmd, | |
1473 | const AHCIOpts *opts) | |
1474 | { | |
1475 | unsigned char *tx = opts->opaque; | |
1476 | unsigned char *rx = g_malloc0(opts->size); | |
1477 | ||
1478 | bufread(opts->buffer, rx, opts->size); | |
1479 | g_assert_cmphex(memcmp(tx, rx, opts->size), ==, 0); | |
1480 | g_free(rx); | |
1481 | ||
1482 | return 0; | |
1483 | } | |
1484 | ||
1485 | static void ahci_test_cdrom(int nsectors, bool dma) | |
1486 | { | |
1487 | AHCIQState *ahci; | |
1488 | unsigned char *tx; | |
1489 | char *iso; | |
1490 | int fd; | |
1491 | AHCIOpts opts = { | |
1492 | .size = (ATAPI_SECTOR_SIZE * nsectors), | |
1493 | .atapi = true, | |
1494 | .atapi_dma = dma, | |
1495 | .post_cb = ahci_cb_cmp_buff, | |
1496 | }; | |
1497 | ||
1498 | /* Prepare ISO and fill 'tx' buffer */ | |
1499 | fd = prepare_iso(1024 * 1024, &tx, &iso); | |
1500 | opts.opaque = tx; | |
1501 | ||
1502 | /* Standard startup wonkery, but use ide-cd and our special iso file */ | |
1503 | ahci = ahci_boot_and_enable("-drive if=none,id=drive0,file=%s,format=raw " | |
1504 | "-M q35 " | |
1505 | "-device ide-cd,drive=drive0 ", iso); | |
1506 | ||
1507 | /* Build & Send AHCI command */ | |
1508 | ahci_exec(ahci, ahci_port_select(ahci), CMD_ATAPI_READ_10, &opts); | |
1509 | ||
1510 | /* Cleanup */ | |
1511 | g_free(tx); | |
1512 | ahci_shutdown(ahci); | |
1513 | remove_iso(fd, iso); | |
1514 | } | |
1515 | ||
1516 | static void test_cdrom_dma(void) | |
1517 | { | |
1518 | ahci_test_cdrom(1, true); | |
1519 | } | |
1520 | ||
1521 | static void test_cdrom_dma_multi(void) | |
1522 | { | |
1523 | ahci_test_cdrom(3, true); | |
1524 | } | |
1525 | ||
1526 | static void test_cdrom_pio(void) | |
1527 | { | |
1528 | ahci_test_cdrom(1, false); | |
1529 | } | |
1530 | ||
1531 | static void test_cdrom_pio_multi(void) | |
1532 | { | |
1533 | ahci_test_cdrom(3, false); | |
1534 | } | |
1535 | ||
bda39dc2 JS |
1536 | /******************************************************************************/ |
1537 | /* AHCI I/O Test Matrix Definitions */ | |
1538 | ||
1539 | enum BuffLen { | |
1540 | LEN_BEGIN = 0, | |
1541 | LEN_SIMPLE = LEN_BEGIN, | |
1542 | LEN_DOUBLE, | |
1543 | LEN_LONG, | |
1544 | LEN_SHORT, | |
1545 | NUM_LENGTHS | |
1546 | }; | |
1547 | ||
1548 | static const char *buff_len_str[NUM_LENGTHS] = { "simple", "double", | |
1549 | "long", "short" }; | |
1550 | ||
1551 | enum AddrMode { | |
1552 | ADDR_MODE_BEGIN = 0, | |
1553 | ADDR_MODE_LBA28 = ADDR_MODE_BEGIN, | |
1554 | ADDR_MODE_LBA48, | |
1555 | NUM_ADDR_MODES | |
1556 | }; | |
1557 | ||
1558 | static const char *addr_mode_str[NUM_ADDR_MODES] = { "lba28", "lba48" }; | |
1559 | ||
1560 | enum IOMode { | |
1561 | MODE_BEGIN = 0, | |
1562 | MODE_PIO = MODE_BEGIN, | |
1563 | MODE_DMA, | |
1564 | NUM_MODES | |
1565 | }; | |
1566 | ||
1567 | static const char *io_mode_str[NUM_MODES] = { "pio", "dma" }; | |
1568 | ||
1569 | enum IOOps { | |
1570 | IO_BEGIN = 0, | |
1571 | IO_READ = IO_BEGIN, | |
1572 | IO_WRITE, | |
1573 | NUM_IO_OPS | |
1574 | }; | |
1575 | ||
727be1a7 JS |
1576 | enum OffsetType { |
1577 | OFFSET_BEGIN = 0, | |
1578 | OFFSET_ZERO = OFFSET_BEGIN, | |
1579 | OFFSET_LOW, | |
1580 | OFFSET_HIGH, | |
1581 | NUM_OFFSETS | |
1582 | }; | |
1583 | ||
1584 | static const char *offset_str[NUM_OFFSETS] = { "zero", "low", "high" }; | |
1585 | ||
bda39dc2 JS |
1586 | typedef struct AHCIIOTestOptions { |
1587 | enum BuffLen length; | |
1588 | enum AddrMode address_type; | |
1589 | enum IOMode io_type; | |
727be1a7 | 1590 | enum OffsetType offset; |
bda39dc2 JS |
1591 | } AHCIIOTestOptions; |
1592 | ||
727be1a7 JS |
1593 | static uint64_t offset_sector(enum OffsetType ofst, |
1594 | enum AddrMode addr_type, | |
1595 | uint64_t buffsize) | |
1596 | { | |
1597 | uint64_t ceil; | |
1598 | uint64_t nsectors; | |
1599 | ||
1600 | switch (ofst) { | |
1601 | case OFFSET_ZERO: | |
1602 | return 0; | |
1603 | case OFFSET_LOW: | |
1604 | return 1; | |
1605 | case OFFSET_HIGH: | |
1606 | ceil = (addr_type == ADDR_MODE_LBA28) ? 0xfffffff : 0xffffffffffff; | |
917158dc | 1607 | ceil = MIN(ceil, mb_to_sectors(test_image_size_mb) - 1); |
727be1a7 JS |
1608 | nsectors = buffsize / AHCI_SECTOR_SIZE; |
1609 | return ceil - nsectors + 1; | |
1610 | default: | |
1611 | g_assert_not_reached(); | |
1612 | } | |
1613 | } | |
1614 | ||
81705ee4 | 1615 | /** |
bda39dc2 | 1616 | * Table of possible I/O ATA commands given a set of enumerations. |
81705ee4 | 1617 | */ |
bda39dc2 JS |
1618 | static const uint8_t io_cmds[NUM_MODES][NUM_ADDR_MODES][NUM_IO_OPS] = { |
1619 | [MODE_PIO] = { | |
1620 | [ADDR_MODE_LBA28] = { | |
1621 | [IO_READ] = CMD_READ_PIO, | |
1622 | [IO_WRITE] = CMD_WRITE_PIO }, | |
1623 | [ADDR_MODE_LBA48] = { | |
1624 | [IO_READ] = CMD_READ_PIO_EXT, | |
1625 | [IO_WRITE] = CMD_WRITE_PIO_EXT } | |
1626 | }, | |
1627 | [MODE_DMA] = { | |
1628 | [ADDR_MODE_LBA28] = { | |
1629 | [IO_READ] = CMD_READ_DMA, | |
1630 | [IO_WRITE] = CMD_WRITE_DMA }, | |
1631 | [ADDR_MODE_LBA48] = { | |
1632 | [IO_READ] = CMD_READ_DMA_EXT, | |
1633 | [IO_WRITE] = CMD_WRITE_DMA_EXT } | |
1634 | } | |
1635 | }; | |
1636 | ||
1637 | /** | |
1638 | * Test a Read/Write pattern using various commands, addressing modes, | |
1639 | * transfer modes, and buffer sizes. | |
1640 | */ | |
1641 | static void test_io_rw_interface(enum AddrMode lba48, enum IOMode dma, | |
727be1a7 | 1642 | unsigned bufsize, uint64_t sector) |
81705ee4 JS |
1643 | { |
1644 | AHCIQState *ahci; | |
1645 | ||
debaaa11 | 1646 | ahci = ahci_boot_and_enable(NULL); |
727be1a7 | 1647 | ahci_test_io_rw_simple(ahci, bufsize, sector, |
bda39dc2 JS |
1648 | io_cmds[dma][lba48][IO_READ], |
1649 | io_cmds[dma][lba48][IO_WRITE]); | |
81705ee4 JS |
1650 | ahci_shutdown(ahci); |
1651 | } | |
1652 | ||
bda39dc2 JS |
1653 | /** |
1654 | * Demultiplex the test data and invoke the actual test routine. | |
1655 | */ | |
1656 | static void test_io_interface(gconstpointer opaque) | |
d6c403ed | 1657 | { |
bda39dc2 JS |
1658 | AHCIIOTestOptions *opts = (AHCIIOTestOptions *)opaque; |
1659 | unsigned bufsize; | |
727be1a7 | 1660 | uint64_t sector; |
d6c403ed | 1661 | |
bda39dc2 JS |
1662 | switch (opts->length) { |
1663 | case LEN_SIMPLE: | |
1664 | bufsize = 4096; | |
1665 | break; | |
1666 | case LEN_DOUBLE: | |
1667 | bufsize = 8192; | |
1668 | break; | |
1669 | case LEN_LONG: | |
1670 | bufsize = 4096 * 64; | |
1671 | break; | |
1672 | case LEN_SHORT: | |
1673 | bufsize = 512; | |
1674 | break; | |
1675 | default: | |
1676 | g_assert_not_reached(); | |
1677 | } | |
d6c403ed | 1678 | |
727be1a7 JS |
1679 | sector = offset_sector(opts->offset, opts->address_type, bufsize); |
1680 | test_io_rw_interface(opts->address_type, opts->io_type, bufsize, sector); | |
bda39dc2 JS |
1681 | g_free(opts); |
1682 | return; | |
d6c403ed JS |
1683 | } |
1684 | ||
bda39dc2 | 1685 | static void create_ahci_io_test(enum IOMode type, enum AddrMode addr, |
727be1a7 | 1686 | enum BuffLen len, enum OffsetType offset) |
d6c403ed | 1687 | { |
bda39dc2 | 1688 | char *name; |
917158dc | 1689 | AHCIIOTestOptions *opts; |
bda39dc2 | 1690 | |
917158dc | 1691 | opts = g_malloc(sizeof(AHCIIOTestOptions)); |
bda39dc2 JS |
1692 | opts->length = len; |
1693 | opts->address_type = addr; | |
1694 | opts->io_type = type; | |
727be1a7 | 1695 | opts->offset = offset; |
bda39dc2 | 1696 | |
53f77e45 | 1697 | name = g_strdup_printf("ahci/io/%s/%s/%s/%s", |
bda39dc2 JS |
1698 | io_mode_str[type], |
1699 | addr_mode_str[addr], | |
727be1a7 JS |
1700 | buff_len_str[len], |
1701 | offset_str[offset]); | |
bda39dc2 | 1702 | |
917158dc JS |
1703 | if ((addr == ADDR_MODE_LBA48) && (offset == OFFSET_HIGH) && |
1704 | (mb_to_sectors(test_image_size_mb) <= 0xFFFFFFF)) { | |
1705 | g_test_message("%s: skipped; test image too small", name); | |
1706 | g_free(name); | |
1707 | return; | |
1708 | } | |
1709 | ||
53f77e45 | 1710 | qtest_add_data_func(name, opts, test_io_interface); |
bda39dc2 | 1711 | g_free(name); |
d6c403ed JS |
1712 | } |
1713 | ||
1cd1031d JS |
1714 | /******************************************************************************/ |
1715 | ||
1716 | int main(int argc, char **argv) | |
1717 | { | |
1718 | const char *arch; | |
1cd1031d | 1719 | int ret; |
cf5aa89e | 1720 | int fd; |
8840a843 | 1721 | int c; |
727be1a7 | 1722 | int i, j, k, m; |
8840a843 JS |
1723 | |
1724 | static struct option long_options[] = { | |
1725 | {"pedantic", no_argument, 0, 'p' }, | |
1726 | {0, 0, 0, 0}, | |
1727 | }; | |
1cd1031d JS |
1728 | |
1729 | /* Should be first to utilize g_test functionality, So we can see errors. */ | |
1730 | g_test_init(&argc, &argv, NULL); | |
1731 | ||
8840a843 JS |
1732 | while (1) { |
1733 | c = getopt_long(argc, argv, "", long_options, NULL); | |
1734 | if (c == -1) { | |
1735 | break; | |
1736 | } | |
1737 | switch (c) { | |
1738 | case -1: | |
1739 | break; | |
1740 | case 'p': | |
1741 | ahci_pedantic = 1; | |
1742 | break; | |
1743 | default: | |
1744 | fprintf(stderr, "Unrecognized ahci_test option.\n"); | |
1745 | g_assert_not_reached(); | |
1746 | } | |
1747 | } | |
1748 | ||
1cd1031d JS |
1749 | /* Check architecture */ |
1750 | arch = qtest_get_arch(); | |
1751 | if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) { | |
1752 | g_test_message("Skipping test for non-x86"); | |
1753 | return 0; | |
1754 | } | |
1755 | ||
b236b610 JS |
1756 | /* Create a temporary image */ |
1757 | fd = mkstemp(tmp_path); | |
1758 | g_assert(fd >= 0); | |
917158dc JS |
1759 | if (have_qemu_img()) { |
1760 | imgfmt = "qcow2"; | |
1761 | test_image_size_mb = TEST_IMAGE_SIZE_MB_LARGE; | |
1762 | mkqcow2(tmp_path, TEST_IMAGE_SIZE_MB_LARGE); | |
1763 | } else { | |
1764 | g_test_message("QTEST_QEMU_IMG not set or qemu-img missing; " | |
1765 | "skipping LBA48 high-sector tests"); | |
1766 | imgfmt = "raw"; | |
1767 | test_image_size_mb = TEST_IMAGE_SIZE_MB_SMALL; | |
1768 | ret = ftruncate(fd, test_image_size_mb * 1024 * 1024); | |
1769 | g_assert(ret == 0); | |
1770 | } | |
b236b610 | 1771 | close(fd); |
1cd1031d | 1772 | |
cf5aa89e JS |
1773 | /* Create temporary blkdebug instructions */ |
1774 | fd = mkstemp(debug_path); | |
1775 | g_assert(fd >= 0); | |
1776 | close(fd); | |
1777 | ||
6d9e7295 JS |
1778 | /* Reserve a hollow file to use as a socket for migration tests */ |
1779 | fd = mkstemp(mig_socket); | |
1780 | g_assert(fd >= 0); | |
1781 | close(fd); | |
1782 | ||
1cd1031d JS |
1783 | /* Run the tests */ |
1784 | qtest_add_func("/ahci/sanity", test_sanity); | |
8840a843 | 1785 | qtest_add_func("/ahci/pci_spec", test_pci_spec); |
96d6d3ba | 1786 | qtest_add_func("/ahci/pci_enable", test_pci_enable); |
c2f3029f | 1787 | qtest_add_func("/ahci/hba_spec", test_hba_spec); |
dbc180e5 | 1788 | qtest_add_func("/ahci/hba_enable", test_hba_enable); |
0fa781e3 | 1789 | qtest_add_func("/ahci/identify", test_identify); |
bda39dc2 JS |
1790 | |
1791 | for (i = MODE_BEGIN; i < NUM_MODES; i++) { | |
1792 | for (j = ADDR_MODE_BEGIN; j < NUM_ADDR_MODES; j++) { | |
1793 | for (k = LEN_BEGIN; k < NUM_LENGTHS; k++) { | |
727be1a7 JS |
1794 | for (m = OFFSET_BEGIN; m < NUM_OFFSETS; m++) { |
1795 | create_ahci_io_test(i, j, k, m); | |
1796 | } | |
bda39dc2 JS |
1797 | } |
1798 | } | |
1799 | } | |
1cd1031d | 1800 | |
e0c59cc7 JS |
1801 | qtest_add_func("/ahci/io/dma/lba28/fragmented", test_dma_fragmented); |
1802 | ||
4e217074 | 1803 | qtest_add_func("/ahci/flush/simple", test_flush); |
cf5aa89e | 1804 | qtest_add_func("/ahci/flush/retry", test_flush_retry); |
a606ce50 | 1805 | qtest_add_func("/ahci/flush/migrate", test_flush_migrate); |
4e217074 | 1806 | |
278128ab | 1807 | qtest_add_func("/ahci/migrate/sanity", test_migrate_sanity); |
5d1cf091 | 1808 | qtest_add_func("/ahci/migrate/dma/simple", test_migrate_dma); |
189d1b61 | 1809 | qtest_add_func("/ahci/io/dma/lba28/retry", test_halted_dma); |
5d1cf091 | 1810 | qtest_add_func("/ahci/migrate/dma/halted", test_migrate_halted_dma); |
278128ab | 1811 | |
0d3e9d1f | 1812 | qtest_add_func("/ahci/max", test_max); |
d31a3ebc | 1813 | qtest_add_func("/ahci/reset", test_reset); |
0d3e9d1f | 1814 | |
26ad0045 | 1815 | qtest_add_func("/ahci/io/ncq/simple", test_ncq_simple); |
07a1ee79 | 1816 | qtest_add_func("/ahci/migrate/ncq/simple", test_migrate_ncq); |
7f6cf5ee | 1817 | qtest_add_func("/ahci/io/ncq/retry", test_halted_ncq); |
8146d7dc | 1818 | qtest_add_func("/ahci/migrate/ncq/halted", test_migrate_halted_ncq); |
26ad0045 | 1819 | |
e8109694 JS |
1820 | qtest_add_func("/ahci/cdrom/dma/single", test_cdrom_dma); |
1821 | qtest_add_func("/ahci/cdrom/dma/multi", test_cdrom_dma_multi); | |
1822 | qtest_add_func("/ahci/cdrom/pio/single", test_cdrom_pio); | |
1823 | qtest_add_func("/ahci/cdrom/pio/multi", test_cdrom_pio_multi); | |
1824 | ||
1cd1031d JS |
1825 | ret = g_test_run(); |
1826 | ||
1827 | /* Cleanup */ | |
1828 | unlink(tmp_path); | |
cf5aa89e | 1829 | unlink(debug_path); |
6d9e7295 | 1830 | unlink(mig_socket); |
1cd1031d JS |
1831 | |
1832 | return ret; | |
1833 | } |