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acbe4801 KW |
1 | /* |
2 | * IDE test cases | |
3 | * | |
4 | * Copyright (c) 2013 Kevin Wolf <kwolf@redhat.com> | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include <stdint.h> | |
26 | #include <string.h> | |
27 | #include <stdio.h> | |
28 | ||
29 | #include <glib.h> | |
30 | ||
31 | #include "libqtest.h" | |
b95739dc KW |
32 | #include "libqos/pci-pc.h" |
33 | #include "libqos/malloc-pc.h" | |
acbe4801 KW |
34 | |
35 | #include "qemu-common.h" | |
b95739dc KW |
36 | #include "hw/pci/pci_ids.h" |
37 | #include "hw/pci/pci_regs.h" | |
acbe4801 KW |
38 | |
39 | #define TEST_IMAGE_SIZE 64 * 1024 * 1024 | |
40 | ||
41 | #define IDE_PCI_DEV 1 | |
42 | #define IDE_PCI_FUNC 1 | |
43 | ||
44 | #define IDE_BASE 0x1f0 | |
45 | #define IDE_PRIMARY_IRQ 14 | |
46 | ||
47 | enum { | |
48 | reg_data = 0x0, | |
49 | reg_nsectors = 0x2, | |
50 | reg_lba_low = 0x3, | |
51 | reg_lba_middle = 0x4, | |
52 | reg_lba_high = 0x5, | |
53 | reg_device = 0x6, | |
54 | reg_status = 0x7, | |
55 | reg_command = 0x7, | |
56 | }; | |
57 | ||
58 | enum { | |
59 | BSY = 0x80, | |
60 | DRDY = 0x40, | |
61 | DF = 0x20, | |
62 | DRQ = 0x08, | |
63 | ERR = 0x01, | |
64 | }; | |
65 | ||
66 | enum { | |
c27d5656 | 67 | DEV = 0x10, |
b95739dc KW |
68 | LBA = 0x40, |
69 | }; | |
70 | ||
71 | enum { | |
72 | bmreg_cmd = 0x0, | |
73 | bmreg_status = 0x2, | |
74 | bmreg_prdt = 0x4, | |
75 | }; | |
76 | ||
77 | enum { | |
78 | CMD_READ_DMA = 0xc8, | |
79 | CMD_WRITE_DMA = 0xca, | |
bd07684a | 80 | CMD_FLUSH_CACHE = 0xe7, |
acbe4801 | 81 | CMD_IDENTIFY = 0xec, |
948eaed1 KW |
82 | |
83 | CMDF_ABORT = 0x100, | |
d7b7e580 | 84 | CMDF_NO_BM = 0x200, |
acbe4801 KW |
85 | }; |
86 | ||
b95739dc KW |
87 | enum { |
88 | BM_CMD_START = 0x1, | |
89 | BM_CMD_WRITE = 0x8, /* write = from device to memory */ | |
90 | }; | |
91 | ||
92 | enum { | |
93 | BM_STS_ACTIVE = 0x1, | |
94 | BM_STS_ERROR = 0x2, | |
95 | BM_STS_INTR = 0x4, | |
96 | }; | |
97 | ||
98 | enum { | |
99 | PRDT_EOT = 0x80000000, | |
100 | }; | |
101 | ||
acbe4801 KW |
102 | #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask)) |
103 | #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0) | |
104 | ||
b95739dc KW |
105 | static QPCIBus *pcibus = NULL; |
106 | static QGuestAllocator *guest_malloc; | |
107 | ||
acbe4801 | 108 | static char tmp_path[] = "/tmp/qtest.XXXXXX"; |
14a92e5f | 109 | static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX"; |
acbe4801 KW |
110 | |
111 | static void ide_test_start(const char *cmdline_fmt, ...) | |
112 | { | |
113 | va_list ap; | |
114 | char *cmdline; | |
115 | ||
116 | va_start(ap, cmdline_fmt); | |
117 | cmdline = g_strdup_vprintf(cmdline_fmt, ap); | |
118 | va_end(ap); | |
119 | ||
120 | qtest_start(cmdline); | |
121 | qtest_irq_intercept_in(global_qtest, "ioapic"); | |
b95739dc | 122 | guest_malloc = pc_alloc_init(); |
acbe4801 KW |
123 | } |
124 | ||
125 | static void ide_test_quit(void) | |
126 | { | |
1d9358e6 | 127 | qtest_end(); |
acbe4801 KW |
128 | } |
129 | ||
b95739dc KW |
130 | static QPCIDevice *get_pci_device(uint16_t *bmdma_base) |
131 | { | |
132 | QPCIDevice *dev; | |
133 | uint16_t vendor_id, device_id; | |
134 | ||
135 | if (!pcibus) { | |
136 | pcibus = qpci_init_pc(); | |
137 | } | |
138 | ||
139 | /* Find PCI device and verify it's the right one */ | |
140 | dev = qpci_device_find(pcibus, QPCI_DEVFN(IDE_PCI_DEV, IDE_PCI_FUNC)); | |
141 | g_assert(dev != NULL); | |
142 | ||
143 | vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID); | |
144 | device_id = qpci_config_readw(dev, PCI_DEVICE_ID); | |
145 | g_assert(vendor_id == PCI_VENDOR_ID_INTEL); | |
146 | g_assert(device_id == PCI_DEVICE_ID_INTEL_82371SB_1); | |
147 | ||
148 | /* Map bmdma BAR */ | |
6ce7100e | 149 | *bmdma_base = (uint16_t)(uintptr_t) qpci_iomap(dev, 4, NULL); |
b95739dc KW |
150 | |
151 | qpci_device_enable(dev); | |
152 | ||
153 | return dev; | |
154 | } | |
155 | ||
156 | static void free_pci_device(QPCIDevice *dev) | |
157 | { | |
158 | /* libqos doesn't have a function for this, so free it manually */ | |
159 | g_free(dev); | |
160 | } | |
161 | ||
162 | typedef struct PrdtEntry { | |
163 | uint32_t addr; | |
164 | uint32_t size; | |
165 | } QEMU_PACKED PrdtEntry; | |
166 | ||
167 | #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask)) | |
168 | #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0) | |
169 | ||
170 | static int send_dma_request(int cmd, uint64_t sector, int nb_sectors, | |
171 | PrdtEntry *prdt, int prdt_entries) | |
172 | { | |
173 | QPCIDevice *dev; | |
174 | uint16_t bmdma_base; | |
175 | uintptr_t guest_prdt; | |
176 | size_t len; | |
177 | bool from_dev; | |
178 | uint8_t status; | |
948eaed1 | 179 | int flags; |
b95739dc KW |
180 | |
181 | dev = get_pci_device(&bmdma_base); | |
182 | ||
948eaed1 KW |
183 | flags = cmd & ~0xff; |
184 | cmd &= 0xff; | |
185 | ||
b95739dc KW |
186 | switch (cmd) { |
187 | case CMD_READ_DMA: | |
188 | from_dev = true; | |
189 | break; | |
190 | case CMD_WRITE_DMA: | |
191 | from_dev = false; | |
192 | break; | |
193 | default: | |
194 | g_assert_not_reached(); | |
195 | } | |
196 | ||
d7b7e580 KW |
197 | if (flags & CMDF_NO_BM) { |
198 | qpci_config_writew(dev, PCI_COMMAND, | |
199 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); | |
200 | } | |
201 | ||
b95739dc KW |
202 | /* Select device 0 */ |
203 | outb(IDE_BASE + reg_device, 0 | LBA); | |
204 | ||
205 | /* Stop any running transfer, clear any pending interrupt */ | |
206 | outb(bmdma_base + bmreg_cmd, 0); | |
207 | outb(bmdma_base + bmreg_status, BM_STS_INTR); | |
208 | ||
209 | /* Setup PRDT */ | |
210 | len = sizeof(*prdt) * prdt_entries; | |
211 | guest_prdt = guest_alloc(guest_malloc, len); | |
212 | memwrite(guest_prdt, prdt, len); | |
213 | outl(bmdma_base + bmreg_prdt, guest_prdt); | |
214 | ||
215 | /* ATA DMA command */ | |
216 | outb(IDE_BASE + reg_nsectors, nb_sectors); | |
217 | ||
218 | outb(IDE_BASE + reg_lba_low, sector & 0xff); | |
219 | outb(IDE_BASE + reg_lba_middle, (sector >> 8) & 0xff); | |
220 | outb(IDE_BASE + reg_lba_high, (sector >> 16) & 0xff); | |
221 | ||
222 | outb(IDE_BASE + reg_command, cmd); | |
223 | ||
224 | /* Start DMA transfer */ | |
225 | outb(bmdma_base + bmreg_cmd, BM_CMD_START | (from_dev ? BM_CMD_WRITE : 0)); | |
226 | ||
948eaed1 KW |
227 | if (flags & CMDF_ABORT) { |
228 | outb(bmdma_base + bmreg_cmd, 0); | |
229 | } | |
230 | ||
b95739dc KW |
231 | /* Wait for the DMA transfer to complete */ |
232 | do { | |
233 | status = inb(bmdma_base + bmreg_status); | |
234 | } while ((status & (BM_STS_ACTIVE | BM_STS_INTR)) == BM_STS_ACTIVE); | |
235 | ||
236 | g_assert_cmpint(get_irq(IDE_PRIMARY_IRQ), ==, !!(status & BM_STS_INTR)); | |
237 | ||
238 | /* Check IDE status code */ | |
239 | assert_bit_set(inb(IDE_BASE + reg_status), DRDY); | |
240 | assert_bit_clear(inb(IDE_BASE + reg_status), BSY | DRQ); | |
241 | ||
242 | /* Reading the status register clears the IRQ */ | |
243 | g_assert(!get_irq(IDE_PRIMARY_IRQ)); | |
244 | ||
245 | /* Stop DMA transfer if still active */ | |
246 | if (status & BM_STS_ACTIVE) { | |
247 | outb(bmdma_base + bmreg_cmd, 0); | |
248 | } | |
249 | ||
250 | free_pci_device(dev); | |
251 | ||
252 | return status; | |
253 | } | |
254 | ||
255 | static void test_bmdma_simple_rw(void) | |
256 | { | |
257 | uint8_t status; | |
258 | uint8_t *buf; | |
259 | uint8_t *cmpbuf; | |
260 | size_t len = 512; | |
261 | uintptr_t guest_buf = guest_alloc(guest_malloc, len); | |
262 | ||
263 | PrdtEntry prdt[] = { | |
262f27b9 KW |
264 | { |
265 | .addr = cpu_to_le32(guest_buf), | |
266 | .size = cpu_to_le32(len | PRDT_EOT), | |
267 | }, | |
b95739dc KW |
268 | }; |
269 | ||
270 | buf = g_malloc(len); | |
271 | cmpbuf = g_malloc(len); | |
272 | ||
273 | /* Write 0x55 pattern to sector 0 */ | |
274 | memset(buf, 0x55, len); | |
275 | memwrite(guest_buf, buf, len); | |
276 | ||
277 | status = send_dma_request(CMD_WRITE_DMA, 0, 1, prdt, ARRAY_SIZE(prdt)); | |
278 | g_assert_cmphex(status, ==, BM_STS_INTR); | |
279 | assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); | |
280 | ||
281 | /* Write 0xaa pattern to sector 1 */ | |
282 | memset(buf, 0xaa, len); | |
283 | memwrite(guest_buf, buf, len); | |
284 | ||
285 | status = send_dma_request(CMD_WRITE_DMA, 1, 1, prdt, ARRAY_SIZE(prdt)); | |
286 | g_assert_cmphex(status, ==, BM_STS_INTR); | |
287 | assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); | |
288 | ||
289 | /* Read and verify 0x55 pattern in sector 0 */ | |
290 | memset(cmpbuf, 0x55, len); | |
291 | ||
292 | status = send_dma_request(CMD_READ_DMA, 0, 1, prdt, ARRAY_SIZE(prdt)); | |
293 | g_assert_cmphex(status, ==, BM_STS_INTR); | |
294 | assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); | |
295 | ||
296 | memread(guest_buf, buf, len); | |
297 | g_assert(memcmp(buf, cmpbuf, len) == 0); | |
298 | ||
299 | /* Read and verify 0xaa pattern in sector 1 */ | |
300 | memset(cmpbuf, 0xaa, len); | |
301 | ||
302 | status = send_dma_request(CMD_READ_DMA, 1, 1, prdt, ARRAY_SIZE(prdt)); | |
303 | g_assert_cmphex(status, ==, BM_STS_INTR); | |
304 | assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); | |
305 | ||
306 | memread(guest_buf, buf, len); | |
307 | g_assert(memcmp(buf, cmpbuf, len) == 0); | |
308 | ||
309 | ||
310 | g_free(buf); | |
311 | g_free(cmpbuf); | |
312 | } | |
313 | ||
948eaed1 KW |
314 | static void test_bmdma_short_prdt(void) |
315 | { | |
316 | uint8_t status; | |
317 | ||
318 | PrdtEntry prdt[] = { | |
262f27b9 KW |
319 | { |
320 | .addr = 0, | |
321 | .size = cpu_to_le32(0x10 | PRDT_EOT), | |
322 | }, | |
948eaed1 KW |
323 | }; |
324 | ||
325 | /* Normal request */ | |
326 | status = send_dma_request(CMD_READ_DMA, 0, 1, | |
327 | prdt, ARRAY_SIZE(prdt)); | |
328 | g_assert_cmphex(status, ==, 0); | |
329 | assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); | |
330 | ||
331 | /* Abort the request before it completes */ | |
332 | status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1, | |
333 | prdt, ARRAY_SIZE(prdt)); | |
334 | g_assert_cmphex(status, ==, 0); | |
335 | assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); | |
336 | } | |
337 | ||
338 | static void test_bmdma_long_prdt(void) | |
339 | { | |
340 | uint8_t status; | |
341 | ||
342 | PrdtEntry prdt[] = { | |
262f27b9 KW |
343 | { |
344 | .addr = 0, | |
345 | .size = cpu_to_le32(0x1000 | PRDT_EOT), | |
346 | }, | |
948eaed1 KW |
347 | }; |
348 | ||
349 | /* Normal request */ | |
350 | status = send_dma_request(CMD_READ_DMA, 0, 1, | |
351 | prdt, ARRAY_SIZE(prdt)); | |
352 | g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR); | |
353 | assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); | |
354 | ||
355 | /* Abort the request before it completes */ | |
356 | status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1, | |
357 | prdt, ARRAY_SIZE(prdt)); | |
358 | g_assert_cmphex(status, ==, BM_STS_INTR); | |
359 | assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); | |
360 | } | |
361 | ||
d7b7e580 KW |
362 | static void test_bmdma_no_busmaster(void) |
363 | { | |
364 | uint8_t status; | |
365 | ||
366 | /* No PRDT_EOT, each entry addr 0/size 64k, and in theory qemu shouldn't be | |
367 | * able to access it anyway because the Bus Master bit in the PCI command | |
368 | * register isn't set. This is complete nonsense, but it used to be pretty | |
369 | * good at confusing and occasionally crashing qemu. */ | |
370 | PrdtEntry prdt[4096] = { }; | |
371 | ||
372 | status = send_dma_request(CMD_READ_DMA | CMDF_NO_BM, 0, 512, | |
373 | prdt, ARRAY_SIZE(prdt)); | |
374 | ||
375 | /* Not entirely clear what the expected result is, but this is what we get | |
376 | * in practice. At least we want to be aware of any changes. */ | |
377 | g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR); | |
378 | assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR); | |
379 | } | |
380 | ||
b95739dc KW |
381 | static void test_bmdma_setup(void) |
382 | { | |
383 | ide_test_start( | |
b95739dc KW |
384 | "-drive file=%s,if=ide,serial=%s,cache=writeback " |
385 | "-global ide-hd.ver=%s", | |
386 | tmp_path, "testdisk", "version"); | |
387 | } | |
388 | ||
389 | static void test_bmdma_teardown(void) | |
390 | { | |
391 | ide_test_quit(); | |
392 | } | |
393 | ||
262f27b9 KW |
394 | static void string_cpu_to_be16(uint16_t *s, size_t bytes) |
395 | { | |
396 | g_assert((bytes & 1) == 0); | |
397 | bytes /= 2; | |
398 | ||
399 | while (bytes--) { | |
400 | *s = cpu_to_be16(*s); | |
401 | s++; | |
402 | } | |
403 | } | |
404 | ||
acbe4801 KW |
405 | static void test_identify(void) |
406 | { | |
407 | uint8_t data; | |
408 | uint16_t buf[256]; | |
409 | int i; | |
410 | int ret; | |
411 | ||
412 | ide_test_start( | |
acbe4801 KW |
413 | "-drive file=%s,if=ide,serial=%s,cache=writeback " |
414 | "-global ide-hd.ver=%s", | |
415 | tmp_path, "testdisk", "version"); | |
416 | ||
417 | /* IDENTIFY command on device 0*/ | |
418 | outb(IDE_BASE + reg_device, 0); | |
419 | outb(IDE_BASE + reg_command, CMD_IDENTIFY); | |
420 | ||
421 | /* Read in the IDENTIFY buffer and check registers */ | |
422 | data = inb(IDE_BASE + reg_device); | |
c27d5656 | 423 | g_assert_cmpint(data & DEV, ==, 0); |
acbe4801 KW |
424 | |
425 | for (i = 0; i < 256; i++) { | |
426 | data = inb(IDE_BASE + reg_status); | |
427 | assert_bit_set(data, DRDY | DRQ); | |
428 | assert_bit_clear(data, BSY | DF | ERR); | |
429 | ||
430 | ((uint16_t*) buf)[i] = inw(IDE_BASE + reg_data); | |
431 | } | |
432 | ||
433 | data = inb(IDE_BASE + reg_status); | |
434 | assert_bit_set(data, DRDY); | |
435 | assert_bit_clear(data, BSY | DF | ERR | DRQ); | |
436 | ||
437 | /* Check serial number/version in the buffer */ | |
262f27b9 KW |
438 | string_cpu_to_be16(&buf[10], 20); |
439 | ret = memcmp(&buf[10], "testdisk ", 20); | |
acbe4801 KW |
440 | g_assert(ret == 0); |
441 | ||
262f27b9 KW |
442 | string_cpu_to_be16(&buf[23], 8); |
443 | ret = memcmp(&buf[23], "version ", 8); | |
acbe4801 KW |
444 | g_assert(ret == 0); |
445 | ||
446 | /* Write cache enabled bit */ | |
447 | assert_bit_set(buf[85], 0x20); | |
448 | ||
449 | ide_test_quit(); | |
450 | } | |
451 | ||
bd07684a KW |
452 | static void test_flush(void) |
453 | { | |
454 | uint8_t data; | |
455 | ||
456 | ide_test_start( | |
bd07684a KW |
457 | "-drive file=blkdebug::%s,if=ide,cache=writeback", |
458 | tmp_path); | |
459 | ||
460 | /* Delay the completion of the flush request until we explicitly do it */ | |
0d1aa05e SH |
461 | qmp_discard_response("{'execute':'human-monitor-command', 'arguments': {" |
462 | " 'command-line':" | |
463 | " 'qemu-io ide0-hd0 \"break flush_to_os A\"'} }"); | |
bd07684a KW |
464 | |
465 | /* FLUSH CACHE command on device 0*/ | |
466 | outb(IDE_BASE + reg_device, 0); | |
467 | outb(IDE_BASE + reg_command, CMD_FLUSH_CACHE); | |
468 | ||
469 | /* Check status while request is in flight*/ | |
470 | data = inb(IDE_BASE + reg_status); | |
471 | assert_bit_set(data, BSY | DRDY); | |
472 | assert_bit_clear(data, DF | ERR | DRQ); | |
473 | ||
474 | /* Complete the command */ | |
0d1aa05e SH |
475 | qmp_discard_response("{'execute':'human-monitor-command', 'arguments': {" |
476 | " 'command-line':" | |
477 | " 'qemu-io ide0-hd0 \"resume A\"'} }"); | |
bd07684a KW |
478 | |
479 | /* Check registers */ | |
480 | data = inb(IDE_BASE + reg_device); | |
481 | g_assert_cmpint(data & DEV, ==, 0); | |
482 | ||
22bfa16e MR |
483 | do { |
484 | data = inb(IDE_BASE + reg_status); | |
485 | } while (data & BSY); | |
486 | ||
bd07684a KW |
487 | assert_bit_set(data, DRDY); |
488 | assert_bit_clear(data, BSY | DF | ERR | DRQ); | |
489 | ||
490 | ide_test_quit(); | |
491 | } | |
492 | ||
14a92e5f PB |
493 | static void prepare_blkdebug_script(const char *debug_fn, const char *event) |
494 | { | |
495 | FILE *debug_file = fopen(debug_fn, "w"); | |
496 | int ret; | |
497 | ||
498 | fprintf(debug_file, "[inject-error]\n"); | |
499 | fprintf(debug_file, "event = \"%s\"\n", event); | |
500 | fprintf(debug_file, "errno = \"5\"\n"); | |
501 | fprintf(debug_file, "state = \"1\"\n"); | |
502 | fprintf(debug_file, "immediately = \"off\"\n"); | |
503 | fprintf(debug_file, "once = \"on\"\n"); | |
504 | ||
505 | fprintf(debug_file, "[set-state]\n"); | |
506 | fprintf(debug_file, "event = \"%s\"\n", event); | |
507 | fprintf(debug_file, "new_state = \"2\"\n"); | |
508 | fflush(debug_file); | |
509 | g_assert(!ferror(debug_file)); | |
510 | ||
511 | ret = fclose(debug_file); | |
512 | g_assert(ret == 0); | |
513 | } | |
514 | ||
515 | static void test_retry_flush(void) | |
516 | { | |
517 | uint8_t data; | |
518 | const char *s; | |
519 | QDict *response; | |
520 | ||
521 | prepare_blkdebug_script(debug_path, "flush_to_disk"); | |
522 | ||
523 | ide_test_start( | |
524 | "-vnc none " | |
525 | "-drive file=blkdebug:%s:%s,if=ide,cache=writeback,rerror=stop,werror=stop", | |
526 | debug_path, tmp_path); | |
527 | ||
528 | /* FLUSH CACHE command on device 0*/ | |
529 | outb(IDE_BASE + reg_device, 0); | |
530 | outb(IDE_BASE + reg_command, CMD_FLUSH_CACHE); | |
531 | ||
532 | /* Check status while request is in flight*/ | |
533 | data = inb(IDE_BASE + reg_status); | |
534 | assert_bit_set(data, BSY | DRDY); | |
535 | assert_bit_clear(data, DF | ERR | DRQ); | |
536 | ||
537 | for (;; response = NULL) { | |
538 | response = qmp_receive(); | |
539 | if ((qdict_haskey(response, "event")) && | |
540 | (strcmp(qdict_get_str(response, "event"), "STOP") == 0)) { | |
541 | QDECREF(response); | |
542 | break; | |
543 | } | |
544 | QDECREF(response); | |
545 | } | |
546 | ||
547 | /* Complete the command */ | |
548 | s = "{'execute':'cont' }"; | |
549 | qmp_discard_response(s); | |
550 | ||
551 | /* Check registers */ | |
552 | data = inb(IDE_BASE + reg_device); | |
553 | g_assert_cmpint(data & DEV, ==, 0); | |
554 | ||
555 | do { | |
556 | data = inb(IDE_BASE + reg_status); | |
557 | } while (data & BSY); | |
558 | ||
559 | assert_bit_set(data, DRDY); | |
560 | assert_bit_clear(data, BSY | DF | ERR | DRQ); | |
561 | ||
562 | ide_test_quit(); | |
563 | } | |
564 | ||
acbe4801 KW |
565 | int main(int argc, char **argv) |
566 | { | |
567 | const char *arch = qtest_get_arch(); | |
568 | int fd; | |
569 | int ret; | |
570 | ||
571 | /* Check architecture */ | |
572 | if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) { | |
573 | g_test_message("Skipping test for non-x86\n"); | |
574 | return 0; | |
575 | } | |
576 | ||
14a92e5f PB |
577 | /* Create temporary blkdebug instructions */ |
578 | fd = mkstemp(debug_path); | |
579 | g_assert(fd >= 0); | |
580 | close(fd); | |
581 | ||
acbe4801 KW |
582 | /* Create a temporary raw image */ |
583 | fd = mkstemp(tmp_path); | |
584 | g_assert(fd >= 0); | |
585 | ret = ftruncate(fd, TEST_IMAGE_SIZE); | |
586 | g_assert(ret == 0); | |
587 | close(fd); | |
588 | ||
589 | /* Run the tests */ | |
590 | g_test_init(&argc, &argv, NULL); | |
591 | ||
592 | qtest_add_func("/ide/identify", test_identify); | |
593 | ||
b95739dc KW |
594 | qtest_add_func("/ide/bmdma/setup", test_bmdma_setup); |
595 | qtest_add_func("/ide/bmdma/simple_rw", test_bmdma_simple_rw); | |
948eaed1 KW |
596 | qtest_add_func("/ide/bmdma/short_prdt", test_bmdma_short_prdt); |
597 | qtest_add_func("/ide/bmdma/long_prdt", test_bmdma_long_prdt); | |
d7b7e580 | 598 | qtest_add_func("/ide/bmdma/no_busmaster", test_bmdma_no_busmaster); |
b95739dc KW |
599 | qtest_add_func("/ide/bmdma/teardown", test_bmdma_teardown); |
600 | ||
bd07684a KW |
601 | qtest_add_func("/ide/flush", test_flush); |
602 | ||
14a92e5f PB |
603 | qtest_add_func("/ide/retry/flush", test_retry_flush); |
604 | ||
acbe4801 KW |
605 | ret = g_test_run(); |
606 | ||
607 | /* Cleanup */ | |
608 | unlink(tmp_path); | |
14a92e5f | 609 | unlink(debug_path); |
acbe4801 KW |
610 | |
611 | return ret; | |
612 | } |