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Commit | Line | Data |
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bbfc2efe AF |
1 | /* |
2 | * QTest testcase for ivshmem | |
3 | * | |
4 | * Copyright (c) 2014 SUSE LINUX Products GmbH | |
ddef6a0d | 5 | * Copyright (c) 2015 Red Hat, Inc. |
bbfc2efe AF |
6 | * |
7 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
8 | * See the COPYING file in the top-level directory. | |
9 | */ | |
10 | ||
681c28a3 | 11 | #include "qemu/osdep.h" |
ddef6a0d | 12 | #include <glib/gstdio.h> |
ddef6a0d MAL |
13 | #include "contrib/ivshmem-server/ivshmem-server.h" |
14 | #include "libqos/pci-pc.h" | |
bbfc2efe | 15 | #include "libqtest.h" |
ddef6a0d | 16 | #include "qemu-common.h" |
bbfc2efe | 17 | |
ddef6a0d MAL |
18 | #define TMPSHMSIZE (1 << 20) |
19 | static char *tmpshm; | |
20 | static void *tmpshmem; | |
21 | static char *tmpdir; | |
22 | static char *tmpserver; | |
bbfc2efe | 23 | |
ddef6a0d | 24 | static void save_fn(QPCIDevice *dev, int devfn, void *data) |
bbfc2efe | 25 | { |
ddef6a0d MAL |
26 | QPCIDevice **pdev = (QPCIDevice **) data; |
27 | ||
28 | *pdev = dev; | |
29 | } | |
30 | ||
1760048a | 31 | static QPCIDevice *get_device(QPCIBus *pcibus) |
ddef6a0d MAL |
32 | { |
33 | QPCIDevice *dev; | |
ddef6a0d | 34 | |
16130947 | 35 | dev = NULL; |
ddef6a0d MAL |
36 | qpci_device_foreach(pcibus, 0x1af4, 0x1110, save_fn, &dev); |
37 | g_assert(dev != NULL); | |
38 | ||
39 | return dev; | |
40 | } | |
41 | ||
42 | typedef struct _IVState { | |
43 | QTestState *qtest; | |
b4ba67d9 | 44 | QPCIBar reg_bar, mem_bar; |
1760048a | 45 | QPCIBus *pcibus; |
ddef6a0d MAL |
46 | QPCIDevice *dev; |
47 | } IVState; | |
48 | ||
49 | enum Reg { | |
50 | INTRMASK = 0, | |
51 | INTRSTATUS = 4, | |
52 | IVPOSITION = 8, | |
53 | DOORBELL = 12, | |
54 | }; | |
55 | ||
56 | static const char* reg2str(enum Reg reg) { | |
57 | switch (reg) { | |
58 | case INTRMASK: | |
59 | return "IntrMask"; | |
60 | case INTRSTATUS: | |
61 | return "IntrStatus"; | |
62 | case IVPOSITION: | |
63 | return "IVPosition"; | |
64 | case DOORBELL: | |
65 | return "DoorBell"; | |
66 | default: | |
67 | return NULL; | |
68 | } | |
69 | } | |
70 | ||
71 | static inline unsigned in_reg(IVState *s, enum Reg reg) | |
72 | { | |
73 | const char *name = reg2str(reg); | |
74 | QTestState *qtest = global_qtest; | |
75 | unsigned res; | |
76 | ||
77 | global_qtest = s->qtest; | |
b4ba67d9 | 78 | res = qpci_io_readl(s->dev, s->reg_bar, reg); |
ddef6a0d MAL |
79 | g_test_message("*%s -> %x\n", name, res); |
80 | global_qtest = qtest; | |
81 | ||
82 | return res; | |
83 | } | |
84 | ||
85 | static inline void out_reg(IVState *s, enum Reg reg, unsigned v) | |
86 | { | |
87 | const char *name = reg2str(reg); | |
88 | QTestState *qtest = global_qtest; | |
89 | ||
90 | global_qtest = s->qtest; | |
91 | g_test_message("%x -> *%s\n", v, name); | |
b4ba67d9 | 92 | qpci_io_writel(s->dev, s->reg_bar, reg, v); |
ddef6a0d MAL |
93 | global_qtest = qtest; |
94 | } | |
95 | ||
204e54b8 DG |
96 | static inline void read_mem(IVState *s, uint64_t off, void *buf, size_t len) |
97 | { | |
98 | QTestState *qtest = global_qtest; | |
99 | ||
100 | global_qtest = s->qtest; | |
b4ba67d9 | 101 | qpci_memread(s->dev, s->mem_bar, off, buf, len); |
204e54b8 DG |
102 | global_qtest = qtest; |
103 | } | |
104 | ||
105 | static inline void write_mem(IVState *s, uint64_t off, | |
106 | const void *buf, size_t len) | |
107 | { | |
108 | QTestState *qtest = global_qtest; | |
109 | ||
110 | global_qtest = s->qtest; | |
b4ba67d9 | 111 | qpci_memwrite(s->dev, s->mem_bar, off, buf, len); |
204e54b8 DG |
112 | global_qtest = qtest; |
113 | } | |
114 | ||
1760048a MAL |
115 | static void cleanup_vm(IVState *s) |
116 | { | |
117 | g_free(s->dev); | |
118 | qpci_free_pc(s->pcibus); | |
119 | qtest_quit(s->qtest); | |
120 | } | |
121 | ||
ddef6a0d MAL |
122 | static void setup_vm_cmd(IVState *s, const char *cmd, bool msix) |
123 | { | |
124 | uint64_t barsize; | |
125 | ||
126 | s->qtest = qtest_start(cmd); | |
2ecd7e2f | 127 | s->pcibus = qpci_init_pc(NULL); |
1760048a | 128 | s->dev = get_device(s->pcibus); |
ddef6a0d | 129 | |
b4ba67d9 | 130 | s->reg_bar = qpci_iomap(s->dev, 0, &barsize); |
99826172 | 131 | g_assert_cmpuint(barsize, ==, 256); |
ddef6a0d MAL |
132 | |
133 | if (msix) { | |
134 | qpci_msix_enable(s->dev); | |
135 | } | |
136 | ||
b4ba67d9 | 137 | s->mem_bar = qpci_iomap(s->dev, 2, &barsize); |
99826172 | 138 | g_assert_cmpuint(barsize, ==, TMPSHMSIZE); |
ddef6a0d MAL |
139 | |
140 | qpci_device_enable(s->dev); | |
141 | } | |
142 | ||
143 | static void setup_vm(IVState *s) | |
144 | { | |
5400c02b MA |
145 | char *cmd = g_strdup_printf("-object memory-backend-file" |
146 | ",id=mb1,size=1M,share,mem-path=/dev/shm%s" | |
147 | " -device ivshmem-plain,memdev=mb1", tmpshm); | |
ddef6a0d MAL |
148 | |
149 | setup_vm_cmd(s, cmd, false); | |
150 | ||
151 | g_free(cmd); | |
152 | } | |
153 | ||
154 | static void test_ivshmem_single(void) | |
155 | { | |
156 | IVState state, *s; | |
157 | uint32_t data[1024]; | |
158 | int i; | |
159 | ||
160 | setup_vm(&state); | |
161 | s = &state; | |
162 | ||
4958fe5d MA |
163 | /* initial state of readable registers */ |
164 | g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0); | |
165 | g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0); | |
166 | g_assert_cmpuint(in_reg(s, IVPOSITION), ==, 0); | |
ddef6a0d | 167 | |
4958fe5d | 168 | /* trigger interrupt via registers */ |
ddef6a0d MAL |
169 | out_reg(s, INTRMASK, 0xffffffff); |
170 | g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0xffffffff); | |
171 | out_reg(s, INTRSTATUS, 1); | |
4958fe5d | 172 | /* check interrupt status */ |
ddef6a0d | 173 | g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 1); |
4958fe5d MA |
174 | /* reading clears */ |
175 | g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0); | |
176 | /* TODO intercept actual interrupt (needs qtest work) */ | |
ddef6a0d | 177 | |
4958fe5d | 178 | /* invalid register access */ |
ddef6a0d | 179 | out_reg(s, IVPOSITION, 1); |
4958fe5d MA |
180 | in_reg(s, DOORBELL); |
181 | ||
182 | /* ring the (non-functional) doorbell */ | |
ddef6a0d MAL |
183 | out_reg(s, DOORBELL, 8 << 16); |
184 | ||
4958fe5d | 185 | /* write shared memory */ |
ddef6a0d MAL |
186 | for (i = 0; i < G_N_ELEMENTS(data); i++) { |
187 | data[i] = i; | |
188 | } | |
204e54b8 | 189 | write_mem(s, 0, data, sizeof(data)); |
ddef6a0d | 190 | |
4958fe5d | 191 | /* verify write */ |
ddef6a0d MAL |
192 | for (i = 0; i < G_N_ELEMENTS(data); i++) { |
193 | g_assert_cmpuint(((uint32_t *)tmpshmem)[i], ==, i); | |
194 | } | |
195 | ||
4958fe5d | 196 | /* read it back and verify read */ |
ddef6a0d | 197 | memset(data, 0, sizeof(data)); |
204e54b8 | 198 | read_mem(s, 0, data, sizeof(data)); |
ddef6a0d MAL |
199 | for (i = 0; i < G_N_ELEMENTS(data); i++) { |
200 | g_assert_cmpuint(data[i], ==, i); | |
201 | } | |
202 | ||
1760048a | 203 | cleanup_vm(s); |
ddef6a0d MAL |
204 | } |
205 | ||
206 | static void test_ivshmem_pair(void) | |
207 | { | |
208 | IVState state1, state2, *s1, *s2; | |
209 | char *data; | |
210 | int i; | |
211 | ||
212 | setup_vm(&state1); | |
213 | s1 = &state1; | |
214 | setup_vm(&state2); | |
215 | s2 = &state2; | |
216 | ||
217 | data = g_malloc0(TMPSHMSIZE); | |
218 | ||
219 | /* host write, guest 1 & 2 read */ | |
220 | memset(tmpshmem, 0x42, TMPSHMSIZE); | |
204e54b8 | 221 | read_mem(s1, 0, data, TMPSHMSIZE); |
ddef6a0d MAL |
222 | for (i = 0; i < TMPSHMSIZE; i++) { |
223 | g_assert_cmpuint(data[i], ==, 0x42); | |
224 | } | |
204e54b8 | 225 | read_mem(s2, 0, data, TMPSHMSIZE); |
ddef6a0d MAL |
226 | for (i = 0; i < TMPSHMSIZE; i++) { |
227 | g_assert_cmpuint(data[i], ==, 0x42); | |
228 | } | |
229 | ||
230 | /* guest 1 write, guest 2 read */ | |
231 | memset(data, 0x43, TMPSHMSIZE); | |
204e54b8 | 232 | write_mem(s1, 0, data, TMPSHMSIZE); |
ddef6a0d | 233 | memset(data, 0, TMPSHMSIZE); |
204e54b8 | 234 | read_mem(s2, 0, data, TMPSHMSIZE); |
ddef6a0d MAL |
235 | for (i = 0; i < TMPSHMSIZE; i++) { |
236 | g_assert_cmpuint(data[i], ==, 0x43); | |
237 | } | |
238 | ||
239 | /* guest 2 write, guest 1 read */ | |
240 | memset(data, 0x44, TMPSHMSIZE); | |
204e54b8 | 241 | write_mem(s2, 0, data, TMPSHMSIZE); |
ddef6a0d | 242 | memset(data, 0, TMPSHMSIZE); |
204e54b8 | 243 | read_mem(s1, 0, data, TMPSHMSIZE); |
ddef6a0d MAL |
244 | for (i = 0; i < TMPSHMSIZE; i++) { |
245 | g_assert_cmpuint(data[i], ==, 0x44); | |
246 | } | |
247 | ||
1760048a MAL |
248 | cleanup_vm(s1); |
249 | cleanup_vm(s2); | |
ddef6a0d MAL |
250 | g_free(data); |
251 | } | |
252 | ||
253 | typedef struct ServerThread { | |
254 | GThread *thread; | |
255 | IvshmemServer *server; | |
256 | int pipe[2]; /* to handle quit */ | |
257 | } ServerThread; | |
258 | ||
259 | static void *server_thread(void *data) | |
260 | { | |
261 | ServerThread *t = data; | |
262 | IvshmemServer *server = t->server; | |
263 | ||
264 | while (true) { | |
265 | fd_set fds; | |
266 | int maxfd, ret; | |
267 | ||
268 | FD_ZERO(&fds); | |
269 | FD_SET(t->pipe[0], &fds); | |
270 | maxfd = t->pipe[0] + 1; | |
271 | ||
272 | ivshmem_server_get_fds(server, &fds, &maxfd); | |
273 | ||
274 | ret = select(maxfd, &fds, NULL, NULL, NULL); | |
275 | ||
276 | if (ret < 0) { | |
277 | if (errno == EINTR) { | |
278 | continue; | |
279 | } | |
280 | ||
281 | g_critical("select error: %s\n", strerror(errno)); | |
282 | break; | |
283 | } | |
284 | if (ret == 0) { | |
285 | continue; | |
286 | } | |
287 | ||
288 | if (FD_ISSET(t->pipe[0], &fds)) { | |
289 | break; | |
290 | } | |
291 | ||
292 | if (ivshmem_server_handle_fds(server, &fds, maxfd) < 0) { | |
293 | g_critical("ivshmem_server_handle_fds() failed\n"); | |
294 | break; | |
295 | } | |
296 | } | |
297 | ||
298 | return NULL; | |
299 | } | |
300 | ||
00ffc3c1 | 301 | static void setup_vm_with_server(IVState *s, int nvectors, bool msi) |
ddef6a0d MAL |
302 | { |
303 | char *cmd = g_strdup_printf("-chardev socket,id=chr0,path=%s,nowait " | |
5400c02b MA |
304 | "-device ivshmem%s,chardev=chr0,vectors=%d", |
305 | tmpserver, | |
306 | msi ? "-doorbell" : ",size=1M,msi=off", | |
307 | nvectors); | |
ddef6a0d | 308 | |
00ffc3c1 | 309 | setup_vm_cmd(s, cmd, msi); |
ddef6a0d MAL |
310 | |
311 | g_free(cmd); | |
312 | } | |
313 | ||
00ffc3c1 | 314 | static void test_ivshmem_server(bool msi) |
ddef6a0d MAL |
315 | { |
316 | IVState state1, state2, *s1, *s2; | |
317 | ServerThread thread; | |
318 | IvshmemServer server; | |
319 | int ret, vm1, vm2; | |
320 | int nvectors = 2; | |
321 | guint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND; | |
322 | ||
3625c739 | 323 | ret = ivshmem_server_init(&server, tmpserver, tmpshm, true, |
ddef6a0d MAL |
324 | TMPSHMSIZE, nvectors, |
325 | g_test_verbose()); | |
326 | g_assert_cmpint(ret, ==, 0); | |
327 | ||
328 | ret = ivshmem_server_start(&server); | |
329 | g_assert_cmpint(ret, ==, 0); | |
330 | ||
ddef6a0d MAL |
331 | thread.server = &server; |
332 | ret = pipe(thread.pipe); | |
333 | g_assert_cmpint(ret, ==, 0); | |
334 | thread.thread = g_thread_new("ivshmem-server", server_thread, &thread); | |
335 | g_assert(thread.thread != NULL); | |
336 | ||
3a55fc0f MA |
337 | setup_vm_with_server(&state1, nvectors, msi); |
338 | s1 = &state1; | |
339 | setup_vm_with_server(&state2, nvectors, msi); | |
340 | s2 = &state2; | |
ddef6a0d MAL |
341 | |
342 | /* check got different VM ids */ | |
343 | vm1 = in_reg(s1, IVPOSITION); | |
344 | vm2 = in_reg(s2, IVPOSITION); | |
3a55fc0f MA |
345 | g_assert_cmpint(vm1, >=, 0); |
346 | g_assert_cmpint(vm2, >=, 0); | |
347 | g_assert_cmpint(vm1, !=, vm2); | |
ddef6a0d | 348 | |
41b65e5e | 349 | /* check number of MSI-X vectors */ |
ddef6a0d | 350 | global_qtest = s1->qtest; |
00ffc3c1 MAL |
351 | if (msi) { |
352 | ret = qpci_msix_table_size(s1->dev); | |
353 | g_assert_cmpuint(ret, ==, nvectors); | |
354 | } | |
ddef6a0d | 355 | |
41b65e5e MA |
356 | /* TODO test behavior before MSI-X is enabled */ |
357 | ||
358 | /* ping vm2 -> vm1 on vector 0 */ | |
00ffc3c1 MAL |
359 | if (msi) { |
360 | ret = qpci_msix_pending(s1->dev, 0); | |
361 | g_assert_cmpuint(ret, ==, 0); | |
362 | } else { | |
41b65e5e | 363 | g_assert_cmpuint(in_reg(s1, INTRSTATUS), ==, 0); |
00ffc3c1 | 364 | } |
ddef6a0d MAL |
365 | out_reg(s2, DOORBELL, vm1 << 16); |
366 | do { | |
367 | g_usleep(10000); | |
00ffc3c1 | 368 | ret = msi ? qpci_msix_pending(s1->dev, 0) : in_reg(s1, INTRSTATUS); |
ddef6a0d MAL |
369 | } while (ret == 0 && g_get_monotonic_time() < end_time); |
370 | g_assert_cmpuint(ret, !=, 0); | |
371 | ||
41b65e5e | 372 | /* ping vm1 -> vm2 on vector 1 */ |
ddef6a0d | 373 | global_qtest = s2->qtest; |
00ffc3c1 | 374 | if (msi) { |
41b65e5e | 375 | ret = qpci_msix_pending(s2->dev, 1); |
00ffc3c1 MAL |
376 | g_assert_cmpuint(ret, ==, 0); |
377 | } else { | |
41b65e5e | 378 | g_assert_cmpuint(in_reg(s2, INTRSTATUS), ==, 0); |
00ffc3c1 | 379 | } |
41b65e5e | 380 | out_reg(s1, DOORBELL, vm2 << 16 | 1); |
ddef6a0d MAL |
381 | do { |
382 | g_usleep(10000); | |
41b65e5e | 383 | ret = msi ? qpci_msix_pending(s2->dev, 1) : in_reg(s2, INTRSTATUS); |
ddef6a0d MAL |
384 | } while (ret == 0 && g_get_monotonic_time() < end_time); |
385 | g_assert_cmpuint(ret, !=, 0); | |
386 | ||
1760048a MAL |
387 | cleanup_vm(s2); |
388 | cleanup_vm(s1); | |
ddef6a0d MAL |
389 | |
390 | if (qemu_write_full(thread.pipe[1], "q", 1) != 1) { | |
391 | g_error("qemu_write_full: %s", g_strerror(errno)); | |
392 | } | |
393 | ||
394 | g_thread_join(thread.thread); | |
395 | ||
396 | ivshmem_server_close(&server); | |
397 | close(thread.pipe[1]); | |
398 | close(thread.pipe[0]); | |
399 | } | |
400 | ||
00ffc3c1 MAL |
401 | static void test_ivshmem_server_msi(void) |
402 | { | |
403 | test_ivshmem_server(true); | |
404 | } | |
405 | ||
406 | static void test_ivshmem_server_irq(void) | |
407 | { | |
408 | test_ivshmem_server(false); | |
409 | } | |
410 | ||
ddef6a0d MAL |
411 | #define PCI_SLOT_HP 0x06 |
412 | ||
413 | static void test_ivshmem_hotplug(void) | |
414 | { | |
415 | gchar *opts; | |
416 | ||
417 | qtest_start(""); | |
418 | ||
419 | opts = g_strdup_printf("'shm': '%s', 'size': '1M'", tmpshm); | |
420 | ||
421 | qpci_plug_device_test("ivshmem", "iv1", PCI_SLOT_HP, opts); | |
422 | qpci_unplug_acpi_device_test("iv1", PCI_SLOT_HP); | |
423 | ||
424 | qtest_end(); | |
425 | g_free(opts); | |
426 | } | |
427 | ||
d9453c93 MAL |
428 | static void test_ivshmem_memdev(void) |
429 | { | |
430 | IVState state; | |
431 | ||
432 | /* just for the sake of checking memory-backend property */ | |
433 | setup_vm_cmd(&state, "-object memory-backend-ram,size=1M,id=mb1" | |
5400c02b | 434 | " -device ivshmem-plain,memdev=mb1", false); |
d9453c93 | 435 | |
1760048a | 436 | cleanup_vm(&state); |
d9453c93 MAL |
437 | } |
438 | ||
ddef6a0d MAL |
439 | static void cleanup(void) |
440 | { | |
441 | if (tmpshmem) { | |
442 | munmap(tmpshmem, TMPSHMSIZE); | |
443 | tmpshmem = NULL; | |
444 | } | |
445 | ||
446 | if (tmpshm) { | |
447 | shm_unlink(tmpshm); | |
448 | g_free(tmpshm); | |
449 | tmpshm = NULL; | |
450 | } | |
451 | ||
452 | if (tmpserver) { | |
453 | g_unlink(tmpserver); | |
454 | g_free(tmpserver); | |
455 | tmpserver = NULL; | |
456 | } | |
457 | ||
458 | if (tmpdir) { | |
459 | g_rmdir(tmpdir); | |
460 | tmpdir = NULL; | |
461 | } | |
462 | } | |
463 | ||
464 | static void abrt_handler(void *data) | |
465 | { | |
466 | cleanup(); | |
467 | } | |
468 | ||
469 | static gchar *mktempshm(int size, int *fd) | |
470 | { | |
471 | while (true) { | |
472 | gchar *name; | |
473 | ||
474 | name = g_strdup_printf("/qtest-%u-%u", getpid(), g_random_int()); | |
475 | *fd = shm_open(name, O_CREAT|O_RDWR|O_EXCL, | |
476 | S_IRWXU|S_IRWXG|S_IRWXO); | |
477 | if (*fd > 0) { | |
478 | g_assert(ftruncate(*fd, size) == 0); | |
479 | return name; | |
480 | } | |
481 | ||
482 | g_free(name); | |
483 | ||
484 | if (errno != EEXIST) { | |
485 | perror("shm_open"); | |
486 | return NULL; | |
487 | } | |
488 | } | |
bbfc2efe AF |
489 | } |
490 | ||
491 | int main(int argc, char **argv) | |
492 | { | |
bbfc2efe | 493 | int ret, fd; |
ddef6a0d MAL |
494 | gchar dir[] = "/tmp/ivshmem-test.XXXXXX"; |
495 | ||
496 | #if !GLIB_CHECK_VERSION(2, 31, 0) | |
497 | if (!g_thread_supported()) { | |
498 | g_thread_init(NULL); | |
499 | } | |
500 | #endif | |
bbfc2efe AF |
501 | |
502 | g_test_init(&argc, &argv, NULL); | |
bbfc2efe | 503 | |
ddef6a0d MAL |
504 | qtest_add_abrt_handler(abrt_handler, NULL); |
505 | /* shm */ | |
506 | tmpshm = mktempshm(TMPSHMSIZE, &fd); | |
507 | if (!tmpshm) { | |
508 | return 0; | |
509 | } | |
510 | tmpshmem = mmap(0, TMPSHMSIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); | |
511 | g_assert(tmpshmem != MAP_FAILED); | |
512 | /* server */ | |
513 | if (mkdtemp(dir) == NULL) { | |
514 | g_error("mkdtemp: %s", g_strerror(errno)); | |
515 | } | |
516 | tmpdir = dir; | |
517 | tmpserver = g_strconcat(tmpdir, "/server", NULL); | |
bbfc2efe | 518 | |
ddef6a0d | 519 | qtest_add_func("/ivshmem/single", test_ivshmem_single); |
ddef6a0d | 520 | qtest_add_func("/ivshmem/hotplug", test_ivshmem_hotplug); |
d9453c93 | 521 | qtest_add_func("/ivshmem/memdev", test_ivshmem_memdev); |
2048a2a4 MAL |
522 | if (g_test_slow()) { |
523 | qtest_add_func("/ivshmem/pair", test_ivshmem_pair); | |
00ffc3c1 MAL |
524 | qtest_add_func("/ivshmem/server-msi", test_ivshmem_server_msi); |
525 | qtest_add_func("/ivshmem/server-irq", test_ivshmem_server_irq); | |
2048a2a4 | 526 | } |
bbfc2efe AF |
527 | |
528 | ret = g_test_run(); | |
529 | ||
ddef6a0d | 530 | cleanup(); |
bbfc2efe AF |
531 | |
532 | return ret; | |
533 | } |