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Commit | Line | Data |
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bbfc2efe AF |
1 | /* |
2 | * QTest testcase for ivshmem | |
3 | * | |
4 | * Copyright (c) 2014 SUSE LINUX Products GmbH | |
ddef6a0d | 5 | * Copyright (c) 2015 Red Hat, Inc. |
bbfc2efe AF |
6 | * |
7 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
8 | * See the COPYING file in the top-level directory. | |
9 | */ | |
10 | ||
681c28a3 | 11 | #include "qemu/osdep.h" |
ddef6a0d | 12 | #include <glib/gstdio.h> |
ddef6a0d | 13 | #include "contrib/ivshmem-server/ivshmem-server.h" |
d69487d5 | 14 | #include "libqos/libqos-pc.h" |
2bf25e07 | 15 | #include "libqos/libqos-spapr.h" |
bbfc2efe | 16 | #include "libqtest.h" |
ddef6a0d | 17 | #include "qemu-common.h" |
bbfc2efe | 18 | |
ddef6a0d MAL |
19 | #define TMPSHMSIZE (1 << 20) |
20 | static char *tmpshm; | |
21 | static void *tmpshmem; | |
22 | static char *tmpdir; | |
23 | static char *tmpserver; | |
bbfc2efe | 24 | |
ddef6a0d | 25 | static void save_fn(QPCIDevice *dev, int devfn, void *data) |
bbfc2efe | 26 | { |
ddef6a0d MAL |
27 | QPCIDevice **pdev = (QPCIDevice **) data; |
28 | ||
29 | *pdev = dev; | |
30 | } | |
31 | ||
1760048a | 32 | static QPCIDevice *get_device(QPCIBus *pcibus) |
ddef6a0d MAL |
33 | { |
34 | QPCIDevice *dev; | |
ddef6a0d | 35 | |
16130947 | 36 | dev = NULL; |
ddef6a0d MAL |
37 | qpci_device_foreach(pcibus, 0x1af4, 0x1110, save_fn, &dev); |
38 | g_assert(dev != NULL); | |
39 | ||
40 | return dev; | |
41 | } | |
42 | ||
43 | typedef struct _IVState { | |
d69487d5 | 44 | QOSState *qs; |
b4ba67d9 | 45 | QPCIBar reg_bar, mem_bar; |
ddef6a0d MAL |
46 | QPCIDevice *dev; |
47 | } IVState; | |
48 | ||
49 | enum Reg { | |
50 | INTRMASK = 0, | |
51 | INTRSTATUS = 4, | |
52 | IVPOSITION = 8, | |
53 | DOORBELL = 12, | |
54 | }; | |
55 | ||
56 | static const char* reg2str(enum Reg reg) { | |
57 | switch (reg) { | |
58 | case INTRMASK: | |
59 | return "IntrMask"; | |
60 | case INTRSTATUS: | |
61 | return "IntrStatus"; | |
62 | case IVPOSITION: | |
63 | return "IVPosition"; | |
64 | case DOORBELL: | |
65 | return "DoorBell"; | |
66 | default: | |
67 | return NULL; | |
68 | } | |
69 | } | |
70 | ||
71 | static inline unsigned in_reg(IVState *s, enum Reg reg) | |
72 | { | |
73 | const char *name = reg2str(reg); | |
74 | QTestState *qtest = global_qtest; | |
75 | unsigned res; | |
76 | ||
d69487d5 | 77 | global_qtest = s->qs->qts; |
b4ba67d9 | 78 | res = qpci_io_readl(s->dev, s->reg_bar, reg); |
ddef6a0d MAL |
79 | g_test_message("*%s -> %x\n", name, res); |
80 | global_qtest = qtest; | |
81 | ||
82 | return res; | |
83 | } | |
84 | ||
85 | static inline void out_reg(IVState *s, enum Reg reg, unsigned v) | |
86 | { | |
87 | const char *name = reg2str(reg); | |
88 | QTestState *qtest = global_qtest; | |
89 | ||
d69487d5 | 90 | global_qtest = s->qs->qts; |
ddef6a0d | 91 | g_test_message("%x -> *%s\n", v, name); |
b4ba67d9 | 92 | qpci_io_writel(s->dev, s->reg_bar, reg, v); |
ddef6a0d MAL |
93 | global_qtest = qtest; |
94 | } | |
95 | ||
204e54b8 DG |
96 | static inline void read_mem(IVState *s, uint64_t off, void *buf, size_t len) |
97 | { | |
98 | QTestState *qtest = global_qtest; | |
99 | ||
d69487d5 | 100 | global_qtest = s->qs->qts; |
b4ba67d9 | 101 | qpci_memread(s->dev, s->mem_bar, off, buf, len); |
204e54b8 DG |
102 | global_qtest = qtest; |
103 | } | |
104 | ||
105 | static inline void write_mem(IVState *s, uint64_t off, | |
106 | const void *buf, size_t len) | |
107 | { | |
108 | QTestState *qtest = global_qtest; | |
109 | ||
d69487d5 | 110 | global_qtest = s->qs->qts; |
b4ba67d9 | 111 | qpci_memwrite(s->dev, s->mem_bar, off, buf, len); |
204e54b8 DG |
112 | global_qtest = qtest; |
113 | } | |
114 | ||
1760048a MAL |
115 | static void cleanup_vm(IVState *s) |
116 | { | |
117 | g_free(s->dev); | |
d69487d5 | 118 | qtest_shutdown(s->qs); |
1760048a MAL |
119 | } |
120 | ||
ddef6a0d MAL |
121 | static void setup_vm_cmd(IVState *s, const char *cmd, bool msix) |
122 | { | |
123 | uint64_t barsize; | |
d69487d5 | 124 | const char *arch = qtest_get_arch(); |
ddef6a0d | 125 | |
d69487d5 LV |
126 | if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { |
127 | s->qs = qtest_pc_boot(cmd); | |
2bf25e07 LV |
128 | } else if (strcmp(arch, "ppc64") == 0) { |
129 | s->qs = qtest_spapr_boot(cmd); | |
d69487d5 | 130 | } else { |
2bf25e07 | 131 | g_printerr("ivshmem-test tests are only available on x86 or ppc64\n"); |
d69487d5 LV |
132 | exit(EXIT_FAILURE); |
133 | } | |
134 | s->dev = get_device(s->qs->pcibus); | |
ddef6a0d | 135 | |
b4ba67d9 | 136 | s->reg_bar = qpci_iomap(s->dev, 0, &barsize); |
99826172 | 137 | g_assert_cmpuint(barsize, ==, 256); |
ddef6a0d MAL |
138 | |
139 | if (msix) { | |
140 | qpci_msix_enable(s->dev); | |
141 | } | |
142 | ||
b4ba67d9 | 143 | s->mem_bar = qpci_iomap(s->dev, 2, &barsize); |
99826172 | 144 | g_assert_cmpuint(barsize, ==, TMPSHMSIZE); |
ddef6a0d MAL |
145 | |
146 | qpci_device_enable(s->dev); | |
147 | } | |
148 | ||
149 | static void setup_vm(IVState *s) | |
150 | { | |
5400c02b MA |
151 | char *cmd = g_strdup_printf("-object memory-backend-file" |
152 | ",id=mb1,size=1M,share,mem-path=/dev/shm%s" | |
153 | " -device ivshmem-plain,memdev=mb1", tmpshm); | |
ddef6a0d MAL |
154 | |
155 | setup_vm_cmd(s, cmd, false); | |
156 | ||
157 | g_free(cmd); | |
158 | } | |
159 | ||
160 | static void test_ivshmem_single(void) | |
161 | { | |
162 | IVState state, *s; | |
163 | uint32_t data[1024]; | |
164 | int i; | |
165 | ||
166 | setup_vm(&state); | |
167 | s = &state; | |
168 | ||
4958fe5d MA |
169 | /* initial state of readable registers */ |
170 | g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0); | |
171 | g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0); | |
172 | g_assert_cmpuint(in_reg(s, IVPOSITION), ==, 0); | |
ddef6a0d | 173 | |
4958fe5d | 174 | /* trigger interrupt via registers */ |
ddef6a0d MAL |
175 | out_reg(s, INTRMASK, 0xffffffff); |
176 | g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0xffffffff); | |
177 | out_reg(s, INTRSTATUS, 1); | |
4958fe5d | 178 | /* check interrupt status */ |
ddef6a0d | 179 | g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 1); |
4958fe5d MA |
180 | /* reading clears */ |
181 | g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0); | |
182 | /* TODO intercept actual interrupt (needs qtest work) */ | |
ddef6a0d | 183 | |
4958fe5d | 184 | /* invalid register access */ |
ddef6a0d | 185 | out_reg(s, IVPOSITION, 1); |
4958fe5d MA |
186 | in_reg(s, DOORBELL); |
187 | ||
188 | /* ring the (non-functional) doorbell */ | |
ddef6a0d MAL |
189 | out_reg(s, DOORBELL, 8 << 16); |
190 | ||
4958fe5d | 191 | /* write shared memory */ |
ddef6a0d MAL |
192 | for (i = 0; i < G_N_ELEMENTS(data); i++) { |
193 | data[i] = i; | |
194 | } | |
204e54b8 | 195 | write_mem(s, 0, data, sizeof(data)); |
ddef6a0d | 196 | |
4958fe5d | 197 | /* verify write */ |
ddef6a0d MAL |
198 | for (i = 0; i < G_N_ELEMENTS(data); i++) { |
199 | g_assert_cmpuint(((uint32_t *)tmpshmem)[i], ==, i); | |
200 | } | |
201 | ||
4958fe5d | 202 | /* read it back and verify read */ |
ddef6a0d | 203 | memset(data, 0, sizeof(data)); |
204e54b8 | 204 | read_mem(s, 0, data, sizeof(data)); |
ddef6a0d MAL |
205 | for (i = 0; i < G_N_ELEMENTS(data); i++) { |
206 | g_assert_cmpuint(data[i], ==, i); | |
207 | } | |
208 | ||
1760048a | 209 | cleanup_vm(s); |
ddef6a0d MAL |
210 | } |
211 | ||
212 | static void test_ivshmem_pair(void) | |
213 | { | |
214 | IVState state1, state2, *s1, *s2; | |
215 | char *data; | |
216 | int i; | |
217 | ||
218 | setup_vm(&state1); | |
219 | s1 = &state1; | |
220 | setup_vm(&state2); | |
221 | s2 = &state2; | |
222 | ||
223 | data = g_malloc0(TMPSHMSIZE); | |
224 | ||
225 | /* host write, guest 1 & 2 read */ | |
226 | memset(tmpshmem, 0x42, TMPSHMSIZE); | |
204e54b8 | 227 | read_mem(s1, 0, data, TMPSHMSIZE); |
ddef6a0d MAL |
228 | for (i = 0; i < TMPSHMSIZE; i++) { |
229 | g_assert_cmpuint(data[i], ==, 0x42); | |
230 | } | |
204e54b8 | 231 | read_mem(s2, 0, data, TMPSHMSIZE); |
ddef6a0d MAL |
232 | for (i = 0; i < TMPSHMSIZE; i++) { |
233 | g_assert_cmpuint(data[i], ==, 0x42); | |
234 | } | |
235 | ||
236 | /* guest 1 write, guest 2 read */ | |
237 | memset(data, 0x43, TMPSHMSIZE); | |
204e54b8 | 238 | write_mem(s1, 0, data, TMPSHMSIZE); |
ddef6a0d | 239 | memset(data, 0, TMPSHMSIZE); |
204e54b8 | 240 | read_mem(s2, 0, data, TMPSHMSIZE); |
ddef6a0d MAL |
241 | for (i = 0; i < TMPSHMSIZE; i++) { |
242 | g_assert_cmpuint(data[i], ==, 0x43); | |
243 | } | |
244 | ||
245 | /* guest 2 write, guest 1 read */ | |
246 | memset(data, 0x44, TMPSHMSIZE); | |
204e54b8 | 247 | write_mem(s2, 0, data, TMPSHMSIZE); |
ddef6a0d | 248 | memset(data, 0, TMPSHMSIZE); |
204e54b8 | 249 | read_mem(s1, 0, data, TMPSHMSIZE); |
ddef6a0d MAL |
250 | for (i = 0; i < TMPSHMSIZE; i++) { |
251 | g_assert_cmpuint(data[i], ==, 0x44); | |
252 | } | |
253 | ||
1760048a MAL |
254 | cleanup_vm(s1); |
255 | cleanup_vm(s2); | |
ddef6a0d MAL |
256 | g_free(data); |
257 | } | |
258 | ||
259 | typedef struct ServerThread { | |
260 | GThread *thread; | |
261 | IvshmemServer *server; | |
262 | int pipe[2]; /* to handle quit */ | |
263 | } ServerThread; | |
264 | ||
265 | static void *server_thread(void *data) | |
266 | { | |
267 | ServerThread *t = data; | |
268 | IvshmemServer *server = t->server; | |
269 | ||
270 | while (true) { | |
271 | fd_set fds; | |
272 | int maxfd, ret; | |
273 | ||
274 | FD_ZERO(&fds); | |
275 | FD_SET(t->pipe[0], &fds); | |
276 | maxfd = t->pipe[0] + 1; | |
277 | ||
278 | ivshmem_server_get_fds(server, &fds, &maxfd); | |
279 | ||
280 | ret = select(maxfd, &fds, NULL, NULL, NULL); | |
281 | ||
282 | if (ret < 0) { | |
283 | if (errno == EINTR) { | |
284 | continue; | |
285 | } | |
286 | ||
287 | g_critical("select error: %s\n", strerror(errno)); | |
288 | break; | |
289 | } | |
290 | if (ret == 0) { | |
291 | continue; | |
292 | } | |
293 | ||
294 | if (FD_ISSET(t->pipe[0], &fds)) { | |
295 | break; | |
296 | } | |
297 | ||
298 | if (ivshmem_server_handle_fds(server, &fds, maxfd) < 0) { | |
299 | g_critical("ivshmem_server_handle_fds() failed\n"); | |
300 | break; | |
301 | } | |
302 | } | |
303 | ||
304 | return NULL; | |
305 | } | |
306 | ||
00ffc3c1 | 307 | static void setup_vm_with_server(IVState *s, int nvectors, bool msi) |
ddef6a0d MAL |
308 | { |
309 | char *cmd = g_strdup_printf("-chardev socket,id=chr0,path=%s,nowait " | |
5400c02b MA |
310 | "-device ivshmem%s,chardev=chr0,vectors=%d", |
311 | tmpserver, | |
312 | msi ? "-doorbell" : ",size=1M,msi=off", | |
313 | nvectors); | |
ddef6a0d | 314 | |
00ffc3c1 | 315 | setup_vm_cmd(s, cmd, msi); |
ddef6a0d MAL |
316 | |
317 | g_free(cmd); | |
318 | } | |
319 | ||
00ffc3c1 | 320 | static void test_ivshmem_server(bool msi) |
ddef6a0d MAL |
321 | { |
322 | IVState state1, state2, *s1, *s2; | |
323 | ServerThread thread; | |
324 | IvshmemServer server; | |
325 | int ret, vm1, vm2; | |
326 | int nvectors = 2; | |
327 | guint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND; | |
328 | ||
3625c739 | 329 | ret = ivshmem_server_init(&server, tmpserver, tmpshm, true, |
ddef6a0d MAL |
330 | TMPSHMSIZE, nvectors, |
331 | g_test_verbose()); | |
332 | g_assert_cmpint(ret, ==, 0); | |
333 | ||
334 | ret = ivshmem_server_start(&server); | |
335 | g_assert_cmpint(ret, ==, 0); | |
336 | ||
ddef6a0d MAL |
337 | thread.server = &server; |
338 | ret = pipe(thread.pipe); | |
339 | g_assert_cmpint(ret, ==, 0); | |
340 | thread.thread = g_thread_new("ivshmem-server", server_thread, &thread); | |
341 | g_assert(thread.thread != NULL); | |
342 | ||
3a55fc0f MA |
343 | setup_vm_with_server(&state1, nvectors, msi); |
344 | s1 = &state1; | |
345 | setup_vm_with_server(&state2, nvectors, msi); | |
346 | s2 = &state2; | |
ddef6a0d MAL |
347 | |
348 | /* check got different VM ids */ | |
349 | vm1 = in_reg(s1, IVPOSITION); | |
350 | vm2 = in_reg(s2, IVPOSITION); | |
3a55fc0f MA |
351 | g_assert_cmpint(vm1, >=, 0); |
352 | g_assert_cmpint(vm2, >=, 0); | |
353 | g_assert_cmpint(vm1, !=, vm2); | |
ddef6a0d | 354 | |
41b65e5e | 355 | /* check number of MSI-X vectors */ |
d69487d5 | 356 | global_qtest = s1->qs->qts; |
00ffc3c1 MAL |
357 | if (msi) { |
358 | ret = qpci_msix_table_size(s1->dev); | |
359 | g_assert_cmpuint(ret, ==, nvectors); | |
360 | } | |
ddef6a0d | 361 | |
41b65e5e MA |
362 | /* TODO test behavior before MSI-X is enabled */ |
363 | ||
364 | /* ping vm2 -> vm1 on vector 0 */ | |
00ffc3c1 MAL |
365 | if (msi) { |
366 | ret = qpci_msix_pending(s1->dev, 0); | |
367 | g_assert_cmpuint(ret, ==, 0); | |
368 | } else { | |
41b65e5e | 369 | g_assert_cmpuint(in_reg(s1, INTRSTATUS), ==, 0); |
00ffc3c1 | 370 | } |
ddef6a0d MAL |
371 | out_reg(s2, DOORBELL, vm1 << 16); |
372 | do { | |
373 | g_usleep(10000); | |
00ffc3c1 | 374 | ret = msi ? qpci_msix_pending(s1->dev, 0) : in_reg(s1, INTRSTATUS); |
ddef6a0d MAL |
375 | } while (ret == 0 && g_get_monotonic_time() < end_time); |
376 | g_assert_cmpuint(ret, !=, 0); | |
377 | ||
41b65e5e | 378 | /* ping vm1 -> vm2 on vector 1 */ |
d69487d5 | 379 | global_qtest = s2->qs->qts; |
00ffc3c1 | 380 | if (msi) { |
41b65e5e | 381 | ret = qpci_msix_pending(s2->dev, 1); |
00ffc3c1 MAL |
382 | g_assert_cmpuint(ret, ==, 0); |
383 | } else { | |
41b65e5e | 384 | g_assert_cmpuint(in_reg(s2, INTRSTATUS), ==, 0); |
00ffc3c1 | 385 | } |
41b65e5e | 386 | out_reg(s1, DOORBELL, vm2 << 16 | 1); |
ddef6a0d MAL |
387 | do { |
388 | g_usleep(10000); | |
41b65e5e | 389 | ret = msi ? qpci_msix_pending(s2->dev, 1) : in_reg(s2, INTRSTATUS); |
ddef6a0d MAL |
390 | } while (ret == 0 && g_get_monotonic_time() < end_time); |
391 | g_assert_cmpuint(ret, !=, 0); | |
392 | ||
1760048a MAL |
393 | cleanup_vm(s2); |
394 | cleanup_vm(s1); | |
ddef6a0d MAL |
395 | |
396 | if (qemu_write_full(thread.pipe[1], "q", 1) != 1) { | |
397 | g_error("qemu_write_full: %s", g_strerror(errno)); | |
398 | } | |
399 | ||
400 | g_thread_join(thread.thread); | |
401 | ||
402 | ivshmem_server_close(&server); | |
403 | close(thread.pipe[1]); | |
404 | close(thread.pipe[0]); | |
405 | } | |
406 | ||
00ffc3c1 MAL |
407 | static void test_ivshmem_server_msi(void) |
408 | { | |
409 | test_ivshmem_server(true); | |
410 | } | |
411 | ||
412 | static void test_ivshmem_server_irq(void) | |
413 | { | |
414 | test_ivshmem_server(false); | |
415 | } | |
416 | ||
ddef6a0d MAL |
417 | #define PCI_SLOT_HP 0x06 |
418 | ||
419 | static void test_ivshmem_hotplug(void) | |
420 | { | |
2bf25e07 | 421 | const char *arch = qtest_get_arch(); |
ddef6a0d MAL |
422 | gchar *opts; |
423 | ||
424 | qtest_start(""); | |
425 | ||
426 | opts = g_strdup_printf("'shm': '%s', 'size': '1M'", tmpshm); | |
427 | ||
428 | qpci_plug_device_test("ivshmem", "iv1", PCI_SLOT_HP, opts); | |
2bf25e07 LV |
429 | if (strcmp(arch, "ppc64") != 0) { |
430 | qpci_unplug_acpi_device_test("iv1", PCI_SLOT_HP); | |
431 | } | |
ddef6a0d MAL |
432 | |
433 | qtest_end(); | |
434 | g_free(opts); | |
435 | } | |
436 | ||
d9453c93 MAL |
437 | static void test_ivshmem_memdev(void) |
438 | { | |
439 | IVState state; | |
440 | ||
441 | /* just for the sake of checking memory-backend property */ | |
442 | setup_vm_cmd(&state, "-object memory-backend-ram,size=1M,id=mb1" | |
5400c02b | 443 | " -device ivshmem-plain,memdev=mb1", false); |
d9453c93 | 444 | |
1760048a | 445 | cleanup_vm(&state); |
d9453c93 MAL |
446 | } |
447 | ||
ddef6a0d MAL |
448 | static void cleanup(void) |
449 | { | |
450 | if (tmpshmem) { | |
451 | munmap(tmpshmem, TMPSHMSIZE); | |
452 | tmpshmem = NULL; | |
453 | } | |
454 | ||
455 | if (tmpshm) { | |
456 | shm_unlink(tmpshm); | |
457 | g_free(tmpshm); | |
458 | tmpshm = NULL; | |
459 | } | |
460 | ||
461 | if (tmpserver) { | |
462 | g_unlink(tmpserver); | |
463 | g_free(tmpserver); | |
464 | tmpserver = NULL; | |
465 | } | |
466 | ||
467 | if (tmpdir) { | |
468 | g_rmdir(tmpdir); | |
469 | tmpdir = NULL; | |
470 | } | |
471 | } | |
472 | ||
473 | static void abrt_handler(void *data) | |
474 | { | |
475 | cleanup(); | |
476 | } | |
477 | ||
478 | static gchar *mktempshm(int size, int *fd) | |
479 | { | |
480 | while (true) { | |
481 | gchar *name; | |
482 | ||
483 | name = g_strdup_printf("/qtest-%u-%u", getpid(), g_random_int()); | |
484 | *fd = shm_open(name, O_CREAT|O_RDWR|O_EXCL, | |
485 | S_IRWXU|S_IRWXG|S_IRWXO); | |
486 | if (*fd > 0) { | |
487 | g_assert(ftruncate(*fd, size) == 0); | |
488 | return name; | |
489 | } | |
490 | ||
491 | g_free(name); | |
492 | ||
493 | if (errno != EEXIST) { | |
494 | perror("shm_open"); | |
495 | return NULL; | |
496 | } | |
497 | } | |
bbfc2efe AF |
498 | } |
499 | ||
500 | int main(int argc, char **argv) | |
501 | { | |
bbfc2efe | 502 | int ret, fd; |
2bf25e07 | 503 | const char *arch = qtest_get_arch(); |
ddef6a0d MAL |
504 | gchar dir[] = "/tmp/ivshmem-test.XXXXXX"; |
505 | ||
506 | #if !GLIB_CHECK_VERSION(2, 31, 0) | |
507 | if (!g_thread_supported()) { | |
508 | g_thread_init(NULL); | |
509 | } | |
510 | #endif | |
bbfc2efe AF |
511 | |
512 | g_test_init(&argc, &argv, NULL); | |
bbfc2efe | 513 | |
ddef6a0d MAL |
514 | qtest_add_abrt_handler(abrt_handler, NULL); |
515 | /* shm */ | |
516 | tmpshm = mktempshm(TMPSHMSIZE, &fd); | |
517 | if (!tmpshm) { | |
518 | return 0; | |
519 | } | |
520 | tmpshmem = mmap(0, TMPSHMSIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0); | |
521 | g_assert(tmpshmem != MAP_FAILED); | |
522 | /* server */ | |
523 | if (mkdtemp(dir) == NULL) { | |
524 | g_error("mkdtemp: %s", g_strerror(errno)); | |
525 | } | |
526 | tmpdir = dir; | |
527 | tmpserver = g_strconcat(tmpdir, "/server", NULL); | |
bbfc2efe | 528 | |
ddef6a0d | 529 | qtest_add_func("/ivshmem/single", test_ivshmem_single); |
ddef6a0d | 530 | qtest_add_func("/ivshmem/hotplug", test_ivshmem_hotplug); |
d9453c93 | 531 | qtest_add_func("/ivshmem/memdev", test_ivshmem_memdev); |
2048a2a4 MAL |
532 | if (g_test_slow()) { |
533 | qtest_add_func("/ivshmem/pair", test_ivshmem_pair); | |
2bf25e07 LV |
534 | if (strcmp(arch, "ppc64") != 0) { |
535 | qtest_add_func("/ivshmem/server-msi", test_ivshmem_server_msi); | |
536 | qtest_add_func("/ivshmem/server-irq", test_ivshmem_server_irq); | |
537 | } | |
2048a2a4 | 538 | } |
bbfc2efe AF |
539 | |
540 | ret = g_test_run(); | |
541 | ||
ddef6a0d | 542 | cleanup(); |
bbfc2efe AF |
543 | |
544 | return ret; | |
545 | } |