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bbfc2efe
AF
1/*
2 * QTest testcase for ivshmem
3 *
4 * Copyright (c) 2014 SUSE LINUX Products GmbH
ddef6a0d 5 * Copyright (c) 2015 Red Hat, Inc.
bbfc2efe
AF
6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
9 */
10
681c28a3 11#include "qemu/osdep.h"
ddef6a0d 12#include <glib/gstdio.h>
ddef6a0d 13#include "contrib/ivshmem-server/ivshmem-server.h"
d69487d5 14#include "libqos/libqos-pc.h"
2bf25e07 15#include "libqos/libqos-spapr.h"
bbfc2efe 16#include "libqtest.h"
ddef6a0d 17#include "qemu-common.h"
bbfc2efe 18
ddef6a0d
MAL
19#define TMPSHMSIZE (1 << 20)
20static char *tmpshm;
21static void *tmpshmem;
22static char *tmpdir;
23static char *tmpserver;
bbfc2efe 24
ddef6a0d 25static void save_fn(QPCIDevice *dev, int devfn, void *data)
bbfc2efe 26{
ddef6a0d
MAL
27 QPCIDevice **pdev = (QPCIDevice **) data;
28
29 *pdev = dev;
30}
31
1760048a 32static QPCIDevice *get_device(QPCIBus *pcibus)
ddef6a0d
MAL
33{
34 QPCIDevice *dev;
ddef6a0d 35
16130947 36 dev = NULL;
ddef6a0d
MAL
37 qpci_device_foreach(pcibus, 0x1af4, 0x1110, save_fn, &dev);
38 g_assert(dev != NULL);
39
40 return dev;
41}
42
43typedef struct _IVState {
d69487d5 44 QOSState *qs;
b4ba67d9 45 QPCIBar reg_bar, mem_bar;
ddef6a0d
MAL
46 QPCIDevice *dev;
47} IVState;
48
49enum Reg {
50 INTRMASK = 0,
51 INTRSTATUS = 4,
52 IVPOSITION = 8,
53 DOORBELL = 12,
54};
55
56static const char* reg2str(enum Reg reg) {
57 switch (reg) {
58 case INTRMASK:
59 return "IntrMask";
60 case INTRSTATUS:
61 return "IntrStatus";
62 case IVPOSITION:
63 return "IVPosition";
64 case DOORBELL:
65 return "DoorBell";
66 default:
67 return NULL;
68 }
69}
70
71static inline unsigned in_reg(IVState *s, enum Reg reg)
72{
73 const char *name = reg2str(reg);
74 QTestState *qtest = global_qtest;
75 unsigned res;
76
d69487d5 77 global_qtest = s->qs->qts;
b4ba67d9 78 res = qpci_io_readl(s->dev, s->reg_bar, reg);
ddef6a0d
MAL
79 g_test_message("*%s -> %x\n", name, res);
80 global_qtest = qtest;
81
82 return res;
83}
84
85static inline void out_reg(IVState *s, enum Reg reg, unsigned v)
86{
87 const char *name = reg2str(reg);
88 QTestState *qtest = global_qtest;
89
d69487d5 90 global_qtest = s->qs->qts;
ddef6a0d 91 g_test_message("%x -> *%s\n", v, name);
b4ba67d9 92 qpci_io_writel(s->dev, s->reg_bar, reg, v);
ddef6a0d
MAL
93 global_qtest = qtest;
94}
95
204e54b8
DG
96static inline void read_mem(IVState *s, uint64_t off, void *buf, size_t len)
97{
98 QTestState *qtest = global_qtest;
99
d69487d5 100 global_qtest = s->qs->qts;
b4ba67d9 101 qpci_memread(s->dev, s->mem_bar, off, buf, len);
204e54b8
DG
102 global_qtest = qtest;
103}
104
105static inline void write_mem(IVState *s, uint64_t off,
106 const void *buf, size_t len)
107{
108 QTestState *qtest = global_qtest;
109
d69487d5 110 global_qtest = s->qs->qts;
b4ba67d9 111 qpci_memwrite(s->dev, s->mem_bar, off, buf, len);
204e54b8
DG
112 global_qtest = qtest;
113}
114
1760048a
MAL
115static void cleanup_vm(IVState *s)
116{
117 g_free(s->dev);
d69487d5 118 qtest_shutdown(s->qs);
1760048a
MAL
119}
120
ddef6a0d
MAL
121static void setup_vm_cmd(IVState *s, const char *cmd, bool msix)
122{
123 uint64_t barsize;
d69487d5 124 const char *arch = qtest_get_arch();
ddef6a0d 125
d69487d5
LV
126 if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
127 s->qs = qtest_pc_boot(cmd);
2bf25e07
LV
128 } else if (strcmp(arch, "ppc64") == 0) {
129 s->qs = qtest_spapr_boot(cmd);
d69487d5 130 } else {
2bf25e07 131 g_printerr("ivshmem-test tests are only available on x86 or ppc64\n");
d69487d5
LV
132 exit(EXIT_FAILURE);
133 }
3d95fb97 134 global_qtest = s->qs->qts;
d69487d5 135 s->dev = get_device(s->qs->pcibus);
ddef6a0d 136
b4ba67d9 137 s->reg_bar = qpci_iomap(s->dev, 0, &barsize);
99826172 138 g_assert_cmpuint(barsize, ==, 256);
ddef6a0d
MAL
139
140 if (msix) {
141 qpci_msix_enable(s->dev);
142 }
143
b4ba67d9 144 s->mem_bar = qpci_iomap(s->dev, 2, &barsize);
99826172 145 g_assert_cmpuint(barsize, ==, TMPSHMSIZE);
ddef6a0d
MAL
146
147 qpci_device_enable(s->dev);
148}
149
150static void setup_vm(IVState *s)
151{
5400c02b
MA
152 char *cmd = g_strdup_printf("-object memory-backend-file"
153 ",id=mb1,size=1M,share,mem-path=/dev/shm%s"
154 " -device ivshmem-plain,memdev=mb1", tmpshm);
ddef6a0d
MAL
155
156 setup_vm_cmd(s, cmd, false);
157
158 g_free(cmd);
159}
160
161static void test_ivshmem_single(void)
162{
163 IVState state, *s;
164 uint32_t data[1024];
165 int i;
166
167 setup_vm(&state);
168 s = &state;
169
4958fe5d
MA
170 /* initial state of readable registers */
171 g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0);
172 g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0);
173 g_assert_cmpuint(in_reg(s, IVPOSITION), ==, 0);
ddef6a0d 174
4958fe5d 175 /* trigger interrupt via registers */
ddef6a0d
MAL
176 out_reg(s, INTRMASK, 0xffffffff);
177 g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0xffffffff);
178 out_reg(s, INTRSTATUS, 1);
4958fe5d 179 /* check interrupt status */
ddef6a0d 180 g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 1);
4958fe5d
MA
181 /* reading clears */
182 g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0);
183 /* TODO intercept actual interrupt (needs qtest work) */
ddef6a0d 184
4958fe5d 185 /* invalid register access */
ddef6a0d 186 out_reg(s, IVPOSITION, 1);
4958fe5d
MA
187 in_reg(s, DOORBELL);
188
189 /* ring the (non-functional) doorbell */
ddef6a0d
MAL
190 out_reg(s, DOORBELL, 8 << 16);
191
4958fe5d 192 /* write shared memory */
ddef6a0d
MAL
193 for (i = 0; i < G_N_ELEMENTS(data); i++) {
194 data[i] = i;
195 }
204e54b8 196 write_mem(s, 0, data, sizeof(data));
ddef6a0d 197
4958fe5d 198 /* verify write */
ddef6a0d
MAL
199 for (i = 0; i < G_N_ELEMENTS(data); i++) {
200 g_assert_cmpuint(((uint32_t *)tmpshmem)[i], ==, i);
201 }
202
4958fe5d 203 /* read it back and verify read */
ddef6a0d 204 memset(data, 0, sizeof(data));
204e54b8 205 read_mem(s, 0, data, sizeof(data));
ddef6a0d
MAL
206 for (i = 0; i < G_N_ELEMENTS(data); i++) {
207 g_assert_cmpuint(data[i], ==, i);
208 }
209
1760048a 210 cleanup_vm(s);
ddef6a0d
MAL
211}
212
213static void test_ivshmem_pair(void)
214{
215 IVState state1, state2, *s1, *s2;
216 char *data;
217 int i;
218
219 setup_vm(&state1);
220 s1 = &state1;
221 setup_vm(&state2);
222 s2 = &state2;
223
224 data = g_malloc0(TMPSHMSIZE);
225
226 /* host write, guest 1 & 2 read */
227 memset(tmpshmem, 0x42, TMPSHMSIZE);
204e54b8 228 read_mem(s1, 0, data, TMPSHMSIZE);
ddef6a0d
MAL
229 for (i = 0; i < TMPSHMSIZE; i++) {
230 g_assert_cmpuint(data[i], ==, 0x42);
231 }
204e54b8 232 read_mem(s2, 0, data, TMPSHMSIZE);
ddef6a0d
MAL
233 for (i = 0; i < TMPSHMSIZE; i++) {
234 g_assert_cmpuint(data[i], ==, 0x42);
235 }
236
237 /* guest 1 write, guest 2 read */
238 memset(data, 0x43, TMPSHMSIZE);
204e54b8 239 write_mem(s1, 0, data, TMPSHMSIZE);
ddef6a0d 240 memset(data, 0, TMPSHMSIZE);
204e54b8 241 read_mem(s2, 0, data, TMPSHMSIZE);
ddef6a0d
MAL
242 for (i = 0; i < TMPSHMSIZE; i++) {
243 g_assert_cmpuint(data[i], ==, 0x43);
244 }
245
246 /* guest 2 write, guest 1 read */
247 memset(data, 0x44, TMPSHMSIZE);
204e54b8 248 write_mem(s2, 0, data, TMPSHMSIZE);
ddef6a0d 249 memset(data, 0, TMPSHMSIZE);
204e54b8 250 read_mem(s1, 0, data, TMPSHMSIZE);
ddef6a0d
MAL
251 for (i = 0; i < TMPSHMSIZE; i++) {
252 g_assert_cmpuint(data[i], ==, 0x44);
253 }
254
1760048a
MAL
255 cleanup_vm(s1);
256 cleanup_vm(s2);
ddef6a0d
MAL
257 g_free(data);
258}
259
260typedef struct ServerThread {
261 GThread *thread;
262 IvshmemServer *server;
263 int pipe[2]; /* to handle quit */
264} ServerThread;
265
266static void *server_thread(void *data)
267{
268 ServerThread *t = data;
269 IvshmemServer *server = t->server;
270
271 while (true) {
272 fd_set fds;
273 int maxfd, ret;
274
275 FD_ZERO(&fds);
276 FD_SET(t->pipe[0], &fds);
277 maxfd = t->pipe[0] + 1;
278
279 ivshmem_server_get_fds(server, &fds, &maxfd);
280
281 ret = select(maxfd, &fds, NULL, NULL, NULL);
282
283 if (ret < 0) {
284 if (errno == EINTR) {
285 continue;
286 }
287
288 g_critical("select error: %s\n", strerror(errno));
289 break;
290 }
291 if (ret == 0) {
292 continue;
293 }
294
295 if (FD_ISSET(t->pipe[0], &fds)) {
296 break;
297 }
298
299 if (ivshmem_server_handle_fds(server, &fds, maxfd) < 0) {
300 g_critical("ivshmem_server_handle_fds() failed\n");
301 break;
302 }
303 }
304
305 return NULL;
306}
307
00ffc3c1 308static void setup_vm_with_server(IVState *s, int nvectors, bool msi)
ddef6a0d
MAL
309{
310 char *cmd = g_strdup_printf("-chardev socket,id=chr0,path=%s,nowait "
5400c02b
MA
311 "-device ivshmem%s,chardev=chr0,vectors=%d",
312 tmpserver,
313 msi ? "-doorbell" : ",size=1M,msi=off",
314 nvectors);
ddef6a0d 315
00ffc3c1 316 setup_vm_cmd(s, cmd, msi);
ddef6a0d
MAL
317
318 g_free(cmd);
319}
320
00ffc3c1 321static void test_ivshmem_server(bool msi)
ddef6a0d
MAL
322{
323 IVState state1, state2, *s1, *s2;
324 ServerThread thread;
325 IvshmemServer server;
326 int ret, vm1, vm2;
327 int nvectors = 2;
328 guint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND;
329
3625c739 330 ret = ivshmem_server_init(&server, tmpserver, tmpshm, true,
ddef6a0d
MAL
331 TMPSHMSIZE, nvectors,
332 g_test_verbose());
333 g_assert_cmpint(ret, ==, 0);
334
335 ret = ivshmem_server_start(&server);
336 g_assert_cmpint(ret, ==, 0);
337
ddef6a0d
MAL
338 thread.server = &server;
339 ret = pipe(thread.pipe);
340 g_assert_cmpint(ret, ==, 0);
341 thread.thread = g_thread_new("ivshmem-server", server_thread, &thread);
342 g_assert(thread.thread != NULL);
343
3a55fc0f
MA
344 setup_vm_with_server(&state1, nvectors, msi);
345 s1 = &state1;
346 setup_vm_with_server(&state2, nvectors, msi);
347 s2 = &state2;
ddef6a0d
MAL
348
349 /* check got different VM ids */
350 vm1 = in_reg(s1, IVPOSITION);
351 vm2 = in_reg(s2, IVPOSITION);
3a55fc0f
MA
352 g_assert_cmpint(vm1, >=, 0);
353 g_assert_cmpint(vm2, >=, 0);
354 g_assert_cmpint(vm1, !=, vm2);
ddef6a0d 355
41b65e5e 356 /* check number of MSI-X vectors */
d69487d5 357 global_qtest = s1->qs->qts;
00ffc3c1
MAL
358 if (msi) {
359 ret = qpci_msix_table_size(s1->dev);
360 g_assert_cmpuint(ret, ==, nvectors);
361 }
ddef6a0d 362
41b65e5e
MA
363 /* TODO test behavior before MSI-X is enabled */
364
365 /* ping vm2 -> vm1 on vector 0 */
00ffc3c1
MAL
366 if (msi) {
367 ret = qpci_msix_pending(s1->dev, 0);
368 g_assert_cmpuint(ret, ==, 0);
369 } else {
41b65e5e 370 g_assert_cmpuint(in_reg(s1, INTRSTATUS), ==, 0);
00ffc3c1 371 }
ddef6a0d
MAL
372 out_reg(s2, DOORBELL, vm1 << 16);
373 do {
374 g_usleep(10000);
00ffc3c1 375 ret = msi ? qpci_msix_pending(s1->dev, 0) : in_reg(s1, INTRSTATUS);
ddef6a0d
MAL
376 } while (ret == 0 && g_get_monotonic_time() < end_time);
377 g_assert_cmpuint(ret, !=, 0);
378
41b65e5e 379 /* ping vm1 -> vm2 on vector 1 */
d69487d5 380 global_qtest = s2->qs->qts;
00ffc3c1 381 if (msi) {
41b65e5e 382 ret = qpci_msix_pending(s2->dev, 1);
00ffc3c1
MAL
383 g_assert_cmpuint(ret, ==, 0);
384 } else {
41b65e5e 385 g_assert_cmpuint(in_reg(s2, INTRSTATUS), ==, 0);
00ffc3c1 386 }
41b65e5e 387 out_reg(s1, DOORBELL, vm2 << 16 | 1);
ddef6a0d
MAL
388 do {
389 g_usleep(10000);
41b65e5e 390 ret = msi ? qpci_msix_pending(s2->dev, 1) : in_reg(s2, INTRSTATUS);
ddef6a0d
MAL
391 } while (ret == 0 && g_get_monotonic_time() < end_time);
392 g_assert_cmpuint(ret, !=, 0);
393
1760048a
MAL
394 cleanup_vm(s2);
395 cleanup_vm(s1);
ddef6a0d
MAL
396
397 if (qemu_write_full(thread.pipe[1], "q", 1) != 1) {
398 g_error("qemu_write_full: %s", g_strerror(errno));
399 }
400
401 g_thread_join(thread.thread);
402
403 ivshmem_server_close(&server);
404 close(thread.pipe[1]);
405 close(thread.pipe[0]);
406}
407
00ffc3c1
MAL
408static void test_ivshmem_server_msi(void)
409{
410 test_ivshmem_server(true);
411}
412
413static void test_ivshmem_server_irq(void)
414{
415 test_ivshmem_server(false);
416}
417
ddef6a0d
MAL
418#define PCI_SLOT_HP 0x06
419
420static void test_ivshmem_hotplug(void)
421{
2bf25e07 422 const char *arch = qtest_get_arch();
ddef6a0d
MAL
423 gchar *opts;
424
425 qtest_start("");
426
427 opts = g_strdup_printf("'shm': '%s', 'size': '1M'", tmpshm);
428
429 qpci_plug_device_test("ivshmem", "iv1", PCI_SLOT_HP, opts);
2bf25e07
LV
430 if (strcmp(arch, "ppc64") != 0) {
431 qpci_unplug_acpi_device_test("iv1", PCI_SLOT_HP);
432 }
ddef6a0d
MAL
433
434 qtest_end();
435 g_free(opts);
436}
437
d9453c93
MAL
438static void test_ivshmem_memdev(void)
439{
440 IVState state;
441
442 /* just for the sake of checking memory-backend property */
443 setup_vm_cmd(&state, "-object memory-backend-ram,size=1M,id=mb1"
5400c02b 444 " -device ivshmem-plain,memdev=mb1", false);
d9453c93 445
1760048a 446 cleanup_vm(&state);
d9453c93
MAL
447}
448
ddef6a0d
MAL
449static void cleanup(void)
450{
451 if (tmpshmem) {
452 munmap(tmpshmem, TMPSHMSIZE);
453 tmpshmem = NULL;
454 }
455
456 if (tmpshm) {
457 shm_unlink(tmpshm);
458 g_free(tmpshm);
459 tmpshm = NULL;
460 }
461
462 if (tmpserver) {
463 g_unlink(tmpserver);
464 g_free(tmpserver);
465 tmpserver = NULL;
466 }
467
468 if (tmpdir) {
469 g_rmdir(tmpdir);
470 tmpdir = NULL;
471 }
472}
473
474static void abrt_handler(void *data)
475{
476 cleanup();
477}
478
479static gchar *mktempshm(int size, int *fd)
480{
481 while (true) {
482 gchar *name;
483
484 name = g_strdup_printf("/qtest-%u-%u", getpid(), g_random_int());
485 *fd = shm_open(name, O_CREAT|O_RDWR|O_EXCL,
486 S_IRWXU|S_IRWXG|S_IRWXO);
487 if (*fd > 0) {
488 g_assert(ftruncate(*fd, size) == 0);
489 return name;
490 }
491
492 g_free(name);
493
494 if (errno != EEXIST) {
495 perror("shm_open");
496 return NULL;
497 }
498 }
bbfc2efe
AF
499}
500
501int main(int argc, char **argv)
502{
bbfc2efe 503 int ret, fd;
2bf25e07 504 const char *arch = qtest_get_arch();
ddef6a0d
MAL
505 gchar dir[] = "/tmp/ivshmem-test.XXXXXX";
506
bbfc2efe 507 g_test_init(&argc, &argv, NULL);
bbfc2efe 508
ddef6a0d
MAL
509 qtest_add_abrt_handler(abrt_handler, NULL);
510 /* shm */
511 tmpshm = mktempshm(TMPSHMSIZE, &fd);
512 if (!tmpshm) {
513 return 0;
514 }
515 tmpshmem = mmap(0, TMPSHMSIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
516 g_assert(tmpshmem != MAP_FAILED);
517 /* server */
518 if (mkdtemp(dir) == NULL) {
519 g_error("mkdtemp: %s", g_strerror(errno));
520 }
521 tmpdir = dir;
522 tmpserver = g_strconcat(tmpdir, "/server", NULL);
bbfc2efe 523
ddef6a0d 524 qtest_add_func("/ivshmem/single", test_ivshmem_single);
ddef6a0d 525 qtest_add_func("/ivshmem/hotplug", test_ivshmem_hotplug);
d9453c93 526 qtest_add_func("/ivshmem/memdev", test_ivshmem_memdev);
2048a2a4
MAL
527 if (g_test_slow()) {
528 qtest_add_func("/ivshmem/pair", test_ivshmem_pair);
2bf25e07
LV
529 if (strcmp(arch, "ppc64") != 0) {
530 qtest_add_func("/ivshmem/server-msi", test_ivshmem_server_msi);
531 qtest_add_func("/ivshmem/server-irq", test_ivshmem_server_irq);
532 }
2048a2a4 533 }
bbfc2efe
AF
534
535 ret = g_test_run();
536
ddef6a0d 537 cleanup();
bbfc2efe
AF
538
539 return ret;
540}