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bbfc2efe
AF
1/*
2 * QTest testcase for ivshmem
3 *
4 * Copyright (c) 2014 SUSE LINUX Products GmbH
ddef6a0d 5 * Copyright (c) 2015 Red Hat, Inc.
bbfc2efe
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6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
9 */
10
681c28a3 11#include "qemu/osdep.h"
bbfc2efe 12#include <glib.h>
ddef6a0d 13#include <glib/gstdio.h>
ddef6a0d 14#include <sys/mman.h>
ddef6a0d
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15#include "contrib/ivshmem-server/ivshmem-server.h"
16#include "libqos/pci-pc.h"
bbfc2efe 17#include "libqtest.h"
ddef6a0d 18#include "qemu-common.h"
bbfc2efe 19
ddef6a0d
MAL
20#define TMPSHMSIZE (1 << 20)
21static char *tmpshm;
22static void *tmpshmem;
23static char *tmpdir;
24static char *tmpserver;
bbfc2efe 25
ddef6a0d 26static void save_fn(QPCIDevice *dev, int devfn, void *data)
bbfc2efe 27{
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MAL
28 QPCIDevice **pdev = (QPCIDevice **) data;
29
30 *pdev = dev;
31}
32
1760048a 33static QPCIDevice *get_device(QPCIBus *pcibus)
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MAL
34{
35 QPCIDevice *dev;
ddef6a0d 36
16130947 37 dev = NULL;
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38 qpci_device_foreach(pcibus, 0x1af4, 0x1110, save_fn, &dev);
39 g_assert(dev != NULL);
40
41 return dev;
42}
43
44typedef struct _IVState {
45 QTestState *qtest;
46 void *reg_base, *mem_base;
1760048a 47 QPCIBus *pcibus;
ddef6a0d
MAL
48 QPCIDevice *dev;
49} IVState;
50
51enum Reg {
52 INTRMASK = 0,
53 INTRSTATUS = 4,
54 IVPOSITION = 8,
55 DOORBELL = 12,
56};
57
58static const char* reg2str(enum Reg reg) {
59 switch (reg) {
60 case INTRMASK:
61 return "IntrMask";
62 case INTRSTATUS:
63 return "IntrStatus";
64 case IVPOSITION:
65 return "IVPosition";
66 case DOORBELL:
67 return "DoorBell";
68 default:
69 return NULL;
70 }
71}
72
73static inline unsigned in_reg(IVState *s, enum Reg reg)
74{
75 const char *name = reg2str(reg);
76 QTestState *qtest = global_qtest;
77 unsigned res;
78
79 global_qtest = s->qtest;
80 res = qpci_io_readl(s->dev, s->reg_base + reg);
81 g_test_message("*%s -> %x\n", name, res);
82 global_qtest = qtest;
83
84 return res;
85}
86
87static inline void out_reg(IVState *s, enum Reg reg, unsigned v)
88{
89 const char *name = reg2str(reg);
90 QTestState *qtest = global_qtest;
91
92 global_qtest = s->qtest;
93 g_test_message("%x -> *%s\n", v, name);
94 qpci_io_writel(s->dev, s->reg_base + reg, v);
95 global_qtest = qtest;
96}
97
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98static void cleanup_vm(IVState *s)
99{
100 g_free(s->dev);
101 qpci_free_pc(s->pcibus);
102 qtest_quit(s->qtest);
103}
104
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105static void setup_vm_cmd(IVState *s, const char *cmd, bool msix)
106{
107 uint64_t barsize;
108
109 s->qtest = qtest_start(cmd);
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110 s->pcibus = qpci_init_pc();
111 s->dev = get_device(s->pcibus);
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112
113 /* FIXME: other bar order fails, mappings changes */
114 s->mem_base = qpci_iomap(s->dev, 2, &barsize);
115 g_assert_nonnull(s->mem_base);
116 g_assert_cmpuint(barsize, ==, TMPSHMSIZE);
117
118 if (msix) {
119 qpci_msix_enable(s->dev);
120 }
121
122 s->reg_base = qpci_iomap(s->dev, 0, &barsize);
123 g_assert_nonnull(s->reg_base);
124 g_assert_cmpuint(barsize, ==, 256);
125
126 qpci_device_enable(s->dev);
127}
128
129static void setup_vm(IVState *s)
130{
131 char *cmd = g_strdup_printf("-device ivshmem,shm=%s,size=1M", tmpshm);
132
133 setup_vm_cmd(s, cmd, false);
134
135 g_free(cmd);
136}
137
138static void test_ivshmem_single(void)
139{
140 IVState state, *s;
141 uint32_t data[1024];
142 int i;
143
144 setup_vm(&state);
145 s = &state;
146
147 /* valid io */
148 out_reg(s, INTRMASK, 0);
149 in_reg(s, INTRSTATUS);
150 in_reg(s, IVPOSITION);
151
152 out_reg(s, INTRMASK, 0xffffffff);
153 g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0xffffffff);
154 out_reg(s, INTRSTATUS, 1);
155 /* XXX: intercept IRQ, not seen in resp */
156 g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 1);
157
158 /* invalid io */
159 out_reg(s, IVPOSITION, 1);
160 out_reg(s, DOORBELL, 8 << 16);
161
162 for (i = 0; i < G_N_ELEMENTS(data); i++) {
163 data[i] = i;
164 }
165 qtest_memwrite(s->qtest, (uintptr_t)s->mem_base, data, sizeof(data));
166
167 for (i = 0; i < G_N_ELEMENTS(data); i++) {
168 g_assert_cmpuint(((uint32_t *)tmpshmem)[i], ==, i);
169 }
170
171 memset(data, 0, sizeof(data));
172
173 qtest_memread(s->qtest, (uintptr_t)s->mem_base, data, sizeof(data));
174 for (i = 0; i < G_N_ELEMENTS(data); i++) {
175 g_assert_cmpuint(data[i], ==, i);
176 }
177
1760048a 178 cleanup_vm(s);
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MAL
179}
180
181static void test_ivshmem_pair(void)
182{
183 IVState state1, state2, *s1, *s2;
184 char *data;
185 int i;
186
187 setup_vm(&state1);
188 s1 = &state1;
189 setup_vm(&state2);
190 s2 = &state2;
191
192 data = g_malloc0(TMPSHMSIZE);
193
194 /* host write, guest 1 & 2 read */
195 memset(tmpshmem, 0x42, TMPSHMSIZE);
196 qtest_memread(s1->qtest, (uintptr_t)s1->mem_base, data, TMPSHMSIZE);
197 for (i = 0; i < TMPSHMSIZE; i++) {
198 g_assert_cmpuint(data[i], ==, 0x42);
199 }
200 qtest_memread(s2->qtest, (uintptr_t)s2->mem_base, data, TMPSHMSIZE);
201 for (i = 0; i < TMPSHMSIZE; i++) {
202 g_assert_cmpuint(data[i], ==, 0x42);
203 }
204
205 /* guest 1 write, guest 2 read */
206 memset(data, 0x43, TMPSHMSIZE);
207 qtest_memwrite(s1->qtest, (uintptr_t)s1->mem_base, data, TMPSHMSIZE);
208 memset(data, 0, TMPSHMSIZE);
209 qtest_memread(s2->qtest, (uintptr_t)s2->mem_base, data, TMPSHMSIZE);
210 for (i = 0; i < TMPSHMSIZE; i++) {
211 g_assert_cmpuint(data[i], ==, 0x43);
212 }
213
214 /* guest 2 write, guest 1 read */
215 memset(data, 0x44, TMPSHMSIZE);
216 qtest_memwrite(s2->qtest, (uintptr_t)s2->mem_base, data, TMPSHMSIZE);
217 memset(data, 0, TMPSHMSIZE);
218 qtest_memread(s1->qtest, (uintptr_t)s2->mem_base, data, TMPSHMSIZE);
219 for (i = 0; i < TMPSHMSIZE; i++) {
220 g_assert_cmpuint(data[i], ==, 0x44);
221 }
222
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MAL
223 cleanup_vm(s1);
224 cleanup_vm(s2);
ddef6a0d
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225 g_free(data);
226}
227
228typedef struct ServerThread {
229 GThread *thread;
230 IvshmemServer *server;
231 int pipe[2]; /* to handle quit */
232} ServerThread;
233
234static void *server_thread(void *data)
235{
236 ServerThread *t = data;
237 IvshmemServer *server = t->server;
238
239 while (true) {
240 fd_set fds;
241 int maxfd, ret;
242
243 FD_ZERO(&fds);
244 FD_SET(t->pipe[0], &fds);
245 maxfd = t->pipe[0] + 1;
246
247 ivshmem_server_get_fds(server, &fds, &maxfd);
248
249 ret = select(maxfd, &fds, NULL, NULL, NULL);
250
251 if (ret < 0) {
252 if (errno == EINTR) {
253 continue;
254 }
255
256 g_critical("select error: %s\n", strerror(errno));
257 break;
258 }
259 if (ret == 0) {
260 continue;
261 }
262
263 if (FD_ISSET(t->pipe[0], &fds)) {
264 break;
265 }
266
267 if (ivshmem_server_handle_fds(server, &fds, maxfd) < 0) {
268 g_critical("ivshmem_server_handle_fds() failed\n");
269 break;
270 }
271 }
272
273 return NULL;
274}
275
00ffc3c1 276static void setup_vm_with_server(IVState *s, int nvectors, bool msi)
ddef6a0d
MAL
277{
278 char *cmd = g_strdup_printf("-chardev socket,id=chr0,path=%s,nowait "
00ffc3c1
MAL
279 "-device ivshmem,size=1M,chardev=chr0,vectors=%d,msi=%s",
280 tmpserver, nvectors, msi ? "true" : "false");
ddef6a0d 281
00ffc3c1 282 setup_vm_cmd(s, cmd, msi);
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MAL
283
284 g_free(cmd);
285}
286
00ffc3c1 287static void test_ivshmem_server(bool msi)
ddef6a0d
MAL
288{
289 IVState state1, state2, *s1, *s2;
290 ServerThread thread;
291 IvshmemServer server;
292 int ret, vm1, vm2;
293 int nvectors = 2;
294 guint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND;
295
296 memset(tmpshmem, 0x42, TMPSHMSIZE);
297 ret = ivshmem_server_init(&server, tmpserver, tmpshm,
298 TMPSHMSIZE, nvectors,
299 g_test_verbose());
300 g_assert_cmpint(ret, ==, 0);
301
302 ret = ivshmem_server_start(&server);
303 g_assert_cmpint(ret, ==, 0);
304
00ffc3c1 305 setup_vm_with_server(&state1, nvectors, msi);
ddef6a0d 306 s1 = &state1;
00ffc3c1 307 setup_vm_with_server(&state2, nvectors, msi);
ddef6a0d
MAL
308 s2 = &state2;
309
310 g_assert_cmpuint(in_reg(s1, IVPOSITION), ==, 0xffffffff);
311 g_assert_cmpuint(in_reg(s2, IVPOSITION), ==, 0xffffffff);
312
313 g_assert_cmpuint(qtest_readb(s1->qtest, (uintptr_t)s1->mem_base), ==, 0x00);
314
315 thread.server = &server;
316 ret = pipe(thread.pipe);
317 g_assert_cmpint(ret, ==, 0);
318 thread.thread = g_thread_new("ivshmem-server", server_thread, &thread);
319 g_assert(thread.thread != NULL);
320
321 /* waiting until mapping is done */
322 while (g_get_monotonic_time() < end_time) {
323 g_usleep(1000);
324
325 if (qtest_readb(s1->qtest, (uintptr_t)s1->mem_base) == 0x42 &&
326 qtest_readb(s2->qtest, (uintptr_t)s2->mem_base) == 0x42) {
327 break;
328 }
329 }
330
331 /* check got different VM ids */
332 vm1 = in_reg(s1, IVPOSITION);
333 vm2 = in_reg(s2, IVPOSITION);
334 g_assert_cmpuint(vm1, !=, vm2);
335
336 global_qtest = s1->qtest;
00ffc3c1
MAL
337 if (msi) {
338 ret = qpci_msix_table_size(s1->dev);
339 g_assert_cmpuint(ret, ==, nvectors);
340 }
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MAL
341
342 /* ping vm2 -> vm1 */
00ffc3c1
MAL
343 if (msi) {
344 ret = qpci_msix_pending(s1->dev, 0);
345 g_assert_cmpuint(ret, ==, 0);
346 } else {
347 out_reg(s1, INTRSTATUS, 0);
348 }
ddef6a0d
MAL
349 out_reg(s2, DOORBELL, vm1 << 16);
350 do {
351 g_usleep(10000);
00ffc3c1 352 ret = msi ? qpci_msix_pending(s1->dev, 0) : in_reg(s1, INTRSTATUS);
ddef6a0d
MAL
353 } while (ret == 0 && g_get_monotonic_time() < end_time);
354 g_assert_cmpuint(ret, !=, 0);
355
356 /* ping vm1 -> vm2 */
357 global_qtest = s2->qtest;
00ffc3c1
MAL
358 if (msi) {
359 ret = qpci_msix_pending(s2->dev, 0);
360 g_assert_cmpuint(ret, ==, 0);
361 } else {
362 out_reg(s2, INTRSTATUS, 0);
363 }
ddef6a0d
MAL
364 out_reg(s1, DOORBELL, vm2 << 16);
365 do {
366 g_usleep(10000);
00ffc3c1 367 ret = msi ? qpci_msix_pending(s2->dev, 0) : in_reg(s2, INTRSTATUS);
ddef6a0d
MAL
368 } while (ret == 0 && g_get_monotonic_time() < end_time);
369 g_assert_cmpuint(ret, !=, 0);
370
1760048a
MAL
371 cleanup_vm(s2);
372 cleanup_vm(s1);
ddef6a0d
MAL
373
374 if (qemu_write_full(thread.pipe[1], "q", 1) != 1) {
375 g_error("qemu_write_full: %s", g_strerror(errno));
376 }
377
378 g_thread_join(thread.thread);
379
380 ivshmem_server_close(&server);
381 close(thread.pipe[1]);
382 close(thread.pipe[0]);
383}
384
00ffc3c1
MAL
385static void test_ivshmem_server_msi(void)
386{
387 test_ivshmem_server(true);
388}
389
390static void test_ivshmem_server_irq(void)
391{
392 test_ivshmem_server(false);
393}
394
ddef6a0d
MAL
395#define PCI_SLOT_HP 0x06
396
397static void test_ivshmem_hotplug(void)
398{
399 gchar *opts;
400
401 qtest_start("");
402
403 opts = g_strdup_printf("'shm': '%s', 'size': '1M'", tmpshm);
404
405 qpci_plug_device_test("ivshmem", "iv1", PCI_SLOT_HP, opts);
406 qpci_unplug_acpi_device_test("iv1", PCI_SLOT_HP);
407
408 qtest_end();
409 g_free(opts);
410}
411
d9453c93
MAL
412static void test_ivshmem_memdev(void)
413{
414 IVState state;
415
416 /* just for the sake of checking memory-backend property */
417 setup_vm_cmd(&state, "-object memory-backend-ram,size=1M,id=mb1"
1d649244 418 " -device ivshmem,x-memdev=mb1", false);
d9453c93 419
1760048a 420 cleanup_vm(&state);
d9453c93
MAL
421}
422
ddef6a0d
MAL
423static void cleanup(void)
424{
425 if (tmpshmem) {
426 munmap(tmpshmem, TMPSHMSIZE);
427 tmpshmem = NULL;
428 }
429
430 if (tmpshm) {
431 shm_unlink(tmpshm);
432 g_free(tmpshm);
433 tmpshm = NULL;
434 }
435
436 if (tmpserver) {
437 g_unlink(tmpserver);
438 g_free(tmpserver);
439 tmpserver = NULL;
440 }
441
442 if (tmpdir) {
443 g_rmdir(tmpdir);
444 tmpdir = NULL;
445 }
446}
447
448static void abrt_handler(void *data)
449{
450 cleanup();
451}
452
453static gchar *mktempshm(int size, int *fd)
454{
455 while (true) {
456 gchar *name;
457
458 name = g_strdup_printf("/qtest-%u-%u", getpid(), g_random_int());
459 *fd = shm_open(name, O_CREAT|O_RDWR|O_EXCL,
460 S_IRWXU|S_IRWXG|S_IRWXO);
461 if (*fd > 0) {
462 g_assert(ftruncate(*fd, size) == 0);
463 return name;
464 }
465
466 g_free(name);
467
468 if (errno != EEXIST) {
469 perror("shm_open");
470 return NULL;
471 }
472 }
bbfc2efe
AF
473}
474
475int main(int argc, char **argv)
476{
bbfc2efe 477 int ret, fd;
ddef6a0d
MAL
478 gchar dir[] = "/tmp/ivshmem-test.XXXXXX";
479
480#if !GLIB_CHECK_VERSION(2, 31, 0)
481 if (!g_thread_supported()) {
482 g_thread_init(NULL);
483 }
484#endif
bbfc2efe
AF
485
486 g_test_init(&argc, &argv, NULL);
bbfc2efe 487
ddef6a0d
MAL
488 qtest_add_abrt_handler(abrt_handler, NULL);
489 /* shm */
490 tmpshm = mktempshm(TMPSHMSIZE, &fd);
491 if (!tmpshm) {
492 return 0;
493 }
494 tmpshmem = mmap(0, TMPSHMSIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
495 g_assert(tmpshmem != MAP_FAILED);
496 /* server */
497 if (mkdtemp(dir) == NULL) {
498 g_error("mkdtemp: %s", g_strerror(errno));
499 }
500 tmpdir = dir;
501 tmpserver = g_strconcat(tmpdir, "/server", NULL);
bbfc2efe 502
ddef6a0d 503 qtest_add_func("/ivshmem/single", test_ivshmem_single);
ddef6a0d 504 qtest_add_func("/ivshmem/hotplug", test_ivshmem_hotplug);
d9453c93 505 qtest_add_func("/ivshmem/memdev", test_ivshmem_memdev);
2048a2a4
MAL
506 if (g_test_slow()) {
507 qtest_add_func("/ivshmem/pair", test_ivshmem_pair);
00ffc3c1
MAL
508 qtest_add_func("/ivshmem/server-msi", test_ivshmem_server_msi);
509 qtest_add_func("/ivshmem/server-irq", test_ivshmem_server_irq);
2048a2a4 510 }
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511
512 ret = g_test_run();
513
ddef6a0d 514 cleanup();
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AF
515
516 return ret;
517}