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bbfc2efe
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1/*
2 * QTest testcase for ivshmem
3 *
4 * Copyright (c) 2014 SUSE LINUX Products GmbH
ddef6a0d 5 * Copyright (c) 2015 Red Hat, Inc.
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6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
9 */
10
681c28a3 11#include "qemu/osdep.h"
ddef6a0d 12#include <glib/gstdio.h>
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13#include "contrib/ivshmem-server/ivshmem-server.h"
14#include "libqos/pci-pc.h"
bbfc2efe 15#include "libqtest.h"
ddef6a0d 16#include "qemu-common.h"
bbfc2efe 17
ddef6a0d
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18#define TMPSHMSIZE (1 << 20)
19static char *tmpshm;
20static void *tmpshmem;
21static char *tmpdir;
22static char *tmpserver;
bbfc2efe 23
ddef6a0d 24static void save_fn(QPCIDevice *dev, int devfn, void *data)
bbfc2efe 25{
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26 QPCIDevice **pdev = (QPCIDevice **) data;
27
28 *pdev = dev;
29}
30
1760048a 31static QPCIDevice *get_device(QPCIBus *pcibus)
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32{
33 QPCIDevice *dev;
ddef6a0d 34
16130947 35 dev = NULL;
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36 qpci_device_foreach(pcibus, 0x1af4, 0x1110, save_fn, &dev);
37 g_assert(dev != NULL);
38
39 return dev;
40}
41
42typedef struct _IVState {
43 QTestState *qtest;
44 void *reg_base, *mem_base;
1760048a 45 QPCIBus *pcibus;
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46 QPCIDevice *dev;
47} IVState;
48
49enum Reg {
50 INTRMASK = 0,
51 INTRSTATUS = 4,
52 IVPOSITION = 8,
53 DOORBELL = 12,
54};
55
56static const char* reg2str(enum Reg reg) {
57 switch (reg) {
58 case INTRMASK:
59 return "IntrMask";
60 case INTRSTATUS:
61 return "IntrStatus";
62 case IVPOSITION:
63 return "IVPosition";
64 case DOORBELL:
65 return "DoorBell";
66 default:
67 return NULL;
68 }
69}
70
71static inline unsigned in_reg(IVState *s, enum Reg reg)
72{
73 const char *name = reg2str(reg);
74 QTestState *qtest = global_qtest;
75 unsigned res;
76
77 global_qtest = s->qtest;
78 res = qpci_io_readl(s->dev, s->reg_base + reg);
79 g_test_message("*%s -> %x\n", name, res);
80 global_qtest = qtest;
81
82 return res;
83}
84
85static inline void out_reg(IVState *s, enum Reg reg, unsigned v)
86{
87 const char *name = reg2str(reg);
88 QTestState *qtest = global_qtest;
89
90 global_qtest = s->qtest;
91 g_test_message("%x -> *%s\n", v, name);
92 qpci_io_writel(s->dev, s->reg_base + reg, v);
93 global_qtest = qtest;
94}
95
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96static void cleanup_vm(IVState *s)
97{
98 g_free(s->dev);
99 qpci_free_pc(s->pcibus);
100 qtest_quit(s->qtest);
101}
102
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103static void setup_vm_cmd(IVState *s, const char *cmd, bool msix)
104{
105 uint64_t barsize;
106
107 s->qtest = qtest_start(cmd);
2ecd7e2f 108 s->pcibus = qpci_init_pc(NULL);
1760048a 109 s->dev = get_device(s->pcibus);
ddef6a0d 110
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111 s->reg_base = qpci_iomap(s->dev, 0, &barsize);
112 g_assert_nonnull(s->reg_base);
113 g_assert_cmpuint(barsize, ==, 256);
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114
115 if (msix) {
116 qpci_msix_enable(s->dev);
117 }
118
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119 s->mem_base = qpci_iomap(s->dev, 2, &barsize);
120 g_assert_nonnull(s->mem_base);
121 g_assert_cmpuint(barsize, ==, TMPSHMSIZE);
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122
123 qpci_device_enable(s->dev);
124}
125
126static void setup_vm(IVState *s)
127{
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128 char *cmd = g_strdup_printf("-object memory-backend-file"
129 ",id=mb1,size=1M,share,mem-path=/dev/shm%s"
130 " -device ivshmem-plain,memdev=mb1", tmpshm);
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131
132 setup_vm_cmd(s, cmd, false);
133
134 g_free(cmd);
135}
136
137static void test_ivshmem_single(void)
138{
139 IVState state, *s;
140 uint32_t data[1024];
141 int i;
142
143 setup_vm(&state);
144 s = &state;
145
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146 /* initial state of readable registers */
147 g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0);
148 g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0);
149 g_assert_cmpuint(in_reg(s, IVPOSITION), ==, 0);
ddef6a0d 150
4958fe5d 151 /* trigger interrupt via registers */
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152 out_reg(s, INTRMASK, 0xffffffff);
153 g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0xffffffff);
154 out_reg(s, INTRSTATUS, 1);
4958fe5d 155 /* check interrupt status */
ddef6a0d 156 g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 1);
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157 /* reading clears */
158 g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0);
159 /* TODO intercept actual interrupt (needs qtest work) */
ddef6a0d 160
4958fe5d 161 /* invalid register access */
ddef6a0d 162 out_reg(s, IVPOSITION, 1);
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163 in_reg(s, DOORBELL);
164
165 /* ring the (non-functional) doorbell */
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166 out_reg(s, DOORBELL, 8 << 16);
167
4958fe5d 168 /* write shared memory */
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169 for (i = 0; i < G_N_ELEMENTS(data); i++) {
170 data[i] = i;
171 }
172 qtest_memwrite(s->qtest, (uintptr_t)s->mem_base, data, sizeof(data));
173
4958fe5d 174 /* verify write */
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175 for (i = 0; i < G_N_ELEMENTS(data); i++) {
176 g_assert_cmpuint(((uint32_t *)tmpshmem)[i], ==, i);
177 }
178
4958fe5d 179 /* read it back and verify read */
ddef6a0d 180 memset(data, 0, sizeof(data));
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181 qtest_memread(s->qtest, (uintptr_t)s->mem_base, data, sizeof(data));
182 for (i = 0; i < G_N_ELEMENTS(data); i++) {
183 g_assert_cmpuint(data[i], ==, i);
184 }
185
1760048a 186 cleanup_vm(s);
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187}
188
189static void test_ivshmem_pair(void)
190{
191 IVState state1, state2, *s1, *s2;
192 char *data;
193 int i;
194
195 setup_vm(&state1);
196 s1 = &state1;
197 setup_vm(&state2);
198 s2 = &state2;
199
200 data = g_malloc0(TMPSHMSIZE);
201
202 /* host write, guest 1 & 2 read */
203 memset(tmpshmem, 0x42, TMPSHMSIZE);
204 qtest_memread(s1->qtest, (uintptr_t)s1->mem_base, data, TMPSHMSIZE);
205 for (i = 0; i < TMPSHMSIZE; i++) {
206 g_assert_cmpuint(data[i], ==, 0x42);
207 }
208 qtest_memread(s2->qtest, (uintptr_t)s2->mem_base, data, TMPSHMSIZE);
209 for (i = 0; i < TMPSHMSIZE; i++) {
210 g_assert_cmpuint(data[i], ==, 0x42);
211 }
212
213 /* guest 1 write, guest 2 read */
214 memset(data, 0x43, TMPSHMSIZE);
215 qtest_memwrite(s1->qtest, (uintptr_t)s1->mem_base, data, TMPSHMSIZE);
216 memset(data, 0, TMPSHMSIZE);
217 qtest_memread(s2->qtest, (uintptr_t)s2->mem_base, data, TMPSHMSIZE);
218 for (i = 0; i < TMPSHMSIZE; i++) {
219 g_assert_cmpuint(data[i], ==, 0x43);
220 }
221
222 /* guest 2 write, guest 1 read */
223 memset(data, 0x44, TMPSHMSIZE);
224 qtest_memwrite(s2->qtest, (uintptr_t)s2->mem_base, data, TMPSHMSIZE);
225 memset(data, 0, TMPSHMSIZE);
226 qtest_memread(s1->qtest, (uintptr_t)s2->mem_base, data, TMPSHMSIZE);
227 for (i = 0; i < TMPSHMSIZE; i++) {
228 g_assert_cmpuint(data[i], ==, 0x44);
229 }
230
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231 cleanup_vm(s1);
232 cleanup_vm(s2);
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233 g_free(data);
234}
235
236typedef struct ServerThread {
237 GThread *thread;
238 IvshmemServer *server;
239 int pipe[2]; /* to handle quit */
240} ServerThread;
241
242static void *server_thread(void *data)
243{
244 ServerThread *t = data;
245 IvshmemServer *server = t->server;
246
247 while (true) {
248 fd_set fds;
249 int maxfd, ret;
250
251 FD_ZERO(&fds);
252 FD_SET(t->pipe[0], &fds);
253 maxfd = t->pipe[0] + 1;
254
255 ivshmem_server_get_fds(server, &fds, &maxfd);
256
257 ret = select(maxfd, &fds, NULL, NULL, NULL);
258
259 if (ret < 0) {
260 if (errno == EINTR) {
261 continue;
262 }
263
264 g_critical("select error: %s\n", strerror(errno));
265 break;
266 }
267 if (ret == 0) {
268 continue;
269 }
270
271 if (FD_ISSET(t->pipe[0], &fds)) {
272 break;
273 }
274
275 if (ivshmem_server_handle_fds(server, &fds, maxfd) < 0) {
276 g_critical("ivshmem_server_handle_fds() failed\n");
277 break;
278 }
279 }
280
281 return NULL;
282}
283
00ffc3c1 284static void setup_vm_with_server(IVState *s, int nvectors, bool msi)
ddef6a0d
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285{
286 char *cmd = g_strdup_printf("-chardev socket,id=chr0,path=%s,nowait "
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MA
287 "-device ivshmem%s,chardev=chr0,vectors=%d",
288 tmpserver,
289 msi ? "-doorbell" : ",size=1M,msi=off",
290 nvectors);
ddef6a0d 291
00ffc3c1 292 setup_vm_cmd(s, cmd, msi);
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MAL
293
294 g_free(cmd);
295}
296
00ffc3c1 297static void test_ivshmem_server(bool msi)
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MAL
298{
299 IVState state1, state2, *s1, *s2;
300 ServerThread thread;
301 IvshmemServer server;
302 int ret, vm1, vm2;
303 int nvectors = 2;
304 guint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND;
305
3625c739 306 ret = ivshmem_server_init(&server, tmpserver, tmpshm, true,
ddef6a0d
MAL
307 TMPSHMSIZE, nvectors,
308 g_test_verbose());
309 g_assert_cmpint(ret, ==, 0);
310
311 ret = ivshmem_server_start(&server);
312 g_assert_cmpint(ret, ==, 0);
313
ddef6a0d
MAL
314 thread.server = &server;
315 ret = pipe(thread.pipe);
316 g_assert_cmpint(ret, ==, 0);
317 thread.thread = g_thread_new("ivshmem-server", server_thread, &thread);
318 g_assert(thread.thread != NULL);
319
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320 setup_vm_with_server(&state1, nvectors, msi);
321 s1 = &state1;
322 setup_vm_with_server(&state2, nvectors, msi);
323 s2 = &state2;
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324
325 /* check got different VM ids */
326 vm1 = in_reg(s1, IVPOSITION);
327 vm2 = in_reg(s2, IVPOSITION);
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MA
328 g_assert_cmpint(vm1, >=, 0);
329 g_assert_cmpint(vm2, >=, 0);
330 g_assert_cmpint(vm1, !=, vm2);
ddef6a0d 331
41b65e5e 332 /* check number of MSI-X vectors */
ddef6a0d 333 global_qtest = s1->qtest;
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334 if (msi) {
335 ret = qpci_msix_table_size(s1->dev);
336 g_assert_cmpuint(ret, ==, nvectors);
337 }
ddef6a0d 338
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MA
339 /* TODO test behavior before MSI-X is enabled */
340
341 /* ping vm2 -> vm1 on vector 0 */
00ffc3c1
MAL
342 if (msi) {
343 ret = qpci_msix_pending(s1->dev, 0);
344 g_assert_cmpuint(ret, ==, 0);
345 } else {
41b65e5e 346 g_assert_cmpuint(in_reg(s1, INTRSTATUS), ==, 0);
00ffc3c1 347 }
ddef6a0d
MAL
348 out_reg(s2, DOORBELL, vm1 << 16);
349 do {
350 g_usleep(10000);
00ffc3c1 351 ret = msi ? qpci_msix_pending(s1->dev, 0) : in_reg(s1, INTRSTATUS);
ddef6a0d
MAL
352 } while (ret == 0 && g_get_monotonic_time() < end_time);
353 g_assert_cmpuint(ret, !=, 0);
354
41b65e5e 355 /* ping vm1 -> vm2 on vector 1 */
ddef6a0d 356 global_qtest = s2->qtest;
00ffc3c1 357 if (msi) {
41b65e5e 358 ret = qpci_msix_pending(s2->dev, 1);
00ffc3c1
MAL
359 g_assert_cmpuint(ret, ==, 0);
360 } else {
41b65e5e 361 g_assert_cmpuint(in_reg(s2, INTRSTATUS), ==, 0);
00ffc3c1 362 }
41b65e5e 363 out_reg(s1, DOORBELL, vm2 << 16 | 1);
ddef6a0d
MAL
364 do {
365 g_usleep(10000);
41b65e5e 366 ret = msi ? qpci_msix_pending(s2->dev, 1) : in_reg(s2, INTRSTATUS);
ddef6a0d
MAL
367 } while (ret == 0 && g_get_monotonic_time() < end_time);
368 g_assert_cmpuint(ret, !=, 0);
369
1760048a
MAL
370 cleanup_vm(s2);
371 cleanup_vm(s1);
ddef6a0d
MAL
372
373 if (qemu_write_full(thread.pipe[1], "q", 1) != 1) {
374 g_error("qemu_write_full: %s", g_strerror(errno));
375 }
376
377 g_thread_join(thread.thread);
378
379 ivshmem_server_close(&server);
380 close(thread.pipe[1]);
381 close(thread.pipe[0]);
382}
383
00ffc3c1
MAL
384static void test_ivshmem_server_msi(void)
385{
386 test_ivshmem_server(true);
387}
388
389static void test_ivshmem_server_irq(void)
390{
391 test_ivshmem_server(false);
392}
393
ddef6a0d
MAL
394#define PCI_SLOT_HP 0x06
395
396static void test_ivshmem_hotplug(void)
397{
398 gchar *opts;
399
400 qtest_start("");
401
402 opts = g_strdup_printf("'shm': '%s', 'size': '1M'", tmpshm);
403
404 qpci_plug_device_test("ivshmem", "iv1", PCI_SLOT_HP, opts);
405 qpci_unplug_acpi_device_test("iv1", PCI_SLOT_HP);
406
407 qtest_end();
408 g_free(opts);
409}
410
d9453c93
MAL
411static void test_ivshmem_memdev(void)
412{
413 IVState state;
414
415 /* just for the sake of checking memory-backend property */
416 setup_vm_cmd(&state, "-object memory-backend-ram,size=1M,id=mb1"
5400c02b 417 " -device ivshmem-plain,memdev=mb1", false);
d9453c93 418
1760048a 419 cleanup_vm(&state);
d9453c93
MAL
420}
421
ddef6a0d
MAL
422static void cleanup(void)
423{
424 if (tmpshmem) {
425 munmap(tmpshmem, TMPSHMSIZE);
426 tmpshmem = NULL;
427 }
428
429 if (tmpshm) {
430 shm_unlink(tmpshm);
431 g_free(tmpshm);
432 tmpshm = NULL;
433 }
434
435 if (tmpserver) {
436 g_unlink(tmpserver);
437 g_free(tmpserver);
438 tmpserver = NULL;
439 }
440
441 if (tmpdir) {
442 g_rmdir(tmpdir);
443 tmpdir = NULL;
444 }
445}
446
447static void abrt_handler(void *data)
448{
449 cleanup();
450}
451
452static gchar *mktempshm(int size, int *fd)
453{
454 while (true) {
455 gchar *name;
456
457 name = g_strdup_printf("/qtest-%u-%u", getpid(), g_random_int());
458 *fd = shm_open(name, O_CREAT|O_RDWR|O_EXCL,
459 S_IRWXU|S_IRWXG|S_IRWXO);
460 if (*fd > 0) {
461 g_assert(ftruncate(*fd, size) == 0);
462 return name;
463 }
464
465 g_free(name);
466
467 if (errno != EEXIST) {
468 perror("shm_open");
469 return NULL;
470 }
471 }
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AF
472}
473
474int main(int argc, char **argv)
475{
bbfc2efe 476 int ret, fd;
ddef6a0d
MAL
477 gchar dir[] = "/tmp/ivshmem-test.XXXXXX";
478
479#if !GLIB_CHECK_VERSION(2, 31, 0)
480 if (!g_thread_supported()) {
481 g_thread_init(NULL);
482 }
483#endif
bbfc2efe
AF
484
485 g_test_init(&argc, &argv, NULL);
bbfc2efe 486
ddef6a0d
MAL
487 qtest_add_abrt_handler(abrt_handler, NULL);
488 /* shm */
489 tmpshm = mktempshm(TMPSHMSIZE, &fd);
490 if (!tmpshm) {
491 return 0;
492 }
493 tmpshmem = mmap(0, TMPSHMSIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
494 g_assert(tmpshmem != MAP_FAILED);
495 /* server */
496 if (mkdtemp(dir) == NULL) {
497 g_error("mkdtemp: %s", g_strerror(errno));
498 }
499 tmpdir = dir;
500 tmpserver = g_strconcat(tmpdir, "/server", NULL);
bbfc2efe 501
ddef6a0d 502 qtest_add_func("/ivshmem/single", test_ivshmem_single);
ddef6a0d 503 qtest_add_func("/ivshmem/hotplug", test_ivshmem_hotplug);
d9453c93 504 qtest_add_func("/ivshmem/memdev", test_ivshmem_memdev);
2048a2a4
MAL
505 if (g_test_slow()) {
506 qtest_add_func("/ivshmem/pair", test_ivshmem_pair);
00ffc3c1
MAL
507 qtest_add_func("/ivshmem/server-msi", test_ivshmem_server_msi);
508 qtest_add_func("/ivshmem/server-irq", test_ivshmem_server_irq);
2048a2a4 509 }
bbfc2efe
AF
510
511 ret = g_test_run();
512
ddef6a0d 513 cleanup();
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514
515 return ret;
516}