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cf716b31 LV |
1 | /* |
2 | * libqos PCI bindings for SPAPR | |
3 | * | |
4 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
5 | * See the COPYING file in the top-level directory. | |
6 | */ | |
7 | ||
8 | #include "qemu/osdep.h" | |
9 | #include "libqtest.h" | |
10 | #include "libqos/pci-spapr.h" | |
11 | #include "libqos/rtas.h" | |
b8782d2a | 12 | #include "libqos/qgraph.h" |
cf716b31 LV |
13 | |
14 | #include "hw/pci/pci_regs.h" | |
15 | ||
16 | #include "qemu-common.h" | |
17 | #include "qemu/host-utils.h" | |
18 | ||
cf716b31 LV |
19 | /* |
20 | * PCI devices are always little-endian | |
21 | * SPAPR by default is big-endian | |
22 | * so PCI accessors need to swap data endianness | |
23 | */ | |
24 | ||
a795fc08 | 25 | static uint8_t qpci_spapr_pio_readb(QPCIBus *bus, uint32_t addr) |
cf716b31 | 26 | { |
cd1b354e | 27 | QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); |
d786f782 | 28 | return qtest_readb(bus->qts, s->pio_cpu_base + addr); |
cf716b31 LV |
29 | } |
30 | ||
a795fc08 | 31 | static void qpci_spapr_pio_writeb(QPCIBus *bus, uint32_t addr, uint8_t val) |
cf716b31 | 32 | { |
cd1b354e | 33 | QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); |
d786f782 | 34 | qtest_writeb(bus->qts, s->pio_cpu_base + addr, val); |
cf716b31 LV |
35 | } |
36 | ||
a795fc08 | 37 | static uint16_t qpci_spapr_pio_readw(QPCIBus *bus, uint32_t addr) |
cf716b31 | 38 | { |
cd1b354e | 39 | QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); |
d786f782 | 40 | return bswap16(qtest_readw(bus->qts, s->pio_cpu_base + addr)); |
cf716b31 LV |
41 | } |
42 | ||
a795fc08 DG |
43 | static void qpci_spapr_pio_writew(QPCIBus *bus, uint32_t addr, uint16_t val) |
44 | { | |
45 | QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); | |
d786f782 | 46 | qtest_writew(bus->qts, s->pio_cpu_base + addr, bswap16(val)); |
a795fc08 DG |
47 | } |
48 | ||
a795fc08 DG |
49 | static uint32_t qpci_spapr_pio_readl(QPCIBus *bus, uint32_t addr) |
50 | { | |
51 | QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); | |
d786f782 | 52 | return bswap32(qtest_readl(bus->qts, s->pio_cpu_base + addr)); |
a795fc08 DG |
53 | } |
54 | ||
a795fc08 DG |
55 | static void qpci_spapr_pio_writel(QPCIBus *bus, uint32_t addr, uint32_t val) |
56 | { | |
57 | QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); | |
d786f782 | 58 | qtest_writel(bus->qts, s->pio_cpu_base + addr, bswap32(val)); |
a795fc08 DG |
59 | } |
60 | ||
f775f45a DG |
61 | static uint64_t qpci_spapr_pio_readq(QPCIBus *bus, uint32_t addr) |
62 | { | |
63 | QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); | |
d786f782 | 64 | return bswap64(qtest_readq(bus->qts, s->pio_cpu_base + addr)); |
f775f45a DG |
65 | } |
66 | ||
67 | static void qpci_spapr_pio_writeq(QPCIBus *bus, uint32_t addr, uint64_t val) | |
68 | { | |
69 | QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); | |
d786f782 | 70 | qtest_writeq(bus->qts, s->pio_cpu_base + addr, bswap64(val)); |
f775f45a DG |
71 | } |
72 | ||
9a84f889 DG |
73 | static void qpci_spapr_memread(QPCIBus *bus, uint32_t addr, |
74 | void *buf, size_t len) | |
75 | { | |
76 | QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); | |
d786f782 | 77 | qtest_memread(bus->qts, s->mmio32_cpu_base + addr, buf, len); |
9a84f889 DG |
78 | } |
79 | ||
80 | static void qpci_spapr_memwrite(QPCIBus *bus, uint32_t addr, | |
81 | const void *buf, size_t len) | |
82 | { | |
83 | QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); | |
d786f782 | 84 | qtest_memwrite(bus->qts, s->mmio32_cpu_base + addr, buf, len); |
9a84f889 DG |
85 | } |
86 | ||
cf716b31 LV |
87 | static uint8_t qpci_spapr_config_readb(QPCIBus *bus, int devfn, uint8_t offset) |
88 | { | |
89 | QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); | |
90 | uint32_t config_addr = (devfn << 8) | offset; | |
9b67af76 EB |
91 | return qrtas_ibm_read_pci_config(bus->qts, s->alloc, s->buid, |
92 | config_addr, 1); | |
cf716b31 LV |
93 | } |
94 | ||
95 | static uint16_t qpci_spapr_config_readw(QPCIBus *bus, int devfn, uint8_t offset) | |
96 | { | |
97 | QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); | |
98 | uint32_t config_addr = (devfn << 8) | offset; | |
9b67af76 EB |
99 | return qrtas_ibm_read_pci_config(bus->qts, s->alloc, s->buid, |
100 | config_addr, 2); | |
cf716b31 LV |
101 | } |
102 | ||
103 | static uint32_t qpci_spapr_config_readl(QPCIBus *bus, int devfn, uint8_t offset) | |
104 | { | |
105 | QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); | |
106 | uint32_t config_addr = (devfn << 8) | offset; | |
9b67af76 EB |
107 | return qrtas_ibm_read_pci_config(bus->qts, s->alloc, s->buid, |
108 | config_addr, 4); | |
cf716b31 LV |
109 | } |
110 | ||
111 | static void qpci_spapr_config_writeb(QPCIBus *bus, int devfn, uint8_t offset, | |
112 | uint8_t value) | |
113 | { | |
114 | QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); | |
115 | uint32_t config_addr = (devfn << 8) | offset; | |
9b67af76 EB |
116 | qrtas_ibm_write_pci_config(bus->qts, s->alloc, s->buid, |
117 | config_addr, 1, value); | |
cf716b31 LV |
118 | } |
119 | ||
120 | static void qpci_spapr_config_writew(QPCIBus *bus, int devfn, uint8_t offset, | |
121 | uint16_t value) | |
122 | { | |
123 | QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); | |
124 | uint32_t config_addr = (devfn << 8) | offset; | |
9b67af76 EB |
125 | qrtas_ibm_write_pci_config(bus->qts, s->alloc, s->buid, |
126 | config_addr, 2, value); | |
cf716b31 LV |
127 | } |
128 | ||
129 | static void qpci_spapr_config_writel(QPCIBus *bus, int devfn, uint8_t offset, | |
130 | uint32_t value) | |
131 | { | |
132 | QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus); | |
133 | uint32_t config_addr = (devfn << 8) | offset; | |
9b67af76 EB |
134 | qrtas_ibm_write_pci_config(bus->qts, s->alloc, s->buid, |
135 | config_addr, 4, value); | |
cf716b31 LV |
136 | } |
137 | ||
357d1e3b DG |
138 | #define SPAPR_PCI_BASE (1ULL << 45) |
139 | ||
8360544a | 140 | #define SPAPR_PCI_MMIO32_WIN_SIZE 0x80000000 /* 2 GiB */ |
cd1b354e DG |
141 | #define SPAPR_PCI_IO_WIN_SIZE 0x10000 |
142 | ||
b8782d2a | 143 | static void *qpci_spapr_get_driver(void *obj, const char *interface) |
cf716b31 | 144 | { |
b8782d2a EGE |
145 | QPCIBusSPAPR *qpci = obj; |
146 | if (!g_strcmp0(interface, "pci-bus")) { | |
147 | return &qpci->bus; | |
148 | } | |
149 | fprintf(stderr, "%s not present in pci-bus-spapr", interface); | |
150 | g_assert_not_reached(); | |
151 | } | |
cf716b31 | 152 | |
b8782d2a EGE |
153 | void qpci_init_spapr(QPCIBusSPAPR *qpci, QTestState *qts, |
154 | QGuestAllocator *alloc) | |
155 | { | |
e5d1730d | 156 | assert(qts); |
cf716b31 | 157 | |
92bbafc7 | 158 | /* tests cannot use spapr, needs to be fixed first */ |
c098aac7 | 159 | qpci->bus.has_buggy_msi = true; |
92bbafc7 | 160 | |
b8782d2a | 161 | qpci->alloc = alloc; |
cf716b31 | 162 | |
b8782d2a EGE |
163 | qpci->bus.pio_readb = qpci_spapr_pio_readb; |
164 | qpci->bus.pio_readw = qpci_spapr_pio_readw; | |
165 | qpci->bus.pio_readl = qpci_spapr_pio_readl; | |
166 | qpci->bus.pio_readq = qpci_spapr_pio_readq; | |
a795fc08 | 167 | |
b8782d2a EGE |
168 | qpci->bus.pio_writeb = qpci_spapr_pio_writeb; |
169 | qpci->bus.pio_writew = qpci_spapr_pio_writew; | |
170 | qpci->bus.pio_writel = qpci_spapr_pio_writel; | |
171 | qpci->bus.pio_writeq = qpci_spapr_pio_writeq; | |
a795fc08 | 172 | |
b8782d2a EGE |
173 | qpci->bus.memread = qpci_spapr_memread; |
174 | qpci->bus.memwrite = qpci_spapr_memwrite; | |
9a84f889 | 175 | |
b8782d2a EGE |
176 | qpci->bus.config_readb = qpci_spapr_config_readb; |
177 | qpci->bus.config_readw = qpci_spapr_config_readw; | |
178 | qpci->bus.config_readl = qpci_spapr_config_readl; | |
cf716b31 | 179 | |
b8782d2a EGE |
180 | qpci->bus.config_writeb = qpci_spapr_config_writeb; |
181 | qpci->bus.config_writew = qpci_spapr_config_writew; | |
182 | qpci->bus.config_writel = qpci_spapr_config_writel; | |
cf716b31 | 183 | |
cd1b354e DG |
184 | /* FIXME: We assume the default location of the PHB for now. |
185 | * Ideally we'd parse the device tree deposited in the guest to | |
186 | * get the window locations */ | |
b8782d2a | 187 | qpci->buid = 0x800000020000000ULL; |
cd1b354e | 188 | |
b8782d2a EGE |
189 | qpci->pio_cpu_base = SPAPR_PCI_BASE; |
190 | qpci->pio.pci_base = 0; | |
191 | qpci->pio.size = SPAPR_PCI_IO_WIN_SIZE; | |
cd1b354e | 192 | |
8360544a | 193 | /* 32-bit portion of the MMIO window is at PCI address 2..4 GiB */ |
b8782d2a EGE |
194 | qpci->mmio32_cpu_base = SPAPR_PCI_BASE; |
195 | qpci->mmio32.pci_base = SPAPR_PCI_MMIO32_WIN_SIZE; | |
196 | qpci->mmio32.size = SPAPR_PCI_MMIO32_WIN_SIZE; | |
cd1b354e | 197 | |
b8782d2a EGE |
198 | qpci->bus.qts = qts; |
199 | qpci->bus.pio_alloc_ptr = 0xc000; | |
200 | qpci->bus.mmio_alloc_ptr = qpci->mmio32.pci_base; | |
201 | qpci->bus.mmio_limit = qpci->mmio32.pci_base + qpci->mmio32.size; | |
cf716b31 | 202 | |
b8782d2a EGE |
203 | qpci->obj.get_driver = qpci_spapr_get_driver; |
204 | } | |
205 | ||
206 | QPCIBus *qpci_new_spapr(QTestState *qts, QGuestAllocator *alloc) | |
207 | { | |
208 | QPCIBusSPAPR *qpci = g_new0(QPCIBusSPAPR, 1); | |
209 | qpci_init_spapr(qpci, qts, alloc); | |
210 | ||
211 | return &qpci->bus; | |
cf716b31 LV |
212 | } |
213 | ||
214 | void qpci_free_spapr(QPCIBus *bus) | |
215 | { | |
b8782d2a EGE |
216 | QPCIBusSPAPR *s; |
217 | ||
218 | if (!bus) { | |
219 | return; | |
220 | } | |
221 | s = container_of(bus, QPCIBusSPAPR, bus); | |
cf716b31 LV |
222 | |
223 | g_free(s); | |
224 | } | |
b8782d2a EGE |
225 | |
226 | static void qpci_spapr_register_nodes(void) | |
227 | { | |
228 | qos_node_create_driver("pci-bus-spapr", NULL); | |
229 | qos_node_produces("pci-bus-spapr", "pci-bus"); | |
230 | } | |
231 | ||
232 | libqos_init(qpci_spapr_register_nodes); |