[mirror_qemu.git] / tests / libqos / virtio-pci.c

/*
 * libqos virtio PCI driver
 *
 * Copyright (c) 2014 Marc Marí
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"
#include "libqtest.h"
#include "libqos/virtio.h"
#include "libqos/virtio-pci.h"
#include "libqos/pci.h"
#include "libqos/pci-pc.h"
#include "libqos/malloc.h"
#include "libqos/malloc-pc.h"
#include "standard-headers/linux/virtio_ring.h"
#include "standard-headers/linux/virtio_pci.h"

#include "hw/pci/pci.h"
#include "hw/pci/pci_regs.h"

typedef struct QVirtioPCIForeachData {
    void (*func)(QVirtioDevice *d, void *data);
    uint16_t device_type;
    void *user_data;
} QVirtioPCIForeachData;

static QVirtioPCIDevice *qpcidevice_to_qvirtiodevice(QPCIDevice *pdev)
{
    QVirtioPCIDevice *vpcidev;
    vpcidev = g_malloc0(sizeof(*vpcidev));

    if (pdev) {
        vpcidev->pdev = pdev;
        vpcidev->vdev.device_type =
                            qpci_config_readw(vpcidev->pdev, PCI_SUBSYSTEM_ID);
    }

    vpcidev->config_msix_entry = -1;

    return vpcidev;
}

static void qvirtio_pci_foreach_callback(
                        QPCIDevice *dev, int devfn, void *data)
{
    QVirtioPCIForeachData *d = data;
    QVirtioPCIDevice *vpcidev = qpcidevice_to_qvirtiodevice(dev);

    if (vpcidev->vdev.device_type == d->device_type) {
        d->func(&vpcidev->vdev, d->user_data);
    } else {
        g_free(vpcidev);
    }
}

static void qvirtio_pci_assign_device(QVirtioDevice *d, void *data)
{
    QVirtioPCIDevice **vpcidev = data;
    *vpcidev = (QVirtioPCIDevice *)d;
}

#define CONFIG_BASE(dev) \
    ((dev)->addr + VIRTIO_PCI_CONFIG_OFF((dev)->pdev->msix_enabled))

static uint8_t qvirtio_pci_config_readb(QVirtioDevice *d, uint64_t off)
{
    QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
    return qpci_io_readb(dev->pdev, CONFIG_BASE(dev) + off);
}

/* PCI is always read in little-endian order
 * but virtio ( < 1.0) is in guest order
 * so with a big-endian guest the order has been reversed,
 * reverse it again
 * virtio-1.0 is always little-endian, like PCI, but this
 * case will be managed inside qvirtio_is_big_endian()
 */

static uint16_t qvirtio_pci_config_readw(QVirtioDevice *d, uint64_t off)
{
    QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
    uint16_t value;

    value = qpci_io_readw(dev->pdev, CONFIG_BASE(dev) + off);
    if (qvirtio_is_big_endian(d)) {
        value = bswap16(value);
    }
    return value;
}

static uint32_t qvirtio_pci_config_readl(QVirtioDevice *d, uint64_t off)
{
    QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
    uint32_t value;

    value = qpci_io_readl(dev->pdev, CONFIG_BASE(dev) + off);
    if (qvirtio_is_big_endian(d)) {
        value = bswap32(value);
    }
    return value;
}

static uint64_t qvirtio_pci_config_readq(QVirtioDevice *d, uint64_t off)
{
    QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
    uint64_t val;

    val = qpci_io_readq(dev->pdev, CONFIG_BASE(dev) + off);
    if (qvirtio_is_big_endian(d)) {
        val = bswap64(val);
    }

    return val;
}

static uint32_t qvirtio_pci_get_features(QVirtioDevice *d)
{
    QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
    return qpci_io_readl(dev->pdev, dev->addr + VIRTIO_PCI_HOST_FEATURES);
}

static void qvirtio_pci_set_features(QVirtioDevice *d, uint32_t features)
{
    QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
    qpci_io_writel(dev->pdev, dev->addr + VIRTIO_PCI_GUEST_FEATURES, features);
}

static uint32_t qvirtio_pci_get_guest_features(QVirtioDevice *d)
{
    QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
    return qpci_io_readl(dev->pdev, dev->addr + VIRTIO_PCI_GUEST_FEATURES);
}

static uint8_t qvirtio_pci_get_status(QVirtioDevice *d)
{
    QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
    return qpci_io_readb(dev->pdev, dev->addr + VIRTIO_PCI_STATUS);
}

static void qvirtio_pci_set_status(QVirtioDevice *d, uint8_t status)
{
    QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
    qpci_io_writeb(dev->pdev, dev->addr + VIRTIO_PCI_STATUS, status);
}

static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice *d, QVirtQueue *vq)
{
    QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
    QVirtQueuePCI *vqpci = (QVirtQueuePCI *)vq;
    uint32_t data;

    if (dev->pdev->msix_enabled) {
        g_assert_cmpint(vqpci->msix_entry, !=, -1);
        if (qpci_msix_masked(dev->pdev, vqpci->msix_entry)) {
            /* No ISR checking should be done if masked, but read anyway */
            return qpci_msix_pending(dev->pdev, vqpci->msix_entry);
        } else {
            data = readl(vqpci->msix_addr);
            if (data == vqpci->msix_data) {
                writel(vqpci->msix_addr, 0);
                return true;
            } else {
                return false;
            }
        }
    } else {
        return qpci_io_readb(dev->pdev, dev->addr + VIRTIO_PCI_ISR) & 1;
    }
}

static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d)
{
    QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
    uint32_t data;

    if (dev->pdev->msix_enabled) {
        g_assert_cmpint(dev->config_msix_entry, !=, -1);
        if (qpci_msix_masked(dev->pdev, dev->config_msix_entry)) {
            /* No ISR checking should be done if masked, but read anyway */
            return qpci_msix_pending(dev->pdev, dev->config_msix_entry);
        } else {
            data = readl(dev->config_msix_addr);
            if (data == dev->config_msix_data) {
                writel(dev->config_msix_addr, 0);
                return true;
            } else {
                return false;
            }
        }
    } else {
        return qpci_io_readb(dev->pdev, dev->addr + VIRTIO_PCI_ISR) & 2;
    }
}

static void qvirtio_pci_queue_select(QVirtioDevice *d, uint16_t index)
{
    QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
    qpci_io_writeb(dev->pdev, dev->addr + VIRTIO_PCI_QUEUE_SEL, index);
}

static uint16_t qvirtio_pci_get_queue_size(QVirtioDevice *d)
{
    QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
    return qpci_io_readw(dev->pdev, dev->addr + VIRTIO_PCI_QUEUE_NUM);
}

static void qvirtio_pci_set_queue_address(QVirtioDevice *d, uint32_t pfn)
{
    QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
    qpci_io_writel(dev->pdev, dev->addr + VIRTIO_PCI_QUEUE_PFN, pfn);
}

static QVirtQueue *qvirtio_pci_virtqueue_setup(QVirtioDevice *d,
                                        QGuestAllocator *alloc, uint16_t index)
{
    uint32_t feat;
    uint64_t addr;
    QVirtQueuePCI *vqpci;

    vqpci = g_malloc0(sizeof(*vqpci));
    feat = qvirtio_pci_get_guest_features(d);

    qvirtio_pci_queue_select(d, index);
    vqpci->vq.index = index;
    vqpci->vq.size = qvirtio_pci_get_queue_size(d);
    vqpci->vq.free_head = 0;
    vqpci->vq.num_free = vqpci->vq.size;
    vqpci->vq.align = VIRTIO_PCI_VRING_ALIGN;
    vqpci->vq.indirect = (feat & (1u << VIRTIO_RING_F_INDIRECT_DESC)) != 0;
    vqpci->vq.event = (feat & (1u << VIRTIO_RING_F_EVENT_IDX)) != 0;

    vqpci->msix_entry = -1;
    vqpci->msix_addr = 0;
    vqpci->msix_data = 0x12345678;

    /* Check different than 0 */
    g_assert_cmpint(vqpci->vq.size, !=, 0);

    /* Check power of 2 */
    g_assert_cmpint(vqpci->vq.size & (vqpci->vq.size - 1), ==, 0);

    addr = guest_alloc(alloc, qvring_size(vqpci->vq.size,
                                          VIRTIO_PCI_VRING_ALIGN));
    qvring_init(alloc, &vqpci->vq, addr);
    qvirtio_pci_set_queue_address(d, vqpci->vq.desc / VIRTIO_PCI_VRING_ALIGN);

    return &vqpci->vq;
}

static void qvirtio_pci_virtqueue_cleanup(QVirtQueue *vq,
                                          QGuestAllocator *alloc)
{
    QVirtQueuePCI *vqpci = container_of(vq, QVirtQueuePCI, vq);

    guest_free(alloc, vq->desc);
    g_free(vqpci);
}

static void qvirtio_pci_virtqueue_kick(QVirtioDevice *d, QVirtQueue *vq)
{
    QVirtioPCIDevice *dev = (QVirtioPCIDevice *)d;
    qpci_io_writew(dev->pdev, dev->addr + VIRTIO_PCI_QUEUE_NOTIFY, vq->index);
}

const QVirtioBus qvirtio_pci = {
    .config_readb = qvirtio_pci_config_readb,
    .config_readw = qvirtio_pci_config_readw,
    .config_readl = qvirtio_pci_config_readl,
    .config_readq = qvirtio_pci_config_readq,
    .get_features = qvirtio_pci_get_features,
    .set_features = qvirtio_pci_set_features,
    .get_guest_features = qvirtio_pci_get_guest_features,
    .get_status = qvirtio_pci_get_status,
    .set_status = qvirtio_pci_set_status,
    .get_queue_isr_status = qvirtio_pci_get_queue_isr_status,
    .get_config_isr_status = qvirtio_pci_get_config_isr_status,
    .queue_select = qvirtio_pci_queue_select,
    .get_queue_size = qvirtio_pci_get_queue_size,
    .set_queue_address = qvirtio_pci_set_queue_address,
    .virtqueue_setup = qvirtio_pci_virtqueue_setup,
    .virtqueue_cleanup = qvirtio_pci_virtqueue_cleanup,
    .virtqueue_kick = qvirtio_pci_virtqueue_kick,
};

void qvirtio_pci_foreach(QPCIBus *bus, uint16_t device_type,
                void (*func)(QVirtioDevice *d, void *data), void *data)
{
    QVirtioPCIForeachData d = { .func = func,
                                .device_type = device_type,
                                .user_data = data };

    qpci_device_foreach(bus, PCI_VENDOR_ID_REDHAT_QUMRANET, -1,
                                qvirtio_pci_foreach_callback, &d);
}

QVirtioPCIDevice *qvirtio_pci_device_find(QPCIBus *bus, uint16_t device_type)
{
    QVirtioPCIDevice *dev = NULL;
    qvirtio_pci_foreach(bus, device_type, qvirtio_pci_assign_device, &dev);

    dev->vdev.bus = &qvirtio_pci;

    return dev;
}

void qvirtio_pci_device_enable(QVirtioPCIDevice *d)
{
    qpci_device_enable(d->pdev);
    d->addr = qpci_iomap(d->pdev, 0, NULL);
    g_assert(d->addr != NULL);
}

void qvirtio_pci_device_disable(QVirtioPCIDevice *d)
{
    qpci_iounmap(d->pdev, d->addr);
    d->addr = NULL;
}

void qvirtqueue_pci_msix_setup(QVirtioPCIDevice *d, QVirtQueuePCI *vqpci,
                                        QGuestAllocator *alloc, uint16_t entry)
{
    uint16_t vector;
    uint32_t control;
    void *addr;

    g_assert(d->pdev->msix_enabled);
    addr = d->pdev->msix_table + (entry * 16);

    g_assert_cmpint(entry, >=, 0);
    g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
    vqpci->msix_entry = entry;

    vqpci->msix_addr = guest_alloc(alloc, 4);
    qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_LOWER_ADDR,
                                                    vqpci->msix_addr & ~0UL);
    qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_UPPER_ADDR,
                                            (vqpci->msix_addr >> 32) & ~0UL);
    qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_DATA, vqpci->msix_data);

    control = qpci_io_readl(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
    qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL,
                                        control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);

    qvirtio_pci_queue_select(&d->vdev, vqpci->vq.index);
    qpci_io_writew(d->pdev, d->addr + VIRTIO_MSI_QUEUE_VECTOR, entry);
    vector = qpci_io_readw(d->pdev, d->addr + VIRTIO_MSI_QUEUE_VECTOR);
    g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
}

void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d,
                                        QGuestAllocator *alloc, uint16_t entry)
{
    uint16_t vector;
    uint32_t control;
    void *addr;

    g_assert(d->pdev->msix_enabled);
    addr = d->pdev->msix_table + (entry * 16);

    g_assert_cmpint(entry, >=, 0);
    g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
    d->config_msix_entry = entry;

    d->config_msix_data = 0x12345678;
    d->config_msix_addr = guest_alloc(alloc, 4);

    qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_LOWER_ADDR,
                                                    d->config_msix_addr & ~0UL);
    qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_UPPER_ADDR,
                                            (d->config_msix_addr >> 32) & ~0UL);
    qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_DATA, d->config_msix_data);

    control = qpci_io_readl(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
    qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL,
                                        control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);

    qpci_io_writew(d->pdev, d->addr + VIRTIO_MSI_CONFIG_VECTOR, entry);
    vector = qpci_io_readw(d->pdev, d->addr + VIRTIO_MSI_CONFIG_VECTOR);
    g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
}
Commit	Line	Data
311e666a MM	1	/*
	2	* libqos virtio PCI driver
	3	*
	4	* Copyright (c) 2014 Marc Marí
	5	*
	6	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	7	* See the COPYING file in the top-level directory.
	8	*/
	9
681c28a3	10	#include "qemu/osdep.h"
311e666a MM	11	#include "libqtest.h"
	12	#include "libqos/virtio.h"
	13	#include "libqos/virtio-pci.h"
	14	#include "libqos/pci.h"
	15	#include "libqos/pci-pc.h"
bf3c63d2 MM	16	#include "libqos/malloc.h"
bf3c63d2 MM	17	#include "libqos/malloc-pc.h"
ee3b850a	18	#include "standard-headers/linux/virtio_ring.h"
c75f4c06	19	#include "standard-headers/linux/virtio_pci.h"
311e666a	20
7ad1e708	21	#include "hw/pci/pci.h"
311e666a MM	22	#include "hw/pci/pci_regs.h"
	23
	24	typedef struct QVirtioPCIForeachData {
	25	void (func)(QVirtioDevice d, void *data);
	26	uint16_t device_type;
	27	void *user_data;
	28	} QVirtioPCIForeachData;
	29
	30	static QVirtioPCIDevice qpcidevice_to_qvirtiodevice(QPCIDevice pdev)
	31	{
	32	QVirtioPCIDevice *vpcidev;
	33	vpcidev = g_malloc0(sizeof(*vpcidev));
	34
	35	if (pdev) {
	36	vpcidev->pdev = pdev;
	37	vpcidev->vdev.device_type =
	38	qpci_config_readw(vpcidev->pdev, PCI_SUBSYSTEM_ID);
	39	}
	40
58368113 MM	41	vpcidev->config_msix_entry = -1;
58368113 MM	42
311e666a MM	43	return vpcidev;
	44	}
	45
	46	static void qvirtio_pci_foreach_callback(
	47	QPCIDevice dev, int devfn, void data)
	48	{
	49	QVirtioPCIForeachData *d = data;
	50	QVirtioPCIDevice *vpcidev = qpcidevice_to_qvirtiodevice(dev);
	51
	52	if (vpcidev->vdev.device_type == d->device_type) {
	53	d->func(&vpcidev->vdev, d->user_data);
	54	} else {
	55	g_free(vpcidev);
	56	}
	57	}
	58
	59	static void qvirtio_pci_assign_device(QVirtioDevice d, void data)
	60	{
	61	QVirtioPCIDevice **vpcidev = data;
	62	vpcidev = (QVirtioPCIDevice )d;
	63	}
	64
246fc0fb DG	65	#define CONFIG_BASE(dev) \
	66	((dev)->addr + VIRTIO_PCI_CONFIG_OFF((dev)->pdev->msix_enabled))
	67
	68	static uint8_t qvirtio_pci_config_readb(QVirtioDevice *d, uint64_t off)
46e0cf76 MM	69	{
46e0cf76 MM	70	QVirtioPCIDevice dev = (QVirtioPCIDevice )d;
246fc0fb	71	return qpci_io_readb(dev->pdev, CONFIG_BASE(dev) + off);
46e0cf76 MM	72	}
46e0cf76 MM	73
30ca440e LV	74	/* PCI is always read in little-endian order
	75	* but virtio ( < 1.0) is in guest order
	76	* so with a big-endian guest the order has been reversed,
	77	* reverse it again
	78	* virtio-1.0 is always little-endian, like PCI, but this
	79	* case will be managed inside qvirtio_is_big_endian()
	80	*/
	81
246fc0fb	82	static uint16_t qvirtio_pci_config_readw(QVirtioDevice *d, uint64_t off)
46e0cf76 MM	83	{
46e0cf76 MM	84	QVirtioPCIDevice dev = (QVirtioPCIDevice )d;
30ca440e LV	85	uint16_t value;
30ca440e LV	86
246fc0fb	87	value = qpci_io_readw(dev->pdev, CONFIG_BASE(dev) + off);
30ca440e LV	88	if (qvirtio_is_big_endian(d)) {
	89	value = bswap16(value);
	90	}
	91	return value;
46e0cf76 MM	92	}
46e0cf76 MM	93
246fc0fb	94	static uint32_t qvirtio_pci_config_readl(QVirtioDevice *d, uint64_t off)
46e0cf76 MM	95	{
46e0cf76 MM	96	QVirtioPCIDevice dev = (QVirtioPCIDevice )d;
30ca440e LV	97	uint32_t value;
30ca440e LV	98
246fc0fb	99	value = qpci_io_readl(dev->pdev, CONFIG_BASE(dev) + off);
30ca440e LV	100	if (qvirtio_is_big_endian(d)) {
	101	value = bswap32(value);
	102	}
	103	return value;
46e0cf76 MM	104	}
46e0cf76 MM	105
246fc0fb	106	static uint64_t qvirtio_pci_config_readq(QVirtioDevice *d, uint64_t off)
46e0cf76 MM	107	{
46e0cf76 MM	108	QVirtioPCIDevice dev = (QVirtioPCIDevice )d;
f775f45a	109	uint64_t val;
46e0cf76	110
f775f45a	111	val = qpci_io_readq(dev->pdev, CONFIG_BASE(dev) + off);
8b4b80c3	112	if (qvirtio_is_big_endian(d)) {
f775f45a	113	val = bswap64(val);
46e0cf76 MM	114	}
46e0cf76 MM	115
f775f45a	116	return val;
46e0cf76 MM	117	}
46e0cf76 MM	118
bf3c63d2 MM	119	static uint32_t qvirtio_pci_get_features(QVirtioDevice *d)
	120	{
	121	QVirtioPCIDevice dev = (QVirtioPCIDevice )d;
c75f4c06	122	return qpci_io_readl(dev->pdev, dev->addr + VIRTIO_PCI_HOST_FEATURES);
bf3c63d2 MM	123	}
	124
	125	static void qvirtio_pci_set_features(QVirtioDevice *d, uint32_t features)
	126	{
	127	QVirtioPCIDevice dev = (QVirtioPCIDevice )d;
c75f4c06	128	qpci_io_writel(dev->pdev, dev->addr + VIRTIO_PCI_GUEST_FEATURES, features);
bf3c63d2 MM	129	}
bf3c63d2 MM	130
f294b029 MM	131	static uint32_t qvirtio_pci_get_guest_features(QVirtioDevice *d)
	132	{
	133	QVirtioPCIDevice dev = (QVirtioPCIDevice )d;
c75f4c06	134	return qpci_io_readl(dev->pdev, dev->addr + VIRTIO_PCI_GUEST_FEATURES);
f294b029 MM	135	}
f294b029 MM	136
46e0cf76 MM	137	static uint8_t qvirtio_pci_get_status(QVirtioDevice *d)
	138	{
	139	QVirtioPCIDevice dev = (QVirtioPCIDevice )d;
c75f4c06	140	return qpci_io_readb(dev->pdev, dev->addr + VIRTIO_PCI_STATUS);
46e0cf76 MM	141	}
	142
	143	static void qvirtio_pci_set_status(QVirtioDevice *d, uint8_t status)
	144	{
	145	QVirtioPCIDevice dev = (QVirtioPCIDevice )d;
c75f4c06	146	qpci_io_writeb(dev->pdev, dev->addr + VIRTIO_PCI_STATUS, status);
46e0cf76 MM	147	}
46e0cf76 MM	148
58368113	149	static bool qvirtio_pci_get_queue_isr_status(QVirtioDevice d, QVirtQueue vq)
bf3c63d2 MM	150	{
bf3c63d2 MM	151	QVirtioPCIDevice dev = (QVirtioPCIDevice )d;
58368113 MM	152	QVirtQueuePCI vqpci = (QVirtQueuePCI )vq;
	153	uint32_t data;
	154
	155	if (dev->pdev->msix_enabled) {
	156	g_assert_cmpint(vqpci->msix_entry, !=, -1);
	157	if (qpci_msix_masked(dev->pdev, vqpci->msix_entry)) {
	158	/* No ISR checking should be done if masked, but read anyway */
	159	return qpci_msix_pending(dev->pdev, vqpci->msix_entry);
	160	} else {
	161	data = readl(vqpci->msix_addr);
1e34cf96 MM	162	if (data == vqpci->msix_data) {
	163	writel(vqpci->msix_addr, 0);
	164	return true;
	165	} else {
	166	return false;
	167	}
58368113 MM	168	}
58368113 MM	169	} else {
c75f4c06	170	return qpci_io_readb(dev->pdev, dev->addr + VIRTIO_PCI_ISR) & 1;
58368113 MM	171	}
	172	}
	173
	174	static bool qvirtio_pci_get_config_isr_status(QVirtioDevice *d)
	175	{
	176	QVirtioPCIDevice dev = (QVirtioPCIDevice )d;
	177	uint32_t data;
	178
	179	if (dev->pdev->msix_enabled) {
	180	g_assert_cmpint(dev->config_msix_entry, !=, -1);
	181	if (qpci_msix_masked(dev->pdev, dev->config_msix_entry)) {
	182	/* No ISR checking should be done if masked, but read anyway */
	183	return qpci_msix_pending(dev->pdev, dev->config_msix_entry);
	184	} else {
	185	data = readl(dev->config_msix_addr);
1e34cf96 MM	186	if (data == dev->config_msix_data) {
	187	writel(dev->config_msix_addr, 0);
	188	return true;
	189	} else {
	190	return false;
	191	}
58368113 MM	192	}
58368113 MM	193	} else {
c75f4c06	194	return qpci_io_readb(dev->pdev, dev->addr + VIRTIO_PCI_ISR) & 2;
58368113	195	}
bf3c63d2 MM	196	}
	197
	198	static void qvirtio_pci_queue_select(QVirtioDevice *d, uint16_t index)
	199	{
	200	QVirtioPCIDevice dev = (QVirtioPCIDevice )d;
c75f4c06	201	qpci_io_writeb(dev->pdev, dev->addr + VIRTIO_PCI_QUEUE_SEL, index);
bf3c63d2 MM	202	}
	203
	204	static uint16_t qvirtio_pci_get_queue_size(QVirtioDevice *d)
	205	{
	206	QVirtioPCIDevice dev = (QVirtioPCIDevice )d;
c75f4c06	207	return qpci_io_readw(dev->pdev, dev->addr + VIRTIO_PCI_QUEUE_NUM);
bf3c63d2 MM	208	}
	209
	210	static void qvirtio_pci_set_queue_address(QVirtioDevice *d, uint32_t pfn)
	211	{
	212	QVirtioPCIDevice dev = (QVirtioPCIDevice )d;
c75f4c06	213	qpci_io_writel(dev->pdev, dev->addr + VIRTIO_PCI_QUEUE_PFN, pfn);
bf3c63d2 MM	214	}
	215
	216	static QVirtQueue qvirtio_pci_virtqueue_setup(QVirtioDevice d,
	217	QGuestAllocator *alloc, uint16_t index)
	218	{
f294b029	219	uint32_t feat;
bf3c63d2	220	uint64_t addr;
58368113	221	QVirtQueuePCI *vqpci;
bf3c63d2	222
58368113	223	vqpci = g_malloc0(sizeof(*vqpci));
f294b029	224	feat = qvirtio_pci_get_guest_features(d);
bf3c63d2 MM	225
bf3c63d2 MM	226	qvirtio_pci_queue_select(d, index);
58368113 MM	227	vqpci->vq.index = index;
	228	vqpci->vq.size = qvirtio_pci_get_queue_size(d);
	229	vqpci->vq.free_head = 0;
	230	vqpci->vq.num_free = vqpci->vq.size;
c75f4c06	231	vqpci->vq.align = VIRTIO_PCI_VRING_ALIGN;
ee3b850a SH	232	vqpci->vq.indirect = (feat & (1u << VIRTIO_RING_F_INDIRECT_DESC)) != 0;
ee3b850a SH	233	vqpci->vq.event = (feat & (1u << VIRTIO_RING_F_EVENT_IDX)) != 0;
58368113 MM	234
	235	vqpci->msix_entry = -1;
	236	vqpci->msix_addr = 0;
	237	vqpci->msix_data = 0x12345678;
bf3c63d2 MM	238
bf3c63d2 MM	239	/* Check different than 0 */
58368113	240	g_assert_cmpint(vqpci->vq.size, !=, 0);
bf3c63d2 MM	241
bf3c63d2 MM	242	/* Check power of 2 */
58368113	243	g_assert_cmpint(vqpci->vq.size & (vqpci->vq.size - 1), ==, 0);
bf3c63d2	244
c75f4c06 SH	245	addr = guest_alloc(alloc, qvring_size(vqpci->vq.size,
c75f4c06 SH	246	VIRTIO_PCI_VRING_ALIGN));
58368113	247	qvring_init(alloc, &vqpci->vq, addr);
c75f4c06	248	qvirtio_pci_set_queue_address(d, vqpci->vq.desc / VIRTIO_PCI_VRING_ALIGN);
bf3c63d2	249
58368113	250	return &vqpci->vq;
bf3c63d2 MM	251	}
bf3c63d2 MM	252
f1d3b991 SH	253	static void qvirtio_pci_virtqueue_cleanup(QVirtQueue *vq,
	254	QGuestAllocator *alloc)
	255	{
	256	QVirtQueuePCI *vqpci = container_of(vq, QVirtQueuePCI, vq);
	257
	258	guest_free(alloc, vq->desc);
	259	g_free(vqpci);
	260	}
	261
bf3c63d2 MM	262	static void qvirtio_pci_virtqueue_kick(QVirtioDevice d, QVirtQueue vq)
	263	{
	264	QVirtioPCIDevice dev = (QVirtioPCIDevice )d;
c75f4c06	265	qpci_io_writew(dev->pdev, dev->addr + VIRTIO_PCI_QUEUE_NOTIFY, vq->index);
bf3c63d2 MM	266	}
bf3c63d2 MM	267
46e0cf76 MM	268	const QVirtioBus qvirtio_pci = {
	269	.config_readb = qvirtio_pci_config_readb,
	270	.config_readw = qvirtio_pci_config_readw,
	271	.config_readl = qvirtio_pci_config_readl,
	272	.config_readq = qvirtio_pci_config_readq,
bf3c63d2 MM	273	.get_features = qvirtio_pci_get_features,
bf3c63d2 MM	274	.set_features = qvirtio_pci_set_features,
f294b029	275	.get_guest_features = qvirtio_pci_get_guest_features,
46e0cf76 MM	276	.get_status = qvirtio_pci_get_status,
46e0cf76 MM	277	.set_status = qvirtio_pci_set_status,
58368113 MM	278	.get_queue_isr_status = qvirtio_pci_get_queue_isr_status,
58368113 MM	279	.get_config_isr_status = qvirtio_pci_get_config_isr_status,
bf3c63d2 MM	280	.queue_select = qvirtio_pci_queue_select,
	281	.get_queue_size = qvirtio_pci_get_queue_size,
	282	.set_queue_address = qvirtio_pci_set_queue_address,
	283	.virtqueue_setup = qvirtio_pci_virtqueue_setup,
f1d3b991	284	.virtqueue_cleanup = qvirtio_pci_virtqueue_cleanup,
bf3c63d2	285	.virtqueue_kick = qvirtio_pci_virtqueue_kick,
46e0cf76 MM	286	};
46e0cf76 MM	287
311e666a MM	288	void qvirtio_pci_foreach(QPCIBus *bus, uint16_t device_type,
	289	void (func)(QVirtioDevice d, void data), void data)
	290	{
	291	QVirtioPCIForeachData d = { .func = func,
	292	.device_type = device_type,
	293	.user_data = data };
	294
7ad1e708	295	qpci_device_foreach(bus, PCI_VENDOR_ID_REDHAT_QUMRANET, -1,
311e666a MM	296	qvirtio_pci_foreach_callback, &d);
	297	}
	298
	299	QVirtioPCIDevice qvirtio_pci_device_find(QPCIBus bus, uint16_t device_type)
	300	{
	301	QVirtioPCIDevice *dev = NULL;
	302	qvirtio_pci_foreach(bus, device_type, qvirtio_pci_assign_device, &dev);
	303
6b9cdf4c LV	304	dev->vdev.bus = &qvirtio_pci;
6b9cdf4c LV	305
311e666a MM	306	return dev;
311e666a MM	307	}
46e0cf76 MM	308
	309	void qvirtio_pci_device_enable(QVirtioPCIDevice *d)
	310	{
	311	qpci_device_enable(d->pdev);
	312	d->addr = qpci_iomap(d->pdev, 0, NULL);
	313	g_assert(d->addr != NULL);
	314	}
	315
	316	void qvirtio_pci_device_disable(QVirtioPCIDevice *d)
	317	{
	318	qpci_iounmap(d->pdev, d->addr);
58368113 MM	319	d->addr = NULL;
	320	}
	321
	322	void qvirtqueue_pci_msix_setup(QVirtioPCIDevice d, QVirtQueuePCI vqpci,
	323	QGuestAllocator *alloc, uint16_t entry)
	324	{
	325	uint16_t vector;
	326	uint32_t control;
	327	void *addr;
	328
	329	g_assert(d->pdev->msix_enabled);
	330	addr = d->pdev->msix_table + (entry * 16);
	331
	332	g_assert_cmpint(entry, >=, 0);
	333	g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
	334	vqpci->msix_entry = entry;
	335
	336	vqpci->msix_addr = guest_alloc(alloc, 4);
	337	qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_LOWER_ADDR,
	338	vqpci->msix_addr & ~0UL);
	339	qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_UPPER_ADDR,
	340	(vqpci->msix_addr >> 32) & ~0UL);
	341	qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_DATA, vqpci->msix_data);
	342
	343	control = qpci_io_readl(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
	344	qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL,
	345	control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
	346
	347	qvirtio_pci_queue_select(&d->vdev, vqpci->vq.index);
c75f4c06 SH	348	qpci_io_writew(d->pdev, d->addr + VIRTIO_MSI_QUEUE_VECTOR, entry);
	349	vector = qpci_io_readw(d->pdev, d->addr + VIRTIO_MSI_QUEUE_VECTOR);
	350	g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
58368113 MM	351	}
	352
	353	void qvirtio_pci_set_msix_configuration_vector(QVirtioPCIDevice *d,
	354	QGuestAllocator *alloc, uint16_t entry)
	355	{
	356	uint16_t vector;
	357	uint32_t control;
	358	void *addr;
	359
	360	g_assert(d->pdev->msix_enabled);
	361	addr = d->pdev->msix_table + (entry * 16);
	362
	363	g_assert_cmpint(entry, >=, 0);
	364	g_assert_cmpint(entry, <, qpci_msix_table_size(d->pdev));
	365	d->config_msix_entry = entry;
	366
	367	d->config_msix_data = 0x12345678;
	368	d->config_msix_addr = guest_alloc(alloc, 4);
	369
	370	qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_LOWER_ADDR,
	371	d->config_msix_addr & ~0UL);
	372	qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_UPPER_ADDR,
	373	(d->config_msix_addr >> 32) & ~0UL);
	374	qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_DATA, d->config_msix_data);
	375
	376	control = qpci_io_readl(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL);
	377	qpci_io_writel(d->pdev, addr + PCI_MSIX_ENTRY_VECTOR_CTRL,
	378	control & ~PCI_MSIX_ENTRY_CTRL_MASKBIT);
	379
c75f4c06 SH	380	qpci_io_writew(d->pdev, d->addr + VIRTIO_MSI_CONFIG_VECTOR, entry);
	381	vector = qpci_io_readw(d->pdev, d->addr + VIRTIO_MSI_CONFIG_VECTOR);
	382	g_assert_cmphex(vector, !=, VIRTIO_MSI_NO_VECTOR);
46e0cf76	383	}