[mirror_qemu.git] / tests / tco-test.c

/*
 * QEMU ICH9 TCO emulation tests
 *
 * Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 */

#include "qemu/osdep.h"

#include "libqtest.h"
#include "libqos/pci.h"
#include "libqos/pci-pc.h"
#include "qapi/qmp/qdict.h"
#include "hw/pci/pci_regs.h"
#include "hw/i386/ich9.h"
#include "hw/acpi/ich9.h"
#include "hw/acpi/tco.h"

#define RCBA_BASE_ADDR    0xfed1c000
#define PM_IO_BASE_ADDR   0xb000

enum {
    TCO_RLD_DEFAULT         = 0x0000,
    TCO_DAT_IN_DEFAULT      = 0x00,
    TCO_DAT_OUT_DEFAULT     = 0x00,
    TCO1_STS_DEFAULT        = 0x0000,
    TCO2_STS_DEFAULT        = 0x0000,
    TCO1_CNT_DEFAULT        = 0x0000,
    TCO2_CNT_DEFAULT        = 0x0008,
    TCO_MESSAGE1_DEFAULT    = 0x00,
    TCO_MESSAGE2_DEFAULT    = 0x00,
    TCO_WDCNT_DEFAULT       = 0x00,
    TCO_TMR_DEFAULT         = 0x0004,
    SW_IRQ_GEN_DEFAULT      = 0x03,
};

#define TCO_SECS_TO_TICKS(secs)     (((secs) * 10) / 6)
#define TCO_TICKS_TO_SECS(ticks)    (((ticks) * 6) / 10)

typedef struct {
    const char *args;
    bool noreboot;
    QPCIDevice *dev;
    QPCIBar tco_io_bar;
    QPCIBus *bus;
} TestData;

static void test_end(TestData *d)
{
    g_free(d->dev);
    qpci_free_pc(d->bus);
    qtest_end();
}

static void test_init(TestData *d)
{
    QTestState *qs;

    qs = qtest_initf("-machine q35 %s %s",
                     d->noreboot ? "" : "-global ICH9-LPC.noreboot=false",
                     !d->args ? "" : d->args);
    global_qtest = qs;
    qtest_irq_intercept_in(qs, "ioapic");

    d->bus = qpci_new_pc(qs, NULL);
    d->dev = qpci_device_find(d->bus, QPCI_DEVFN(0x1f, 0x00));
    g_assert(d->dev != NULL);

    qpci_device_enable(d->dev);

    /* set ACPI PM I/O space base address */
    qpci_config_writel(d->dev, ICH9_LPC_PMBASE, PM_IO_BASE_ADDR | 0x1);
    /* enable ACPI I/O */
    qpci_config_writeb(d->dev, ICH9_LPC_ACPI_CTRL, 0x80);
    /* set Root Complex BAR */
    qpci_config_writel(d->dev, ICH9_LPC_RCBA, RCBA_BASE_ADDR | 0x1);

    d->tco_io_bar = qpci_legacy_iomap(d->dev, PM_IO_BASE_ADDR + 0x60);
}

static void stop_tco(const TestData *d)
{
    uint32_t val;

    val = qpci_io_readw(d->dev, d->tco_io_bar, TCO1_CNT);
    val |= TCO_TMR_HLT;
    qpci_io_writew(d->dev, d->tco_io_bar, TCO1_CNT, val);
}

static void start_tco(const TestData *d)
{
    uint32_t val;

    val = qpci_io_readw(d->dev, d->tco_io_bar, TCO1_CNT);
    val &= ~TCO_TMR_HLT;
    qpci_io_writew(d->dev, d->tco_io_bar, TCO1_CNT, val);
}

static void load_tco(const TestData *d)
{
    qpci_io_writew(d->dev, d->tco_io_bar, TCO_RLD, 4);
}

static void set_tco_timeout(const TestData *d, uint16_t ticks)
{
    qpci_io_writew(d->dev, d->tco_io_bar, TCO_TMR, ticks);
}

static void clear_tco_status(const TestData *d)
{
    qpci_io_writew(d->dev, d->tco_io_bar, TCO1_STS, 0x0008);
    qpci_io_writew(d->dev, d->tco_io_bar, TCO2_STS, 0x0002);
    qpci_io_writew(d->dev, d->tco_io_bar, TCO2_STS, 0x0004);
}

static void reset_on_second_timeout(bool enable)
{
    uint32_t val;

    val = readl(RCBA_BASE_ADDR + ICH9_CC_GCS);
    if (enable) {
        val &= ~ICH9_CC_GCS_NO_REBOOT;
    } else {
        val |= ICH9_CC_GCS_NO_REBOOT;
    }
    writel(RCBA_BASE_ADDR + ICH9_CC_GCS, val);
}

static void test_tco_defaults(void)
{
    TestData d;

    d.args = NULL;
    d.noreboot = true;
    test_init(&d);
    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD), ==,
                    TCO_RLD_DEFAULT);
    /* TCO_DAT_IN & TCO_DAT_OUT */
    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_DAT_IN), ==,
                    (TCO_DAT_OUT_DEFAULT << 8) | TCO_DAT_IN_DEFAULT);
    /* TCO1_STS & TCO2_STS */
    g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_bar, TCO1_STS), ==,
                    (TCO2_STS_DEFAULT << 16) | TCO1_STS_DEFAULT);
    /* TCO1_CNT & TCO2_CNT */
    g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_bar, TCO1_CNT), ==,
                    (TCO2_CNT_DEFAULT << 16) | TCO1_CNT_DEFAULT);
    /* TCO_MESSAGE1 & TCO_MESSAGE2 */
    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_MESSAGE1), ==,
                    (TCO_MESSAGE2_DEFAULT << 8) | TCO_MESSAGE1_DEFAULT);
    g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_bar, TCO_WDCNT), ==,
                    TCO_WDCNT_DEFAULT);
    g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_bar, SW_IRQ_GEN), ==,
                    SW_IRQ_GEN_DEFAULT);
    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_TMR), ==,
                    TCO_TMR_DEFAULT);
    test_end(&d);
}

static void test_tco_timeout(void)
{
    TestData d;
    const uint16_t ticks = TCO_SECS_TO_TICKS(4);
    uint32_t val;
    int ret;

    d.args = NULL;
    d.noreboot = true;
    test_init(&d);

    stop_tco(&d);
    clear_tco_status(&d);
    reset_on_second_timeout(false);
    set_tco_timeout(&d, ticks);
    load_tco(&d);
    start_tco(&d);
    clock_step(ticks * TCO_TICK_NSEC);

    /* test first timeout */
    val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
    ret = val & TCO_TIMEOUT ? 1 : 0;
    g_assert(ret == 1);

    /* test clearing timeout bit */
    val |= TCO_TIMEOUT;
    qpci_io_writew(d.dev, d.tco_io_bar, TCO1_STS, val);
    val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
    ret = val & TCO_TIMEOUT ? 1 : 0;
    g_assert(ret == 0);

    /* test second timeout */
    clock_step(ticks * TCO_TICK_NSEC);
    val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
    ret = val & TCO_TIMEOUT ? 1 : 0;
    g_assert(ret == 1);
    val = qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS);
    ret = val & TCO_SECOND_TO_STS ? 1 : 0;
    g_assert(ret == 1);

    stop_tco(&d);
    test_end(&d);
}

static void test_tco_max_timeout(void)
{
    TestData d;
    const uint16_t ticks = 0xffff;
    uint32_t val;
    int ret;

    d.args = NULL;
    d.noreboot = true;
    test_init(&d);

    stop_tco(&d);
    clear_tco_status(&d);
    reset_on_second_timeout(false);
    set_tco_timeout(&d, ticks);
    load_tco(&d);
    start_tco(&d);
    clock_step(((ticks & TCO_TMR_MASK) - 1) * TCO_TICK_NSEC);

    val = qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD);
    g_assert_cmpint(val & TCO_RLD_MASK, ==, 1);
    val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
    ret = val & TCO_TIMEOUT ? 1 : 0;
    g_assert(ret == 0);
    clock_step(TCO_TICK_NSEC);
    val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
    ret = val & TCO_TIMEOUT ? 1 : 0;
    g_assert(ret == 1);

    stop_tco(&d);
    test_end(&d);
}

static QDict *get_watchdog_action(void)
{
    QDict *ev = qmp_eventwait_ref("WATCHDOG");
    QDict *data;

    data = qdict_get_qdict(ev, "data");
    qobject_ref(data);
    qobject_unref(ev);
    return data;
}

static void test_tco_second_timeout_pause(void)
{
    TestData td;
    const uint16_t ticks = TCO_SECS_TO_TICKS(32);
    QDict *ad;

    td.args = "-watchdog-action pause";
    td.noreboot = false;
    test_init(&td);

    stop_tco(&td);
    clear_tco_status(&td);
    reset_on_second_timeout(true);
    set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
    load_tco(&td);
    start_tco(&td);
    clock_step(ticks * TCO_TICK_NSEC * 2);
    ad = get_watchdog_action();
    g_assert(!strcmp(qdict_get_str(ad, "action"), "pause"));
    qobject_unref(ad);

    stop_tco(&td);
    test_end(&td);
}

static void test_tco_second_timeout_reset(void)
{
    TestData td;
    const uint16_t ticks = TCO_SECS_TO_TICKS(16);
    QDict *ad;

    td.args = "-watchdog-action reset";
    td.noreboot = false;
    test_init(&td);

    stop_tco(&td);
    clear_tco_status(&td);
    reset_on_second_timeout(true);
    set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
    load_tco(&td);
    start_tco(&td);
    clock_step(ticks * TCO_TICK_NSEC * 2);
    ad = get_watchdog_action();
    g_assert(!strcmp(qdict_get_str(ad, "action"), "reset"));
    qobject_unref(ad);

    stop_tco(&td);
    test_end(&td);
}

static void test_tco_second_timeout_shutdown(void)
{
    TestData td;
    const uint16_t ticks = TCO_SECS_TO_TICKS(128);
    QDict *ad;

    td.args = "-watchdog-action shutdown";
    td.noreboot = false;
    test_init(&td);

    stop_tco(&td);
    clear_tco_status(&td);
    reset_on_second_timeout(true);
    set_tco_timeout(&td, ticks);
    load_tco(&td);
    start_tco(&td);
    clock_step(ticks * TCO_TICK_NSEC * 2);
    ad = get_watchdog_action();
    g_assert(!strcmp(qdict_get_str(ad, "action"), "shutdown"));
    qobject_unref(ad);

    stop_tco(&td);
    test_end(&td);
}

static void test_tco_second_timeout_none(void)
{
    TestData td;
    const uint16_t ticks = TCO_SECS_TO_TICKS(256);
    QDict *ad;

    td.args = "-watchdog-action none";
    td.noreboot = false;
    test_init(&td);

    stop_tco(&td);
    clear_tco_status(&td);
    reset_on_second_timeout(true);
    set_tco_timeout(&td, ticks);
    load_tco(&td);
    start_tco(&td);
    clock_step(ticks * TCO_TICK_NSEC * 2);
    ad = get_watchdog_action();
    g_assert(!strcmp(qdict_get_str(ad, "action"), "none"));
    qobject_unref(ad);

    stop_tco(&td);
    test_end(&td);
}

static void test_tco_ticks_counter(void)
{
    TestData d;
    uint16_t ticks = TCO_SECS_TO_TICKS(8);
    uint16_t rld;

    d.args = NULL;
    d.noreboot = true;
    test_init(&d);

    stop_tco(&d);
    clear_tco_status(&d);
    reset_on_second_timeout(false);
    set_tco_timeout(&d, ticks);
    load_tco(&d);
    start_tco(&d);

    do {
        rld = qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD) & TCO_RLD_MASK;
        g_assert_cmpint(rld, ==, ticks);
        clock_step(TCO_TICK_NSEC);
        ticks--;
    } while (!(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS) & TCO_TIMEOUT));

    stop_tco(&d);
    test_end(&d);
}

static void test_tco1_control_bits(void)
{
    TestData d;
    uint16_t val;

    d.args = NULL;
    d.noreboot = true;
    test_init(&d);

    val = TCO_LOCK;
    qpci_io_writew(d.dev, d.tco_io_bar, TCO1_CNT, val);
    val &= ~TCO_LOCK;
    qpci_io_writew(d.dev, d.tco_io_bar, TCO1_CNT, val);
    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_CNT), ==,
                    TCO_LOCK);
    test_end(&d);
}

static void test_tco1_status_bits(void)
{
    TestData d;
    uint16_t ticks = 8;
    uint16_t val;
    int ret;

    d.args = NULL;
    d.noreboot = true;
    test_init(&d);

    stop_tco(&d);
    clear_tco_status(&d);
    reset_on_second_timeout(false);
    set_tco_timeout(&d, ticks);
    load_tco(&d);
    start_tco(&d);
    clock_step(ticks * TCO_TICK_NSEC);

    qpci_io_writeb(d.dev, d.tco_io_bar, TCO_DAT_IN, 0);
    qpci_io_writeb(d.dev, d.tco_io_bar, TCO_DAT_OUT, 0);
    val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
    ret = val & (TCO_TIMEOUT | SW_TCO_SMI | TCO_INT_STS) ? 1 : 0;
    g_assert(ret == 1);
    qpci_io_writew(d.dev, d.tco_io_bar, TCO1_STS, val);
    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS), ==, 0);
    test_end(&d);
}

static void test_tco2_status_bits(void)
{
    TestData d;
    uint16_t ticks = 8;
    uint16_t val;
    int ret;

    d.args = NULL;
    d.noreboot = true;
    test_init(&d);

    stop_tco(&d);
    clear_tco_status(&d);
    reset_on_second_timeout(true);
    set_tco_timeout(&d, ticks);
    load_tco(&d);
    start_tco(&d);
    clock_step(ticks * TCO_TICK_NSEC * 2);

    val = qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS);
    ret = val & (TCO_SECOND_TO_STS | TCO_BOOT_STS) ? 1 : 0;
    g_assert(ret == 1);
    qpci_io_writew(d.dev, d.tco_io_bar, TCO2_STS, val);
    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS), ==, 0);
    test_end(&d);
}

int main(int argc, char **argv)
{
    g_test_init(&argc, &argv, NULL);

    qtest_add_func("tco/defaults", test_tco_defaults);
    qtest_add_func("tco/timeout/no_action", test_tco_timeout);
    qtest_add_func("tco/timeout/no_action/max", test_tco_max_timeout);
    qtest_add_func("tco/second_timeout/pause", test_tco_second_timeout_pause);
    qtest_add_func("tco/second_timeout/reset", test_tco_second_timeout_reset);
    qtest_add_func("tco/second_timeout/shutdown",
                   test_tco_second_timeout_shutdown);
    qtest_add_func("tco/second_timeout/none", test_tco_second_timeout_none);
    qtest_add_func("tco/counter", test_tco_ticks_counter);
    qtest_add_func("tco/tco1_control/bits", test_tco1_control_bits);
    qtest_add_func("tco/tco1_status/bits", test_tco1_status_bits);
    qtest_add_func("tco/tco2_status/bits", test_tco2_status_bits);
    return g_test_run();
}
Commit	Line	Data
45dcdb9d PA	1	/*
	2	* QEMU ICH9 TCO emulation tests
	3	*
	4	* Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
	5	*
	6	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	7	* See the COPYING file in the top-level directory.
	8	*/
452fcdbc	9
681c28a3	10	#include "qemu/osdep.h"
45dcdb9d PA	11
	12	#include "libqtest.h"
	13	#include "libqos/pci.h"
	14	#include "libqos/pci-pc.h"
452fcdbc	15	#include "qapi/qmp/qdict.h"
45dcdb9d PA	16	#include "hw/pci/pci_regs.h"
	17	#include "hw/i386/ich9.h"
	18	#include "hw/acpi/ich9.h"
	19	#include "hw/acpi/tco.h"
	20
	21	#define RCBA_BASE_ADDR 0xfed1c000
	22	#define PM_IO_BASE_ADDR 0xb000
	23
	24	enum {
	25	TCO_RLD_DEFAULT = 0x0000,
	26	TCO_DAT_IN_DEFAULT = 0x00,
	27	TCO_DAT_OUT_DEFAULT = 0x00,
	28	TCO1_STS_DEFAULT = 0x0000,
	29	TCO2_STS_DEFAULT = 0x0000,
	30	TCO1_CNT_DEFAULT = 0x0000,
	31	TCO2_CNT_DEFAULT = 0x0008,
	32	TCO_MESSAGE1_DEFAULT = 0x00,
	33	TCO_MESSAGE2_DEFAULT = 0x00,
	34	TCO_WDCNT_DEFAULT = 0x00,
	35	TCO_TMR_DEFAULT = 0x0004,
	36	SW_IRQ_GEN_DEFAULT = 0x03,
	37	};
	38
	39	#define TCO_SECS_TO_TICKS(secs) (((secs) * 10) / 6)
	40	#define TCO_TICKS_TO_SECS(ticks) (((ticks) * 6) / 10)
	41
	42	typedef struct {
	43	const char *args;
5add35be	44	bool noreboot;
45dcdb9d	45	QPCIDevice *dev;
b4ba67d9	46	QPCIBar tco_io_bar;
34779e8c	47	QPCIBus *bus;
45dcdb9d PA	48	} TestData;
45dcdb9d PA	49
34779e8c MAL	50	static void test_end(TestData *d)
	51	{
	52	g_free(d->dev);
	53	qpci_free_pc(d->bus);
	54	qtest_end();
	55	}
	56
45dcdb9d PA	57	static void test_init(TestData *d)
45dcdb9d PA	58	{
45dcdb9d	59	QTestState *qs;
45dcdb9d	60
88b988c8 MA	61	qs = qtest_initf("-machine q35 %s %s",
	62	d->noreboot ? "" : "-global ICH9-LPC.noreboot=false",
	63	!d->args ? "" : d->args);
78b27bad	64	global_qtest = qs;
45dcdb9d	65	qtest_irq_intercept_in(qs, "ioapic");
45dcdb9d	66
143e6db6	67	d->bus = qpci_new_pc(qs, NULL);
34779e8c	68	d->dev = qpci_device_find(d->bus, QPCI_DEVFN(0x1f, 0x00));
45dcdb9d PA	69	g_assert(d->dev != NULL);
45dcdb9d PA	70
45dcdb9d PA	71	qpci_device_enable(d->dev);
45dcdb9d PA	72
45dcdb9d	73	/* set ACPI PM I/O space base address */
c4fc82bf	74	qpci_config_writel(d->dev, ICH9_LPC_PMBASE, PM_IO_BASE_ADDR \| 0x1);
45dcdb9d	75	/* enable ACPI I/O */
c4fc82bf	76	qpci_config_writeb(d->dev, ICH9_LPC_ACPI_CTRL, 0x80);
45dcdb9d	77	/* set Root Complex BAR */
c4fc82bf	78	qpci_config_writel(d->dev, ICH9_LPC_RCBA, RCBA_BASE_ADDR \| 0x1);
45dcdb9d	79
b4ba67d9	80	d->tco_io_bar = qpci_legacy_iomap(d->dev, PM_IO_BASE_ADDR + 0x60);
45dcdb9d PA	81	}
	82
	83	static void stop_tco(const TestData *d)
	84	{
	85	uint32_t val;
	86
b4ba67d9	87	val = qpci_io_readw(d->dev, d->tco_io_bar, TCO1_CNT);
45dcdb9d	88	val \|= TCO_TMR_HLT;
b4ba67d9	89	qpci_io_writew(d->dev, d->tco_io_bar, TCO1_CNT, val);
45dcdb9d PA	90	}
	91
	92	static void start_tco(const TestData *d)
	93	{
	94	uint32_t val;
	95
b4ba67d9	96	val = qpci_io_readw(d->dev, d->tco_io_bar, TCO1_CNT);
45dcdb9d	97	val &= ~TCO_TMR_HLT;
b4ba67d9	98	qpci_io_writew(d->dev, d->tco_io_bar, TCO1_CNT, val);
45dcdb9d PA	99	}
	100
	101	static void load_tco(const TestData *d)
	102	{
b4ba67d9	103	qpci_io_writew(d->dev, d->tco_io_bar, TCO_RLD, 4);
45dcdb9d PA	104	}
	105
	106	static void set_tco_timeout(const TestData *d, uint16_t ticks)
	107	{
b4ba67d9	108	qpci_io_writew(d->dev, d->tco_io_bar, TCO_TMR, ticks);
45dcdb9d PA	109	}
	110
	111	static void clear_tco_status(const TestData *d)
	112	{
b4ba67d9 DG	113	qpci_io_writew(d->dev, d->tco_io_bar, TCO1_STS, 0x0008);
	114	qpci_io_writew(d->dev, d->tco_io_bar, TCO2_STS, 0x0002);
	115	qpci_io_writew(d->dev, d->tco_io_bar, TCO2_STS, 0x0004);
45dcdb9d PA	116	}
	117
	118	static void reset_on_second_timeout(bool enable)
	119	{
	120	uint32_t val;
	121
	122	val = readl(RCBA_BASE_ADDR + ICH9_CC_GCS);
	123	if (enable) {
	124	val &= ~ICH9_CC_GCS_NO_REBOOT;
	125	} else {
	126	val \|= ICH9_CC_GCS_NO_REBOOT;
	127	}
	128	writel(RCBA_BASE_ADDR + ICH9_CC_GCS, val);
	129	}
	130
	131	static void test_tco_defaults(void)
	132	{
	133	TestData d;
	134
	135	d.args = NULL;
5add35be	136	d.noreboot = true;
45dcdb9d	137	test_init(&d);
b4ba67d9	138	g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD), ==,
45dcdb9d PA	139	TCO_RLD_DEFAULT);
45dcdb9d PA	140	/* TCO_DAT_IN & TCO_DAT_OUT */
b4ba67d9	141	g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_DAT_IN), ==,
45dcdb9d PA	142	(TCO_DAT_OUT_DEFAULT << 8) \| TCO_DAT_IN_DEFAULT);
45dcdb9d PA	143	/* TCO1_STS & TCO2_STS */
b4ba67d9	144	g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_bar, TCO1_STS), ==,
45dcdb9d PA	145	(TCO2_STS_DEFAULT << 16) \| TCO1_STS_DEFAULT);
45dcdb9d PA	146	/* TCO1_CNT & TCO2_CNT */
b4ba67d9	147	g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_bar, TCO1_CNT), ==,
45dcdb9d PA	148	(TCO2_CNT_DEFAULT << 16) \| TCO1_CNT_DEFAULT);
45dcdb9d PA	149	/* TCO_MESSAGE1 & TCO_MESSAGE2 */
b4ba67d9	150	g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_MESSAGE1), ==,
45dcdb9d	151	(TCO_MESSAGE2_DEFAULT << 8) \| TCO_MESSAGE1_DEFAULT);
b4ba67d9	152	g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_bar, TCO_WDCNT), ==,
45dcdb9d	153	TCO_WDCNT_DEFAULT);
b4ba67d9	154	g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_bar, SW_IRQ_GEN), ==,
45dcdb9d	155	SW_IRQ_GEN_DEFAULT);
b4ba67d9	156	g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO_TMR), ==,
45dcdb9d	157	TCO_TMR_DEFAULT);
34779e8c	158	test_end(&d);
45dcdb9d PA	159	}
	160
	161	static void test_tco_timeout(void)
	162	{
	163	TestData d;
	164	const uint16_t ticks = TCO_SECS_TO_TICKS(4);
	165	uint32_t val;
	166	int ret;
	167
	168	d.args = NULL;
5add35be	169	d.noreboot = true;
45dcdb9d PA	170	test_init(&d);
	171
	172	stop_tco(&d);
	173	clear_tco_status(&d);
	174	reset_on_second_timeout(false);
	175	set_tco_timeout(&d, ticks);
	176	load_tco(&d);
	177	start_tco(&d);
	178	clock_step(ticks * TCO_TICK_NSEC);
	179
	180	/* test first timeout */
b4ba67d9	181	val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
45dcdb9d PA	182	ret = val & TCO_TIMEOUT ? 1 : 0;
	183	g_assert(ret == 1);
	184
	185	/* test clearing timeout bit */
	186	val \|= TCO_TIMEOUT;
b4ba67d9 DG	187	qpci_io_writew(d.dev, d.tco_io_bar, TCO1_STS, val);
b4ba67d9 DG	188	val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
45dcdb9d PA	189	ret = val & TCO_TIMEOUT ? 1 : 0;
	190	g_assert(ret == 0);
	191
	192	/* test second timeout */
	193	clock_step(ticks * TCO_TICK_NSEC);
b4ba67d9	194	val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
45dcdb9d PA	195	ret = val & TCO_TIMEOUT ? 1 : 0;
45dcdb9d PA	196	g_assert(ret == 1);
b4ba67d9	197	val = qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS);
45dcdb9d PA	198	ret = val & TCO_SECOND_TO_STS ? 1 : 0;
	199	g_assert(ret == 1);
	200
	201	stop_tco(&d);
34779e8c	202	test_end(&d);
45dcdb9d PA	203	}
	204
	205	static void test_tco_max_timeout(void)
	206	{
	207	TestData d;
	208	const uint16_t ticks = 0xffff;
	209	uint32_t val;
	210	int ret;
	211
	212	d.args = NULL;
5add35be	213	d.noreboot = true;
45dcdb9d PA	214	test_init(&d);
	215
	216	stop_tco(&d);
	217	clear_tco_status(&d);
	218	reset_on_second_timeout(false);
	219	set_tco_timeout(&d, ticks);
	220	load_tco(&d);
	221	start_tco(&d);
	222	clock_step(((ticks & TCO_TMR_MASK) - 1) * TCO_TICK_NSEC);
	223
b4ba67d9	224	val = qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD);
45dcdb9d	225	g_assert_cmpint(val & TCO_RLD_MASK, ==, 1);
b4ba67d9	226	val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
45dcdb9d PA	227	ret = val & TCO_TIMEOUT ? 1 : 0;
	228	g_assert(ret == 0);
	229	clock_step(TCO_TICK_NSEC);
b4ba67d9	230	val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
45dcdb9d PA	231	ret = val & TCO_TIMEOUT ? 1 : 0;
	232	g_assert(ret == 1);
	233
	234	stop_tco(&d);
34779e8c	235	test_end(&d);
45dcdb9d PA	236	}
	237
	238	static QDict *get_watchdog_action(void)
	239	{
2c58c27b	240	QDict *ev = qmp_eventwait_ref("WATCHDOG");
45dcdb9d	241	QDict *data;
45dcdb9d PA	242
45dcdb9d PA	243	data = qdict_get_qdict(ev, "data");
cb3e7f08 MAL	244	qobject_ref(data);
cb3e7f08 MAL	245	qobject_unref(ev);
45dcdb9d PA	246	return data;
	247	}
	248
	249	static void test_tco_second_timeout_pause(void)
	250	{
	251	TestData td;
	252	const uint16_t ticks = TCO_SECS_TO_TICKS(32);
	253	QDict *ad;
	254
	255	td.args = "-watchdog-action pause";
5add35be	256	td.noreboot = false;
45dcdb9d PA	257	test_init(&td);
	258
	259	stop_tco(&td);
	260	clear_tco_status(&td);
	261	reset_on_second_timeout(true);
	262	set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
	263	load_tco(&td);
	264	start_tco(&td);
	265	clock_step(ticks * TCO_TICK_NSEC * 2);
	266	ad = get_watchdog_action();
	267	g_assert(!strcmp(qdict_get_str(ad, "action"), "pause"));
cb3e7f08	268	qobject_unref(ad);
45dcdb9d PA	269
45dcdb9d PA	270	stop_tco(&td);
34779e8c	271	test_end(&td);
45dcdb9d PA	272	}
	273
	274	static void test_tco_second_timeout_reset(void)
	275	{
	276	TestData td;
	277	const uint16_t ticks = TCO_SECS_TO_TICKS(16);
	278	QDict *ad;
	279
	280	td.args = "-watchdog-action reset";
5add35be	281	td.noreboot = false;
45dcdb9d PA	282	test_init(&td);
	283
	284	stop_tco(&td);
	285	clear_tco_status(&td);
	286	reset_on_second_timeout(true);
	287	set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
	288	load_tco(&td);
	289	start_tco(&td);
	290	clock_step(ticks * TCO_TICK_NSEC * 2);
	291	ad = get_watchdog_action();
	292	g_assert(!strcmp(qdict_get_str(ad, "action"), "reset"));
cb3e7f08	293	qobject_unref(ad);
45dcdb9d PA	294
45dcdb9d PA	295	stop_tco(&td);
34779e8c	296	test_end(&td);
45dcdb9d PA	297	}
	298
	299	static void test_tco_second_timeout_shutdown(void)
	300	{
	301	TestData td;
	302	const uint16_t ticks = TCO_SECS_TO_TICKS(128);
	303	QDict *ad;
	304
	305	td.args = "-watchdog-action shutdown";
5add35be	306	td.noreboot = false;
45dcdb9d PA	307	test_init(&td);
	308
	309	stop_tco(&td);
	310	clear_tco_status(&td);
	311	reset_on_second_timeout(true);
	312	set_tco_timeout(&td, ticks);
	313	load_tco(&td);
	314	start_tco(&td);
	315	clock_step(ticks * TCO_TICK_NSEC * 2);
	316	ad = get_watchdog_action();
	317	g_assert(!strcmp(qdict_get_str(ad, "action"), "shutdown"));
cb3e7f08	318	qobject_unref(ad);
45dcdb9d PA	319
45dcdb9d PA	320	stop_tco(&td);
34779e8c	321	test_end(&td);
45dcdb9d PA	322	}
	323
	324	static void test_tco_second_timeout_none(void)
	325	{
	326	TestData td;
	327	const uint16_t ticks = TCO_SECS_TO_TICKS(256);
	328	QDict *ad;
	329
	330	td.args = "-watchdog-action none";
5add35be	331	td.noreboot = false;
45dcdb9d PA	332	test_init(&td);
	333
	334	stop_tco(&td);
	335	clear_tco_status(&td);
	336	reset_on_second_timeout(true);
	337	set_tco_timeout(&td, ticks);
	338	load_tco(&td);
	339	start_tco(&td);
	340	clock_step(ticks * TCO_TICK_NSEC * 2);
	341	ad = get_watchdog_action();
	342	g_assert(!strcmp(qdict_get_str(ad, "action"), "none"));
cb3e7f08	343	qobject_unref(ad);
45dcdb9d PA	344
45dcdb9d PA	345	stop_tco(&td);
34779e8c	346	test_end(&td);
45dcdb9d PA	347	}
	348
	349	static void test_tco_ticks_counter(void)
	350	{
	351	TestData d;
	352	uint16_t ticks = TCO_SECS_TO_TICKS(8);
	353	uint16_t rld;
	354
	355	d.args = NULL;
5add35be	356	d.noreboot = true;
45dcdb9d PA	357	test_init(&d);
	358
	359	stop_tco(&d);
	360	clear_tco_status(&d);
	361	reset_on_second_timeout(false);
	362	set_tco_timeout(&d, ticks);
	363	load_tco(&d);
	364	start_tco(&d);
	365
	366	do {
b4ba67d9	367	rld = qpci_io_readw(d.dev, d.tco_io_bar, TCO_RLD) & TCO_RLD_MASK;
45dcdb9d PA	368	g_assert_cmpint(rld, ==, ticks);
	369	clock_step(TCO_TICK_NSEC);
	370	ticks--;
b4ba67d9	371	} while (!(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS) & TCO_TIMEOUT));
45dcdb9d PA	372
45dcdb9d PA	373	stop_tco(&d);
34779e8c	374	test_end(&d);
45dcdb9d PA	375	}
	376
	377	static void test_tco1_control_bits(void)
	378	{
	379	TestData d;
	380	uint16_t val;
	381
	382	d.args = NULL;
5add35be	383	d.noreboot = true;
45dcdb9d PA	384	test_init(&d);
	385
	386	val = TCO_LOCK;
b4ba67d9	387	qpci_io_writew(d.dev, d.tco_io_bar, TCO1_CNT, val);
45dcdb9d	388	val &= ~TCO_LOCK;
b4ba67d9 DG	389	qpci_io_writew(d.dev, d.tco_io_bar, TCO1_CNT, val);
b4ba67d9 DG	390	g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_CNT), ==,
45dcdb9d	391	TCO_LOCK);
34779e8c	392	test_end(&d);
45dcdb9d PA	393	}
	394
	395	static void test_tco1_status_bits(void)
	396	{
	397	TestData d;
	398	uint16_t ticks = 8;
	399	uint16_t val;
	400	int ret;
	401
	402	d.args = NULL;
5add35be	403	d.noreboot = true;
45dcdb9d PA	404	test_init(&d);
	405
	406	stop_tco(&d);
	407	clear_tco_status(&d);
	408	reset_on_second_timeout(false);
	409	set_tco_timeout(&d, ticks);
	410	load_tco(&d);
	411	start_tco(&d);
	412	clock_step(ticks * TCO_TICK_NSEC);
	413
b4ba67d9 DG	414	qpci_io_writeb(d.dev, d.tco_io_bar, TCO_DAT_IN, 0);
	415	qpci_io_writeb(d.dev, d.tco_io_bar, TCO_DAT_OUT, 0);
	416	val = qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS);
45dcdb9d PA	417	ret = val & (TCO_TIMEOUT \| SW_TCO_SMI \| TCO_INT_STS) ? 1 : 0;
45dcdb9d PA	418	g_assert(ret == 1);
b4ba67d9 DG	419	qpci_io_writew(d.dev, d.tco_io_bar, TCO1_STS, val);
b4ba67d9 DG	420	g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO1_STS), ==, 0);
34779e8c	421	test_end(&d);
45dcdb9d PA	422	}
	423
	424	static void test_tco2_status_bits(void)
	425	{
	426	TestData d;
	427	uint16_t ticks = 8;
	428	uint16_t val;
	429	int ret;
	430
5add35be PA	431	d.args = NULL;
5add35be PA	432	d.noreboot = true;
45dcdb9d PA	433	test_init(&d);
	434
	435	stop_tco(&d);
	436	clear_tco_status(&d);
	437	reset_on_second_timeout(true);
	438	set_tco_timeout(&d, ticks);
	439	load_tco(&d);
	440	start_tco(&d);
	441	clock_step(ticks * TCO_TICK_NSEC * 2);
	442
b4ba67d9	443	val = qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS);
45dcdb9d PA	444	ret = val & (TCO_SECOND_TO_STS \| TCO_BOOT_STS) ? 1 : 0;
45dcdb9d PA	445	g_assert(ret == 1);
b4ba67d9 DG	446	qpci_io_writew(d.dev, d.tco_io_bar, TCO2_STS, val);
b4ba67d9 DG	447	g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_bar, TCO2_STS), ==, 0);
34779e8c	448	test_end(&d);
45dcdb9d PA	449	}
	450
	451	int main(int argc, char **argv)
	452	{
	453	g_test_init(&argc, &argv, NULL);
	454
	455	qtest_add_func("tco/defaults", test_tco_defaults);
	456	qtest_add_func("tco/timeout/no_action", test_tco_timeout);
	457	qtest_add_func("tco/timeout/no_action/max", test_tco_max_timeout);
	458	qtest_add_func("tco/second_timeout/pause", test_tco_second_timeout_pause);
	459	qtest_add_func("tco/second_timeout/reset", test_tco_second_timeout_reset);
	460	qtest_add_func("tco/second_timeout/shutdown",
	461	test_tco_second_timeout_shutdown);
	462	qtest_add_func("tco/second_timeout/none", test_tco_second_timeout_none);
	463	qtest_add_func("tco/counter", test_tco_ticks_counter);
	464	qtest_add_func("tco/tco1_control/bits", test_tco1_control_bits);
	465	qtest_add_func("tco/tco1_status/bits", test_tco1_status_bits);
	466	qtest_add_func("tco/tco2_status/bits", test_tco2_status_bits);
	467	return g_test_run();
	468	}