[mirror_qemu.git] / tests / tco-test.c

/*
 * QEMU ICH9 TCO emulation tests
 *
 * Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2 or later.
 * See the COPYING file in the top-level directory.
 */
#include "qemu/osdep.h"

#include "libqtest.h"
#include "libqos/pci.h"
#include "libqos/pci-pc.h"
#include "hw/pci/pci_regs.h"
#include "hw/i386/ich9.h"
#include "hw/acpi/ich9.h"
#include "hw/acpi/tco.h"

#define RCBA_BASE_ADDR    0xfed1c000
#define PM_IO_BASE_ADDR   0xb000

enum {
    TCO_RLD_DEFAULT         = 0x0000,
    TCO_DAT_IN_DEFAULT      = 0x00,
    TCO_DAT_OUT_DEFAULT     = 0x00,
    TCO1_STS_DEFAULT        = 0x0000,
    TCO2_STS_DEFAULT        = 0x0000,
    TCO1_CNT_DEFAULT        = 0x0000,
    TCO2_CNT_DEFAULT        = 0x0008,
    TCO_MESSAGE1_DEFAULT    = 0x00,
    TCO_MESSAGE2_DEFAULT    = 0x00,
    TCO_WDCNT_DEFAULT       = 0x00,
    TCO_TMR_DEFAULT         = 0x0004,
    SW_IRQ_GEN_DEFAULT      = 0x03,
};

#define TCO_SECS_TO_TICKS(secs)     (((secs) * 10) / 6)
#define TCO_TICKS_TO_SECS(ticks)    (((ticks) * 6) / 10)

typedef struct {
    const char *args;
    bool noreboot;
    QPCIDevice *dev;
    void *tco_io_base;
} TestData;

static void test_init(TestData *d)
{
    QPCIBus *bus;
    QTestState *qs;
    char *s;

    s = g_strdup_printf("-machine q35 %s %s",
                        d->noreboot ? "" : "-global ICH9-LPC.noreboot=false",
                        !d->args ? "" : d->args);
    qs = qtest_start(s);
    qtest_irq_intercept_in(qs, "ioapic");
    g_free(s);

    bus = qpci_init_pc(NULL);
    d->dev = qpci_device_find(bus, QPCI_DEVFN(0x1f, 0x00));
    g_assert(d->dev != NULL);

    qpci_device_enable(d->dev);

    /* set ACPI PM I/O space base address */
    qpci_config_writel(d->dev, ICH9_LPC_PMBASE, PM_IO_BASE_ADDR | 0x1);
    /* enable ACPI I/O */
    qpci_config_writeb(d->dev, ICH9_LPC_ACPI_CTRL, 0x80);
    /* set Root Complex BAR */
    qpci_config_writel(d->dev, ICH9_LPC_RCBA, RCBA_BASE_ADDR | 0x1);

    d->tco_io_base = qpci_legacy_iomap(d->dev, PM_IO_BASE_ADDR + 0x60);
}

static void stop_tco(const TestData *d)
{
    uint32_t val;

    val = qpci_io_readw(d->dev, d->tco_io_base + TCO1_CNT);
    val |= TCO_TMR_HLT;
    qpci_io_writew(d->dev, d->tco_io_base + TCO1_CNT, val);
}

static void start_tco(const TestData *d)
{
    uint32_t val;

    val = qpci_io_readw(d->dev, d->tco_io_base + TCO1_CNT);
    val &= ~TCO_TMR_HLT;
    qpci_io_writew(d->dev, d->tco_io_base + TCO1_CNT, val);
}

static void load_tco(const TestData *d)
{
    qpci_io_writew(d->dev, d->tco_io_base + TCO_RLD, 4);
}

static void set_tco_timeout(const TestData *d, uint16_t ticks)
{
    qpci_io_writew(d->dev, d->tco_io_base + TCO_TMR, ticks);
}

static void clear_tco_status(const TestData *d)
{
    qpci_io_writew(d->dev, d->tco_io_base + TCO1_STS, 0x0008);
    qpci_io_writew(d->dev, d->tco_io_base + TCO2_STS, 0x0002);
    qpci_io_writew(d->dev, d->tco_io_base + TCO2_STS, 0x0004);
}

static void reset_on_second_timeout(bool enable)
{
    uint32_t val;

    val = readl(RCBA_BASE_ADDR + ICH9_CC_GCS);
    if (enable) {
        val &= ~ICH9_CC_GCS_NO_REBOOT;
    } else {
        val |= ICH9_CC_GCS_NO_REBOOT;
    }
    writel(RCBA_BASE_ADDR + ICH9_CC_GCS, val);
}

static void test_tco_defaults(void)
{
    TestData d;

    d.args = NULL;
    d.noreboot = true;
    test_init(&d);
    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_RLD), ==,
                    TCO_RLD_DEFAULT);
    /* TCO_DAT_IN & TCO_DAT_OUT */
    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_DAT_IN), ==,
                    (TCO_DAT_OUT_DEFAULT << 8) | TCO_DAT_IN_DEFAULT);
    /* TCO1_STS & TCO2_STS */
    g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_base + TCO1_STS), ==,
                    (TCO2_STS_DEFAULT << 16) | TCO1_STS_DEFAULT);
    /* TCO1_CNT & TCO2_CNT */
    g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_base + TCO1_CNT), ==,
                    (TCO2_CNT_DEFAULT << 16) | TCO1_CNT_DEFAULT);
    /* TCO_MESSAGE1 & TCO_MESSAGE2 */
    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_MESSAGE1), ==,
                    (TCO_MESSAGE2_DEFAULT << 8) | TCO_MESSAGE1_DEFAULT);
    g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_base + TCO_WDCNT), ==,
                    TCO_WDCNT_DEFAULT);
    g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_base + SW_IRQ_GEN), ==,
                    SW_IRQ_GEN_DEFAULT);
    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_TMR), ==,
                    TCO_TMR_DEFAULT);
    qtest_end();
}

static void test_tco_timeout(void)
{
    TestData d;
    const uint16_t ticks = TCO_SECS_TO_TICKS(4);
    uint32_t val;
    int ret;

    d.args = NULL;
    d.noreboot = true;
    test_init(&d);

    stop_tco(&d);
    clear_tco_status(&d);
    reset_on_second_timeout(false);
    set_tco_timeout(&d, ticks);
    load_tco(&d);
    start_tco(&d);
    clock_step(ticks * TCO_TICK_NSEC);

    /* test first timeout */
    val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
    ret = val & TCO_TIMEOUT ? 1 : 0;
    g_assert(ret == 1);

    /* test clearing timeout bit */
    val |= TCO_TIMEOUT;
    qpci_io_writew(d.dev, d.tco_io_base + TCO1_STS, val);
    val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
    ret = val & TCO_TIMEOUT ? 1 : 0;
    g_assert(ret == 0);

    /* test second timeout */
    clock_step(ticks * TCO_TICK_NSEC);
    val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
    ret = val & TCO_TIMEOUT ? 1 : 0;
    g_assert(ret == 1);
    val = qpci_io_readw(d.dev, d.tco_io_base + TCO2_STS);
    ret = val & TCO_SECOND_TO_STS ? 1 : 0;
    g_assert(ret == 1);

    stop_tco(&d);
    qtest_end();
}

static void test_tco_max_timeout(void)
{
    TestData d;
    const uint16_t ticks = 0xffff;
    uint32_t val;
    int ret;

    d.args = NULL;
    d.noreboot = true;
    test_init(&d);

    stop_tco(&d);
    clear_tco_status(&d);
    reset_on_second_timeout(false);
    set_tco_timeout(&d, ticks);
    load_tco(&d);
    start_tco(&d);
    clock_step(((ticks & TCO_TMR_MASK) - 1) * TCO_TICK_NSEC);

    val = qpci_io_readw(d.dev, d.tco_io_base + TCO_RLD);
    g_assert_cmpint(val & TCO_RLD_MASK, ==, 1);
    val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
    ret = val & TCO_TIMEOUT ? 1 : 0;
    g_assert(ret == 0);
    clock_step(TCO_TICK_NSEC);
    val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
    ret = val & TCO_TIMEOUT ? 1 : 0;
    g_assert(ret == 1);

    stop_tco(&d);
    qtest_end();
}

static QDict *get_watchdog_action(void)
{
    QDict *ev = qmp("");
    QDict *data;
    g_assert(!strcmp(qdict_get_str(ev, "event"), "WATCHDOG"));

    data = qdict_get_qdict(ev, "data");
    QINCREF(data);
    QDECREF(ev);
    return data;
}

static void test_tco_second_timeout_pause(void)
{
    TestData td;
    const uint16_t ticks = TCO_SECS_TO_TICKS(32);
    QDict *ad;

    td.args = "-watchdog-action pause";
    td.noreboot = false;
    test_init(&td);

    stop_tco(&td);
    clear_tco_status(&td);
    reset_on_second_timeout(true);
    set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
    load_tco(&td);
    start_tco(&td);
    clock_step(ticks * TCO_TICK_NSEC * 2);
    ad = get_watchdog_action();
    g_assert(!strcmp(qdict_get_str(ad, "action"), "pause"));
    QDECREF(ad);

    stop_tco(&td);
    qtest_end();
}

static void test_tco_second_timeout_reset(void)
{
    TestData td;
    const uint16_t ticks = TCO_SECS_TO_TICKS(16);
    QDict *ad;

    td.args = "-watchdog-action reset";
    td.noreboot = false;
    test_init(&td);

    stop_tco(&td);
    clear_tco_status(&td);
    reset_on_second_timeout(true);
    set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
    load_tco(&td);
    start_tco(&td);
    clock_step(ticks * TCO_TICK_NSEC * 2);
    ad = get_watchdog_action();
    g_assert(!strcmp(qdict_get_str(ad, "action"), "reset"));
    QDECREF(ad);

    stop_tco(&td);
    qtest_end();
}

static void test_tco_second_timeout_shutdown(void)
{
    TestData td;
    const uint16_t ticks = TCO_SECS_TO_TICKS(128);
    QDict *ad;

    td.args = "-watchdog-action shutdown";
    td.noreboot = false;
    test_init(&td);

    stop_tco(&td);
    clear_tco_status(&td);
    reset_on_second_timeout(true);
    set_tco_timeout(&td, ticks);
    load_tco(&td);
    start_tco(&td);
    clock_step(ticks * TCO_TICK_NSEC * 2);
    ad = get_watchdog_action();
    g_assert(!strcmp(qdict_get_str(ad, "action"), "shutdown"));
    QDECREF(ad);

    stop_tco(&td);
    qtest_end();
}

static void test_tco_second_timeout_none(void)
{
    TestData td;
    const uint16_t ticks = TCO_SECS_TO_TICKS(256);
    QDict *ad;

    td.args = "-watchdog-action none";
    td.noreboot = false;
    test_init(&td);

    stop_tco(&td);
    clear_tco_status(&td);
    reset_on_second_timeout(true);
    set_tco_timeout(&td, ticks);
    load_tco(&td);
    start_tco(&td);
    clock_step(ticks * TCO_TICK_NSEC * 2);
    ad = get_watchdog_action();
    g_assert(!strcmp(qdict_get_str(ad, "action"), "none"));
    QDECREF(ad);

    stop_tco(&td);
    qtest_end();
}

static void test_tco_ticks_counter(void)
{
    TestData d;
    uint16_t ticks = TCO_SECS_TO_TICKS(8);
    uint16_t rld;

    d.args = NULL;
    d.noreboot = true;
    test_init(&d);

    stop_tco(&d);
    clear_tco_status(&d);
    reset_on_second_timeout(false);
    set_tco_timeout(&d, ticks);
    load_tco(&d);
    start_tco(&d);

    do {
        rld = qpci_io_readw(d.dev, d.tco_io_base + TCO_RLD) & TCO_RLD_MASK;
        g_assert_cmpint(rld, ==, ticks);
        clock_step(TCO_TICK_NSEC);
        ticks--;
    } while (!(qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS) & TCO_TIMEOUT));

    stop_tco(&d);
    qtest_end();
}

static void test_tco1_control_bits(void)
{
    TestData d;
    uint16_t val;

    d.args = NULL;
    d.noreboot = true;
    test_init(&d);

    val = TCO_LOCK;
    qpci_io_writew(d.dev, d.tco_io_base + TCO1_CNT, val);
    val &= ~TCO_LOCK;
    qpci_io_writew(d.dev, d.tco_io_base + TCO1_CNT, val);
    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO1_CNT), ==,
                    TCO_LOCK);
    qtest_end();
}

static void test_tco1_status_bits(void)
{
    TestData d;
    uint16_t ticks = 8;
    uint16_t val;
    int ret;

    d.args = NULL;
    d.noreboot = true;
    test_init(&d);

    stop_tco(&d);
    clear_tco_status(&d);
    reset_on_second_timeout(false);
    set_tco_timeout(&d, ticks);
    load_tco(&d);
    start_tco(&d);
    clock_step(ticks * TCO_TICK_NSEC);

    qpci_io_writeb(d.dev, d.tco_io_base + TCO_DAT_IN, 0);
    qpci_io_writeb(d.dev, d.tco_io_base + TCO_DAT_OUT, 0);
    val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
    ret = val & (TCO_TIMEOUT | SW_TCO_SMI | TCO_INT_STS) ? 1 : 0;
    g_assert(ret == 1);
    qpci_io_writew(d.dev, d.tco_io_base + TCO1_STS, val);
    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS), ==, 0);
    qtest_end();
}

static void test_tco2_status_bits(void)
{
    TestData d;
    uint16_t ticks = 8;
    uint16_t val;
    int ret;

    d.args = NULL;
    d.noreboot = true;
    test_init(&d);

    stop_tco(&d);
    clear_tco_status(&d);
    reset_on_second_timeout(true);
    set_tco_timeout(&d, ticks);
    load_tco(&d);
    start_tco(&d);
    clock_step(ticks * TCO_TICK_NSEC * 2);

    val = qpci_io_readw(d.dev, d.tco_io_base + TCO2_STS);
    ret = val & (TCO_SECOND_TO_STS | TCO_BOOT_STS) ? 1 : 0;
    g_assert(ret == 1);
    qpci_io_writew(d.dev, d.tco_io_base + TCO2_STS, val);
    g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO2_STS), ==, 0);
    qtest_end();
}

int main(int argc, char **argv)
{
    g_test_init(&argc, &argv, NULL);

    qtest_add_func("tco/defaults", test_tco_defaults);
    qtest_add_func("tco/timeout/no_action", test_tco_timeout);
    qtest_add_func("tco/timeout/no_action/max", test_tco_max_timeout);
    qtest_add_func("tco/second_timeout/pause", test_tco_second_timeout_pause);
    qtest_add_func("tco/second_timeout/reset", test_tco_second_timeout_reset);
    qtest_add_func("tco/second_timeout/shutdown",
                   test_tco_second_timeout_shutdown);
    qtest_add_func("tco/second_timeout/none", test_tco_second_timeout_none);
    qtest_add_func("tco/counter", test_tco_ticks_counter);
    qtest_add_func("tco/tco1_control/bits", test_tco1_control_bits);
    qtest_add_func("tco/tco1_status/bits", test_tco1_status_bits);
    qtest_add_func("tco/tco2_status/bits", test_tco2_status_bits);
    return g_test_run();
}
Commit	Line	Data
45dcdb9d PA	1	/*
	2	* QEMU ICH9 TCO emulation tests
	3	*
	4	* Copyright (c) 2015 Paulo Alcantara <pcacjr@zytor.com>
	5	*
	6	* This work is licensed under the terms of the GNU GPL, version 2 or later.
	7	* See the COPYING file in the top-level directory.
	8	*/
681c28a3	9	#include "qemu/osdep.h"
45dcdb9d PA	10
	11	#include "libqtest.h"
	12	#include "libqos/pci.h"
	13	#include "libqos/pci-pc.h"
	14	#include "hw/pci/pci_regs.h"
	15	#include "hw/i386/ich9.h"
	16	#include "hw/acpi/ich9.h"
	17	#include "hw/acpi/tco.h"
	18
	19	#define RCBA_BASE_ADDR 0xfed1c000
	20	#define PM_IO_BASE_ADDR 0xb000
	21
	22	enum {
	23	TCO_RLD_DEFAULT = 0x0000,
	24	TCO_DAT_IN_DEFAULT = 0x00,
	25	TCO_DAT_OUT_DEFAULT = 0x00,
	26	TCO1_STS_DEFAULT = 0x0000,
	27	TCO2_STS_DEFAULT = 0x0000,
	28	TCO1_CNT_DEFAULT = 0x0000,
	29	TCO2_CNT_DEFAULT = 0x0008,
	30	TCO_MESSAGE1_DEFAULT = 0x00,
	31	TCO_MESSAGE2_DEFAULT = 0x00,
	32	TCO_WDCNT_DEFAULT = 0x00,
	33	TCO_TMR_DEFAULT = 0x0004,
	34	SW_IRQ_GEN_DEFAULT = 0x03,
	35	};
	36
	37	#define TCO_SECS_TO_TICKS(secs) (((secs) * 10) / 6)
	38	#define TCO_TICKS_TO_SECS(ticks) (((ticks) * 6) / 10)
	39
	40	typedef struct {
	41	const char *args;
5add35be	42	bool noreboot;
45dcdb9d	43	QPCIDevice *dev;
45dcdb9d PA	44	void *tco_io_base;
	45	} TestData;
	46
	47	static void test_init(TestData *d)
	48	{
	49	QPCIBus *bus;
	50	QTestState *qs;
	51	char *s;
	52
5add35be PA	53	s = g_strdup_printf("-machine q35 %s %s",
	54	d->noreboot ? "" : "-global ICH9-LPC.noreboot=false",
	55	!d->args ? "" : d->args);
45dcdb9d PA	56	qs = qtest_start(s);
	57	qtest_irq_intercept_in(qs, "ioapic");
	58	g_free(s);
	59
2ecd7e2f	60	bus = qpci_init_pc(NULL);
45dcdb9d PA	61	d->dev = qpci_device_find(bus, QPCI_DEVFN(0x1f, 0x00));
	62	g_assert(d->dev != NULL);
	63
45dcdb9d PA	64	qpci_device_enable(d->dev);
45dcdb9d PA	65
45dcdb9d	66	/* set ACPI PM I/O space base address */
c4fc82bf	67	qpci_config_writel(d->dev, ICH9_LPC_PMBASE, PM_IO_BASE_ADDR \| 0x1);
45dcdb9d	68	/* enable ACPI I/O */
c4fc82bf	69	qpci_config_writeb(d->dev, ICH9_LPC_ACPI_CTRL, 0x80);
45dcdb9d	70	/* set Root Complex BAR */
c4fc82bf	71	qpci_config_writel(d->dev, ICH9_LPC_RCBA, RCBA_BASE_ADDR \| 0x1);
45dcdb9d	72
9ff50be2	73	d->tco_io_base = qpci_legacy_iomap(d->dev, PM_IO_BASE_ADDR + 0x60);
45dcdb9d PA	74	}
	75
	76	static void stop_tco(const TestData *d)
	77	{
	78	uint32_t val;
	79
	80	val = qpci_io_readw(d->dev, d->tco_io_base + TCO1_CNT);
	81	val \|= TCO_TMR_HLT;
	82	qpci_io_writew(d->dev, d->tco_io_base + TCO1_CNT, val);
	83	}
	84
	85	static void start_tco(const TestData *d)
	86	{
	87	uint32_t val;
	88
	89	val = qpci_io_readw(d->dev, d->tco_io_base + TCO1_CNT);
	90	val &= ~TCO_TMR_HLT;
	91	qpci_io_writew(d->dev, d->tco_io_base + TCO1_CNT, val);
	92	}
	93
	94	static void load_tco(const TestData *d)
	95	{
	96	qpci_io_writew(d->dev, d->tco_io_base + TCO_RLD, 4);
	97	}
	98
	99	static void set_tco_timeout(const TestData *d, uint16_t ticks)
	100	{
	101	qpci_io_writew(d->dev, d->tco_io_base + TCO_TMR, ticks);
	102	}
	103
	104	static void clear_tco_status(const TestData *d)
	105	{
	106	qpci_io_writew(d->dev, d->tco_io_base + TCO1_STS, 0x0008);
	107	qpci_io_writew(d->dev, d->tco_io_base + TCO2_STS, 0x0002);
	108	qpci_io_writew(d->dev, d->tco_io_base + TCO2_STS, 0x0004);
	109	}
	110
	111	static void reset_on_second_timeout(bool enable)
	112	{
	113	uint32_t val;
	114
	115	val = readl(RCBA_BASE_ADDR + ICH9_CC_GCS);
	116	if (enable) {
	117	val &= ~ICH9_CC_GCS_NO_REBOOT;
	118	} else {
	119	val \|= ICH9_CC_GCS_NO_REBOOT;
	120	}
	121	writel(RCBA_BASE_ADDR + ICH9_CC_GCS, val);
	122	}
	123
	124	static void test_tco_defaults(void)
	125	{
	126	TestData d;
	127
	128	d.args = NULL;
5add35be	129	d.noreboot = true;
45dcdb9d PA	130	test_init(&d);
	131	g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_RLD), ==,
	132	TCO_RLD_DEFAULT);
	133	/* TCO_DAT_IN & TCO_DAT_OUT */
	134	g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_DAT_IN), ==,
	135	(TCO_DAT_OUT_DEFAULT << 8) \| TCO_DAT_IN_DEFAULT);
	136	/* TCO1_STS & TCO2_STS */
	137	g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_base + TCO1_STS), ==,
	138	(TCO2_STS_DEFAULT << 16) \| TCO1_STS_DEFAULT);
	139	/* TCO1_CNT & TCO2_CNT */
	140	g_assert_cmpint(qpci_io_readl(d.dev, d.tco_io_base + TCO1_CNT), ==,
	141	(TCO2_CNT_DEFAULT << 16) \| TCO1_CNT_DEFAULT);
	142	/* TCO_MESSAGE1 & TCO_MESSAGE2 */
	143	g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_MESSAGE1), ==,
	144	(TCO_MESSAGE2_DEFAULT << 8) \| TCO_MESSAGE1_DEFAULT);
	145	g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_base + TCO_WDCNT), ==,
	146	TCO_WDCNT_DEFAULT);
	147	g_assert_cmpint(qpci_io_readb(d.dev, d.tco_io_base + SW_IRQ_GEN), ==,
	148	SW_IRQ_GEN_DEFAULT);
	149	g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO_TMR), ==,
	150	TCO_TMR_DEFAULT);
	151	qtest_end();
	152	}
	153
	154	static void test_tco_timeout(void)
	155	{
	156	TestData d;
	157	const uint16_t ticks = TCO_SECS_TO_TICKS(4);
	158	uint32_t val;
	159	int ret;
	160
	161	d.args = NULL;
5add35be	162	d.noreboot = true;
45dcdb9d PA	163	test_init(&d);
	164
	165	stop_tco(&d);
	166	clear_tco_status(&d);
	167	reset_on_second_timeout(false);
	168	set_tco_timeout(&d, ticks);
	169	load_tco(&d);
	170	start_tco(&d);
	171	clock_step(ticks * TCO_TICK_NSEC);
	172
	173	/* test first timeout */
	174	val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
	175	ret = val & TCO_TIMEOUT ? 1 : 0;
	176	g_assert(ret == 1);
	177
	178	/* test clearing timeout bit */
	179	val \|= TCO_TIMEOUT;
	180	qpci_io_writew(d.dev, d.tco_io_base + TCO1_STS, val);
	181	val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
	182	ret = val & TCO_TIMEOUT ? 1 : 0;
	183	g_assert(ret == 0);
	184
	185	/* test second timeout */
	186	clock_step(ticks * TCO_TICK_NSEC);
	187	val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
	188	ret = val & TCO_TIMEOUT ? 1 : 0;
	189	g_assert(ret == 1);
	190	val = qpci_io_readw(d.dev, d.tco_io_base + TCO2_STS);
	191	ret = val & TCO_SECOND_TO_STS ? 1 : 0;
	192	g_assert(ret == 1);
	193
	194	stop_tco(&d);
	195	qtest_end();
	196	}
	197
	198	static void test_tco_max_timeout(void)
	199	{
	200	TestData d;
	201	const uint16_t ticks = 0xffff;
	202	uint32_t val;
	203	int ret;
	204
	205	d.args = NULL;
5add35be	206	d.noreboot = true;
45dcdb9d PA	207	test_init(&d);
	208
	209	stop_tco(&d);
	210	clear_tco_status(&d);
	211	reset_on_second_timeout(false);
	212	set_tco_timeout(&d, ticks);
	213	load_tco(&d);
	214	start_tco(&d);
	215	clock_step(((ticks & TCO_TMR_MASK) - 1) * TCO_TICK_NSEC);
	216
	217	val = qpci_io_readw(d.dev, d.tco_io_base + TCO_RLD);
	218	g_assert_cmpint(val & TCO_RLD_MASK, ==, 1);
	219	val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
	220	ret = val & TCO_TIMEOUT ? 1 : 0;
	221	g_assert(ret == 0);
	222	clock_step(TCO_TICK_NSEC);
	223	val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
	224	ret = val & TCO_TIMEOUT ? 1 : 0;
	225	g_assert(ret == 1);
	226
	227	stop_tco(&d);
	228	qtest_end();
	229	}
	230
	231	static QDict *get_watchdog_action(void)
	232	{
	233	QDict *ev = qmp("");
	234	QDict *data;
	235	g_assert(!strcmp(qdict_get_str(ev, "event"), "WATCHDOG"));
	236
	237	data = qdict_get_qdict(ev, "data");
	238	QINCREF(data);
	239	QDECREF(ev);
	240	return data;
	241	}
	242
	243	static void test_tco_second_timeout_pause(void)
	244	{
	245	TestData td;
	246	const uint16_t ticks = TCO_SECS_TO_TICKS(32);
	247	QDict *ad;
	248
	249	td.args = "-watchdog-action pause";
5add35be	250	td.noreboot = false;
45dcdb9d PA	251	test_init(&td);
	252
	253	stop_tco(&td);
	254	clear_tco_status(&td);
	255	reset_on_second_timeout(true);
	256	set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
	257	load_tco(&td);
	258	start_tco(&td);
	259	clock_step(ticks * TCO_TICK_NSEC * 2);
	260	ad = get_watchdog_action();
	261	g_assert(!strcmp(qdict_get_str(ad, "action"), "pause"));
	262	QDECREF(ad);
	263
	264	stop_tco(&td);
	265	qtest_end();
	266	}
	267
	268	static void test_tco_second_timeout_reset(void)
	269	{
	270	TestData td;
	271	const uint16_t ticks = TCO_SECS_TO_TICKS(16);
	272	QDict *ad;
	273
	274	td.args = "-watchdog-action reset";
5add35be	275	td.noreboot = false;
45dcdb9d PA	276	test_init(&td);
	277
	278	stop_tco(&td);
	279	clear_tco_status(&td);
	280	reset_on_second_timeout(true);
	281	set_tco_timeout(&td, TCO_SECS_TO_TICKS(16));
	282	load_tco(&td);
	283	start_tco(&td);
	284	clock_step(ticks * TCO_TICK_NSEC * 2);
	285	ad = get_watchdog_action();
	286	g_assert(!strcmp(qdict_get_str(ad, "action"), "reset"));
	287	QDECREF(ad);
	288
	289	stop_tco(&td);
	290	qtest_end();
	291	}
	292
	293	static void test_tco_second_timeout_shutdown(void)
	294	{
	295	TestData td;
	296	const uint16_t ticks = TCO_SECS_TO_TICKS(128);
	297	QDict *ad;
	298
	299	td.args = "-watchdog-action shutdown";
5add35be	300	td.noreboot = false;
45dcdb9d PA	301	test_init(&td);
	302
	303	stop_tco(&td);
	304	clear_tco_status(&td);
	305	reset_on_second_timeout(true);
	306	set_tco_timeout(&td, ticks);
	307	load_tco(&td);
	308	start_tco(&td);
	309	clock_step(ticks * TCO_TICK_NSEC * 2);
	310	ad = get_watchdog_action();
	311	g_assert(!strcmp(qdict_get_str(ad, "action"), "shutdown"));
	312	QDECREF(ad);
	313
	314	stop_tco(&td);
	315	qtest_end();
	316	}
	317
	318	static void test_tco_second_timeout_none(void)
	319	{
	320	TestData td;
	321	const uint16_t ticks = TCO_SECS_TO_TICKS(256);
	322	QDict *ad;
	323
	324	td.args = "-watchdog-action none";
5add35be	325	td.noreboot = false;
45dcdb9d PA	326	test_init(&td);
	327
	328	stop_tco(&td);
	329	clear_tco_status(&td);
	330	reset_on_second_timeout(true);
	331	set_tco_timeout(&td, ticks);
	332	load_tco(&td);
	333	start_tco(&td);
	334	clock_step(ticks * TCO_TICK_NSEC * 2);
	335	ad = get_watchdog_action();
	336	g_assert(!strcmp(qdict_get_str(ad, "action"), "none"));
	337	QDECREF(ad);
	338
	339	stop_tco(&td);
	340	qtest_end();
	341	}
	342
	343	static void test_tco_ticks_counter(void)
	344	{
	345	TestData d;
	346	uint16_t ticks = TCO_SECS_TO_TICKS(8);
	347	uint16_t rld;
	348
	349	d.args = NULL;
5add35be	350	d.noreboot = true;
45dcdb9d PA	351	test_init(&d);
	352
	353	stop_tco(&d);
	354	clear_tco_status(&d);
	355	reset_on_second_timeout(false);
	356	set_tco_timeout(&d, ticks);
	357	load_tco(&d);
	358	start_tco(&d);
	359
	360	do {
	361	rld = qpci_io_readw(d.dev, d.tco_io_base + TCO_RLD) & TCO_RLD_MASK;
	362	g_assert_cmpint(rld, ==, ticks);
	363	clock_step(TCO_TICK_NSEC);
	364	ticks--;
	365	} while (!(qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS) & TCO_TIMEOUT));
	366
	367	stop_tco(&d);
	368	qtest_end();
	369	}
	370
	371	static void test_tco1_control_bits(void)
	372	{
	373	TestData d;
	374	uint16_t val;
	375
	376	d.args = NULL;
5add35be	377	d.noreboot = true;
45dcdb9d PA	378	test_init(&d);
	379
	380	val = TCO_LOCK;
	381	qpci_io_writew(d.dev, d.tco_io_base + TCO1_CNT, val);
	382	val &= ~TCO_LOCK;
	383	qpci_io_writew(d.dev, d.tco_io_base + TCO1_CNT, val);
	384	g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO1_CNT), ==,
	385	TCO_LOCK);
	386	qtest_end();
	387	}
	388
	389	static void test_tco1_status_bits(void)
	390	{
	391	TestData d;
	392	uint16_t ticks = 8;
	393	uint16_t val;
	394	int ret;
	395
	396	d.args = NULL;
5add35be	397	d.noreboot = true;
45dcdb9d PA	398	test_init(&d);
	399
	400	stop_tco(&d);
	401	clear_tco_status(&d);
	402	reset_on_second_timeout(false);
	403	set_tco_timeout(&d, ticks);
	404	load_tco(&d);
	405	start_tco(&d);
	406	clock_step(ticks * TCO_TICK_NSEC);
	407
	408	qpci_io_writeb(d.dev, d.tco_io_base + TCO_DAT_IN, 0);
	409	qpci_io_writeb(d.dev, d.tco_io_base + TCO_DAT_OUT, 0);
	410	val = qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS);
	411	ret = val & (TCO_TIMEOUT \| SW_TCO_SMI \| TCO_INT_STS) ? 1 : 0;
	412	g_assert(ret == 1);
	413	qpci_io_writew(d.dev, d.tco_io_base + TCO1_STS, val);
	414	g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO1_STS), ==, 0);
	415	qtest_end();
	416	}
	417
	418	static void test_tco2_status_bits(void)
	419	{
	420	TestData d;
	421	uint16_t ticks = 8;
	422	uint16_t val;
	423	int ret;
	424
5add35be PA	425	d.args = NULL;
5add35be PA	426	d.noreboot = true;
45dcdb9d PA	427	test_init(&d);
	428
	429	stop_tco(&d);
	430	clear_tco_status(&d);
	431	reset_on_second_timeout(true);
	432	set_tco_timeout(&d, ticks);
	433	load_tco(&d);
	434	start_tco(&d);
	435	clock_step(ticks * TCO_TICK_NSEC * 2);
	436
	437	val = qpci_io_readw(d.dev, d.tco_io_base + TCO2_STS);
	438	ret = val & (TCO_SECOND_TO_STS \| TCO_BOOT_STS) ? 1 : 0;
	439	g_assert(ret == 1);
	440	qpci_io_writew(d.dev, d.tco_io_base + TCO2_STS, val);
	441	g_assert_cmpint(qpci_io_readw(d.dev, d.tco_io_base + TCO2_STS), ==, 0);
	442	qtest_end();
	443	}
	444
	445	int main(int argc, char **argv)
	446	{
	447	g_test_init(&argc, &argv, NULL);
	448
	449	qtest_add_func("tco/defaults", test_tco_defaults);
	450	qtest_add_func("tco/timeout/no_action", test_tco_timeout);
	451	qtest_add_func("tco/timeout/no_action/max", test_tco_max_timeout);
	452	qtest_add_func("tco/second_timeout/pause", test_tco_second_timeout_pause);
	453	qtest_add_func("tco/second_timeout/reset", test_tco_second_timeout_reset);
	454	qtest_add_func("tco/second_timeout/shutdown",
	455	test_tco_second_timeout_shutdown);
	456	qtest_add_func("tco/second_timeout/none", test_tco_second_timeout_none);
	457	qtest_add_func("tco/counter", test_tco_ticks_counter);
	458	qtest_add_func("tco/tco1_control/bits", test_tco1_control_bits);
	459	qtest_add_func("tco/tco1_status/bits", test_tco1_status_bits);
	460	qtest_add_func("tco/tco2_status/bits", test_tco2_status_bits);
	461	return g_test_run();
	462	}