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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
827634ad ACM |
2 | /* |
3 | * Copied from the kernel sources: | |
4 | * | |
5 | * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima | |
6 | * Copyright (C) 2002 Paul Mundt | |
7 | */ | |
8 | #ifndef __TOOLS_LINUX_ASM_SH_BARRIER_H | |
9 | #define __TOOLS_LINUX_ASM_SH_BARRIER_H | |
10 | ||
11 | /* | |
12 | * A brief note on ctrl_barrier(), the control register write barrier. | |
13 | * | |
14 | * Legacy SH cores typically require a sequence of 8 nops after | |
15 | * modification of a control register in order for the changes to take | |
16 | * effect. On newer cores (like the sh4a and sh5) this is accomplished | |
17 | * with icbi. | |
18 | * | |
19 | * Also note that on sh4a in the icbi case we can forego a synco for the | |
20 | * write barrier, as it's not necessary for control registers. | |
21 | * | |
22 | * Historically we have only done this type of barrier for the MMUCR, but | |
23 | * it's also necessary for the CCR, so we make it generic here instead. | |
24 | */ | |
25 | #if defined(__SH4A__) || defined(__SH5__) | |
26 | #define mb() __asm__ __volatile__ ("synco": : :"memory") | |
27 | #define rmb() mb() | |
28 | #define wmb() mb() | |
29 | #endif | |
30 | ||
31 | #include <asm-generic/barrier.h> | |
32 | ||
33 | #endif /* __TOOLS_LINUX_ASM_SH_BARRIER_H */ |