[mirror_ubuntu-zesty-kernel.git] / tools / perf / Documentation / perf-list.txt

perf-list(1)
============

NAME
----
perf-list - List all symbolic event types

SYNOPSIS
--------
[verse]
'perf list' [hw|sw|cache|tracepoint|event_glob]

DESCRIPTION
-----------
This command displays the symbolic event types which can be selected in the
various perf commands with the -e option.

EVENT MODIFIERS
---------------

Events can optionally have a modifer by appending a colon and one or
more modifiers.  Modifiers allow the user to restrict when events are
counted with 'u' for user-space, 'k' for kernel, 'h' for hypervisor.

The 'p' modifier can be used for specifying how precise the instruction
address should be. The 'p' modifier is currently only implemented for
Intel PEBS and can be specified multiple times:
  0 - SAMPLE_IP can have arbitrary skid
  1 - SAMPLE_IP must have constant skid
  2 - SAMPLE_IP requested to have 0 skid
  3 - SAMPLE_IP must have 0 skid

The PEBS implementation now supports up to 2.

RAW HARDWARE EVENT DESCRIPTOR
-----------------------------
Even when an event is not available in a symbolic form within perf right now,
it can be encoded in a per processor specific way.

For instance For x86 CPUs NNN represents the raw register encoding with the
layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).

Example:

If the Intel docs for a QM720 Core i7 describe an event as:

  Event  Umask  Event Mask
  Num.   Value  Mnemonic    Description                        Comment

  A8H      01H  LSD.UOPS    Counts the number of micro-ops     Use cmask=1 and
                            delivered by loop stream detector  invert to count
                                                               cycles

raw encoding of 0x1A8 can be used:

 perf stat -e r1a8 -a sleep 1
 perf record -e r1a8 ...

You should refer to the processor specific documentation for getting these
details. Some of them are referenced in the SEE ALSO section below.

OPTIONS
-------

Without options all known events will be listed.

To limit the list use:

. 'hw' or 'hardware' to list hardware events such as cache-misses, etc.

. 'sw' or 'software' to list software events such as context switches, etc.

. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.

. 'tracepoint' to list all tracepoint events, alternatively use
  'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
  block, etc.

. If none of the above is matched, it will apply the supplied glob to all
  events, printing the ones that match.

One or more types can be used at the same time, listing the events for the
types specified.

SEE ALSO
--------
linkperf:perf-stat[1], linkperf:perf-top[1],
linkperf:perf-record[1],
http://www.intel.com/Assets/PDF/manual/253669.pdf[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
http://support.amd.com/us/Processor_TechDocs/24593.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]
Commit	Line	Data
386b05e3	1	perf-list(1)
6e6b754f	2	============
386b05e3 TG	3
	4	NAME
	5	----
	6	perf-list - List all symbolic event types
	7
	8	SYNOPSIS
	9	--------
	10	[verse]
668b8788	11	'perf list' [hw\|sw\|cache\|tracepoint\|event_glob]
386b05e3 TG	12
	13	DESCRIPTION
	14	-----------
	15	This command displays the symbolic event types which can be selected in the
	16	various perf commands with the -e option.
	17
ffec5169 SR	18	EVENT MODIFIERS
	19	---------------
	20
	21	Events can optionally have a modifer by appending a colon and one or
	22	more modifiers. Modifiers allow the user to restrict when events are
	23	counted with 'u' for user-space, 'k' for kernel, 'h' for hypervisor.
	24
	25	The 'p' modifier can be used for specifying how precise the instruction
	26	address should be. The 'p' modifier is currently only implemented for
	27	Intel PEBS and can be specified multiple times:
	28	0 - SAMPLE_IP can have arbitrary skid
	29	1 - SAMPLE_IP must have constant skid
	30	2 - SAMPLE_IP requested to have 0 skid
	31	3 - SAMPLE_IP must have 0 skid
	32
	33	The PEBS implementation now supports up to 2.
	34
9e32a3cb ACM	35	RAW HARDWARE EVENT DESCRIPTOR
	36	-----------------------------
	37	Even when an event is not available in a symbolic form within perf right now,
1cf4a063 ACM	38	it can be encoded in a per processor specific way.
	39
	40	For instance For x86 CPUs NNN represents the raw register encoding with the
	41	layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
	42	of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
	43	Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
	44
	45	Example:
	46
	47	If the Intel docs for a QM720 Core i7 describe an event as:
9e32a3cb ACM	48
	49	Event Umask Event Mask
	50	Num. Value Mnemonic Description Comment
	51
	52	A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
	53	delivered by loop stream detector invert to count
	54	cycles
	55
	56	raw encoding of 0x1A8 can be used:
	57
	58	perf stat -e r1a8 -a sleep 1
	59	perf record -e r1a8 ...
	60
1cf4a063 ACM	61	You should refer to the processor specific documentation for getting these
	62	details. Some of them are referenced in the SEE ALSO section below.
	63
386b05e3 TG	64	OPTIONS
386b05e3 TG	65	-------
668b8788 ACM	66
	67	Without options all known events will be listed.
	68
	69	To limit the list use:
	70
	71	. 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
	72
	73	. 'sw' or 'software' to list software events such as context switches, etc.
	74
	75	. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
	76
	77	. 'tracepoint' to list all tracepoint events, alternatively use
	78	'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
	79	block, etc.
	80
	81	. If none of the above is matched, it will apply the supplied glob to all
	82	events, printing the ones that match.
	83
	84	One or more types can be used at the same time, listing the events for the
	85	types specified.
386b05e3 TG	86
	87	SEE ALSO
	88	--------
	89	linkperf:perf-stat[1], linkperf:perf-top[1],
1cf4a063 ACM	90	linkperf:perf-record[1],
	91	http://www.intel.com/Assets/PDF/manual/253669.pdf[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
	92	http://support.amd.com/us/Processor_TechDocs/24593.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]