[mirror_ubuntu-hirsute-kernel.git] / tools / perf / arch / riscv / include / perf_regs.h

/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (C) 2019 Hangzhou C-SKY Microsystems co.,ltd. */

#ifndef ARCH_PERF_REGS_H
#define ARCH_PERF_REGS_H

#include <stdlib.h>
#include <linux/types.h>
#include <asm/perf_regs.h>

#define PERF_REGS_MASK	((1ULL << PERF_REG_RISCV_MAX) - 1)
#define PERF_REGS_MAX	PERF_REG_RISCV_MAX
#if __riscv_xlen == 64
#define PERF_SAMPLE_REGS_ABI    PERF_SAMPLE_REGS_ABI_64
#else
#define PERF_SAMPLE_REGS_ABI	PERF_SAMPLE_REGS_ABI_32
#endif

#define PERF_REG_IP	PERF_REG_RISCV_PC
#define PERF_REG_SP	PERF_REG_RISCV_SP

static inline const char *__perf_reg_name(int id)
{
	switch (id) {
	case PERF_REG_RISCV_PC:
		return "pc";
	case PERF_REG_RISCV_RA:
		return "ra";
	case PERF_REG_RISCV_SP:
		return "sp";
	case PERF_REG_RISCV_GP:
		return "gp";
	case PERF_REG_RISCV_TP:
		return "tp";
	case PERF_REG_RISCV_T0:
		return "t0";
	case PERF_REG_RISCV_T1:
		return "t1";
	case PERF_REG_RISCV_T2:
		return "t2";
	case PERF_REG_RISCV_S0:
		return "s0";
	case PERF_REG_RISCV_S1:
		return "s1";
	case PERF_REG_RISCV_A0:
		return "a0";
	case PERF_REG_RISCV_A1:
		return "a1";
	case PERF_REG_RISCV_A2:
		return "a2";
	case PERF_REG_RISCV_A3:
		return "a3";
	case PERF_REG_RISCV_A4:
		return "a4";
	case PERF_REG_RISCV_A5:
		return "a5";
	case PERF_REG_RISCV_A6:
		return "a6";
	case PERF_REG_RISCV_A7:
		return "a7";
	case PERF_REG_RISCV_S2:
		return "s2";
	case PERF_REG_RISCV_S3:
		return "s3";
	case PERF_REG_RISCV_S4:
		return "s4";
	case PERF_REG_RISCV_S5:
		return "s5";
	case PERF_REG_RISCV_S6:
		return "s6";
	case PERF_REG_RISCV_S7:
		return "s7";
	case PERF_REG_RISCV_S8:
		return "s8";
	case PERF_REG_RISCV_S9:
		return "s9";
	case PERF_REG_RISCV_S10:
		return "s10";
	case PERF_REG_RISCV_S11:
		return "s11";
	case PERF_REG_RISCV_T3:
		return "t3";
	case PERF_REG_RISCV_T4:
		return "t4";
	case PERF_REG_RISCV_T5:
		return "t5";
	case PERF_REG_RISCV_T6:
		return "t6";
	default:
		return NULL;
	}

	return NULL;
}

#endif /* ARCH_PERF_REGS_H */
Commit	Line	Data
51bc620b MH	1	/* SPDX-License-Identifier: GPL-2.0 */
	2	/* Copyright (C) 2019 Hangzhou C-SKY Microsystems co.,ltd. */
	3
	4	#ifndef ARCH_PERF_REGS_H
	5	#define ARCH_PERF_REGS_H
	6
	7	#include <stdlib.h>
	8	#include <linux/types.h>
	9	#include <asm/perf_regs.h>
	10
	11	#define PERF_REGS_MASK ((1ULL << PERF_REG_RISCV_MAX) - 1)
	12	#define PERF_REGS_MAX PERF_REG_RISCV_MAX
	13	#if __riscv_xlen == 64
	14	#define PERF_SAMPLE_REGS_ABI PERF_SAMPLE_REGS_ABI_64
	15	#else
	16	#define PERF_SAMPLE_REGS_ABI PERF_SAMPLE_REGS_ABI_32
	17	#endif
	18
	19	#define PERF_REG_IP PERF_REG_RISCV_PC
	20	#define PERF_REG_SP PERF_REG_RISCV_SP
	21
92186c88	22	static inline const char *__perf_reg_name(int id)
51bc620b MH	23	{
	24	switch (id) {
	25	case PERF_REG_RISCV_PC:
	26	return "pc";
	27	case PERF_REG_RISCV_RA:
	28	return "ra";
	29	case PERF_REG_RISCV_SP:
	30	return "sp";
	31	case PERF_REG_RISCV_GP:
	32	return "gp";
	33	case PERF_REG_RISCV_TP:
	34	return "tp";
	35	case PERF_REG_RISCV_T0:
	36	return "t0";
	37	case PERF_REG_RISCV_T1:
	38	return "t1";
	39	case PERF_REG_RISCV_T2:
	40	return "t2";
	41	case PERF_REG_RISCV_S0:
	42	return "s0";
	43	case PERF_REG_RISCV_S1:
	44	return "s1";
	45	case PERF_REG_RISCV_A0:
	46	return "a0";
	47	case PERF_REG_RISCV_A1:
	48	return "a1";
	49	case PERF_REG_RISCV_A2:
	50	return "a2";
	51	case PERF_REG_RISCV_A3:
	52	return "a3";
	53	case PERF_REG_RISCV_A4:
	54	return "a4";
	55	case PERF_REG_RISCV_A5:
	56	return "a5";
	57	case PERF_REG_RISCV_A6:
	58	return "a6";
	59	case PERF_REG_RISCV_A7:
	60	return "a7";
	61	case PERF_REG_RISCV_S2:
	62	return "s2";
	63	case PERF_REG_RISCV_S3:
	64	return "s3";
	65	case PERF_REG_RISCV_S4:
	66	return "s4";
	67	case PERF_REG_RISCV_S5:
	68	return "s5";
	69	case PERF_REG_RISCV_S6:
	70	return "s6";
	71	case PERF_REG_RISCV_S7:
	72	return "s7";
	73	case PERF_REG_RISCV_S8:
	74	return "s8";
	75	case PERF_REG_RISCV_S9:
	76	return "s9";
	77	case PERF_REG_RISCV_S10:
	78	return "s10";
	79	case PERF_REG_RISCV_S11:
	80	return "s11";
	81	case PERF_REG_RISCV_T3:
	82	return "t3";
	83	case PERF_REG_RISCV_T4:
	84	return "t4";
	85	case PERF_REG_RISCV_T5:
	86	return "t5";
87	case PERF_REG_RISCV_T6:
88	return "t6";
89	default:
90	return NULL;
91	}
92
93	return NULL;
94	}
95
96	#endif /* ARCH_PERF_REGS_H */