]>
Commit | Line | Data |
---|---|---|
6eda5838 TG |
1 | #ifndef _PERF_PERF_H |
2 | #define _PERF_PERF_H | |
3 | ||
d2709c7c DH |
4 | #include <asm/unistd.h> |
5 | ||
11d1578f | 6 | #if defined(__i386__) |
a94d342b PZ |
7 | #define mb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory") |
8 | #define wmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory") | |
11d1578f VW |
9 | #define rmb() asm volatile("lock; addl $0,0(%%esp)" ::: "memory") |
10 | #define cpu_relax() asm volatile("rep; nop" ::: "memory"); | |
fbe96f29 | 11 | #define CPUINFO_PROC "model name" |
eae7a755 IM |
12 | #ifndef __NR_perf_event_open |
13 | # define __NR_perf_event_open 336 | |
14 | #endif | |
a0439711 DB |
15 | #ifndef __NR_futex |
16 | # define __NR_futex 240 | |
17 | #endif | |
11d1578f VW |
18 | #endif |
19 | ||
20 | #if defined(__x86_64__) | |
a94d342b PZ |
21 | #define mb() asm volatile("mfence" ::: "memory") |
22 | #define wmb() asm volatile("sfence" ::: "memory") | |
1a482f38 PZ |
23 | #define rmb() asm volatile("lfence" ::: "memory") |
24 | #define cpu_relax() asm volatile("rep; nop" ::: "memory"); | |
fbe96f29 | 25 | #define CPUINFO_PROC "model name" |
eae7a755 IM |
26 | #ifndef __NR_perf_event_open |
27 | # define __NR_perf_event_open 298 | |
28 | #endif | |
a0439711 DB |
29 | #ifndef __NR_futex |
30 | # define __NR_futex 202 | |
31 | #endif | |
1a482f38 PZ |
32 | #endif |
33 | ||
34 | #ifdef __powerpc__ | |
1483c2ae | 35 | #include "../../arch/powerpc/include/uapi/asm/unistd.h" |
a94d342b PZ |
36 | #define mb() asm volatile ("sync" ::: "memory") |
37 | #define wmb() asm volatile ("sync" ::: "memory") | |
1a482f38 | 38 | #define rmb() asm volatile ("sync" ::: "memory") |
fbe96f29 | 39 | #define CPUINFO_PROC "cpu" |
1a482f38 PZ |
40 | #endif |
41 | ||
12310e9c | 42 | #ifdef __s390__ |
a94d342b PZ |
43 | #define mb() asm volatile("bcr 15,0" ::: "memory") |
44 | #define wmb() asm volatile("bcr 15,0" ::: "memory") | |
12310e9c | 45 | #define rmb() asm volatile("bcr 15,0" ::: "memory") |
12310e9c MS |
46 | #endif |
47 | ||
febe8345 | 48 | #ifdef __sh__ |
febe8345 | 49 | #if defined(__SH4A__) || defined(__SH5__) |
a94d342b PZ |
50 | # define mb() asm volatile("synco" ::: "memory") |
51 | # define wmb() asm volatile("synco" ::: "memory") | |
febe8345 PM |
52 | # define rmb() asm volatile("synco" ::: "memory") |
53 | #else | |
a94d342b PZ |
54 | # define mb() asm volatile("" ::: "memory") |
55 | # define wmb() asm volatile("" ::: "memory") | |
febe8345 PM |
56 | # define rmb() asm volatile("" ::: "memory") |
57 | #endif | |
fbe96f29 | 58 | #define CPUINFO_PROC "cpu type" |
febe8345 PM |
59 | #endif |
60 | ||
2d4618dc | 61 | #ifdef __hppa__ |
a94d342b PZ |
62 | #define mb() asm volatile("" ::: "memory") |
63 | #define wmb() asm volatile("" ::: "memory") | |
2d4618dc | 64 | #define rmb() asm volatile("" ::: "memory") |
fbe96f29 | 65 | #define CPUINFO_PROC "cpu" |
2d4618dc KM |
66 | #endif |
67 | ||
825c9fb4 | 68 | #ifdef __sparc__ |
a94d342b PZ |
69 | #ifdef __LP64__ |
70 | #define mb() asm volatile("ba,pt %%xcc, 1f\n" \ | |
71 | "membar #StoreLoad\n" \ | |
72 | "1:\n":::"memory") | |
73 | #else | |
74 | #define mb() asm volatile("":::"memory") | |
75 | #endif | |
76 | #define wmb() asm volatile("":::"memory") | |
825c9fb4 | 77 | #define rmb() asm volatile("":::"memory") |
fbe96f29 | 78 | #define CPUINFO_PROC "cpu" |
825c9fb4 JA |
79 | #endif |
80 | ||
fcd14b32 | 81 | #ifdef __alpha__ |
a94d342b PZ |
82 | #define mb() asm volatile("mb" ::: "memory") |
83 | #define wmb() asm volatile("wmb" ::: "memory") | |
fcd14b32 | 84 | #define rmb() asm volatile("mb" ::: "memory") |
fbe96f29 | 85 | #define CPUINFO_PROC "cpu model" |
fcd14b32 MC |
86 | #endif |
87 | ||
11ada26c | 88 | #ifdef __ia64__ |
a94d342b PZ |
89 | #define mb() asm volatile ("mf" ::: "memory") |
90 | #define wmb() asm volatile ("mf" ::: "memory") | |
11ada26c TL |
91 | #define rmb() asm volatile ("mf" ::: "memory") |
92 | #define cpu_relax() asm volatile ("hint @pause" ::: "memory") | |
fbe96f29 | 93 | #define CPUINFO_PROC "model name" |
11ada26c TL |
94 | #endif |
95 | ||
58e9f941 | 96 | #ifdef __arm__ |
58e9f941 JI |
97 | /* |
98 | * Use the __kuser_memory_barrier helper in the CPU helper page. See | |
99 | * arch/arm/kernel/entry-armv.S in the kernel source for details. | |
100 | */ | |
a94d342b PZ |
101 | #define mb() ((void(*)(void))0xffff0fa0)() |
102 | #define wmb() ((void(*)(void))0xffff0fa0)() | |
da7196e1 | 103 | #define rmb() ((void(*)(void))0xffff0fa0)() |
fbe96f29 | 104 | #define CPUINFO_PROC "Processor" |
58e9f941 JI |
105 | #endif |
106 | ||
03089688 | 107 | #ifdef __aarch64__ |
a94d342b | 108 | #define mb() asm volatile("dmb ish" ::: "memory") |
f428ebd1 PZ |
109 | #define wmb() asm volatile("dmb ishst" ::: "memory") |
110 | #define rmb() asm volatile("dmb ishld" ::: "memory") | |
03089688 WD |
111 | #define cpu_relax() asm volatile("yield" ::: "memory") |
112 | #endif | |
113 | ||
c1e028ef | 114 | #ifdef __mips__ |
a94d342b | 115 | #define mb() asm volatile( \ |
c1e028ef DCZ |
116 | ".set mips2\n\t" \ |
117 | "sync\n\t" \ | |
118 | ".set mips0" \ | |
119 | : /* no output */ \ | |
120 | : /* no input */ \ | |
121 | : "memory") | |
a94d342b PZ |
122 | #define wmb() mb() |
123 | #define rmb() mb() | |
fbe96f29 | 124 | #define CPUINFO_PROC "cpu model" |
c1e028ef DCZ |
125 | #endif |
126 | ||
9854783e | 127 | #ifdef __arc__ |
a94d342b PZ |
128 | #define mb() asm volatile("" ::: "memory") |
129 | #define wmb() asm volatile("" ::: "memory") | |
9854783e | 130 | #define rmb() asm volatile("" ::: "memory") |
9854783e VG |
131 | #define CPUINFO_PROC "Processor" |
132 | #endif | |
133 | ||
1bea5b81 | 134 | #ifdef __metag__ |
a94d342b PZ |
135 | #define mb() asm volatile("" ::: "memory") |
136 | #define wmb() asm volatile("" ::: "memory") | |
1bea5b81 | 137 | #define rmb() asm volatile("" ::: "memory") |
1bea5b81 JH |
138 | #define CPUINFO_PROC "CPU" |
139 | #endif | |
140 | ||
3a46817f BS |
141 | #ifdef __xtensa__ |
142 | #define mb() asm volatile("memw" ::: "memory") | |
143 | #define wmb() asm volatile("memw" ::: "memory") | |
144 | #define rmb() asm volatile("" ::: "memory") | |
145 | #define CPUINFO_PROC "core ID" | |
146 | #endif | |
147 | ||
620830b6 ZL |
148 | #ifdef __tile__ |
149 | #define mb() asm volatile ("mf" ::: "memory") | |
150 | #define wmb() asm volatile ("mf" ::: "memory") | |
151 | #define rmb() asm volatile ("mf" ::: "memory") | |
152 | #define cpu_relax() asm volatile ("mfspr zero, PASS" ::: "memory") | |
153 | #define CPUINFO_PROC "model name" | |
154 | #endif | |
155 | ||
a94d342b PZ |
156 | #define barrier() asm volatile ("" ::: "memory") |
157 | ||
158 | #ifndef cpu_relax | |
159 | #define cpu_relax() barrier() | |
160 | #endif | |
161 | ||
162 | #define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x)) | |
163 | ||
164 | ||
1a482f38 PZ |
165 | #include <time.h> |
166 | #include <unistd.h> | |
167 | #include <sys/types.h> | |
168 | #include <sys/syscall.h> | |
169 | ||
d2709c7c | 170 | #include <linux/perf_event.h> |
7c6a1c65 | 171 | #include "util/types.h" |
8035458f | 172 | #include <stdbool.h> |
1a482f38 | 173 | |
6eda5838 | 174 | /* |
cdd6c482 | 175 | * prctl(PR_TASK_PERF_EVENTS_DISABLE) will (cheaply) disable all |
6eda5838 TG |
176 | * counters in the current task. |
177 | */ | |
cdd6c482 IM |
178 | #define PR_TASK_PERF_EVENTS_DISABLE 31 |
179 | #define PR_TASK_PERF_EVENTS_ENABLE 32 | |
6eda5838 | 180 | |
a92e7023 TG |
181 | #ifndef NSEC_PER_SEC |
182 | # define NSEC_PER_SEC 1000000000ULL | |
183 | #endif | |
70f7b4a7 DA |
184 | #ifndef NSEC_PER_USEC |
185 | # define NSEC_PER_USEC 1000ULL | |
186 | #endif | |
a92e7023 TG |
187 | |
188 | static inline unsigned long long rdclock(void) | |
189 | { | |
190 | struct timespec ts; | |
191 | ||
192 | clock_gettime(CLOCK_MONOTONIC, &ts); | |
193 | return ts.tv_sec * 1000000000ULL + ts.tv_nsec; | |
194 | } | |
6eda5838 TG |
195 | |
196 | /* | |
197 | * Pick up some kernel type conventions: | |
198 | */ | |
199 | #define __user | |
200 | #define asmlinkage | |
201 | ||
6eda5838 TG |
202 | #define unlikely(x) __builtin_expect(!!(x), 0) |
203 | #define min(x, y) ({ \ | |
204 | typeof(x) _min1 = (x); \ | |
205 | typeof(y) _min2 = (y); \ | |
206 | (void) (&_min1 == &_min2); \ | |
207 | _min1 < _min2 ? _min1 : _min2; }) | |
208 | ||
52502bf2 JO |
209 | extern bool test_attr__enabled; |
210 | void test_attr__init(void); | |
211 | void test_attr__open(struct perf_event_attr *attr, pid_t pid, int cpu, | |
212 | int fd, int group_fd, unsigned long flags); | |
213 | ||
6eda5838 | 214 | static inline int |
cdd6c482 | 215 | sys_perf_event_open(struct perf_event_attr *attr, |
6eda5838 TG |
216 | pid_t pid, int cpu, int group_fd, |
217 | unsigned long flags) | |
218 | { | |
52502bf2 JO |
219 | int fd; |
220 | ||
221 | fd = syscall(__NR_perf_event_open, attr, pid, cpu, | |
222 | group_fd, flags); | |
223 | ||
224 | if (unlikely(test_attr__enabled)) | |
225 | test_attr__open(attr, pid, cpu, fd, group_fd, flags); | |
226 | ||
227 | return fd; | |
6eda5838 TG |
228 | } |
229 | ||
85a9f920 IM |
230 | #define MAX_COUNTERS 256 |
231 | #define MAX_NR_CPUS 256 | |
6eda5838 | 232 | |
8cb76d99 FW |
233 | struct ip_callchain { |
234 | u64 nr; | |
235 | u64 ips[0]; | |
f5970550 PZ |
236 | }; |
237 | ||
b5387528 RAV |
238 | struct branch_flags { |
239 | u64 mispred:1; | |
240 | u64 predicted:1; | |
f5d05bce AK |
241 | u64 in_tx:1; |
242 | u64 abort:1; | |
243 | u64 reserved:60; | |
b5387528 RAV |
244 | }; |
245 | ||
246 | struct branch_entry { | |
247 | u64 from; | |
248 | u64 to; | |
249 | struct branch_flags flags; | |
250 | }; | |
251 | ||
252 | struct branch_stack { | |
253 | u64 nr; | |
254 | struct branch_entry entries[0]; | |
255 | }; | |
256 | ||
70cb4e96 | 257 | extern const char *input_name; |
8035458f | 258 | extern bool perf_host, perf_guest; |
fbe96f29 | 259 | extern const char perf_version_string[]; |
a1645ce1 | 260 | |
3af6e338 ACM |
261 | void pthread__unblock_sigwinch(void); |
262 | ||
12864b31 | 263 | #include "util/target.h" |
bea03405 | 264 | |
26d33022 JO |
265 | enum perf_call_graph_mode { |
266 | CALLCHAIN_NONE, | |
267 | CALLCHAIN_FP, | |
a601fdff JO |
268 | CALLCHAIN_DWARF, |
269 | CALLCHAIN_MAX | |
26d33022 JO |
270 | }; |
271 | ||
b4006796 | 272 | struct record_opts { |
602ad878 | 273 | struct target target; |
26d33022 | 274 | int call_graph; |
eb853e80 | 275 | bool call_graph_enabled; |
ed80f581 | 276 | bool group; |
0f82ebc4 | 277 | bool inherit_stat; |
509051ea | 278 | bool no_buffering; |
0f82ebc4 | 279 | bool no_inherit; |
69e7e5b0 | 280 | bool no_inherit_set; |
0f82ebc4 ACM |
281 | bool no_samples; |
282 | bool raw_samples; | |
283 | bool sample_address; | |
05484298 | 284 | bool sample_weight; |
0f82ebc4 | 285 | bool sample_time; |
3e76ac78 | 286 | bool period; |
0f82ebc4 | 287 | unsigned int freq; |
01c2d99b | 288 | unsigned int mmap_pages; |
0f82ebc4 | 289 | unsigned int user_freq; |
a00dc319 | 290 | u64 branch_stack; |
0f82ebc4 ACM |
291 | u64 default_interval; |
292 | u64 user_interval; | |
26d33022 | 293 | u16 stack_dump_size; |
475eeab9 | 294 | bool sample_transaction; |
6619a53e | 295 | unsigned initial_delay; |
0f82ebc4 ACM |
296 | }; |
297 | ||
6eda5838 | 298 | #endif |