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Commit | Line | Data |
---|---|---|
093c280d GK |
1 | [ |
2 | { | |
4b553a9f | 3 | "ArchStdEvent": "L1D_CACHE_RD", |
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4 | }, |
5 | { | |
4b553a9f | 6 | "ArchStdEvent": "L1D_CACHE_WR", |
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7 | }, |
8 | { | |
4b553a9f | 9 | "ArchStdEvent": "L1D_CACHE_REFILL_RD", |
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10 | }, |
11 | { | |
4b553a9f | 12 | "ArchStdEvent": "L1D_CACHE_REFILL_WR", |
093c280d | 13 | }, |
9f1e2b50 GK |
14 | { |
15 | "ArchStdEvent": "L1D_CACHE_REFILL_INNER", | |
16 | }, | |
17 | { | |
18 | "ArchStdEvent": "L1D_CACHE_REFILL_OUTER", | |
19 | }, | |
20 | { | |
21 | "ArchStdEvent": "L1D_CACHE_WB_VICTIM", | |
22 | }, | |
23 | { | |
24 | "ArchStdEvent": "L1D_CACHE_WB_CLEAN", | |
25 | }, | |
26 | { | |
27 | "ArchStdEvent": "L1D_CACHE_INVAL", | |
28 | }, | |
093c280d | 29 | { |
4b553a9f | 30 | "ArchStdEvent": "L1D_TLB_REFILL_RD", |
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31 | }, |
32 | { | |
4b553a9f | 33 | "ArchStdEvent": "L1D_TLB_REFILL_WR", |
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34 | }, |
35 | { | |
4b553a9f | 36 | "ArchStdEvent": "L1D_TLB_RD", |
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37 | }, |
38 | { | |
4b553a9f | 39 | "ArchStdEvent": "L1D_TLB_WR", |
093c280d | 40 | }, |
9f1e2b50 GK |
41 | { |
42 | "ArchStdEvent": "L2D_TLB_REFILL_RD", | |
43 | }, | |
44 | { | |
45 | "ArchStdEvent": "L2D_TLB_REFILL_WR", | |
46 | }, | |
47 | { | |
48 | "ArchStdEvent": "L2D_TLB_RD", | |
49 | }, | |
50 | { | |
51 | "ArchStdEvent": "L2D_TLB_WR", | |
52 | }, | |
093c280d | 53 | { |
4b553a9f | 54 | "ArchStdEvent": "BUS_ACCESS_RD", |
9f1e2b50 GK |
55 | }, |
56 | { | |
4b553a9f | 57 | "ArchStdEvent": "BUS_ACCESS_WR", |
9f1e2b50 GK |
58 | }, |
59 | { | |
60 | "ArchStdEvent": "MEM_ACCESS_RD", | |
61 | }, | |
62 | { | |
63 | "ArchStdEvent": "MEM_ACCESS_WR", | |
64 | }, | |
65 | { | |
66 | "ArchStdEvent": "UNALIGNED_LD_SPEC", | |
67 | }, | |
68 | { | |
69 | "ArchStdEvent": "UNALIGNED_ST_SPEC", | |
70 | }, | |
71 | { | |
72 | "ArchStdEvent": "UNALIGNED_LDST_SPEC", | |
73 | }, | |
74 | { | |
75 | "ArchStdEvent": "EXC_UNDEF", | |
76 | }, | |
77 | { | |
78 | "ArchStdEvent": "EXC_SVC", | |
79 | }, | |
80 | { | |
81 | "ArchStdEvent": "EXC_PABORT", | |
82 | }, | |
83 | { | |
84 | "ArchStdEvent": "EXC_DABORT", | |
85 | }, | |
86 | { | |
87 | "ArchStdEvent": "EXC_IRQ", | |
88 | }, | |
89 | { | |
90 | "ArchStdEvent": "EXC_FIQ", | |
91 | }, | |
92 | { | |
93 | "ArchStdEvent": "EXC_SMC", | |
94 | }, | |
95 | { | |
96 | "ArchStdEvent": "EXC_HVC", | |
97 | }, | |
98 | { | |
99 | "ArchStdEvent": "EXC_TRAP_PABORT", | |
100 | }, | |
101 | { | |
102 | "ArchStdEvent": "EXC_TRAP_DABORT", | |
103 | }, | |
104 | { | |
105 | "ArchStdEvent": "EXC_TRAP_OTHER", | |
106 | }, | |
107 | { | |
108 | "ArchStdEvent": "EXC_TRAP_IRQ", | |
109 | }, | |
110 | { | |
111 | "ArchStdEvent": "EXC_TRAP_FIQ", | |
112 | } | |
093c280d | 113 | ] |