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Commit | Line | Data |
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826db0f1 SB |
1 | [ |
2 | {, | |
3c22ba52 SB |
3 | "EventCode": "0x300F4", |
4 | "EventName": "PM_THRD_CONC_RUN_INST", | |
5 | "BriefDescription": "PPC Instructions Finished by this thread when all threads in the core had the run-latch set" | |
826db0f1 SB |
6 | }, |
7 | {, | |
3c22ba52 SB |
8 | "EventCode": "0x1E056", |
9 | "EventName": "PM_CMPLU_STALL_FLUSH_ANY_THREAD", | |
10 | "BriefDescription": "Cycles in which the NTC instruction is not allowed to complete because any of the 4 threads in the same core suffered a flush, which blocks completion" | |
826db0f1 SB |
11 | }, |
12 | {, | |
3c22ba52 SB |
13 | "EventCode": "0x4D016", |
14 | "EventName": "PM_CMPLU_STALL_FXLONG", | |
15 | "BriefDescription": "Completion stall due to a long latency scalar fixed point instruction (division, square root)" | |
826db0f1 SB |
16 | }, |
17 | {, | |
3c22ba52 SB |
18 | "EventCode": "0x2D016", |
19 | "EventName": "PM_CMPLU_STALL_FXU", | |
20 | "BriefDescription": "Finish stall due to a scalar fixed point or CR instruction in the execution pipeline. These instructions get routed to the ALU, ALU2, and DIV pipes" | |
826db0f1 SB |
21 | }, |
22 | {, | |
3c22ba52 SB |
23 | "EventCode": "0x1D15C", |
24 | "EventName": "PM_MRK_DTLB_MISS_1G", | |
25 | "BriefDescription": "Marked Data TLB reload (after a miss) page size 2M. Implies radix translation was used" | |
826db0f1 SB |
26 | }, |
27 | {, | |
3c22ba52 SB |
28 | "EventCode": "0x4D12A", |
29 | "EventName": "PM_MRK_DATA_FROM_RL4_CYC", | |
30 | "BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load" | |
826db0f1 SB |
31 | }, |
32 | {, | |
3c22ba52 SB |
33 | "EventCode": "0x1003C", |
34 | "EventName": "PM_CMPLU_STALL_DMISS_L2L3", | |
35 | "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3" | |
826db0f1 SB |
36 | }, |
37 | {, | |
3c22ba52 SB |
38 | "EventCode": "0x4C014", |
39 | "EventName": "PM_CMPLU_STALL_LMQ_FULL", | |
40 | "BriefDescription": "Finish stall because the NTF instruction was a load that missed in the L1 and the LMQ was unable to accept this load miss request because it was full" | |
826db0f1 SB |
41 | }, |
42 | {, | |
3c22ba52 SB |
43 | "EventCode": "0x14048", |
44 | "EventName": "PM_INST_FROM_ON_CHIP_CACHE", | |
45 | "BriefDescription": "The processor's Instruction cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to an instruction fetch (not prefetch)" | |
826db0f1 SB |
46 | }, |
47 | {, | |
3c22ba52 SB |
48 | "EventCode": "0x4D014", |
49 | "EventName": "PM_CMPLU_STALL_LOAD_FINISH", | |
50 | "BriefDescription": "Finish stall because the NTF instruction was a load instruction with all its dependencies satisfied just going through the LSU pipe to finish" | |
826db0f1 SB |
51 | }, |
52 | {, | |
3c22ba52 SB |
53 | "EventCode": "0x2404A", |
54 | "EventName": "PM_INST_FROM_RL4", | |
55 | "BriefDescription": "The processor's Instruction cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to an instruction fetch (not prefetch)" | |
826db0f1 SB |
56 | }, |
57 | {, | |
3c22ba52 SB |
58 | "EventCode": "0x1404A", |
59 | "EventName": "PM_INST_FROM_RL2L3_SHR", | |
60 | "BriefDescription": "The processor's Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)" | |
826db0f1 SB |
61 | }, |
62 | {, | |
3c22ba52 SB |
63 | "EventCode": "0x401EA", |
64 | "EventName": "PM_THRESH_EXC_128", | |
65 | "BriefDescription": "Threshold counter exceeded a value of 128" | |
826db0f1 SB |
66 | }, |
67 | {, | |
3c22ba52 SB |
68 | "EventCode": "0x400F6", |
69 | "EventName": "PM_BR_MPRED_CMPL", | |
70 | "BriefDescription": "Number of Branch Mispredicts" | |
826db0f1 SB |
71 | }, |
72 | {, | |
73 | "EventCode": "0x2F140", | |
74 | "EventName": "PM_MRK_DPTEG_FROM_L2_MEPF", | |
3c22ba52 | 75 | "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" |
826db0f1 SB |
76 | }, |
77 | {, | |
3c22ba52 SB |
78 | "EventCode": "0x101E6", |
79 | "EventName": "PM_THRESH_EXC_4096", | |
80 | "BriefDescription": "Threshold counter exceed a count of 4096" | |
826db0f1 SB |
81 | }, |
82 | {, | |
83 | "EventCode": "0x3D156", | |
84 | "EventName": "PM_MRK_DTLB_MISS_64K", | |
3c22ba52 | 85 | "BriefDescription": "Marked Data TLB Miss page size 64K" |
826db0f1 SB |
86 | }, |
87 | {, | |
3c22ba52 SB |
88 | "EventCode": "0x4C15E", |
89 | "EventName": "PM_MRK_DTLB_MISS_16M", | |
90 | "BriefDescription": "Marked Data TLB Miss page size 16M" | |
826db0f1 SB |
91 | }, |
92 | {, | |
3c22ba52 SB |
93 | "EventCode": "0x2D15E", |
94 | "EventName": "PM_MRK_DTLB_MISS_16G", | |
95 | "BriefDescription": "Marked Data TLB Miss page size 16G" | |
826db0f1 SB |
96 | }, |
97 | {, | |
3c22ba52 SB |
98 | "EventCode": "0x3F14A", |
99 | "EventName": "PM_MRK_DPTEG_FROM_RMEM", | |
100 | "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" | |
826db0f1 SB |
101 | }, |
102 | {, | |
103 | "EventCode": "0x4C016", | |
104 | "EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT", | |
3c22ba52 | 105 | "BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict" |
826db0f1 SB |
106 | }, |
107 | {, | |
3c22ba52 SB |
108 | "EventCode": "0x2C01A", |
109 | "EventName": "PM_CMPLU_STALL_LHS", | |
110 | "BriefDescription": "Finish stall because the NTF instruction was a load that hit on an older store and it was waiting for store data" | |
826db0f1 SB |
111 | }, |
112 | {, | |
3c22ba52 SB |
113 | "EventCode": "0x401E4", |
114 | "EventName": "PM_MRK_DTLB_MISS", | |
115 | "BriefDescription": "Marked dtlb miss" | |
826db0f1 SB |
116 | }, |
117 | {, | |
3c22ba52 SB |
118 | "EventCode": "0x24046", |
119 | "EventName": "PM_INST_FROM_RL2L3_MOD", | |
120 | "BriefDescription": "The processor's Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to an instruction fetch (not prefetch)" | |
826db0f1 SB |
121 | }, |
122 | {, | |
3c22ba52 SB |
123 | "EventCode": "0x1002A", |
124 | "EventName": "PM_CMPLU_STALL_LARX", | |
125 | "BriefDescription": "Finish stall because the NTF instruction was a larx waiting to be satisfied" | |
826db0f1 | 126 | }, |
826db0f1 | 127 | {, |
3c22ba52 SB |
128 | "EventCode": "0x1C058", |
129 | "EventName": "PM_DTLB_MISS_16G", | |
130 | "BriefDescription": "Data TLB Miss page size 16G" | |
826db0f1 | 131 | } |
3c22ba52 | 132 | ] |