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Commit | Line | Data |
---|---|---|
00f954ba SB |
1 | [ |
2 | {, | |
5d6d79e0 SB |
3 | "EventCode": "0x20036", |
4 | "EventName": "PM_BR_2PATH", | |
5 | "BriefDescription": "Branches that are not strongly biased" | |
00f954ba | 6 | }, |
00f954ba | 7 | {, |
5d6d79e0 SB |
8 | "EventCode": "0x40056", |
9 | "EventName": "PM_MEM_LOC_THRESH_LSU_HIGH", | |
10 | "BriefDescription": "Local memory above threshold for LSU medium" | |
00f954ba SB |
11 | }, |
12 | {, | |
5d6d79e0 SB |
13 | "EventCode": "0x2C056", |
14 | "EventName": "PM_DTLB_MISS_4K", | |
15 | "BriefDescription": "Data TLB Miss page size 4k" | |
00f954ba SB |
16 | }, |
17 | {, | |
5d6d79e0 SB |
18 | "EventCode": "0x40118", |
19 | "EventName": "PM_MRK_DCACHE_RELOAD_INTV", | |
20 | "BriefDescription": "Combined Intervention event" | |
00f954ba SB |
21 | }, |
22 | {, | |
5d6d79e0 SB |
23 | "EventCode": "0x4F148", |
24 | "EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD", | |
25 | "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" | |
00f954ba SB |
26 | }, |
27 | {, | |
5d6d79e0 SB |
28 | "EventCode": "0x301E8", |
29 | "EventName": "PM_THRESH_EXC_64", | |
30 | "BriefDescription": "Threshold counter exceeded a value of 64" | |
00f954ba SB |
31 | }, |
32 | {, | |
5d6d79e0 SB |
33 | "EventCode": "0x4E04E", |
34 | "EventName": "PM_DPTEG_FROM_L3MISS", | |
35 | "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" | |
00f954ba SB |
36 | }, |
37 | {, | |
5d6d79e0 SB |
38 | "EventCode": "0x40050", |
39 | "EventName": "PM_SYS_PUMP_MPRED_RTY", | |
40 | "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)" | |
00f954ba SB |
41 | }, |
42 | {, | |
5d6d79e0 SB |
43 | "EventCode": "0x1F14E", |
44 | "EventName": "PM_MRK_DPTEG_FROM_L2MISS", | |
45 | "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" | |
00f954ba SB |
46 | }, |
47 | {, | |
5d6d79e0 SB |
48 | "EventCode": "0x4D018", |
49 | "EventName": "PM_CMPLU_STALL_BRU", | |
50 | "BriefDescription": "Completion stall due to a Branch Unit" | |
00f954ba SB |
51 | }, |
52 | {, | |
5d6d79e0 SB |
53 | "EventCode": "0x45052", |
54 | "EventName": "PM_4FLOP_CMPL", | |
55 | "BriefDescription": "4 FLOP instruction completed" | |
00f954ba SB |
56 | }, |
57 | {, | |
5d6d79e0 SB |
58 | "EventCode": "0x3D142", |
59 | "EventName": "PM_MRK_DATA_FROM_LMEM", | |
60 | "BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load" | |
00f954ba SB |
61 | }, |
62 | {, | |
63 | "EventCode": "0x4C01E", | |
64 | "EventName": "PM_CMPLU_STALL_CRYPTO", | |
5d6d79e0 | 65 | "BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish" |
00f954ba SB |
66 | }, |
67 | {, | |
5d6d79e0 SB |
68 | "EventCode": "0x3000C", |
69 | "EventName": "PM_FREQ_DOWN", | |
70 | "BriefDescription": "Power Management: Below Threshold B" | |
00f954ba SB |
71 | }, |
72 | {, | |
73 | "EventCode": "0x4D128", | |
74 | "EventName": "PM_MRK_DATA_FROM_LMEM_CYC", | |
5d6d79e0 | 75 | "BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load" |
00f954ba SB |
76 | }, |
77 | {, | |
5d6d79e0 SB |
78 | "EventCode": "0x4D054", |
79 | "EventName": "PM_8FLOP_CMPL", | |
80 | "BriefDescription": "8 FLOP instruction completed" | |
00f954ba SB |
81 | }, |
82 | {, | |
5d6d79e0 SB |
83 | "EventCode": "0x10026", |
84 | "EventName": "PM_TABLEWALK_CYC", | |
85 | "BriefDescription": "Cycles when an instruction tablewalk is active" | |
00f954ba SB |
86 | }, |
87 | {, | |
5d6d79e0 SB |
88 | "EventCode": "0x2C012", |
89 | "EventName": "PM_CMPLU_STALL_DCACHE_MISS", | |
90 | "BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest" | |
00f954ba SB |
91 | }, |
92 | {, | |
5d6d79e0 SB |
93 | "EventCode": "0x2E04C", |
94 | "EventName": "PM_DPTEG_FROM_MEMORY", | |
95 | "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" | |
00f954ba SB |
96 | }, |
97 | {, | |
5d6d79e0 SB |
98 | "EventCode": "0x3F142", |
99 | "EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT", | |
100 | "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" | |
00f954ba SB |
101 | }, |
102 | {, | |
5d6d79e0 SB |
103 | "EventCode": "0x4F142", |
104 | "EventName": "PM_MRK_DPTEG_FROM_L3", | |
105 | "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" | |
00f954ba SB |
106 | }, |
107 | {, | |
5d6d79e0 SB |
108 | "EventCode": "0x10060", |
109 | "EventName": "PM_TM_TRANS_RUN_CYC", | |
110 | "BriefDescription": "run cycles in transactional state" | |
00f954ba SB |
111 | }, |
112 | {, | |
5d6d79e0 SB |
113 | "EventCode": "0x1E04C", |
114 | "EventName": "PM_DPTEG_FROM_LL4", | |
115 | "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included" | |
116 | }, | |
117 | {, | |
118 | "EventCode": "0x45050", | |
119 | "EventName": "PM_1FLOP_CMPL", | |
120 | "BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed" | |
00f954ba | 121 | } |
034307c6 | 122 | ] |