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Commit | Line | Data |
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2099f51d AK |
1 | [ |
2 | { | |
fd550098 | 3 | "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend", |
61ec07f5 | 4 | "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)", |
fd550098 | 5 | "MetricGroup": "TopdownL1", |
61ec07f5 HS |
6 | "MetricName": "Frontend_Bound", |
7 | "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound." | |
fd550098 AK |
8 | }, |
9 | { | |
fd550098 | 10 | "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", |
61ec07f5 | 11 | "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", |
fd550098 | 12 | "MetricGroup": "TopdownL1_SMT", |
61ec07f5 HS |
13 | "MetricName": "Frontend_Bound_SMT", |
14 | "PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-ops (uops). Ideally the Frontend can issue 4 uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU." | |
fd550098 AK |
15 | }, |
16 | { | |
fd550098 | 17 | "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations", |
61ec07f5 | 18 | "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)", |
fd550098 | 19 | "MetricGroup": "TopdownL1", |
61ec07f5 HS |
20 | "MetricName": "Bad_Speculation", |
21 | "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example." | |
fd550098 AK |
22 | }, |
23 | { | |
fd550098 | 24 | "BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.", |
61ec07f5 | 25 | "MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", |
fd550098 | 26 | "MetricGroup": "TopdownL1_SMT", |
61ec07f5 HS |
27 | "MetricName": "Bad_Speculation_SMT", |
28 | "PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU." | |
fd550098 AK |
29 | }, |
30 | { | |
fd550098 | 31 | "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend", |
61ec07f5 | 32 | "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * cycles)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * cycles)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)) )", |
fd550098 | 33 | "MetricGroup": "TopdownL1", |
61ec07f5 HS |
34 | "MetricName": "Backend_Bound", |
35 | "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound." | |
fd550098 AK |
36 | }, |
37 | { | |
fd550098 | 38 | "BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.", |
61ec07f5 | 39 | "MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * (( INT_MISC.RECOVERY_CYCLES_ANY / 2 )) ) / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) )", |
fd550098 | 40 | "MetricGroup": "TopdownL1_SMT", |
61ec07f5 HS |
41 | "MetricName": "Backend_Bound_SMT", |
42 | "PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU." | |
fd550098 AK |
43 | }, |
44 | { | |
fd550098 | 45 | "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired", |
61ec07f5 | 46 | "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * cycles)", |
fd550098 | 47 | "MetricGroup": "TopdownL1", |
61ec07f5 HS |
48 | "MetricName": "Retiring", |
49 | "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. " | |
fd550098 AK |
50 | }, |
51 | { | |
fd550098 | 52 | "BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.", |
61ec07f5 | 53 | "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))", |
fd550098 | 54 | "MetricGroup": "TopdownL1_SMT", |
61ec07f5 HS |
55 | "MetricName": "Retiring_SMT", |
56 | "PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum 4 uops retired per cycle has been achieved. Maximizing Retiring typically increases the Instruction-Per-Cycle metric. Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Microcode assists are categorized under Retiring. They hurt performance and can often be avoided. SMT version; use when SMT is enabled and measuring per logical CPU." | |
fd550098 AK |
57 | }, |
58 | { | |
61ec07f5 | 59 | "BriefDescription": "Instructions Per Cycle (per Logical Processor)", |
2099f51d AK |
60 | "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", |
61 | "MetricGroup": "TopDownL1", | |
62 | "MetricName": "IPC" | |
63 | }, | |
64 | { | |
fd550098 | 65 | "BriefDescription": "Uops Per Instruction", |
61ec07f5 HS |
66 | "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", |
67 | "MetricGroup": "Pipeline;Retire", | |
2099f51d AK |
68 | "MetricName": "UPI" |
69 | }, | |
70 | { | |
fd550098 | 71 | "BriefDescription": "Instruction per taken branch", |
61ec07f5 HS |
72 | "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", |
73 | "MetricGroup": "Branches;Fetch_BW;PGO", | |
fd550098 AK |
74 | "MetricName": "IpTB" |
75 | }, | |
76 | { | |
fd550098 | 77 | "BriefDescription": "Branch instructions per taken branch. ", |
61ec07f5 | 78 | "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN", |
fd550098 AK |
79 | "MetricGroup": "Branches;PGO", |
80 | "MetricName": "BpTB" | |
81 | }, | |
82 | { | |
fd550098 | 83 | "BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely (includes speculatively fetches) consumed by program instructions", |
61ec07f5 HS |
84 | "MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( (UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY) * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )", |
85 | "MetricGroup": "PGO;IcMiss", | |
2099f51d AK |
86 | "MetricName": "IFetch_Line_Utilization" |
87 | }, | |
88 | { | |
fd550098 | 89 | "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)", |
61ec07f5 HS |
90 | "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )", |
91 | "MetricGroup": "DSB;Fetch_BW", | |
2099f51d AK |
92 | "MetricName": "DSB_Coverage" |
93 | }, | |
94 | { | |
61ec07f5 | 95 | "BriefDescription": "Cycles Per Instruction (per Logical Processor)", |
0fba08e2 | 96 | "MetricExpr": "1 / (INST_RETIRED.ANY / cycles)", |
2099f51d AK |
97 | "MetricGroup": "Pipeline;Summary", |
98 | "MetricName": "CPI" | |
99 | }, | |
100 | { | |
61ec07f5 | 101 | "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.", |
2099f51d AK |
102 | "MetricExpr": "CPU_CLK_UNHALTED.THREAD", |
103 | "MetricGroup": "Summary", | |
104 | "MetricName": "CLKS" | |
105 | }, | |
106 | { | |
61ec07f5 | 107 | "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", |
fd550098 | 108 | "MetricExpr": "4 * cycles", |
2099f51d AK |
109 | "MetricGroup": "TopDownL1", |
110 | "MetricName": "SLOTS" | |
111 | }, | |
112 | { | |
61ec07f5 | 113 | "BriefDescription": "Total issue-pipeline slots (per-Physical Core)", |
fd550098 | 114 | "MetricExpr": "4 * (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", |
fd550098 AK |
115 | "MetricGroup": "TopDownL1_SMT", |
116 | "MetricName": "SLOTS_SMT" | |
117 | }, | |
118 | { | |
61ec07f5 | 119 | "BriefDescription": "Instructions per Load (lower number means higher occurance rate)", |
fd550098 | 120 | "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", |
61ec07f5 | 121 | "MetricGroup": "Instruction_Type", |
fd550098 AK |
122 | "MetricName": "IpL" |
123 | }, | |
124 | { | |
61ec07f5 | 125 | "BriefDescription": "Instructions per Store (lower number means higher occurance rate)", |
fd550098 | 126 | "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", |
61ec07f5 | 127 | "MetricGroup": "Instruction_Type", |
fd550098 AK |
128 | "MetricName": "IpS" |
129 | }, | |
130 | { | |
61ec07f5 | 131 | "BriefDescription": "Instructions per Branch (lower number means higher occurance rate)", |
fd550098 | 132 | "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", |
61ec07f5 | 133 | "MetricGroup": "Branches;Instruction_Type", |
fd550098 AK |
134 | "MetricName": "IpB" |
135 | }, | |
136 | { | |
61ec07f5 | 137 | "BriefDescription": "Instruction per (near) call (lower number means higher occurance rate)", |
fd550098 | 138 | "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", |
fd550098 AK |
139 | "MetricGroup": "Branches", |
140 | "MetricName": "IpCall" | |
141 | }, | |
142 | { | |
fd550098 | 143 | "BriefDescription": "Total number of retired Instructions", |
61ec07f5 | 144 | "MetricExpr": "INST_RETIRED.ANY", |
2099f51d AK |
145 | "MetricGroup": "Summary", |
146 | "MetricName": "Instructions" | |
147 | }, | |
148 | { | |
149 | "BriefDescription": "Instructions Per Cycle (per physical core)", | |
61ec07f5 | 150 | "MetricExpr": "INST_RETIRED.ANY / cycles", |
2099f51d AK |
151 | "MetricGroup": "SMT", |
152 | "MetricName": "CoreIPC" | |
153 | }, | |
154 | { | |
fd550098 | 155 | "BriefDescription": "Instructions Per Cycle (per physical core)", |
61ec07f5 | 156 | "MetricExpr": "INST_RETIRED.ANY / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", |
fd550098 AK |
157 | "MetricGroup": "SMT", |
158 | "MetricName": "CoreIPC_SMT" | |
159 | }, | |
160 | { | |
2099f51d | 161 | "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", |
61ec07f5 HS |
162 | "MetricExpr": "( UOPS_EXECUTED.CORE / 2 / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@) ) if #SMT_on else UOPS_EXECUTED.CORE / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@)", |
163 | "MetricGroup": "Pipeline", | |
2099f51d AK |
164 | "MetricName": "ILP" |
165 | }, | |
166 | { | |
fd550098 | 167 | "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)", |
61ec07f5 HS |
168 | "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", |
169 | "MetricGroup": "BrMispredicts", | |
fd550098 | 170 | "MetricName": "IpMispredict" |
2099f51d AK |
171 | }, |
172 | { | |
61ec07f5 | 173 | "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core", |
fd550098 | 174 | "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )", |
2099f51d AK |
175 | "MetricGroup": "SMT", |
176 | "MetricName": "CORE_CLKS" | |
177 | }, | |
178 | { | |
fd550098 | 179 | "BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads (in core cycles)", |
61ec07f5 | 180 | "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )", |
2099f51d AK |
181 | "MetricGroup": "Memory_Bound;Memory_Lat", |
182 | "MetricName": "Load_Miss_Real_Latency" | |
183 | }, | |
184 | { | |
61ec07f5 | 185 | "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)", |
fd550098 | 186 | "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES", |
2099f51d AK |
187 | "MetricGroup": "Memory_Bound;Memory_BW", |
188 | "MetricName": "MLP" | |
189 | }, | |
190 | { | |
191 | "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", | |
61ec07f5 | 192 | "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / cycles", |
2099f51d AK |
193 | "MetricGroup": "TLB", |
194 | "MetricName": "Page_Walks_Utilization" | |
195 | }, | |
196 | { | |
fd550098 | 197 | "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", |
61ec07f5 | 198 | "MetricExpr": "( ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_DURATION + DTLB_STORE_MISSES.WALK_DURATION ) / (( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))", |
fd550098 AK |
199 | "MetricGroup": "TLB_SMT", |
200 | "MetricName": "Page_Walks_Utilization_SMT" | |
201 | }, | |
202 | { | |
fd550098 | 203 | "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]", |
61ec07f5 | 204 | "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time", |
fd550098 AK |
205 | "MetricGroup": "Memory_BW", |
206 | "MetricName": "L1D_Cache_Fill_BW" | |
207 | }, | |
208 | { | |
fd550098 | 209 | "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]", |
61ec07f5 | 210 | "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time", |
fd550098 AK |
211 | "MetricGroup": "Memory_BW", |
212 | "MetricName": "L2_Cache_Fill_BW" | |
213 | }, | |
214 | { | |
fd550098 | 215 | "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]", |
61ec07f5 | 216 | "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time", |
fd550098 AK |
217 | "MetricGroup": "Memory_BW", |
218 | "MetricName": "L3_Cache_Fill_BW" | |
219 | }, | |
220 | { | |
fd550098 | 221 | "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads", |
61ec07f5 HS |
222 | "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY", |
223 | "MetricGroup": "Cache_Misses", | |
fd550098 AK |
224 | "MetricName": "L1MPKI" |
225 | }, | |
226 | { | |
fd550098 | 227 | "BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads", |
61ec07f5 HS |
228 | "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", |
229 | "MetricGroup": "Cache_Misses", | |
fd550098 AK |
230 | "MetricName": "L2MPKI" |
231 | }, | |
232 | { | |
fd550098 | 233 | "BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)", |
61ec07f5 HS |
234 | "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", |
235 | "MetricGroup": "Cache_Misses", | |
fd550098 AK |
236 | "MetricName": "L2MPKI_All" |
237 | }, | |
238 | { | |
fd550098 | 239 | "BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)", |
61ec07f5 HS |
240 | "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", |
241 | "MetricGroup": "Cache_Misses", | |
fd550098 AK |
242 | "MetricName": "L2HPKI_All" |
243 | }, | |
244 | { | |
fd550098 | 245 | "BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads", |
61ec07f5 HS |
246 | "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY", |
247 | "MetricGroup": "Cache_Misses", | |
fd550098 AK |
248 | "MetricName": "L3MPKI" |
249 | }, | |
250 | { | |
fd550098 | 251 | "BriefDescription": "Average CPU Utilization", |
61ec07f5 | 252 | "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", |
2099f51d AK |
253 | "MetricGroup": "Summary", |
254 | "MetricName": "CPU_Utilization" | |
255 | }, | |
256 | { | |
fd550098 | 257 | "BriefDescription": "Average Frequency Utilization relative nominal frequency", |
61ec07f5 | 258 | "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC", |
2099f51d AK |
259 | "MetricGroup": "Power", |
260 | "MetricName": "Turbo_Utilization" | |
261 | }, | |
262 | { | |
61ec07f5 | 263 | "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active", |
2099f51d AK |
264 | "MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", |
265 | "MetricGroup": "SMT;Summary", | |
266 | "MetricName": "SMT_2T_Utilization" | |
267 | }, | |
268 | { | |
fd550098 | 269 | "BriefDescription": "Fraction of cycles spent in Kernel mode", |
0dd674ef | 270 | "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC:k / CPU_CLK_UNHALTED.REF_TSC", |
2099f51d AK |
271 | "MetricGroup": "Summary", |
272 | "MetricName": "Kernel_Utilization" | |
273 | }, | |
274 | { | |
fd550098 | 275 | "BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]", |
61ec07f5 | 276 | "MetricExpr": "64 * ( arb@event\\=0x81\\,umask\\=0x1@ + arb@event\\=0x84\\,umask\\=0x1@ ) / 1000000 / duration_time / 1000", |
fd550098 AK |
277 | "MetricGroup": "Memory_BW", |
278 | "MetricName": "DRAM_BW_Use" | |
279 | }, | |
280 | { | |
61ec07f5 | 281 | "BriefDescription": "C3 residency percent per core", |
2099f51d AK |
282 | "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", |
283 | "MetricGroup": "Power", | |
284 | "MetricName": "C3_Core_Residency" | |
285 | }, | |
286 | { | |
61ec07f5 | 287 | "BriefDescription": "C6 residency percent per core", |
2099f51d AK |
288 | "MetricExpr": "(cstate_core@c6\\-residency@ / msr@tsc@) * 100", |
289 | "MetricGroup": "Power", | |
290 | "MetricName": "C6_Core_Residency" | |
291 | }, | |
292 | { | |
61ec07f5 | 293 | "BriefDescription": "C7 residency percent per core", |
2099f51d AK |
294 | "MetricExpr": "(cstate_core@c7\\-residency@ / msr@tsc@) * 100", |
295 | "MetricGroup": "Power", | |
296 | "MetricName": "C7_Core_Residency" | |
297 | }, | |
298 | { | |
61ec07f5 | 299 | "BriefDescription": "C2 residency percent per package", |
2099f51d AK |
300 | "MetricExpr": "(cstate_pkg@c2\\-residency@ / msr@tsc@) * 100", |
301 | "MetricGroup": "Power", | |
302 | "MetricName": "C2_Pkg_Residency" | |
303 | }, | |
304 | { | |
61ec07f5 | 305 | "BriefDescription": "C3 residency percent per package", |
2099f51d AK |
306 | "MetricExpr": "(cstate_pkg@c3\\-residency@ / msr@tsc@) * 100", |
307 | "MetricGroup": "Power", | |
308 | "MetricName": "C3_Pkg_Residency" | |
309 | }, | |
310 | { | |
61ec07f5 | 311 | "BriefDescription": "C6 residency percent per package", |
2099f51d AK |
312 | "MetricExpr": "(cstate_pkg@c6\\-residency@ / msr@tsc@) * 100", |
313 | "MetricGroup": "Power", | |
314 | "MetricName": "C6_Pkg_Residency" | |
315 | }, | |
316 | { | |
61ec07f5 | 317 | "BriefDescription": "C7 residency percent per package", |
2099f51d AK |
318 | "MetricExpr": "(cstate_pkg@c7\\-residency@ / msr@tsc@) * 100", |
319 | "MetricGroup": "Power", | |
320 | "MetricName": "C7_Pkg_Residency" | |
321 | } | |
322 | ] |