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Commit | Line | Data |
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47cbd67e AK |
1 | [ |
2 | { | |
c93240a7 AK |
3 | "PublicDescription": "Number of times a TSX line had a cache conflict.", |
4 | "EventCode": "0x54", | |
5 | "Counter": "0,1,2,3", | |
6 | "UMask": "0x1", | |
7 | "EventName": "TX_MEM.ABORT_CONFLICT", | |
8 | "SampleAfterValue": "2000003", | |
9 | "BriefDescription": "Number of times a transactional abort was signaled due to a data conflict on a transactionally accessed address", | |
10 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
11 | }, | |
12 | { | |
13 | "EventCode": "0x54", | |
14 | "Counter": "0,1,2,3", | |
15 | "UMask": "0x2", | |
16 | "EventName": "TX_MEM.ABORT_CAPACITY", | |
17 | "SampleAfterValue": "2000003", | |
18 | "BriefDescription": "Number of times a transactional abort was signaled due to a data capacity limitation for transactional reads or writes.", | |
19 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
20 | }, | |
21 | { | |
22 | "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", | |
23 | "EventCode": "0x54", | |
24 | "Counter": "0,1,2,3", | |
25 | "UMask": "0x4", | |
26 | "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", | |
27 | "SampleAfterValue": "2000003", | |
28 | "BriefDescription": "Number of times a HLE transactional region aborted due to a non XRELEASE prefixed instruction writing to an elided lock in the elision buffer", | |
29 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
30 | }, | |
31 | { | |
32 | "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", | |
33 | "EventCode": "0x54", | |
34 | "Counter": "0,1,2,3", | |
35 | "UMask": "0x8", | |
36 | "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", | |
37 | "SampleAfterValue": "2000003", | |
38 | "BriefDescription": "Number of times an HLE transactional execution aborted due to NoAllocatedElisionBuffer being non-zero.", | |
39 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
40 | }, | |
41 | { | |
42 | "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", | |
43 | "EventCode": "0x54", | |
44 | "Counter": "0,1,2,3", | |
45 | "UMask": "0x10", | |
46 | "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", | |
47 | "SampleAfterValue": "2000003", | |
48 | "BriefDescription": "Number of times an HLE transactional execution aborted due to XRELEASE lock not satisfying the address and value requirements in the elision buffer", | |
49 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
50 | }, | |
51 | { | |
52 | "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", | |
53 | "EventCode": "0x54", | |
54 | "Counter": "0,1,2,3", | |
55 | "UMask": "0x20", | |
56 | "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", | |
57 | "SampleAfterValue": "2000003", | |
58 | "BriefDescription": "Number of times an HLE transactional execution aborted due to an unsupported read alignment from the elision buffer.", | |
59 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
60 | }, | |
61 | { | |
62 | "PublicDescription": "Number of times we could not allocate Lock Buffer.", | |
63 | "EventCode": "0x54", | |
64 | "Counter": "0,1,2,3", | |
65 | "UMask": "0x40", | |
66 | "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", | |
67 | "SampleAfterValue": "2000003", | |
68 | "BriefDescription": "Number of times HLE lock could not be elided due to ElisionBufferAvailable being zero.", | |
69 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
70 | }, | |
71 | { | |
47cbd67e AK |
72 | "EventCode": "0x5d", |
73 | "Counter": "0,1,2,3", | |
74 | "UMask": "0x1", | |
75 | "EventName": "TX_EXEC.MISC1", | |
76 | "SampleAfterValue": "2000003", | |
77 | "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", | |
78 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
79 | }, | |
80 | { | |
c93240a7 | 81 | "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", |
47cbd67e AK |
82 | "EventCode": "0x5d", |
83 | "Counter": "0,1,2,3", | |
84 | "UMask": "0x2", | |
85 | "EventName": "TX_EXEC.MISC2", | |
86 | "SampleAfterValue": "2000003", | |
87 | "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", | |
88 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
89 | }, | |
90 | { | |
91 | "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", | |
92 | "EventCode": "0x5d", | |
93 | "Counter": "0,1,2,3", | |
94 | "UMask": "0x4", | |
95 | "EventName": "TX_EXEC.MISC3", | |
96 | "SampleAfterValue": "2000003", | |
97 | "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", | |
98 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
99 | }, | |
100 | { | |
101 | "PublicDescription": "RTM region detected inside HLE.", | |
102 | "EventCode": "0x5d", | |
103 | "Counter": "0,1,2,3", | |
104 | "UMask": "0x8", | |
105 | "EventName": "TX_EXEC.MISC4", | |
106 | "SampleAfterValue": "2000003", | |
107 | "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", | |
108 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
109 | }, | |
110 | { | |
111 | "PublicDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", | |
112 | "EventCode": "0x5d", | |
113 | "Counter": "0,1,2,3", | |
114 | "UMask": "0x10", | |
115 | "EventName": "TX_EXEC.MISC5", | |
116 | "SampleAfterValue": "2000003", | |
117 | "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region", | |
118 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
119 | }, | |
120 | { | |
c93240a7 AK |
121 | "EventCode": "0x60", |
122 | "Counter": "0,1,2,3", | |
123 | "UMask": "0x10", | |
124 | "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", | |
125 | "SampleAfterValue": "2000003", | |
126 | "BriefDescription": "Counts number of Offcore outstanding Demand Data Read requests that miss L3 cache in the superQ every cycle.", | |
127 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
128 | }, | |
129 | { | |
130 | "EventCode": "0x60", | |
131 | "Counter": "0,1,2,3", | |
132 | "UMask": "0x10", | |
133 | "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEMAND_DATA_RD", | |
134 | "SampleAfterValue": "2000003", | |
135 | "BriefDescription": "Cycles with at least 1 Demand Data Read requests who miss L3 cache in the superQ.", | |
136 | "CounterMask": "1", | |
137 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
138 | }, | |
139 | { | |
140 | "EventCode": "0x60", | |
141 | "Counter": "0,1,2,3", | |
142 | "UMask": "0x10", | |
143 | "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_GE_6", | |
144 | "SampleAfterValue": "2000003", | |
145 | "BriefDescription": "Cycles with at least 6 Demand Data Read requests that miss L3 cache in the superQ.", | |
146 | "CounterMask": "6", | |
147 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
148 | }, | |
149 | { | |
150 | "EventCode": "0xA3", | |
151 | "Counter": "0,1,2,3", | |
152 | "UMask": "0x2", | |
153 | "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", | |
154 | "SampleAfterValue": "2000003", | |
155 | "BriefDescription": "Cycles while L3 cache miss demand load is outstanding.", | |
156 | "CounterMask": "2", | |
157 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
158 | }, | |
159 | { | |
160 | "EventCode": "0xA3", | |
161 | "Counter": "0,1,2,3", | |
162 | "UMask": "0x6", | |
163 | "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", | |
164 | "SampleAfterValue": "2000003", | |
165 | "BriefDescription": "Execution stalls while L3 cache miss demand load is outstanding.", | |
166 | "CounterMask": "6", | |
167 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
168 | }, | |
169 | { | |
170 | "PublicDescription": "Demand Data Read requests who miss L3 cache.", | |
171 | "EventCode": "0xB0", | |
172 | "Counter": "0,1,2,3", | |
173 | "UMask": "0x10", | |
174 | "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", | |
175 | "SampleAfterValue": "100003", | |
176 | "BriefDescription": "Demand Data Read requests who miss L3 cache", | |
177 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
178 | }, | |
179 | { | |
180 | "PublicDescription": "Counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:a. memory disambiguation,b. external snoop, orc. cross SMT-HW-thread snoop (stores) hitting load buffer.", | |
181 | "EventCode": "0xC3", | |
182 | "Counter": "0,1,2,3", | |
183 | "UMask": "0x2", | |
184 | "Errata": "SKL089", | |
185 | "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", | |
186 | "SampleAfterValue": "100003", | |
187 | "BriefDescription": "Counts the number of machine clears due to memory order conflicts.", | |
188 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
189 | }, | |
190 | { | |
191 | "PublicDescription": "Number of times we entered an HLE region. Does not count nested transactions.", | |
47cbd67e AK |
192 | "EventCode": "0xC8", |
193 | "Counter": "0,1,2,3", | |
194 | "UMask": "0x1", | |
195 | "EventName": "HLE_RETIRED.START", | |
196 | "SampleAfterValue": "2000003", | |
197 | "BriefDescription": "Number of times an HLE execution started.", | |
198 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
199 | }, | |
200 | { | |
201 | "PublicDescription": "Number of times HLE commit succeeded.", | |
202 | "EventCode": "0xC8", | |
203 | "Counter": "0,1,2,3", | |
204 | "UMask": "0x2", | |
205 | "EventName": "HLE_RETIRED.COMMIT", | |
206 | "SampleAfterValue": "2000003", | |
207 | "BriefDescription": "Number of times an HLE execution successfully committed", | |
208 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
209 | }, | |
210 | { | |
211 | "PEBS": "1", | |
c93240a7 | 212 | "PublicDescription": "Number of times HLE abort was triggered. (PEBS)", |
47cbd67e AK |
213 | "EventCode": "0xC8", |
214 | "Counter": "0,1,2,3", | |
215 | "UMask": "0x4", | |
216 | "EventName": "HLE_RETIRED.ABORTED", | |
217 | "SampleAfterValue": "2000003", | |
218 | "BriefDescription": "Number of times an HLE execution aborted due to any reasons (multiple categories may count as one). ", | |
219 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
220 | }, | |
221 | { | |
222 | "EventCode": "0xC8", | |
223 | "Counter": "0,1,2,3", | |
224 | "UMask": "0x8", | |
225 | "EventName": "HLE_RETIRED.ABORTED_MEM", | |
226 | "SampleAfterValue": "2000003", | |
227 | "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).", | |
228 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
229 | }, | |
230 | { | |
231 | "EventCode": "0xC8", | |
232 | "Counter": "0,1,2,3", | |
233 | "UMask": "0x10", | |
234 | "EventName": "HLE_RETIRED.ABORTED_TIMER", | |
235 | "SampleAfterValue": "2000003", | |
236 | "BriefDescription": "Number of times an HLE execution aborted due to hardware timer expiration.", | |
237 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
238 | }, | |
239 | { | |
47cbd67e AK |
240 | "EventCode": "0xC8", |
241 | "Counter": "0,1,2,3", | |
242 | "UMask": "0x20", | |
243 | "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", | |
244 | "SampleAfterValue": "2000003", | |
c93240a7 | 245 | "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions and certain unfriendly events (such as AD assists etc.).", |
47cbd67e AK |
246 | "CounterHTOff": "0,1,2,3,4,5,6,7" |
247 | }, | |
248 | { | |
249 | "PublicDescription": "Number of times an HLE execution aborted due to incompatible memory type.", | |
250 | "EventCode": "0xC8", | |
251 | "Counter": "0,1,2,3", | |
252 | "UMask": "0x40", | |
253 | "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", | |
254 | "SampleAfterValue": "2000003", | |
255 | "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type", | |
256 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
257 | }, | |
258 | { | |
259 | "EventCode": "0xC8", | |
260 | "Counter": "0,1,2,3", | |
261 | "UMask": "0x80", | |
262 | "EventName": "HLE_RETIRED.ABORTED_EVENTS", | |
263 | "SampleAfterValue": "2000003", | |
264 | "BriefDescription": "Number of times an HLE execution aborted due to unfriendly events (such as interrupts).", | |
265 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
266 | }, | |
267 | { | |
c93240a7 | 268 | "PublicDescription": "Number of times we entered an RTM region. Does not count nested transactions.", |
47cbd67e AK |
269 | "EventCode": "0xC9", |
270 | "Counter": "0,1,2,3", | |
271 | "UMask": "0x1", | |
272 | "EventName": "RTM_RETIRED.START", | |
273 | "SampleAfterValue": "2000003", | |
274 | "BriefDescription": "Number of times an RTM execution started.", | |
275 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
276 | }, | |
277 | { | |
278 | "PublicDescription": "Number of times RTM commit succeeded.", | |
279 | "EventCode": "0xC9", | |
280 | "Counter": "0,1,2,3", | |
281 | "UMask": "0x2", | |
282 | "EventName": "RTM_RETIRED.COMMIT", | |
283 | "SampleAfterValue": "2000003", | |
284 | "BriefDescription": "Number of times an RTM execution successfully committed", | |
285 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
286 | }, | |
287 | { | |
288 | "PEBS": "1", | |
c93240a7 | 289 | "PublicDescription": "Number of times RTM abort was triggered. (PEBS)", |
47cbd67e AK |
290 | "EventCode": "0xC9", |
291 | "Counter": "0,1,2,3", | |
292 | "UMask": "0x4", | |
293 | "EventName": "RTM_RETIRED.ABORTED", | |
294 | "SampleAfterValue": "2000003", | |
295 | "BriefDescription": "Number of times an RTM execution aborted due to any reasons (multiple categories may count as one). ", | |
296 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
297 | }, | |
298 | { | |
299 | "PublicDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts).", | |
300 | "EventCode": "0xC9", | |
301 | "Counter": "0,1,2,3", | |
302 | "UMask": "0x8", | |
303 | "EventName": "RTM_RETIRED.ABORTED_MEM", | |
304 | "SampleAfterValue": "2000003", | |
305 | "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)", | |
306 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
307 | }, | |
308 | { | |
309 | "EventCode": "0xC9", | |
310 | "Counter": "0,1,2,3", | |
311 | "UMask": "0x10", | |
312 | "EventName": "RTM_RETIRED.ABORTED_TIMER", | |
313 | "SampleAfterValue": "2000003", | |
314 | "BriefDescription": "Number of times an RTM execution aborted due to uncommon conditions.", | |
315 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
316 | }, | |
317 | { | |
318 | "PublicDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions.", | |
319 | "EventCode": "0xC9", | |
320 | "Counter": "0,1,2,3", | |
321 | "UMask": "0x20", | |
322 | "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", | |
323 | "SampleAfterValue": "2000003", | |
324 | "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions", | |
325 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
326 | }, | |
327 | { | |
328 | "PublicDescription": "Number of times an RTM execution aborted due to incompatible memory type.", | |
329 | "EventCode": "0xC9", | |
330 | "Counter": "0,1,2,3", | |
331 | "UMask": "0x40", | |
332 | "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", | |
333 | "SampleAfterValue": "2000003", | |
334 | "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type", | |
335 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
336 | }, | |
337 | { | |
338 | "PublicDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt).", | |
339 | "EventCode": "0xC9", | |
340 | "Counter": "0,1,2,3", | |
341 | "UMask": "0x80", | |
342 | "EventName": "RTM_RETIRED.ABORTED_EVENTS", | |
343 | "SampleAfterValue": "2000003", | |
344 | "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)", | |
345 | "CounterHTOff": "0,1,2,3,4,5,6,7" | |
346 | }, | |
47cbd67e AK |
347 | { |
348 | "PEBS": "2", | |
349 | "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 4 cycles. Reported latency may be longer than just the memory latency.", | |
350 | "EventCode": "0xCD", | |
351 | "MSRValue": "0x4", | |
352 | "Counter": "0,1,2,3", | |
353 | "UMask": "0x1", | |
354 | "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", | |
355 | "MSRIndex": "0x3F6", | |
356 | "SampleAfterValue": "100003", | |
357 | "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 4 cycles.", | |
358 | "TakenAlone": "1", | |
359 | "CounterHTOff": "0,1,2,3" | |
360 | }, | |
361 | { | |
362 | "PEBS": "2", | |
363 | "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 8 cycles. Reported latency may be longer than just the memory latency.", | |
364 | "EventCode": "0xCD", | |
365 | "MSRValue": "0x8", | |
366 | "Counter": "0,1,2,3", | |
367 | "UMask": "0x1", | |
368 | "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", | |
369 | "MSRIndex": "0x3F6", | |
370 | "SampleAfterValue": "50021", | |
371 | "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 8 cycles.", | |
372 | "TakenAlone": "1", | |
373 | "CounterHTOff": "0,1,2,3" | |
374 | }, | |
375 | { | |
376 | "PEBS": "2", | |
377 | "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 16 cycles. Reported latency may be longer than just the memory latency.", | |
378 | "EventCode": "0xCD", | |
379 | "MSRValue": "0x10", | |
380 | "Counter": "0,1,2,3", | |
381 | "UMask": "0x1", | |
382 | "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", | |
383 | "MSRIndex": "0x3F6", | |
384 | "SampleAfterValue": "20011", | |
385 | "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 16 cycles.", | |
386 | "TakenAlone": "1", | |
387 | "CounterHTOff": "0,1,2,3" | |
388 | }, | |
389 | { | |
390 | "PEBS": "2", | |
391 | "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 32 cycles. Reported latency may be longer than just the memory latency.", | |
392 | "EventCode": "0xCD", | |
393 | "MSRValue": "0x20", | |
394 | "Counter": "0,1,2,3", | |
395 | "UMask": "0x1", | |
396 | "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", | |
397 | "MSRIndex": "0x3F6", | |
398 | "SampleAfterValue": "100007", | |
399 | "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 32 cycles.", | |
400 | "TakenAlone": "1", | |
401 | "CounterHTOff": "0,1,2,3" | |
402 | }, | |
403 | { | |
404 | "PEBS": "2", | |
405 | "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 64 cycles. Reported latency may be longer than just the memory latency.", | |
406 | "EventCode": "0xCD", | |
407 | "MSRValue": "0x40", | |
408 | "Counter": "0,1,2,3", | |
409 | "UMask": "0x1", | |
410 | "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", | |
411 | "MSRIndex": "0x3F6", | |
412 | "SampleAfterValue": "2003", | |
413 | "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 64 cycles.", | |
414 | "TakenAlone": "1", | |
415 | "CounterHTOff": "0,1,2,3" | |
416 | }, | |
417 | { | |
418 | "PEBS": "2", | |
419 | "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 128 cycles. Reported latency may be longer than just the memory latency.", | |
420 | "EventCode": "0xCD", | |
421 | "MSRValue": "0x80", | |
422 | "Counter": "0,1,2,3", | |
423 | "UMask": "0x1", | |
424 | "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", | |
425 | "MSRIndex": "0x3F6", | |
426 | "SampleAfterValue": "1009", | |
427 | "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 128 cycles.", | |
428 | "TakenAlone": "1", | |
429 | "CounterHTOff": "0,1,2,3" | |
430 | }, | |
431 | { | |
432 | "PEBS": "2", | |
433 | "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 256 cycles. Reported latency may be longer than just the memory latency.", | |
434 | "EventCode": "0xCD", | |
435 | "MSRValue": "0x100", | |
436 | "Counter": "0,1,2,3", | |
437 | "UMask": "0x1", | |
438 | "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", | |
439 | "MSRIndex": "0x3F6", | |
440 | "SampleAfterValue": "503", | |
441 | "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 256 cycles.", | |
442 | "TakenAlone": "1", | |
443 | "CounterHTOff": "0,1,2,3" | |
444 | }, | |
445 | { | |
446 | "PEBS": "2", | |
447 | "PublicDescription": "Counts loads when the latency from first dispatch to completion is greater than 512 cycles. Reported latency may be longer than just the memory latency.", | |
448 | "EventCode": "0xCD", | |
449 | "MSRValue": "0x200", | |
450 | "Counter": "0,1,2,3", | |
451 | "UMask": "0x1", | |
452 | "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", | |
453 | "MSRIndex": "0x3F6", | |
454 | "SampleAfterValue": "101", | |
455 | "BriefDescription": "Counts loads when the latency from first dispatch to completion is greater than 512 cycles.", | |
456 | "TakenAlone": "1", | |
457 | "CounterHTOff": "0,1,2,3" | |
458 | }, | |
459 | { | |
c93240a7 AK |
460 | "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
461 | "EventCode": "0xB7, 0xBB", | |
462 | "MSRValue": "0x3ffc000001 ", | |
47cbd67e AK |
463 | "Counter": "0,1,2,3", |
464 | "UMask": "0x1", | |
c93240a7 AK |
465 | "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", |
466 | "MSRIndex": "0x1a6,0x1a7", | |
467 | "SampleAfterValue": "100003", | |
468 | "BriefDescription": "DEMAND_DATA_RD & L3_MISS & ANY_SNOOP", | |
469 | "Offcore": "1", | |
470 | "CounterHTOff": "0,1,2,3" | |
47cbd67e AK |
471 | }, |
472 | { | |
c93240a7 AK |
473 | "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
474 | "EventCode": "0xB7, 0xBB", | |
475 | "MSRValue": "0x103c000001 ", | |
47cbd67e | 476 | "Counter": "0,1,2,3", |
c93240a7 AK |
477 | "UMask": "0x1", |
478 | "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM", | |
479 | "MSRIndex": "0x1a6,0x1a7", | |
480 | "SampleAfterValue": "100003", | |
481 | "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_HITM", | |
482 | "Offcore": "1", | |
483 | "CounterHTOff": "0,1,2,3" | |
47cbd67e AK |
484 | }, |
485 | { | |
c93240a7 AK |
486 | "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
487 | "EventCode": "0xB7, 0xBB", | |
488 | "MSRValue": "0x043c000001 ", | |
47cbd67e | 489 | "Counter": "0,1,2,3", |
c93240a7 AK |
490 | "UMask": "0x1", |
491 | "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO_FWD", | |
492 | "MSRIndex": "0x1a6,0x1a7", | |
493 | "SampleAfterValue": "100003", | |
494 | "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_HIT_NO_FWD", | |
495 | "Offcore": "1", | |
496 | "CounterHTOff": "0,1,2,3" | |
47cbd67e AK |
497 | }, |
498 | { | |
c93240a7 AK |
499 | "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
500 | "EventCode": "0xB7, 0xBB", | |
501 | "MSRValue": "0x023c000001 ", | |
47cbd67e | 502 | "Counter": "0,1,2,3", |
c93240a7 AK |
503 | "UMask": "0x1", |
504 | "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", | |
505 | "MSRIndex": "0x1a6,0x1a7", | |
506 | "SampleAfterValue": "100003", | |
507 | "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_MISS", | |
508 | "Offcore": "1", | |
509 | "CounterHTOff": "0,1,2,3" | |
47cbd67e AK |
510 | }, |
511 | { | |
c93240a7 AK |
512 | "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
513 | "EventCode": "0xB7, 0xBB", | |
514 | "MSRValue": "0x013c000001 ", | |
47cbd67e | 515 | "Counter": "0,1,2,3", |
c93240a7 AK |
516 | "UMask": "0x1", |
517 | "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NEEDED", | |
518 | "MSRIndex": "0x1a6,0x1a7", | |
519 | "SampleAfterValue": "100003", | |
520 | "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_NOT_NEEDED", | |
521 | "Offcore": "1", | |
522 | "CounterHTOff": "0,1,2,3" | |
47cbd67e AK |
523 | }, |
524 | { | |
c93240a7 AK |
525 | "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
526 | "EventCode": "0xB7, 0xBB", | |
527 | "MSRValue": "0x00bc000001 ", | |
47cbd67e | 528 | "Counter": "0,1,2,3", |
c93240a7 AK |
529 | "UMask": "0x1", |
530 | "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", | |
531 | "MSRIndex": "0x1a6,0x1a7", | |
532 | "SampleAfterValue": "100003", | |
533 | "BriefDescription": "DEMAND_DATA_RD & L3_MISS & SNOOP_NONE", | |
534 | "Offcore": "1", | |
535 | "CounterHTOff": "0,1,2,3" | |
47cbd67e AK |
536 | }, |
537 | { | |
c93240a7 AK |
538 | "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
539 | "EventCode": "0xB7, 0xBB", | |
540 | "MSRValue": "0x3fc4000001 ", | |
47cbd67e AK |
541 | "Counter": "0,1,2,3", |
542 | "UMask": "0x1", | |
543 | "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", | |
544 | "MSRIndex": "0x1a6,0x1a7", | |
545 | "SampleAfterValue": "100003", | |
546 | "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & ANY_SNOOP", | |
547 | "Offcore": "1", | |
548 | "CounterHTOff": "0,1,2,3" | |
549 | }, | |
550 | { | |
c93240a7 | 551 | "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
47cbd67e AK |
552 | "EventCode": "0xB7, 0xBB", |
553 | "MSRValue": "0x1004000001 ", | |
554 | "Counter": "0,1,2,3", | |
555 | "UMask": "0x1", | |
556 | "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HITM", | |
557 | "MSRIndex": "0x1a6,0x1a7", | |
558 | "SampleAfterValue": "100003", | |
559 | "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HITM", | |
560 | "Offcore": "1", | |
561 | "CounterHTOff": "0,1,2,3" | |
562 | }, | |
563 | { | |
c93240a7 | 564 | "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
47cbd67e AK |
565 | "EventCode": "0xB7, 0xBB", |
566 | "MSRValue": "0x0404000001 ", | |
567 | "Counter": "0,1,2,3", | |
568 | "UMask": "0x1", | |
569 | "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_HIT_NO_FWD", | |
570 | "MSRIndex": "0x1a6,0x1a7", | |
571 | "SampleAfterValue": "100003", | |
572 | "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_HIT_NO_FWD", | |
573 | "Offcore": "1", | |
574 | "CounterHTOff": "0,1,2,3" | |
575 | }, | |
576 | { | |
c93240a7 | 577 | "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
47cbd67e AK |
578 | "EventCode": "0xB7, 0xBB", |
579 | "MSRValue": "0x0204000001 ", | |
580 | "Counter": "0,1,2,3", | |
581 | "UMask": "0x1", | |
582 | "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", | |
583 | "MSRIndex": "0x1a6,0x1a7", | |
584 | "SampleAfterValue": "100003", | |
585 | "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_MISS", | |
586 | "Offcore": "1", | |
587 | "CounterHTOff": "0,1,2,3" | |
588 | }, | |
589 | { | |
c93240a7 | 590 | "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
47cbd67e AK |
591 | "EventCode": "0xB7, 0xBB", |
592 | "MSRValue": "0x0104000001 ", | |
593 | "Counter": "0,1,2,3", | |
594 | "UMask": "0x1", | |
595 | "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NOT_NEEDED", | |
596 | "MSRIndex": "0x1a6,0x1a7", | |
597 | "SampleAfterValue": "100003", | |
598 | "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NOT_NEEDED", | |
599 | "Offcore": "1", | |
600 | "CounterHTOff": "0,1,2,3" | |
601 | }, | |
602 | { | |
c93240a7 | 603 | "PublicDescription": "tbd Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
47cbd67e AK |
604 | "EventCode": "0xB7, 0xBB", |
605 | "MSRValue": "0x0084000001 ", | |
606 | "Counter": "0,1,2,3", | |
607 | "UMask": "0x1", | |
608 | "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", | |
609 | "MSRIndex": "0x1a6,0x1a7", | |
610 | "SampleAfterValue": "100003", | |
611 | "BriefDescription": "DEMAND_DATA_RD & L3_MISS_LOCAL_DRAM & SNOOP_NONE", | |
612 | "Offcore": "1", | |
613 | "CounterHTOff": "0,1,2,3" | |
47cbd67e AK |
614 | } |
615 | ] |