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7fe2f639 DB |
1 | /* |
2 | * (C) 2010,2011 Thomas Renninger <trenn@suse.de>, Novell Inc. | |
3 | * | |
4 | * Licensed under the terms of the GNU GPL License version 2. | |
5 | * | |
6 | * Miscellaneous helpers which do not fit or are worth | |
7 | * to put into separate headers | |
8 | */ | |
9 | ||
10 | #ifndef __CPUPOWERUTILS_HELPERS__ | |
11 | #define __CPUPOWERUTILS_HELPERS__ | |
12 | ||
13 | #include <libintl.h> | |
14 | #include <locale.h> | |
15 | ||
16 | #include "helpers/bitmask.h" | |
17 | ||
18 | /* Internationalization ****************************/ | |
19 | #define _(String) gettext(String) | |
20 | #ifndef gettext_noop | |
21 | #define gettext_noop(String) String | |
22 | #endif | |
2cd005ca | 23 | #define N_(String) gettext_noop(String) |
7fe2f639 DB |
24 | /* Internationalization ****************************/ |
25 | ||
26 | extern int run_as_root; | |
27 | extern struct bitmask *cpus_chosen; | |
28 | ||
29 | /* Global verbose (-d) stuff *********************************/ | |
30 | /* | |
31 | * define DEBUG via global Makefile variable | |
32 | * Debug output is sent to stderr, do: | |
33 | * cpupower monitor 2>/tmp/debug | |
34 | * to split debug output away from normal output | |
35 | */ | |
36 | #ifdef DEBUG | |
37 | extern int be_verbose; | |
38 | ||
39 | #define dprint(fmt, ...) { \ | |
40 | if (be_verbose) { \ | |
41 | fprintf(stderr, "%s: " fmt, \ | |
2cd005ca | 42 | __func__, ##__VA_ARGS__); \ |
7fe2f639 DB |
43 | } \ |
44 | } | |
45 | #else | |
2cd005ca | 46 | static inline void dprint(const char *fmt, ...) { } |
7fe2f639 DB |
47 | #endif |
48 | extern int be_verbose; | |
49 | /* Global verbose (-v) stuff *********************************/ | |
50 | ||
51 | /* cpuid and cpuinfo helpers **************************/ | |
52 | enum cpupower_cpu_vendor {X86_VENDOR_UNKNOWN = 0, X86_VENDOR_INTEL, | |
53 | X86_VENDOR_AMD, X86_VENDOR_MAX}; | |
54 | ||
8fb2e440 TR |
55 | #define CPUPOWER_CAP_INV_TSC 0x00000001 |
56 | #define CPUPOWER_CAP_APERF 0x00000002 | |
57 | #define CPUPOWER_CAP_AMD_CBP 0x00000004 | |
58 | #define CPUPOWER_CAP_PERF_BIAS 0x00000008 | |
59 | #define CPUPOWER_CAP_HAS_TURBO_RATIO 0x00000010 | |
60 | #define CPUPOWER_CAP_IS_SNB 0x00000011 | |
7fe2f639 DB |
61 | |
62 | #define MAX_HW_PSTATES 10 | |
63 | ||
64 | struct cpupower_cpu_info { | |
65 | enum cpupower_cpu_vendor vendor; | |
66 | unsigned int family; | |
67 | unsigned int model; | |
68 | unsigned int stepping; | |
69 | /* CPU capabilities read out from cpuid */ | |
70 | unsigned long long caps; | |
71 | }; | |
72 | ||
73 | /* get_cpu_info | |
74 | * | |
75 | * Extract CPU vendor, family, model, stepping info from /proc/cpuinfo | |
76 | * | |
77 | * Returns 0 on success or a negativ error code | |
78 | * Only used on x86, below global's struct values are zero/unknown on | |
79 | * other archs | |
80 | */ | |
81 | extern int get_cpu_info(unsigned int cpu, struct cpupower_cpu_info *cpu_info); | |
82 | extern struct cpupower_cpu_info cpupower_cpu_info; | |
83 | /* cpuid and cpuinfo helpers **************************/ | |
84 | ||
85 | ||
86 | /* CPU topology/hierarchy parsing ******************/ | |
87 | struct cpupower_topology { | |
88 | /* Amount of CPU cores, packages and threads per core in the system */ | |
89 | unsigned int cores; | |
90 | unsigned int pkgs; | |
91 | unsigned int threads; /* per core */ | |
92 | ||
93 | /* Array gets mallocated with cores entries, holding per core info */ | |
94 | struct { | |
95 | int pkg; | |
96 | int core; | |
97 | int cpu; | |
98 | } *core_info; | |
99 | }; | |
100 | ||
101 | extern int get_cpu_topology(struct cpupower_topology *cpu_top); | |
102 | extern void cpu_topology_release(struct cpupower_topology cpu_top); | |
103 | /* CPU topology/hierarchy parsing ******************/ | |
104 | ||
105 | /* X86 ONLY ****************************************/ | |
106 | #if defined(__i386__) || defined(__x86_64__) | |
107 | ||
108 | #include <pci/pci.h> | |
109 | ||
110 | /* Read/Write msr ****************************/ | |
111 | extern int read_msr(int cpu, unsigned int idx, unsigned long long *val); | |
112 | extern int write_msr(int cpu, unsigned int idx, unsigned long long val); | |
113 | ||
114 | extern int msr_intel_set_perf_bias(unsigned int cpu, unsigned int val); | |
115 | extern int msr_intel_get_perf_bias(unsigned int cpu); | |
8fb2e440 | 116 | extern unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu); |
7fe2f639 DB |
117 | |
118 | extern int msr_intel_has_boost_support(unsigned int cpu); | |
119 | extern int msr_intel_boost_is_active(unsigned int cpu); | |
120 | ||
121 | /* Read/Write msr ****************************/ | |
122 | ||
123 | /* PCI stuff ****************************/ | |
124 | extern int amd_pci_get_num_boost_states(int *active, int *states); | |
125 | extern struct pci_dev *pci_acc_init(struct pci_access **pacc, int vendor_id, | |
126 | int *dev_ids); | |
127 | ||
128 | /* PCI stuff ****************************/ | |
129 | ||
130 | /* AMD HW pstate decoding **************************/ | |
131 | ||
132 | extern int decode_pstates(unsigned int cpu, unsigned int cpu_family, | |
133 | int boost_states, unsigned long *pstates, int *no); | |
134 | ||
135 | /* AMD HW pstate decoding **************************/ | |
136 | ||
137 | extern int cpufreq_has_boost_support(unsigned int cpu, int *support, | |
138 | int *active, int * states); | |
139 | /* | |
140 | * CPUID functions returning a single datum | |
141 | */ | |
142 | unsigned int cpuid_eax(unsigned int op); | |
143 | unsigned int cpuid_ebx(unsigned int op); | |
144 | unsigned int cpuid_ecx(unsigned int op); | |
145 | unsigned int cpuid_edx(unsigned int op); | |
146 | ||
147 | /* cpuid and cpuinfo helpers **************************/ | |
148 | /* X86 ONLY ********************************************/ | |
149 | #else | |
150 | static inline int decode_pstates(unsigned int cpu, unsigned int cpu_family, | |
151 | int boost_states, unsigned long *pstates, | |
152 | int *no) | |
153 | { return -1; }; | |
154 | ||
155 | static inline int read_msr(int cpu, unsigned int idx, unsigned long long *val) | |
156 | { return -1; }; | |
157 | static inline int write_msr(int cpu, unsigned int idx, unsigned long long val) | |
158 | { return -1; }; | |
159 | static inline int msr_intel_set_perf_bias(unsigned int cpu, unsigned int val) | |
160 | { return -1; }; | |
161 | static inline int msr_intel_get_perf_bias(unsigned int cpu) | |
162 | { return -1; }; | |
8fb2e440 TR |
163 | static inline unsigned long long msr_intel_get_turbo_ratio(unsigned int cpu) |
164 | { return 0; }; | |
7fe2f639 DB |
165 | |
166 | static inline int msr_intel_has_boost_support(unsigned int cpu) | |
167 | { return -1; }; | |
168 | static inline int msr_intel_boost_is_active(unsigned int cpu) | |
169 | { return -1; }; | |
170 | ||
171 | /* Read/Write msr ****************************/ | |
172 | ||
173 | static inline int cpufreq_has_boost_support(unsigned int cpu, int *support, | |
174 | int *active, int * states) | |
175 | { return -1; } | |
176 | ||
177 | /* cpuid and cpuinfo helpers **************************/ | |
178 | ||
179 | static inline unsigned int cpuid_eax(unsigned int op) { return 0; }; | |
180 | static inline unsigned int cpuid_ebx(unsigned int op) { return 0; }; | |
181 | static inline unsigned int cpuid_ecx(unsigned int op) { return 0; }; | |
182 | static inline unsigned int cpuid_edx(unsigned int op) { return 0; }; | |
183 | #endif /* defined(__i386__) || defined(__x86_64__) */ | |
184 | ||
185 | #endif /* __CPUPOWERUTILS_HELPERS__ */ |