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Commit | Line | Data |
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103a8fea LB |
1 | /* |
2 | * turbostat -- show CPU frequency and C-state residency | |
3 | * on modern Intel turbo-capable processors. | |
4 | * | |
144b44b1 | 5 | * Copyright (c) 2013 Intel Corporation. |
103a8fea LB |
6 | * Len Brown <len.brown@intel.com> |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms and conditions of the GNU General Public License, | |
10 | * version 2, as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
15 | * more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along with | |
18 | * this program; if not, write to the Free Software Foundation, Inc., | |
19 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
20 | */ | |
21 | ||
88c3281f | 22 | #define _GNU_SOURCE |
b731f311 | 23 | #include MSRHEADER |
95aebc44 | 24 | #include <stdarg.h> |
103a8fea | 25 | #include <stdio.h> |
b2c95d90 | 26 | #include <err.h> |
103a8fea LB |
27 | #include <unistd.h> |
28 | #include <sys/types.h> | |
29 | #include <sys/wait.h> | |
30 | #include <sys/stat.h> | |
31 | #include <sys/resource.h> | |
32 | #include <fcntl.h> | |
33 | #include <signal.h> | |
34 | #include <sys/time.h> | |
35 | #include <stdlib.h> | |
d8af6f5f | 36 | #include <getopt.h> |
103a8fea LB |
37 | #include <dirent.h> |
38 | #include <string.h> | |
39 | #include <ctype.h> | |
88c3281f | 40 | #include <sched.h> |
2a0609c0 | 41 | #include <time.h> |
2b92865e | 42 | #include <cpuid.h> |
98481e79 LB |
43 | #include <linux/capability.h> |
44 | #include <errno.h> | |
103a8fea | 45 | |
103a8fea | 46 | char *proc_stat = "/proc/stat"; |
b7d8c148 | 47 | FILE *outf; |
36229897 | 48 | int *fd_percpu; |
2a0609c0 | 49 | struct timespec interval_ts = {5, 0}; |
d8af6f5f LB |
50 | unsigned int debug; |
51 | unsigned int rapl_joules; | |
52 | unsigned int summary_only; | |
53 | unsigned int dump_only; | |
103a8fea LB |
54 | unsigned int skip_c0; |
55 | unsigned int skip_c1; | |
56 | unsigned int do_nhm_cstates; | |
57 | unsigned int do_snb_cstates; | |
fb5d4327 | 58 | unsigned int do_knl_cstates; |
ee7e38e3 LB |
59 | unsigned int do_pc2; |
60 | unsigned int do_pc3; | |
61 | unsigned int do_pc6; | |
62 | unsigned int do_pc7; | |
ca58710f | 63 | unsigned int do_c8_c9_c10; |
0b2bb692 | 64 | unsigned int do_skl_residency; |
144b44b1 LB |
65 | unsigned int do_slm_cstates; |
66 | unsigned int use_c1_residency_msr; | |
103a8fea | 67 | unsigned int has_aperf; |
889facbe | 68 | unsigned int has_epb; |
fc04cc67 | 69 | unsigned int units = 1000000; /* MHz etc */ |
103a8fea LB |
70 | unsigned int genuine_intel; |
71 | unsigned int has_invariant_tsc; | |
d7899447 | 72 | unsigned int do_nhm_platform_info; |
2f32edf1 LB |
73 | unsigned int extra_msr_offset32; |
74 | unsigned int extra_msr_offset64; | |
8e180f3c LB |
75 | unsigned int extra_delta_offset32; |
76 | unsigned int extra_delta_offset64; | |
b2b34dfe | 77 | unsigned int aperf_mperf_multiplier = 1; |
562a2d37 | 78 | int do_irq = 1; |
1ed51011 | 79 | int do_smi; |
103a8fea | 80 | double bclk; |
a2b7b749 | 81 | double base_hz; |
21ed5574 | 82 | unsigned int has_base_hz; |
a2b7b749 | 83 | double tsc_tweak = 1.0; |
103a8fea LB |
84 | unsigned int show_pkg; |
85 | unsigned int show_core; | |
86 | unsigned int show_cpu; | |
c98d5d94 LB |
87 | unsigned int show_pkg_only; |
88 | unsigned int show_core_only; | |
89 | char *output_buffer, *outp; | |
889facbe LB |
90 | unsigned int do_rapl; |
91 | unsigned int do_dts; | |
92 | unsigned int do_ptm; | |
fdf676e5 LB |
93 | unsigned int do_gfx_rc6_ms; |
94 | unsigned long long gfx_cur_rc6_ms; | |
27d47356 LB |
95 | unsigned int do_gfx_mhz; |
96 | unsigned int gfx_cur_mhz; | |
889facbe LB |
97 | unsigned int tcc_activation_temp; |
98 | unsigned int tcc_activation_temp_override; | |
40ee8e3b AS |
99 | double rapl_power_units, rapl_time_units; |
100 | double rapl_dram_energy_units, rapl_energy_units; | |
889facbe | 101 | double rapl_joule_counter_range; |
3a9a941d LB |
102 | unsigned int do_core_perf_limit_reasons; |
103 | unsigned int do_gfx_perf_limit_reasons; | |
104 | unsigned int do_ring_perf_limit_reasons; | |
8a5bdf41 LB |
105 | unsigned int crystal_hz; |
106 | unsigned long long tsc_hz; | |
7ce7d5de | 107 | int base_cpu; |
21ed5574 | 108 | double discover_bclk(unsigned int family, unsigned int model); |
7f5c258e LB |
109 | unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */ |
110 | /* IA32_HWP_REQUEST, IA32_HWP_STATUS */ | |
111 | unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */ | |
112 | unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */ | |
113 | unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */ | |
114 | unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */ | |
889facbe | 115 | |
e6f9bb3c LB |
116 | #define RAPL_PKG (1 << 0) |
117 | /* 0x610 MSR_PKG_POWER_LIMIT */ | |
118 | /* 0x611 MSR_PKG_ENERGY_STATUS */ | |
119 | #define RAPL_PKG_PERF_STATUS (1 << 1) | |
120 | /* 0x613 MSR_PKG_PERF_STATUS */ | |
121 | #define RAPL_PKG_POWER_INFO (1 << 2) | |
122 | /* 0x614 MSR_PKG_POWER_INFO */ | |
123 | ||
124 | #define RAPL_DRAM (1 << 3) | |
125 | /* 0x618 MSR_DRAM_POWER_LIMIT */ | |
126 | /* 0x619 MSR_DRAM_ENERGY_STATUS */ | |
e6f9bb3c LB |
127 | #define RAPL_DRAM_PERF_STATUS (1 << 4) |
128 | /* 0x61b MSR_DRAM_PERF_STATUS */ | |
0b2bb692 LB |
129 | #define RAPL_DRAM_POWER_INFO (1 << 5) |
130 | /* 0x61c MSR_DRAM_POWER_INFO */ | |
e6f9bb3c | 131 | |
0b2bb692 | 132 | #define RAPL_CORES (1 << 6) |
e6f9bb3c LB |
133 | /* 0x638 MSR_PP0_POWER_LIMIT */ |
134 | /* 0x639 MSR_PP0_ENERGY_STATUS */ | |
0b2bb692 | 135 | #define RAPL_CORE_POLICY (1 << 7) |
e6f9bb3c LB |
136 | /* 0x63a MSR_PP0_POLICY */ |
137 | ||
0b2bb692 | 138 | #define RAPL_GFX (1 << 8) |
e6f9bb3c LB |
139 | /* 0x640 MSR_PP1_POWER_LIMIT */ |
140 | /* 0x641 MSR_PP1_ENERGY_STATUS */ | |
141 | /* 0x642 MSR_PP1_POLICY */ | |
889facbe LB |
142 | #define TJMAX_DEFAULT 100 |
143 | ||
144 | #define MAX(a, b) ((a) > (b) ? (a) : (b)) | |
103a8fea LB |
145 | |
146 | int aperf_mperf_unstable; | |
147 | int backwards_count; | |
148 | char *progname; | |
103a8fea | 149 | |
c98d5d94 LB |
150 | cpu_set_t *cpu_present_set, *cpu_affinity_set; |
151 | size_t cpu_present_setsize, cpu_affinity_setsize; | |
152 | ||
153 | struct thread_data { | |
154 | unsigned long long tsc; | |
155 | unsigned long long aperf; | |
156 | unsigned long long mperf; | |
144b44b1 | 157 | unsigned long long c1; |
2f32edf1 | 158 | unsigned long long extra_msr64; |
8e180f3c LB |
159 | unsigned long long extra_delta64; |
160 | unsigned long long extra_msr32; | |
161 | unsigned long long extra_delta32; | |
562a2d37 | 162 | unsigned int irq_count; |
1ed51011 | 163 | unsigned int smi_count; |
c98d5d94 LB |
164 | unsigned int cpu_id; |
165 | unsigned int flags; | |
166 | #define CPU_IS_FIRST_THREAD_IN_CORE 0x2 | |
167 | #define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4 | |
168 | } *thread_even, *thread_odd; | |
169 | ||
170 | struct core_data { | |
171 | unsigned long long c3; | |
172 | unsigned long long c6; | |
173 | unsigned long long c7; | |
889facbe | 174 | unsigned int core_temp_c; |
c98d5d94 LB |
175 | unsigned int core_id; |
176 | } *core_even, *core_odd; | |
177 | ||
178 | struct pkg_data { | |
179 | unsigned long long pc2; | |
180 | unsigned long long pc3; | |
181 | unsigned long long pc6; | |
182 | unsigned long long pc7; | |
ca58710f KCA |
183 | unsigned long long pc8; |
184 | unsigned long long pc9; | |
185 | unsigned long long pc10; | |
0b2bb692 LB |
186 | unsigned long long pkg_wtd_core_c0; |
187 | unsigned long long pkg_any_core_c0; | |
188 | unsigned long long pkg_any_gfxe_c0; | |
189 | unsigned long long pkg_both_core_gfxe_c0; | |
fdf676e5 | 190 | unsigned long long gfx_rc6_ms; |
27d47356 | 191 | unsigned int gfx_mhz; |
c98d5d94 | 192 | unsigned int package_id; |
889facbe LB |
193 | unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */ |
194 | unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */ | |
195 | unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */ | |
196 | unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */ | |
197 | unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */ | |
198 | unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */ | |
199 | unsigned int pkg_temp_c; | |
200 | ||
c98d5d94 LB |
201 | } *package_even, *package_odd; |
202 | ||
203 | #define ODD_COUNTERS thread_odd, core_odd, package_odd | |
204 | #define EVEN_COUNTERS thread_even, core_even, package_even | |
205 | ||
206 | #define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \ | |
207 | (thread_base + (pkg_no) * topo.num_cores_per_pkg * \ | |
208 | topo.num_threads_per_core + \ | |
209 | (core_no) * topo.num_threads_per_core + (thread_no)) | |
210 | #define GET_CORE(core_base, core_no, pkg_no) \ | |
211 | (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no)) | |
212 | #define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no) | |
213 | ||
214 | struct system_summary { | |
215 | struct thread_data threads; | |
216 | struct core_data cores; | |
217 | struct pkg_data packages; | |
218 | } sum, average; | |
219 | ||
220 | ||
221 | struct topo_params { | |
222 | int num_packages; | |
223 | int num_cpus; | |
224 | int num_cores; | |
225 | int max_cpu_num; | |
226 | int num_cores_per_pkg; | |
227 | int num_threads_per_core; | |
228 | } topo; | |
229 | ||
230 | struct timeval tv_even, tv_odd, tv_delta; | |
231 | ||
562a2d37 LB |
232 | int *irq_column_2_cpu; /* /proc/interrupts column numbers */ |
233 | int *irqs_per_cpu; /* indexed by cpu_num */ | |
234 | ||
c98d5d94 LB |
235 | void setup_all_buffers(void); |
236 | ||
237 | int cpu_is_not_present(int cpu) | |
d15cf7c1 | 238 | { |
c98d5d94 | 239 | return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set); |
d15cf7c1 | 240 | } |
88c3281f | 241 | /* |
c98d5d94 LB |
242 | * run func(thread, core, package) in topology order |
243 | * skip non-present cpus | |
88c3281f | 244 | */ |
c98d5d94 LB |
245 | |
246 | int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *), | |
247 | struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base) | |
88c3281f | 248 | { |
c98d5d94 | 249 | int retval, pkg_no, core_no, thread_no; |
d15cf7c1 | 250 | |
c98d5d94 LB |
251 | for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { |
252 | for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { | |
253 | for (thread_no = 0; thread_no < | |
254 | topo.num_threads_per_core; ++thread_no) { | |
255 | struct thread_data *t; | |
256 | struct core_data *c; | |
257 | struct pkg_data *p; | |
88c3281f | 258 | |
c98d5d94 LB |
259 | t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); |
260 | ||
261 | if (cpu_is_not_present(t->cpu_id)) | |
262 | continue; | |
263 | ||
264 | c = GET_CORE(core_base, core_no, pkg_no); | |
265 | p = GET_PKG(pkg_base, pkg_no); | |
266 | ||
267 | retval = func(t, c, p); | |
268 | if (retval) | |
269 | return retval; | |
270 | } | |
271 | } | |
272 | } | |
273 | return 0; | |
88c3281f LB |
274 | } |
275 | ||
276 | int cpu_migrate(int cpu) | |
277 | { | |
c98d5d94 LB |
278 | CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); |
279 | CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set); | |
280 | if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1) | |
88c3281f LB |
281 | return -1; |
282 | else | |
283 | return 0; | |
284 | } | |
36229897 | 285 | int get_msr_fd(int cpu) |
103a8fea | 286 | { |
103a8fea LB |
287 | char pathname[32]; |
288 | int fd; | |
289 | ||
36229897 LB |
290 | fd = fd_percpu[cpu]; |
291 | ||
292 | if (fd) | |
293 | return fd; | |
294 | ||
103a8fea LB |
295 | sprintf(pathname, "/dev/cpu/%d/msr", cpu); |
296 | fd = open(pathname, O_RDONLY); | |
15aaa346 | 297 | if (fd < 0) |
98481e79 | 298 | err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname); |
103a8fea | 299 | |
36229897 LB |
300 | fd_percpu[cpu] = fd; |
301 | ||
302 | return fd; | |
303 | } | |
304 | ||
305 | int get_msr(int cpu, off_t offset, unsigned long long *msr) | |
306 | { | |
307 | ssize_t retval; | |
308 | ||
309 | retval = pread(get_msr_fd(cpu), msr, sizeof(*msr), offset); | |
15aaa346 | 310 | |
98481e79 | 311 | if (retval != sizeof *msr) |
36229897 | 312 | err(-1, "msr %d offset 0x%llx read failed", cpu, (unsigned long long)offset); |
15aaa346 LB |
313 | |
314 | return 0; | |
103a8fea LB |
315 | } |
316 | ||
fc04cc67 LB |
317 | /* |
318 | * Example Format w/ field column widths: | |
319 | * | |
27d47356 | 320 | * Package Core CPU Avg_MHz Bzy_MHz TSC_MHz IRQ SMI Busy% CPU_%c1 CPU_%c3 CPU_%c6 CPU_%c7 CoreTmp PkgTmp GFXMHz Pkg%pc2 Pkg%pc3 Pkg%pc6 Pkg%pc7 PkgWatt CorWatt GFXWatt |
562a2d37 | 321 | * 12345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678 |
fc04cc67 LB |
322 | */ |
323 | ||
a829eb4d | 324 | void print_header(void) |
103a8fea LB |
325 | { |
326 | if (show_pkg) | |
e7c95ff3 | 327 | outp += sprintf(outp, " Package"); |
103a8fea | 328 | if (show_core) |
e7c95ff3 | 329 | outp += sprintf(outp, " Core"); |
103a8fea | 330 | if (show_cpu) |
e7c95ff3 | 331 | outp += sprintf(outp, " CPU"); |
fc04cc67 | 332 | if (has_aperf) |
e7c95ff3 | 333 | outp += sprintf(outp, " Avg_MHz"); |
d7899447 | 334 | if (has_aperf) |
75d2e44e | 335 | outp += sprintf(outp, " Busy%%"); |
103a8fea | 336 | if (has_aperf) |
e7c95ff3 LB |
337 | outp += sprintf(outp, " Bzy_MHz"); |
338 | outp += sprintf(outp, " TSC_MHz"); | |
1cc21f7b | 339 | |
8e180f3c | 340 | if (extra_delta_offset32) |
e7c95ff3 | 341 | outp += sprintf(outp, " count 0x%03X", extra_delta_offset32); |
8e180f3c | 342 | if (extra_delta_offset64) |
e7c95ff3 | 343 | outp += sprintf(outp, " COUNT 0x%03X", extra_delta_offset64); |
2f32edf1 | 344 | if (extra_msr_offset32) |
e7c95ff3 | 345 | outp += sprintf(outp, " MSR 0x%03X", extra_msr_offset32); |
2f32edf1 | 346 | if (extra_msr_offset64) |
e7c95ff3 | 347 | outp += sprintf(outp, " MSR 0x%03X", extra_msr_offset64); |
1cc21f7b LB |
348 | |
349 | if (!debug) | |
350 | goto done; | |
351 | ||
562a2d37 LB |
352 | if (do_irq) |
353 | outp += sprintf(outp, " IRQ"); | |
1cc21f7b LB |
354 | if (do_smi) |
355 | outp += sprintf(outp, " SMI"); | |
356 | ||
103a8fea | 357 | if (do_nhm_cstates) |
e7c95ff3 | 358 | outp += sprintf(outp, " CPU%%c1"); |
fb5d4327 | 359 | if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates) |
e7c95ff3 | 360 | outp += sprintf(outp, " CPU%%c3"); |
103a8fea | 361 | if (do_nhm_cstates) |
e7c95ff3 | 362 | outp += sprintf(outp, " CPU%%c6"); |
103a8fea | 363 | if (do_snb_cstates) |
e7c95ff3 | 364 | outp += sprintf(outp, " CPU%%c7"); |
889facbe LB |
365 | |
366 | if (do_dts) | |
e7c95ff3 | 367 | outp += sprintf(outp, " CoreTmp"); |
889facbe | 368 | if (do_ptm) |
e7c95ff3 | 369 | outp += sprintf(outp, " PkgTmp"); |
889facbe | 370 | |
fdf676e5 LB |
371 | if (do_gfx_rc6_ms) |
372 | outp += sprintf(outp, " GFX%%rc6"); | |
373 | ||
27d47356 LB |
374 | if (do_gfx_mhz) |
375 | outp += sprintf(outp, " GFXMHz"); | |
376 | ||
0b2bb692 LB |
377 | if (do_skl_residency) { |
378 | outp += sprintf(outp, " Totl%%C0"); | |
379 | outp += sprintf(outp, " Any%%C0"); | |
380 | outp += sprintf(outp, " GFX%%C0"); | |
381 | outp += sprintf(outp, " CPUGFX%%"); | |
382 | } | |
383 | ||
ee7e38e3 | 384 | if (do_pc2) |
e7c95ff3 | 385 | outp += sprintf(outp, " Pkg%%pc2"); |
ee7e38e3 | 386 | if (do_pc3) |
e7c95ff3 | 387 | outp += sprintf(outp, " Pkg%%pc3"); |
ee7e38e3 | 388 | if (do_pc6) |
e7c95ff3 | 389 | outp += sprintf(outp, " Pkg%%pc6"); |
ee7e38e3 | 390 | if (do_pc7) |
e7c95ff3 | 391 | outp += sprintf(outp, " Pkg%%pc7"); |
ca58710f | 392 | if (do_c8_c9_c10) { |
e7c95ff3 LB |
393 | outp += sprintf(outp, " Pkg%%pc8"); |
394 | outp += sprintf(outp, " Pkg%%pc9"); | |
395 | outp += sprintf(outp, " Pk%%pc10"); | |
ca58710f | 396 | } |
103a8fea | 397 | |
5c56be9a DB |
398 | if (do_rapl && !rapl_joules) { |
399 | if (do_rapl & RAPL_PKG) | |
e7c95ff3 | 400 | outp += sprintf(outp, " PkgWatt"); |
5c56be9a | 401 | if (do_rapl & RAPL_CORES) |
e7c95ff3 | 402 | outp += sprintf(outp, " CorWatt"); |
5c56be9a | 403 | if (do_rapl & RAPL_GFX) |
e7c95ff3 | 404 | outp += sprintf(outp, " GFXWatt"); |
5c56be9a | 405 | if (do_rapl & RAPL_DRAM) |
e7c95ff3 | 406 | outp += sprintf(outp, " RAMWatt"); |
5c56be9a | 407 | if (do_rapl & RAPL_PKG_PERF_STATUS) |
e7c95ff3 | 408 | outp += sprintf(outp, " PKG_%%"); |
5c56be9a | 409 | if (do_rapl & RAPL_DRAM_PERF_STATUS) |
e7c95ff3 | 410 | outp += sprintf(outp, " RAM_%%"); |
d7899447 | 411 | } else if (do_rapl && rapl_joules) { |
5c56be9a | 412 | if (do_rapl & RAPL_PKG) |
e7c95ff3 | 413 | outp += sprintf(outp, " Pkg_J"); |
5c56be9a | 414 | if (do_rapl & RAPL_CORES) |
e7c95ff3 | 415 | outp += sprintf(outp, " Cor_J"); |
5c56be9a | 416 | if (do_rapl & RAPL_GFX) |
e7c95ff3 | 417 | outp += sprintf(outp, " GFX_J"); |
5c56be9a | 418 | if (do_rapl & RAPL_DRAM) |
bd6906ed | 419 | outp += sprintf(outp, " RAM_J"); |
5c56be9a | 420 | if (do_rapl & RAPL_PKG_PERF_STATUS) |
e7c95ff3 | 421 | outp += sprintf(outp, " PKG_%%"); |
5c56be9a | 422 | if (do_rapl & RAPL_DRAM_PERF_STATUS) |
e7c95ff3 LB |
423 | outp += sprintf(outp, " RAM_%%"); |
424 | outp += sprintf(outp, " time"); | |
889facbe | 425 | |
5c56be9a | 426 | } |
1cc21f7b | 427 | done: |
c98d5d94 | 428 | outp += sprintf(outp, "\n"); |
103a8fea LB |
429 | } |
430 | ||
c98d5d94 LB |
431 | int dump_counters(struct thread_data *t, struct core_data *c, |
432 | struct pkg_data *p) | |
103a8fea | 433 | { |
3b4d5c7f | 434 | outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p); |
c98d5d94 LB |
435 | |
436 | if (t) { | |
3b4d5c7f AS |
437 | outp += sprintf(outp, "CPU: %d flags 0x%x\n", |
438 | t->cpu_id, t->flags); | |
439 | outp += sprintf(outp, "TSC: %016llX\n", t->tsc); | |
440 | outp += sprintf(outp, "aperf: %016llX\n", t->aperf); | |
441 | outp += sprintf(outp, "mperf: %016llX\n", t->mperf); | |
442 | outp += sprintf(outp, "c1: %016llX\n", t->c1); | |
443 | outp += sprintf(outp, "msr0x%x: %08llX\n", | |
8e180f3c | 444 | extra_delta_offset32, t->extra_delta32); |
3b4d5c7f | 445 | outp += sprintf(outp, "msr0x%x: %016llX\n", |
8e180f3c | 446 | extra_delta_offset64, t->extra_delta64); |
3b4d5c7f | 447 | outp += sprintf(outp, "msr0x%x: %08llX\n", |
2f32edf1 | 448 | extra_msr_offset32, t->extra_msr32); |
3b4d5c7f | 449 | outp += sprintf(outp, "msr0x%x: %016llX\n", |
2f32edf1 | 450 | extra_msr_offset64, t->extra_msr64); |
562a2d37 LB |
451 | if (do_irq) |
452 | outp += sprintf(outp, "IRQ: %08X\n", t->irq_count); | |
1ed51011 | 453 | if (do_smi) |
3b4d5c7f | 454 | outp += sprintf(outp, "SMI: %08X\n", t->smi_count); |
c98d5d94 | 455 | } |
103a8fea | 456 | |
c98d5d94 | 457 | if (c) { |
3b4d5c7f AS |
458 | outp += sprintf(outp, "core: %d\n", c->core_id); |
459 | outp += sprintf(outp, "c3: %016llX\n", c->c3); | |
460 | outp += sprintf(outp, "c6: %016llX\n", c->c6); | |
461 | outp += sprintf(outp, "c7: %016llX\n", c->c7); | |
462 | outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c); | |
c98d5d94 | 463 | } |
103a8fea | 464 | |
c98d5d94 | 465 | if (p) { |
3b4d5c7f | 466 | outp += sprintf(outp, "package: %d\n", p->package_id); |
0b2bb692 LB |
467 | |
468 | outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0); | |
469 | outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0); | |
470 | outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0); | |
471 | outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0); | |
472 | ||
3b4d5c7f | 473 | outp += sprintf(outp, "pc2: %016llX\n", p->pc2); |
ee7e38e3 LB |
474 | if (do_pc3) |
475 | outp += sprintf(outp, "pc3: %016llX\n", p->pc3); | |
476 | if (do_pc6) | |
477 | outp += sprintf(outp, "pc6: %016llX\n", p->pc6); | |
478 | if (do_pc7) | |
479 | outp += sprintf(outp, "pc7: %016llX\n", p->pc7); | |
3b4d5c7f AS |
480 | outp += sprintf(outp, "pc8: %016llX\n", p->pc8); |
481 | outp += sprintf(outp, "pc9: %016llX\n", p->pc9); | |
482 | outp += sprintf(outp, "pc10: %016llX\n", p->pc10); | |
483 | outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg); | |
484 | outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores); | |
485 | outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx); | |
486 | outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram); | |
487 | outp += sprintf(outp, "Throttle PKG: %0X\n", | |
488 | p->rapl_pkg_perf_status); | |
489 | outp += sprintf(outp, "Throttle RAM: %0X\n", | |
490 | p->rapl_dram_perf_status); | |
491 | outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c); | |
c98d5d94 | 492 | } |
3b4d5c7f AS |
493 | |
494 | outp += sprintf(outp, "\n"); | |
495 | ||
c98d5d94 | 496 | return 0; |
103a8fea LB |
497 | } |
498 | ||
e23da037 LB |
499 | /* |
500 | * column formatting convention & formats | |
e23da037 | 501 | */ |
c98d5d94 LB |
502 | int format_counters(struct thread_data *t, struct core_data *c, |
503 | struct pkg_data *p) | |
103a8fea LB |
504 | { |
505 | double interval_float; | |
fc04cc67 | 506 | char *fmt8; |
103a8fea | 507 | |
c98d5d94 LB |
508 | /* if showing only 1st thread in core and this isn't one, bail out */ |
509 | if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) | |
510 | return 0; | |
511 | ||
512 | /* if showing only 1st thread in pkg and this isn't one, bail out */ | |
513 | if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
514 | return 0; | |
515 | ||
103a8fea LB |
516 | interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0; |
517 | ||
c98d5d94 LB |
518 | /* topo columns, print blanks on 1st (average) line */ |
519 | if (t == &average.threads) { | |
103a8fea | 520 | if (show_pkg) |
fc04cc67 | 521 | outp += sprintf(outp, " -"); |
103a8fea | 522 | if (show_core) |
fc04cc67 | 523 | outp += sprintf(outp, " -"); |
103a8fea | 524 | if (show_cpu) |
fc04cc67 | 525 | outp += sprintf(outp, " -"); |
103a8fea | 526 | } else { |
c98d5d94 LB |
527 | if (show_pkg) { |
528 | if (p) | |
fc04cc67 | 529 | outp += sprintf(outp, "%8d", p->package_id); |
c98d5d94 | 530 | else |
fc04cc67 | 531 | outp += sprintf(outp, " -"); |
c98d5d94 | 532 | } |
c98d5d94 LB |
533 | if (show_core) { |
534 | if (c) | |
fc04cc67 | 535 | outp += sprintf(outp, "%8d", c->core_id); |
c98d5d94 | 536 | else |
fc04cc67 | 537 | outp += sprintf(outp, " -"); |
c98d5d94 | 538 | } |
103a8fea | 539 | if (show_cpu) |
fc04cc67 | 540 | outp += sprintf(outp, "%8d", t->cpu_id); |
103a8fea | 541 | } |
fc04cc67 | 542 | |
d7899447 | 543 | /* Avg_MHz */ |
fc04cc67 LB |
544 | if (has_aperf) |
545 | outp += sprintf(outp, "%8.0f", | |
546 | 1.0 / units * t->aperf / interval_float); | |
547 | ||
75d2e44e | 548 | /* Busy% */ |
d7899447 | 549 | if (has_aperf) { |
103a8fea | 550 | if (!skip_c0) |
a2b7b749 | 551 | outp += sprintf(outp, "%8.2f", 100.0 * t->mperf/t->tsc/tsc_tweak); |
103a8fea | 552 | else |
fc04cc67 | 553 | outp += sprintf(outp, "********"); |
103a8fea LB |
554 | } |
555 | ||
d7899447 | 556 | /* Bzy_MHz */ |
21ed5574 LB |
557 | if (has_aperf) { |
558 | if (has_base_hz) | |
559 | outp += sprintf(outp, "%8.0f", base_hz / units * t->aperf / t->mperf); | |
560 | else | |
561 | outp += sprintf(outp, "%8.0f", | |
562 | 1.0 * t->tsc / units * t->aperf / t->mperf / interval_float); | |
563 | } | |
103a8fea | 564 | |
d7899447 | 565 | /* TSC_MHz */ |
fc04cc67 | 566 | outp += sprintf(outp, "%8.0f", 1.0 * t->tsc/units/interval_float); |
103a8fea | 567 | |
8e180f3c LB |
568 | /* delta */ |
569 | if (extra_delta_offset32) | |
570 | outp += sprintf(outp, " %11llu", t->extra_delta32); | |
571 | ||
572 | /* DELTA */ | |
573 | if (extra_delta_offset64) | |
574 | outp += sprintf(outp, " %11llu", t->extra_delta64); | |
2f32edf1 LB |
575 | /* msr */ |
576 | if (extra_msr_offset32) | |
8e180f3c | 577 | outp += sprintf(outp, " 0x%08llx", t->extra_msr32); |
2f32edf1 | 578 | |
130ff304 | 579 | /* MSR */ |
2f32edf1 LB |
580 | if (extra_msr_offset64) |
581 | outp += sprintf(outp, " 0x%016llx", t->extra_msr64); | |
130ff304 | 582 | |
1cc21f7b LB |
583 | if (!debug) |
584 | goto done; | |
585 | ||
562a2d37 LB |
586 | /* IRQ */ |
587 | if (do_irq) | |
588 | outp += sprintf(outp, "%8d", t->irq_count); | |
589 | ||
1cc21f7b LB |
590 | /* SMI */ |
591 | if (do_smi) | |
592 | outp += sprintf(outp, "%8d", t->smi_count); | |
593 | ||
103a8fea LB |
594 | if (do_nhm_cstates) { |
595 | if (!skip_c1) | |
fc04cc67 | 596 | outp += sprintf(outp, "%8.2f", 100.0 * t->c1/t->tsc); |
103a8fea | 597 | else |
fc04cc67 | 598 | outp += sprintf(outp, "********"); |
103a8fea | 599 | } |
c98d5d94 LB |
600 | |
601 | /* print per-core data only for 1st thread in core */ | |
602 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) | |
603 | goto done; | |
604 | ||
fb5d4327 | 605 | if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates) |
fc04cc67 | 606 | outp += sprintf(outp, "%8.2f", 100.0 * c->c3/t->tsc); |
103a8fea | 607 | if (do_nhm_cstates) |
fc04cc67 | 608 | outp += sprintf(outp, "%8.2f", 100.0 * c->c6/t->tsc); |
103a8fea | 609 | if (do_snb_cstates) |
fc04cc67 | 610 | outp += sprintf(outp, "%8.2f", 100.0 * c->c7/t->tsc); |
c98d5d94 | 611 | |
889facbe | 612 | if (do_dts) |
fc04cc67 | 613 | outp += sprintf(outp, "%8d", c->core_temp_c); |
889facbe | 614 | |
c98d5d94 LB |
615 | /* print per-package data only for 1st core in package */ |
616 | if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
617 | goto done; | |
618 | ||
0b2bb692 | 619 | /* PkgTmp */ |
889facbe | 620 | if (do_ptm) |
fc04cc67 | 621 | outp += sprintf(outp, "%8d", p->pkg_temp_c); |
889facbe | 622 | |
fdf676e5 LB |
623 | /* GFXrc6 */ |
624 | if (do_gfx_rc6_ms) | |
625 | outp += sprintf(outp, "%8.2f", 100.0 * p->gfx_rc6_ms / 1000.0 / interval_float); | |
626 | ||
27d47356 LB |
627 | /* GFXMHz */ |
628 | if (do_gfx_mhz) | |
629 | outp += sprintf(outp, "%8d", p->gfx_mhz); | |
630 | ||
0b2bb692 LB |
631 | /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */ |
632 | if (do_skl_residency) { | |
633 | outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_wtd_core_c0/t->tsc); | |
634 | outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_any_core_c0/t->tsc); | |
635 | outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_any_gfxe_c0/t->tsc); | |
636 | outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_both_core_gfxe_c0/t->tsc); | |
637 | } | |
638 | ||
ee7e38e3 | 639 | if (do_pc2) |
fc04cc67 | 640 | outp += sprintf(outp, "%8.2f", 100.0 * p->pc2/t->tsc); |
ee7e38e3 | 641 | if (do_pc3) |
fc04cc67 | 642 | outp += sprintf(outp, "%8.2f", 100.0 * p->pc3/t->tsc); |
ee7e38e3 | 643 | if (do_pc6) |
fc04cc67 | 644 | outp += sprintf(outp, "%8.2f", 100.0 * p->pc6/t->tsc); |
ee7e38e3 | 645 | if (do_pc7) |
fc04cc67 | 646 | outp += sprintf(outp, "%8.2f", 100.0 * p->pc7/t->tsc); |
ca58710f | 647 | if (do_c8_c9_c10) { |
fc04cc67 LB |
648 | outp += sprintf(outp, "%8.2f", 100.0 * p->pc8/t->tsc); |
649 | outp += sprintf(outp, "%8.2f", 100.0 * p->pc9/t->tsc); | |
650 | outp += sprintf(outp, "%8.2f", 100.0 * p->pc10/t->tsc); | |
ca58710f | 651 | } |
889facbe LB |
652 | |
653 | /* | |
654 | * If measurement interval exceeds minimum RAPL Joule Counter range, | |
655 | * indicate that results are suspect by printing "**" in fraction place. | |
656 | */ | |
fc04cc67 LB |
657 | if (interval_float < rapl_joule_counter_range) |
658 | fmt8 = "%8.2f"; | |
659 | else | |
660 | fmt8 = " %6.0f**"; | |
889facbe | 661 | |
5c56be9a DB |
662 | if (do_rapl && !rapl_joules) { |
663 | if (do_rapl & RAPL_PKG) | |
fc04cc67 | 664 | outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float); |
5c56be9a | 665 | if (do_rapl & RAPL_CORES) |
fc04cc67 | 666 | outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float); |
5c56be9a | 667 | if (do_rapl & RAPL_GFX) |
fc04cc67 | 668 | outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float); |
5c56be9a | 669 | if (do_rapl & RAPL_DRAM) |
40ee8e3b | 670 | outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units / interval_float); |
5c56be9a | 671 | if (do_rapl & RAPL_PKG_PERF_STATUS) |
fc04cc67 | 672 | outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); |
5c56be9a | 673 | if (do_rapl & RAPL_DRAM_PERF_STATUS) |
fc04cc67 | 674 | outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); |
d7899447 | 675 | } else if (do_rapl && rapl_joules) { |
5c56be9a | 676 | if (do_rapl & RAPL_PKG) |
fc04cc67 | 677 | outp += sprintf(outp, fmt8, |
5c56be9a DB |
678 | p->energy_pkg * rapl_energy_units); |
679 | if (do_rapl & RAPL_CORES) | |
fc04cc67 | 680 | outp += sprintf(outp, fmt8, |
5c56be9a DB |
681 | p->energy_cores * rapl_energy_units); |
682 | if (do_rapl & RAPL_GFX) | |
fc04cc67 | 683 | outp += sprintf(outp, fmt8, |
5c56be9a DB |
684 | p->energy_gfx * rapl_energy_units); |
685 | if (do_rapl & RAPL_DRAM) | |
fc04cc67 | 686 | outp += sprintf(outp, fmt8, |
40ee8e3b | 687 | p->energy_dram * rapl_dram_energy_units); |
5c56be9a | 688 | if (do_rapl & RAPL_PKG_PERF_STATUS) |
fc04cc67 | 689 | outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float); |
5c56be9a | 690 | if (do_rapl & RAPL_DRAM_PERF_STATUS) |
fc04cc67 | 691 | outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float); |
889facbe | 692 | |
d7899447 | 693 | outp += sprintf(outp, fmt8, interval_float); |
5c56be9a | 694 | } |
c98d5d94 | 695 | done: |
c98d5d94 LB |
696 | outp += sprintf(outp, "\n"); |
697 | ||
698 | return 0; | |
103a8fea LB |
699 | } |
700 | ||
b7d8c148 | 701 | void flush_output_stdout(void) |
c98d5d94 | 702 | { |
b7d8c148 LB |
703 | FILE *filep; |
704 | ||
705 | if (outf == stderr) | |
706 | filep = stdout; | |
707 | else | |
708 | filep = outf; | |
709 | ||
710 | fputs(output_buffer, filep); | |
711 | fflush(filep); | |
712 | ||
c98d5d94 LB |
713 | outp = output_buffer; |
714 | } | |
b7d8c148 | 715 | void flush_output_stderr(void) |
c98d5d94 | 716 | { |
b7d8c148 LB |
717 | fputs(output_buffer, outf); |
718 | fflush(outf); | |
c98d5d94 LB |
719 | outp = output_buffer; |
720 | } | |
721 | void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
103a8fea | 722 | { |
e23da037 | 723 | static int printed; |
103a8fea | 724 | |
e23da037 LB |
725 | if (!printed || !summary_only) |
726 | print_header(); | |
103a8fea | 727 | |
c98d5d94 LB |
728 | if (topo.num_cpus > 1) |
729 | format_counters(&average.threads, &average.cores, | |
730 | &average.packages); | |
103a8fea | 731 | |
e23da037 LB |
732 | printed = 1; |
733 | ||
734 | if (summary_only) | |
735 | return; | |
736 | ||
c98d5d94 | 737 | for_all_cpus(format_counters, t, c, p); |
103a8fea LB |
738 | } |
739 | ||
889facbe LB |
740 | #define DELTA_WRAP32(new, old) \ |
741 | if (new > old) { \ | |
742 | old = new - old; \ | |
743 | } else { \ | |
744 | old = 0x100000000 + new - old; \ | |
745 | } | |
746 | ||
c98d5d94 LB |
747 | void |
748 | delta_package(struct pkg_data *new, struct pkg_data *old) | |
749 | { | |
0b2bb692 LB |
750 | |
751 | if (do_skl_residency) { | |
752 | old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0; | |
753 | old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0; | |
754 | old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0; | |
755 | old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0; | |
756 | } | |
c98d5d94 | 757 | old->pc2 = new->pc2 - old->pc2; |
ee7e38e3 LB |
758 | if (do_pc3) |
759 | old->pc3 = new->pc3 - old->pc3; | |
760 | if (do_pc6) | |
761 | old->pc6 = new->pc6 - old->pc6; | |
762 | if (do_pc7) | |
763 | old->pc7 = new->pc7 - old->pc7; | |
ca58710f KCA |
764 | old->pc8 = new->pc8 - old->pc8; |
765 | old->pc9 = new->pc9 - old->pc9; | |
766 | old->pc10 = new->pc10 - old->pc10; | |
889facbe LB |
767 | old->pkg_temp_c = new->pkg_temp_c; |
768 | ||
fdf676e5 | 769 | old->gfx_rc6_ms = new->gfx_rc6_ms - old->gfx_rc6_ms; |
27d47356 LB |
770 | old->gfx_mhz = new->gfx_mhz; |
771 | ||
889facbe LB |
772 | DELTA_WRAP32(new->energy_pkg, old->energy_pkg); |
773 | DELTA_WRAP32(new->energy_cores, old->energy_cores); | |
774 | DELTA_WRAP32(new->energy_gfx, old->energy_gfx); | |
775 | DELTA_WRAP32(new->energy_dram, old->energy_dram); | |
776 | DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status); | |
777 | DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status); | |
c98d5d94 | 778 | } |
103a8fea | 779 | |
c98d5d94 LB |
780 | void |
781 | delta_core(struct core_data *new, struct core_data *old) | |
103a8fea | 782 | { |
c98d5d94 LB |
783 | old->c3 = new->c3 - old->c3; |
784 | old->c6 = new->c6 - old->c6; | |
785 | old->c7 = new->c7 - old->c7; | |
889facbe | 786 | old->core_temp_c = new->core_temp_c; |
c98d5d94 | 787 | } |
103a8fea | 788 | |
c3ae331d LB |
789 | /* |
790 | * old = new - old | |
791 | */ | |
c98d5d94 LB |
792 | void |
793 | delta_thread(struct thread_data *new, struct thread_data *old, | |
794 | struct core_data *core_delta) | |
795 | { | |
796 | old->tsc = new->tsc - old->tsc; | |
797 | ||
798 | /* check for TSC < 1 Mcycles over interval */ | |
b2c95d90 JT |
799 | if (old->tsc < (1000 * 1000)) |
800 | errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n" | |
801 | "You can disable all c-states by booting with \"idle=poll\"\n" | |
802 | "or just the deep ones with \"processor.max_cstate=1\""); | |
103a8fea | 803 | |
c98d5d94 | 804 | old->c1 = new->c1 - old->c1; |
103a8fea | 805 | |
a729617c LB |
806 | if (has_aperf) { |
807 | if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) { | |
808 | old->aperf = new->aperf - old->aperf; | |
809 | old->mperf = new->mperf - old->mperf; | |
810 | } else { | |
103a8fea | 811 | |
a729617c | 812 | if (!aperf_mperf_unstable) { |
b7d8c148 LB |
813 | fprintf(outf, "%s: APERF or MPERF went backwards *\n", progname); |
814 | fprintf(outf, "* Frequency results do not cover entire interval *\n"); | |
815 | fprintf(outf, "* fix this by running Linux-2.6.30 or later *\n"); | |
103a8fea | 816 | |
a729617c LB |
817 | aperf_mperf_unstable = 1; |
818 | } | |
819 | /* | |
820 | * mperf delta is likely a huge "positive" number | |
821 | * can not use it for calculating c0 time | |
822 | */ | |
823 | skip_c0 = 1; | |
824 | skip_c1 = 1; | |
103a8fea | 825 | } |
c98d5d94 | 826 | } |
103a8fea | 827 | |
103a8fea | 828 | |
144b44b1 LB |
829 | if (use_c1_residency_msr) { |
830 | /* | |
831 | * Some models have a dedicated C1 residency MSR, | |
832 | * which should be more accurate than the derivation below. | |
833 | */ | |
834 | } else { | |
835 | /* | |
836 | * As counter collection is not atomic, | |
837 | * it is possible for mperf's non-halted cycles + idle states | |
838 | * to exceed TSC's all cycles: show c1 = 0% in that case. | |
839 | */ | |
840 | if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc) | |
841 | old->c1 = 0; | |
842 | else { | |
843 | /* normal case, derive c1 */ | |
844 | old->c1 = old->tsc - old->mperf - core_delta->c3 | |
c98d5d94 | 845 | - core_delta->c6 - core_delta->c7; |
144b44b1 | 846 | } |
c98d5d94 | 847 | } |
c3ae331d | 848 | |
c98d5d94 | 849 | if (old->mperf == 0) { |
b7d8c148 LB |
850 | if (debug > 1) |
851 | fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id); | |
c98d5d94 | 852 | old->mperf = 1; /* divide by 0 protection */ |
103a8fea | 853 | } |
c98d5d94 | 854 | |
8e180f3c LB |
855 | old->extra_delta32 = new->extra_delta32 - old->extra_delta32; |
856 | old->extra_delta32 &= 0xFFFFFFFF; | |
857 | ||
858 | old->extra_delta64 = new->extra_delta64 - old->extra_delta64; | |
859 | ||
c98d5d94 | 860 | /* |
8e180f3c | 861 | * Extra MSR is just a snapshot, simply copy latest w/o subtracting |
c98d5d94 | 862 | */ |
2f32edf1 LB |
863 | old->extra_msr32 = new->extra_msr32; |
864 | old->extra_msr64 = new->extra_msr64; | |
1ed51011 | 865 | |
562a2d37 LB |
866 | if (do_irq) |
867 | old->irq_count = new->irq_count - old->irq_count; | |
868 | ||
1ed51011 LB |
869 | if (do_smi) |
870 | old->smi_count = new->smi_count - old->smi_count; | |
c98d5d94 LB |
871 | } |
872 | ||
873 | int delta_cpu(struct thread_data *t, struct core_data *c, | |
874 | struct pkg_data *p, struct thread_data *t2, | |
875 | struct core_data *c2, struct pkg_data *p2) | |
876 | { | |
877 | /* calculate core delta only for 1st thread in core */ | |
878 | if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE) | |
879 | delta_core(c, c2); | |
880 | ||
881 | /* always calculate thread delta */ | |
882 | delta_thread(t, t2, c2); /* c2 is core delta */ | |
883 | ||
884 | /* calculate package delta only for 1st core in package */ | |
885 | if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE) | |
886 | delta_package(p, p2); | |
887 | ||
103a8fea LB |
888 | return 0; |
889 | } | |
890 | ||
c98d5d94 LB |
891 | void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) |
892 | { | |
893 | t->tsc = 0; | |
894 | t->aperf = 0; | |
895 | t->mperf = 0; | |
896 | t->c1 = 0; | |
897 | ||
8e180f3c LB |
898 | t->extra_delta32 = 0; |
899 | t->extra_delta64 = 0; | |
900 | ||
562a2d37 LB |
901 | t->irq_count = 0; |
902 | t->smi_count = 0; | |
903 | ||
c98d5d94 LB |
904 | /* tells format_counters to dump all fields from this set */ |
905 | t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE; | |
906 | ||
907 | c->c3 = 0; | |
908 | c->c6 = 0; | |
909 | c->c7 = 0; | |
889facbe | 910 | c->core_temp_c = 0; |
c98d5d94 | 911 | |
0b2bb692 LB |
912 | p->pkg_wtd_core_c0 = 0; |
913 | p->pkg_any_core_c0 = 0; | |
914 | p->pkg_any_gfxe_c0 = 0; | |
915 | p->pkg_both_core_gfxe_c0 = 0; | |
916 | ||
c98d5d94 | 917 | p->pc2 = 0; |
ee7e38e3 LB |
918 | if (do_pc3) |
919 | p->pc3 = 0; | |
920 | if (do_pc6) | |
921 | p->pc6 = 0; | |
922 | if (do_pc7) | |
923 | p->pc7 = 0; | |
ca58710f KCA |
924 | p->pc8 = 0; |
925 | p->pc9 = 0; | |
926 | p->pc10 = 0; | |
889facbe LB |
927 | |
928 | p->energy_pkg = 0; | |
929 | p->energy_dram = 0; | |
930 | p->energy_cores = 0; | |
931 | p->energy_gfx = 0; | |
932 | p->rapl_pkg_perf_status = 0; | |
933 | p->rapl_dram_perf_status = 0; | |
934 | p->pkg_temp_c = 0; | |
27d47356 | 935 | |
fdf676e5 | 936 | p->gfx_rc6_ms = 0; |
27d47356 | 937 | p->gfx_mhz = 0; |
c98d5d94 LB |
938 | } |
939 | int sum_counters(struct thread_data *t, struct core_data *c, | |
940 | struct pkg_data *p) | |
103a8fea | 941 | { |
c98d5d94 LB |
942 | average.threads.tsc += t->tsc; |
943 | average.threads.aperf += t->aperf; | |
944 | average.threads.mperf += t->mperf; | |
945 | average.threads.c1 += t->c1; | |
103a8fea | 946 | |
8e180f3c LB |
947 | average.threads.extra_delta32 += t->extra_delta32; |
948 | average.threads.extra_delta64 += t->extra_delta64; | |
949 | ||
562a2d37 LB |
950 | average.threads.irq_count += t->irq_count; |
951 | average.threads.smi_count += t->smi_count; | |
952 | ||
c98d5d94 LB |
953 | /* sum per-core values only for 1st thread in core */ |
954 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) | |
955 | return 0; | |
103a8fea | 956 | |
c98d5d94 LB |
957 | average.cores.c3 += c->c3; |
958 | average.cores.c6 += c->c6; | |
959 | average.cores.c7 += c->c7; | |
960 | ||
889facbe LB |
961 | average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c); |
962 | ||
c98d5d94 LB |
963 | /* sum per-pkg values only for 1st core in pkg */ |
964 | if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
965 | return 0; | |
966 | ||
0b2bb692 LB |
967 | if (do_skl_residency) { |
968 | average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0; | |
969 | average.packages.pkg_any_core_c0 += p->pkg_any_core_c0; | |
970 | average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0; | |
971 | average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0; | |
972 | } | |
973 | ||
c98d5d94 | 974 | average.packages.pc2 += p->pc2; |
ee7e38e3 LB |
975 | if (do_pc3) |
976 | average.packages.pc3 += p->pc3; | |
977 | if (do_pc6) | |
978 | average.packages.pc6 += p->pc6; | |
979 | if (do_pc7) | |
980 | average.packages.pc7 += p->pc7; | |
ca58710f KCA |
981 | average.packages.pc8 += p->pc8; |
982 | average.packages.pc9 += p->pc9; | |
983 | average.packages.pc10 += p->pc10; | |
c98d5d94 | 984 | |
889facbe LB |
985 | average.packages.energy_pkg += p->energy_pkg; |
986 | average.packages.energy_dram += p->energy_dram; | |
987 | average.packages.energy_cores += p->energy_cores; | |
988 | average.packages.energy_gfx += p->energy_gfx; | |
989 | ||
fdf676e5 | 990 | average.packages.gfx_rc6_ms = p->gfx_rc6_ms; |
27d47356 LB |
991 | average.packages.gfx_mhz = p->gfx_mhz; |
992 | ||
889facbe LB |
993 | average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c); |
994 | ||
995 | average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status; | |
996 | average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status; | |
c98d5d94 LB |
997 | return 0; |
998 | } | |
999 | /* | |
1000 | * sum the counters for all cpus in the system | |
1001 | * compute the weighted average | |
1002 | */ | |
1003 | void compute_average(struct thread_data *t, struct core_data *c, | |
1004 | struct pkg_data *p) | |
1005 | { | |
1006 | clear_counters(&average.threads, &average.cores, &average.packages); | |
1007 | ||
1008 | for_all_cpus(sum_counters, t, c, p); | |
1009 | ||
1010 | average.threads.tsc /= topo.num_cpus; | |
1011 | average.threads.aperf /= topo.num_cpus; | |
1012 | average.threads.mperf /= topo.num_cpus; | |
1013 | average.threads.c1 /= topo.num_cpus; | |
1014 | ||
8e180f3c LB |
1015 | average.threads.extra_delta32 /= topo.num_cpus; |
1016 | average.threads.extra_delta32 &= 0xFFFFFFFF; | |
1017 | ||
1018 | average.threads.extra_delta64 /= topo.num_cpus; | |
1019 | ||
c98d5d94 LB |
1020 | average.cores.c3 /= topo.num_cores; |
1021 | average.cores.c6 /= topo.num_cores; | |
1022 | average.cores.c7 /= topo.num_cores; | |
1023 | ||
0b2bb692 LB |
1024 | if (do_skl_residency) { |
1025 | average.packages.pkg_wtd_core_c0 /= topo.num_packages; | |
1026 | average.packages.pkg_any_core_c0 /= topo.num_packages; | |
1027 | average.packages.pkg_any_gfxe_c0 /= topo.num_packages; | |
1028 | average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages; | |
1029 | } | |
1030 | ||
c98d5d94 | 1031 | average.packages.pc2 /= topo.num_packages; |
ee7e38e3 LB |
1032 | if (do_pc3) |
1033 | average.packages.pc3 /= topo.num_packages; | |
1034 | if (do_pc6) | |
1035 | average.packages.pc6 /= topo.num_packages; | |
1036 | if (do_pc7) | |
1037 | average.packages.pc7 /= topo.num_packages; | |
ca58710f KCA |
1038 | |
1039 | average.packages.pc8 /= topo.num_packages; | |
1040 | average.packages.pc9 /= topo.num_packages; | |
1041 | average.packages.pc10 /= topo.num_packages; | |
103a8fea LB |
1042 | } |
1043 | ||
c98d5d94 | 1044 | static unsigned long long rdtsc(void) |
103a8fea | 1045 | { |
c98d5d94 | 1046 | unsigned int low, high; |
15aaa346 | 1047 | |
c98d5d94 | 1048 | asm volatile("rdtsc" : "=a" (low), "=d" (high)); |
15aaa346 | 1049 | |
c98d5d94 LB |
1050 | return low | ((unsigned long long)high) << 32; |
1051 | } | |
15aaa346 | 1052 | |
c98d5d94 LB |
1053 | /* |
1054 | * get_counters(...) | |
1055 | * migrate to cpu | |
1056 | * acquire and record local counters for that cpu | |
1057 | */ | |
1058 | int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
1059 | { | |
1060 | int cpu = t->cpu_id; | |
889facbe | 1061 | unsigned long long msr; |
0102b067 | 1062 | int aperf_mperf_retry_count = 0; |
88c3281f | 1063 | |
e52966c0 | 1064 | if (cpu_migrate(cpu)) { |
b7d8c148 | 1065 | fprintf(outf, "Could not migrate to CPU %d\n", cpu); |
c98d5d94 | 1066 | return -1; |
e52966c0 | 1067 | } |
15aaa346 | 1068 | |
0102b067 | 1069 | retry: |
c98d5d94 LB |
1070 | t->tsc = rdtsc(); /* we are running on local CPU of interest */ |
1071 | ||
1072 | if (has_aperf) { | |
0102b067 LB |
1073 | unsigned long long tsc_before, tsc_between, tsc_after, aperf_time, mperf_time; |
1074 | ||
1075 | /* | |
1076 | * The TSC, APERF and MPERF must be read together for | |
1077 | * APERF/MPERF and MPERF/TSC to give accurate results. | |
1078 | * | |
1079 | * Unfortunately, APERF and MPERF are read by | |
1080 | * individual system call, so delays may occur | |
1081 | * between them. If the time to read them | |
1082 | * varies by a large amount, we re-read them. | |
1083 | */ | |
1084 | ||
1085 | /* | |
1086 | * This initial dummy APERF read has been seen to | |
1087 | * reduce jitter in the subsequent reads. | |
1088 | */ | |
1089 | ||
1090 | if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) | |
1091 | return -3; | |
1092 | ||
1093 | t->tsc = rdtsc(); /* re-read close to APERF */ | |
1094 | ||
1095 | tsc_before = t->tsc; | |
1096 | ||
9c63a650 | 1097 | if (get_msr(cpu, MSR_IA32_APERF, &t->aperf)) |
c98d5d94 | 1098 | return -3; |
0102b067 LB |
1099 | |
1100 | tsc_between = rdtsc(); | |
1101 | ||
9c63a650 | 1102 | if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf)) |
c98d5d94 | 1103 | return -4; |
0102b067 LB |
1104 | |
1105 | tsc_after = rdtsc(); | |
1106 | ||
1107 | aperf_time = tsc_between - tsc_before; | |
1108 | mperf_time = tsc_after - tsc_between; | |
1109 | ||
1110 | /* | |
1111 | * If the system call latency to read APERF and MPERF | |
1112 | * differ by more than 2x, then try again. | |
1113 | */ | |
1114 | if ((aperf_time > (2 * mperf_time)) || (mperf_time > (2 * aperf_time))) { | |
1115 | aperf_mperf_retry_count++; | |
1116 | if (aperf_mperf_retry_count < 5) | |
1117 | goto retry; | |
1118 | else | |
1119 | warnx("cpu%d jitter %lld %lld", | |
1120 | cpu, aperf_time, mperf_time); | |
1121 | } | |
1122 | aperf_mperf_retry_count = 0; | |
1123 | ||
b2b34dfe HC |
1124 | t->aperf = t->aperf * aperf_mperf_multiplier; |
1125 | t->mperf = t->mperf * aperf_mperf_multiplier; | |
c98d5d94 LB |
1126 | } |
1127 | ||
562a2d37 LB |
1128 | if (do_irq) |
1129 | t->irq_count = irqs_per_cpu[cpu]; | |
1ed51011 LB |
1130 | if (do_smi) { |
1131 | if (get_msr(cpu, MSR_SMI_COUNT, &msr)) | |
1132 | return -5; | |
1133 | t->smi_count = msr & 0xFFFFFFFF; | |
1134 | } | |
8e180f3c | 1135 | if (extra_delta_offset32) { |
889facbe | 1136 | if (get_msr(cpu, extra_delta_offset32, &msr)) |
8e180f3c | 1137 | return -5; |
889facbe | 1138 | t->extra_delta32 = msr & 0xFFFFFFFF; |
8e180f3c LB |
1139 | } |
1140 | ||
1141 | if (extra_delta_offset64) | |
1142 | if (get_msr(cpu, extra_delta_offset64, &t->extra_delta64)) | |
2f32edf1 LB |
1143 | return -5; |
1144 | ||
8e180f3c | 1145 | if (extra_msr_offset32) { |
889facbe | 1146 | if (get_msr(cpu, extra_msr_offset32, &msr)) |
8e180f3c | 1147 | return -5; |
889facbe | 1148 | t->extra_msr32 = msr & 0xFFFFFFFF; |
8e180f3c LB |
1149 | } |
1150 | ||
2f32edf1 LB |
1151 | if (extra_msr_offset64) |
1152 | if (get_msr(cpu, extra_msr_offset64, &t->extra_msr64)) | |
c98d5d94 LB |
1153 | return -5; |
1154 | ||
144b44b1 LB |
1155 | if (use_c1_residency_msr) { |
1156 | if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1)) | |
1157 | return -6; | |
1158 | } | |
1159 | ||
c98d5d94 LB |
1160 | /* collect core counters only for 1st thread in core */ |
1161 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) | |
1162 | return 0; | |
1163 | ||
fb5d4327 | 1164 | if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates) { |
c98d5d94 LB |
1165 | if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3)) |
1166 | return -6; | |
144b44b1 LB |
1167 | } |
1168 | ||
fb5d4327 | 1169 | if (do_nhm_cstates && !do_knl_cstates) { |
c98d5d94 LB |
1170 | if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6)) |
1171 | return -7; | |
fb5d4327 DC |
1172 | } else if (do_knl_cstates) { |
1173 | if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6)) | |
1174 | return -7; | |
c98d5d94 LB |
1175 | } |
1176 | ||
1177 | if (do_snb_cstates) | |
1178 | if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7)) | |
1179 | return -8; | |
1180 | ||
889facbe LB |
1181 | if (do_dts) { |
1182 | if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) | |
1183 | return -9; | |
1184 | c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); | |
1185 | } | |
1186 | ||
1187 | ||
c98d5d94 LB |
1188 | /* collect package counters only for 1st core in package */ |
1189 | if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
1190 | return 0; | |
1191 | ||
0b2bb692 LB |
1192 | if (do_skl_residency) { |
1193 | if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0)) | |
1194 | return -10; | |
1195 | if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0)) | |
1196 | return -11; | |
1197 | if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0)) | |
1198 | return -12; | |
1199 | if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0)) | |
1200 | return -13; | |
1201 | } | |
ee7e38e3 | 1202 | if (do_pc3) |
c98d5d94 LB |
1203 | if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3)) |
1204 | return -9; | |
ee7e38e3 | 1205 | if (do_pc6) |
c98d5d94 LB |
1206 | if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6)) |
1207 | return -10; | |
ee7e38e3 | 1208 | if (do_pc2) |
c98d5d94 LB |
1209 | if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2)) |
1210 | return -11; | |
ee7e38e3 | 1211 | if (do_pc7) |
c98d5d94 LB |
1212 | if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7)) |
1213 | return -12; | |
ca58710f KCA |
1214 | if (do_c8_c9_c10) { |
1215 | if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8)) | |
1216 | return -13; | |
1217 | if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9)) | |
1218 | return -13; | |
1219 | if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10)) | |
1220 | return -13; | |
1221 | } | |
889facbe LB |
1222 | if (do_rapl & RAPL_PKG) { |
1223 | if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr)) | |
1224 | return -13; | |
1225 | p->energy_pkg = msr & 0xFFFFFFFF; | |
1226 | } | |
1227 | if (do_rapl & RAPL_CORES) { | |
1228 | if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr)) | |
1229 | return -14; | |
1230 | p->energy_cores = msr & 0xFFFFFFFF; | |
1231 | } | |
1232 | if (do_rapl & RAPL_DRAM) { | |
1233 | if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr)) | |
1234 | return -15; | |
1235 | p->energy_dram = msr & 0xFFFFFFFF; | |
1236 | } | |
1237 | if (do_rapl & RAPL_GFX) { | |
1238 | if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr)) | |
1239 | return -16; | |
1240 | p->energy_gfx = msr & 0xFFFFFFFF; | |
1241 | } | |
1242 | if (do_rapl & RAPL_PKG_PERF_STATUS) { | |
1243 | if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr)) | |
1244 | return -16; | |
1245 | p->rapl_pkg_perf_status = msr & 0xFFFFFFFF; | |
1246 | } | |
1247 | if (do_rapl & RAPL_DRAM_PERF_STATUS) { | |
1248 | if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr)) | |
1249 | return -16; | |
1250 | p->rapl_dram_perf_status = msr & 0xFFFFFFFF; | |
1251 | } | |
1252 | if (do_ptm) { | |
1253 | if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) | |
1254 | return -17; | |
1255 | p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F); | |
1256 | } | |
fdf676e5 LB |
1257 | |
1258 | if (do_gfx_rc6_ms) | |
1259 | p->gfx_rc6_ms = gfx_cur_rc6_ms; | |
1260 | ||
27d47356 LB |
1261 | if (do_gfx_mhz) |
1262 | p->gfx_mhz = gfx_cur_mhz; | |
1263 | ||
15aaa346 | 1264 | return 0; |
103a8fea LB |
1265 | } |
1266 | ||
ee7e38e3 LB |
1267 | /* |
1268 | * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit: | |
1269 | * If you change the values, note they are used both in comparisons | |
1270 | * (>= PCL__7) and to index pkg_cstate_limit_strings[]. | |
1271 | */ | |
1272 | ||
1273 | #define PCLUKN 0 /* Unknown */ | |
1274 | #define PCLRSV 1 /* Reserved */ | |
1275 | #define PCL__0 2 /* PC0 */ | |
1276 | #define PCL__1 3 /* PC1 */ | |
1277 | #define PCL__2 4 /* PC2 */ | |
1278 | #define PCL__3 5 /* PC3 */ | |
1279 | #define PCL__4 6 /* PC4 */ | |
1280 | #define PCL__6 7 /* PC6 */ | |
1281 | #define PCL_6N 8 /* PC6 No Retention */ | |
1282 | #define PCL_6R 9 /* PC6 Retention */ | |
1283 | #define PCL__7 10 /* PC7 */ | |
1284 | #define PCL_7S 11 /* PC7 Shrink */ | |
0b2bb692 LB |
1285 | #define PCL__8 12 /* PC8 */ |
1286 | #define PCL__9 13 /* PC9 */ | |
1287 | #define PCLUNL 14 /* Unlimited */ | |
ee7e38e3 LB |
1288 | |
1289 | int pkg_cstate_limit = PCLUKN; | |
1290 | char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2", | |
0b2bb692 | 1291 | "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"}; |
ee7e38e3 | 1292 | |
e9257f5f LB |
1293 | int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; |
1294 | int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; | |
1295 | int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; | |
1296 | int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; | |
1297 | int amt_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; | |
1298 | int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV}; | |
ee7e38e3 | 1299 | |
a2b7b749 LB |
1300 | |
1301 | static void | |
1302 | calculate_tsc_tweak() | |
1303 | { | |
a2b7b749 LB |
1304 | tsc_tweak = base_hz / tsc_hz; |
1305 | } | |
1306 | ||
fcd17211 LB |
1307 | static void |
1308 | dump_nhm_platform_info(void) | |
103a8fea LB |
1309 | { |
1310 | unsigned long long msr; | |
1311 | unsigned int ratio; | |
1312 | ||
ec0adc53 | 1313 | get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); |
103a8fea | 1314 | |
b7d8c148 | 1315 | fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr); |
6574a5d5 | 1316 | |
103a8fea | 1317 | ratio = (msr >> 40) & 0xFF; |
b7d8c148 | 1318 | fprintf(outf, "%d * %.0f = %.0f MHz max efficiency frequency\n", |
103a8fea LB |
1319 | ratio, bclk, ratio * bclk); |
1320 | ||
1321 | ratio = (msr >> 8) & 0xFF; | |
b7d8c148 | 1322 | fprintf(outf, "%d * %.0f = %.0f MHz base frequency\n", |
103a8fea LB |
1323 | ratio, bclk, ratio * bclk); |
1324 | ||
7ce7d5de | 1325 | get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr); |
b7d8c148 | 1326 | fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n", |
bfae2052 | 1327 | base_cpu, msr, msr & 0x2 ? "EN" : "DIS"); |
67920418 | 1328 | |
fcd17211 LB |
1329 | return; |
1330 | } | |
1331 | ||
1332 | static void | |
1333 | dump_hsw_turbo_ratio_limits(void) | |
1334 | { | |
1335 | unsigned long long msr; | |
1336 | unsigned int ratio; | |
1337 | ||
7ce7d5de | 1338 | get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr); |
fcd17211 | 1339 | |
b7d8c148 | 1340 | fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr); |
fcd17211 LB |
1341 | |
1342 | ratio = (msr >> 8) & 0xFF; | |
1343 | if (ratio) | |
b7d8c148 | 1344 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 18 active cores\n", |
fcd17211 LB |
1345 | ratio, bclk, ratio * bclk); |
1346 | ||
1347 | ratio = (msr >> 0) & 0xFF; | |
1348 | if (ratio) | |
b7d8c148 | 1349 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 17 active cores\n", |
fcd17211 LB |
1350 | ratio, bclk, ratio * bclk); |
1351 | return; | |
1352 | } | |
1353 | ||
1354 | static void | |
1355 | dump_ivt_turbo_ratio_limits(void) | |
1356 | { | |
1357 | unsigned long long msr; | |
1358 | unsigned int ratio; | |
6574a5d5 | 1359 | |
7ce7d5de | 1360 | get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr); |
6574a5d5 | 1361 | |
b7d8c148 | 1362 | fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr); |
6574a5d5 LB |
1363 | |
1364 | ratio = (msr >> 56) & 0xFF; | |
1365 | if (ratio) | |
b7d8c148 | 1366 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 16 active cores\n", |
6574a5d5 LB |
1367 | ratio, bclk, ratio * bclk); |
1368 | ||
1369 | ratio = (msr >> 48) & 0xFF; | |
1370 | if (ratio) | |
b7d8c148 | 1371 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 15 active cores\n", |
6574a5d5 LB |
1372 | ratio, bclk, ratio * bclk); |
1373 | ||
1374 | ratio = (msr >> 40) & 0xFF; | |
1375 | if (ratio) | |
b7d8c148 | 1376 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 14 active cores\n", |
6574a5d5 LB |
1377 | ratio, bclk, ratio * bclk); |
1378 | ||
1379 | ratio = (msr >> 32) & 0xFF; | |
1380 | if (ratio) | |
b7d8c148 | 1381 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 13 active cores\n", |
6574a5d5 LB |
1382 | ratio, bclk, ratio * bclk); |
1383 | ||
1384 | ratio = (msr >> 24) & 0xFF; | |
1385 | if (ratio) | |
b7d8c148 | 1386 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 12 active cores\n", |
6574a5d5 LB |
1387 | ratio, bclk, ratio * bclk); |
1388 | ||
1389 | ratio = (msr >> 16) & 0xFF; | |
1390 | if (ratio) | |
b7d8c148 | 1391 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 11 active cores\n", |
6574a5d5 LB |
1392 | ratio, bclk, ratio * bclk); |
1393 | ||
1394 | ratio = (msr >> 8) & 0xFF; | |
1395 | if (ratio) | |
b7d8c148 | 1396 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 10 active cores\n", |
6574a5d5 LB |
1397 | ratio, bclk, ratio * bclk); |
1398 | ||
1399 | ratio = (msr >> 0) & 0xFF; | |
1400 | if (ratio) | |
b7d8c148 | 1401 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 9 active cores\n", |
6574a5d5 | 1402 | ratio, bclk, ratio * bclk); |
fcd17211 LB |
1403 | return; |
1404 | } | |
6574a5d5 | 1405 | |
fcd17211 LB |
1406 | static void |
1407 | dump_nhm_turbo_ratio_limits(void) | |
1408 | { | |
1409 | unsigned long long msr; | |
1410 | unsigned int ratio; | |
103a8fea | 1411 | |
7ce7d5de | 1412 | get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr); |
103a8fea | 1413 | |
b7d8c148 | 1414 | fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr); |
6574a5d5 LB |
1415 | |
1416 | ratio = (msr >> 56) & 0xFF; | |
1417 | if (ratio) | |
b7d8c148 | 1418 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 8 active cores\n", |
6574a5d5 LB |
1419 | ratio, bclk, ratio * bclk); |
1420 | ||
1421 | ratio = (msr >> 48) & 0xFF; | |
1422 | if (ratio) | |
b7d8c148 | 1423 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 7 active cores\n", |
6574a5d5 LB |
1424 | ratio, bclk, ratio * bclk); |
1425 | ||
1426 | ratio = (msr >> 40) & 0xFF; | |
1427 | if (ratio) | |
b7d8c148 | 1428 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 6 active cores\n", |
6574a5d5 LB |
1429 | ratio, bclk, ratio * bclk); |
1430 | ||
1431 | ratio = (msr >> 32) & 0xFF; | |
1432 | if (ratio) | |
b7d8c148 | 1433 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 5 active cores\n", |
6574a5d5 LB |
1434 | ratio, bclk, ratio * bclk); |
1435 | ||
103a8fea LB |
1436 | ratio = (msr >> 24) & 0xFF; |
1437 | if (ratio) | |
b7d8c148 | 1438 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 4 active cores\n", |
103a8fea LB |
1439 | ratio, bclk, ratio * bclk); |
1440 | ||
1441 | ratio = (msr >> 16) & 0xFF; | |
1442 | if (ratio) | |
b7d8c148 | 1443 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 3 active cores\n", |
103a8fea LB |
1444 | ratio, bclk, ratio * bclk); |
1445 | ||
1446 | ratio = (msr >> 8) & 0xFF; | |
1447 | if (ratio) | |
b7d8c148 | 1448 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 2 active cores\n", |
103a8fea LB |
1449 | ratio, bclk, ratio * bclk); |
1450 | ||
1451 | ratio = (msr >> 0) & 0xFF; | |
1452 | if (ratio) | |
b7d8c148 | 1453 | fprintf(outf, "%d * %.0f = %.0f MHz max turbo 1 active cores\n", |
103a8fea | 1454 | ratio, bclk, ratio * bclk); |
fcd17211 LB |
1455 | return; |
1456 | } | |
3a9a941d | 1457 | |
fb5d4327 DC |
1458 | static void |
1459 | dump_knl_turbo_ratio_limits(void) | |
1460 | { | |
cbf97aba HC |
1461 | const unsigned int buckets_no = 7; |
1462 | ||
fb5d4327 | 1463 | unsigned long long msr; |
cbf97aba HC |
1464 | int delta_cores, delta_ratio; |
1465 | int i, b_nr; | |
1466 | unsigned int cores[buckets_no]; | |
1467 | unsigned int ratio[buckets_no]; | |
fb5d4327 | 1468 | |
7ce7d5de | 1469 | get_msr(base_cpu, MSR_NHM_TURBO_RATIO_LIMIT, &msr); |
fb5d4327 | 1470 | |
b7d8c148 | 1471 | fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", |
bfae2052 | 1472 | base_cpu, msr); |
fb5d4327 DC |
1473 | |
1474 | /** | |
1475 | * Turbo encoding in KNL is as follows: | |
cbf97aba HC |
1476 | * [0] -- Reserved |
1477 | * [7:1] -- Base value of number of active cores of bucket 1. | |
fb5d4327 DC |
1478 | * [15:8] -- Base value of freq ratio of bucket 1. |
1479 | * [20:16] -- +ve delta of number of active cores of bucket 2. | |
1480 | * i.e. active cores of bucket 2 = | |
1481 | * active cores of bucket 1 + delta | |
1482 | * [23:21] -- Negative delta of freq ratio of bucket 2. | |
1483 | * i.e. freq ratio of bucket 2 = | |
1484 | * freq ratio of bucket 1 - delta | |
1485 | * [28:24]-- +ve delta of number of active cores of bucket 3. | |
1486 | * [31:29]-- -ve delta of freq ratio of bucket 3. | |
1487 | * [36:32]-- +ve delta of number of active cores of bucket 4. | |
1488 | * [39:37]-- -ve delta of freq ratio of bucket 4. | |
1489 | * [44:40]-- +ve delta of number of active cores of bucket 5. | |
1490 | * [47:45]-- -ve delta of freq ratio of bucket 5. | |
1491 | * [52:48]-- +ve delta of number of active cores of bucket 6. | |
1492 | * [55:53]-- -ve delta of freq ratio of bucket 6. | |
1493 | * [60:56]-- +ve delta of number of active cores of bucket 7. | |
1494 | * [63:61]-- -ve delta of freq ratio of bucket 7. | |
1495 | */ | |
cbf97aba HC |
1496 | |
1497 | b_nr = 0; | |
1498 | cores[b_nr] = (msr & 0xFF) >> 1; | |
1499 | ratio[b_nr] = (msr >> 8) & 0xFF; | |
1500 | ||
1501 | for (i = 16; i < 64; i += 8) { | |
fb5d4327 | 1502 | delta_cores = (msr >> i) & 0x1F; |
cbf97aba HC |
1503 | delta_ratio = (msr >> (i + 5)) & 0x7; |
1504 | ||
1505 | cores[b_nr + 1] = cores[b_nr] + delta_cores; | |
1506 | ratio[b_nr + 1] = ratio[b_nr] - delta_ratio; | |
1507 | b_nr++; | |
fb5d4327 | 1508 | } |
cbf97aba HC |
1509 | |
1510 | for (i = buckets_no - 1; i >= 0; i--) | |
1511 | if (i > 0 ? ratio[i] != ratio[i - 1] : 1) | |
b7d8c148 | 1512 | fprintf(outf, |
fb5d4327 | 1513 | "%d * %.0f = %.0f MHz max turbo %d active cores\n", |
cbf97aba | 1514 | ratio[i], bclk, ratio[i] * bclk, cores[i]); |
fb5d4327 DC |
1515 | } |
1516 | ||
fcd17211 LB |
1517 | static void |
1518 | dump_nhm_cst_cfg(void) | |
1519 | { | |
1520 | unsigned long long msr; | |
1521 | ||
7ce7d5de | 1522 | get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr); |
fcd17211 LB |
1523 | |
1524 | #define SNB_C1_AUTO_UNDEMOTE (1UL << 27) | |
1525 | #define SNB_C3_AUTO_UNDEMOTE (1UL << 28) | |
1526 | ||
b7d8c148 | 1527 | fprintf(outf, "cpu%d: MSR_NHM_SNB_PKG_CST_CFG_CTL: 0x%08llx", base_cpu, msr); |
fcd17211 | 1528 | |
b7d8c148 | 1529 | fprintf(outf, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n", |
fcd17211 LB |
1530 | (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "", |
1531 | (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "", | |
1532 | (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "", | |
1533 | (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "", | |
1534 | (msr & (1 << 15)) ? "" : "UN", | |
6c34f160 | 1535 | (unsigned int)msr & 0xF, |
fcd17211 LB |
1536 | pkg_cstate_limit_strings[pkg_cstate_limit]); |
1537 | return; | |
103a8fea LB |
1538 | } |
1539 | ||
6fb3143b LB |
1540 | static void |
1541 | dump_config_tdp(void) | |
1542 | { | |
1543 | unsigned long long msr; | |
1544 | ||
1545 | get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr); | |
b7d8c148 | 1546 | fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr); |
685b535b | 1547 | fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xFF); |
6fb3143b LB |
1548 | |
1549 | get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr); | |
b7d8c148 | 1550 | fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr); |
6fb3143b | 1551 | if (msr) { |
685b535b CY |
1552 | fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0x7FFF); |
1553 | fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0x7FFF); | |
1554 | fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); | |
1555 | fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0x7FFF); | |
6fb3143b | 1556 | } |
b7d8c148 | 1557 | fprintf(outf, ")\n"); |
6fb3143b LB |
1558 | |
1559 | get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr); | |
b7d8c148 | 1560 | fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr); |
6fb3143b | 1561 | if (msr) { |
685b535b CY |
1562 | fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0x7FFF); |
1563 | fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0x7FFF); | |
1564 | fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xFF); | |
1565 | fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0x7FFF); | |
6fb3143b | 1566 | } |
b7d8c148 | 1567 | fprintf(outf, ")\n"); |
6fb3143b LB |
1568 | |
1569 | get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr); | |
b7d8c148 | 1570 | fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr); |
6fb3143b | 1571 | if ((msr) & 0x3) |
b7d8c148 LB |
1572 | fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3); |
1573 | fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); | |
1574 | fprintf(outf, ")\n"); | |
36229897 | 1575 | |
6fb3143b | 1576 | get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr); |
b7d8c148 | 1577 | fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr); |
685b535b | 1578 | fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0xFF); |
b7d8c148 LB |
1579 | fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1); |
1580 | fprintf(outf, ")\n"); | |
6fb3143b | 1581 | } |
36229897 LB |
1582 | void free_fd_percpu(void) |
1583 | { | |
1584 | int i; | |
1585 | ||
1586 | for (i = 0; i < topo.max_cpu_num; ++i) { | |
1587 | if (fd_percpu[i] != 0) | |
1588 | close(fd_percpu[i]); | |
1589 | } | |
1590 | ||
1591 | free(fd_percpu); | |
6fb3143b LB |
1592 | } |
1593 | ||
c98d5d94 | 1594 | void free_all_buffers(void) |
103a8fea | 1595 | { |
c98d5d94 LB |
1596 | CPU_FREE(cpu_present_set); |
1597 | cpu_present_set = NULL; | |
36229897 | 1598 | cpu_present_setsize = 0; |
103a8fea | 1599 | |
c98d5d94 LB |
1600 | CPU_FREE(cpu_affinity_set); |
1601 | cpu_affinity_set = NULL; | |
1602 | cpu_affinity_setsize = 0; | |
103a8fea | 1603 | |
c98d5d94 LB |
1604 | free(thread_even); |
1605 | free(core_even); | |
1606 | free(package_even); | |
103a8fea | 1607 | |
c98d5d94 LB |
1608 | thread_even = NULL; |
1609 | core_even = NULL; | |
1610 | package_even = NULL; | |
103a8fea | 1611 | |
c98d5d94 LB |
1612 | free(thread_odd); |
1613 | free(core_odd); | |
1614 | free(package_odd); | |
103a8fea | 1615 | |
c98d5d94 LB |
1616 | thread_odd = NULL; |
1617 | core_odd = NULL; | |
1618 | package_odd = NULL; | |
103a8fea | 1619 | |
c98d5d94 LB |
1620 | free(output_buffer); |
1621 | output_buffer = NULL; | |
1622 | outp = NULL; | |
36229897 LB |
1623 | |
1624 | free_fd_percpu(); | |
562a2d37 LB |
1625 | |
1626 | free(irq_column_2_cpu); | |
1627 | free(irqs_per_cpu); | |
103a8fea LB |
1628 | } |
1629 | ||
57a42a34 JT |
1630 | /* |
1631 | * Open a file, and exit on failure | |
1632 | */ | |
1633 | FILE *fopen_or_die(const char *path, const char *mode) | |
1634 | { | |
b7d8c148 | 1635 | FILE *filep = fopen(path, mode); |
b2c95d90 JT |
1636 | if (!filep) |
1637 | err(1, "%s: open failed", path); | |
57a42a34 JT |
1638 | return filep; |
1639 | } | |
1640 | ||
c98d5d94 | 1641 | /* |
95aebc44 | 1642 | * Parse a file containing a single int. |
c98d5d94 | 1643 | */ |
95aebc44 | 1644 | int parse_int_file(const char *fmt, ...) |
103a8fea | 1645 | { |
95aebc44 JT |
1646 | va_list args; |
1647 | char path[PATH_MAX]; | |
c98d5d94 | 1648 | FILE *filep; |
95aebc44 | 1649 | int value; |
103a8fea | 1650 | |
95aebc44 JT |
1651 | va_start(args, fmt); |
1652 | vsnprintf(path, sizeof(path), fmt, args); | |
1653 | va_end(args); | |
57a42a34 | 1654 | filep = fopen_or_die(path, "r"); |
b2c95d90 JT |
1655 | if (fscanf(filep, "%d", &value) != 1) |
1656 | err(1, "%s: failed to parse number from file", path); | |
c98d5d94 | 1657 | fclose(filep); |
95aebc44 JT |
1658 | return value; |
1659 | } | |
1660 | ||
1661 | /* | |
e275b388 DC |
1662 | * get_cpu_position_in_core(cpu) |
1663 | * return the position of the CPU among its HT siblings in the core | |
1664 | * return -1 if the sibling is not in list | |
95aebc44 | 1665 | */ |
e275b388 | 1666 | int get_cpu_position_in_core(int cpu) |
95aebc44 | 1667 | { |
e275b388 DC |
1668 | char path[64]; |
1669 | FILE *filep; | |
1670 | int this_cpu; | |
1671 | char character; | |
1672 | int i; | |
1673 | ||
1674 | sprintf(path, | |
1675 | "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", | |
1676 | cpu); | |
1677 | filep = fopen(path, "r"); | |
1678 | if (filep == NULL) { | |
1679 | perror(path); | |
1680 | exit(1); | |
1681 | } | |
1682 | ||
1683 | for (i = 0; i < topo.num_threads_per_core; i++) { | |
1684 | fscanf(filep, "%d", &this_cpu); | |
1685 | if (this_cpu == cpu) { | |
1686 | fclose(filep); | |
1687 | return i; | |
1688 | } | |
1689 | ||
1690 | /* Account for no separator after last thread*/ | |
1691 | if (i != (topo.num_threads_per_core - 1)) | |
1692 | fscanf(filep, "%c", &character); | |
1693 | } | |
1694 | ||
1695 | fclose(filep); | |
1696 | return -1; | |
103a8fea LB |
1697 | } |
1698 | ||
c98d5d94 LB |
1699 | /* |
1700 | * cpu_is_first_core_in_package(cpu) | |
1701 | * return 1 if given CPU is 1st core in package | |
1702 | */ | |
1703 | int cpu_is_first_core_in_package(int cpu) | |
103a8fea | 1704 | { |
95aebc44 | 1705 | return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu); |
103a8fea LB |
1706 | } |
1707 | ||
1708 | int get_physical_package_id(int cpu) | |
1709 | { | |
95aebc44 | 1710 | return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu); |
103a8fea LB |
1711 | } |
1712 | ||
1713 | int get_core_id(int cpu) | |
1714 | { | |
95aebc44 | 1715 | return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu); |
103a8fea LB |
1716 | } |
1717 | ||
c98d5d94 LB |
1718 | int get_num_ht_siblings(int cpu) |
1719 | { | |
1720 | char path[80]; | |
1721 | FILE *filep; | |
e275b388 DC |
1722 | int sib1; |
1723 | int matches = 0; | |
c98d5d94 | 1724 | char character; |
e275b388 DC |
1725 | char str[100]; |
1726 | char *ch; | |
c98d5d94 LB |
1727 | |
1728 | sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu); | |
57a42a34 | 1729 | filep = fopen_or_die(path, "r"); |
e275b388 | 1730 | |
c98d5d94 LB |
1731 | /* |
1732 | * file format: | |
e275b388 DC |
1733 | * A ',' separated or '-' separated set of numbers |
1734 | * (eg 1-2 or 1,3,4,5) | |
c98d5d94 | 1735 | */ |
e275b388 DC |
1736 | fscanf(filep, "%d%c\n", &sib1, &character); |
1737 | fseek(filep, 0, SEEK_SET); | |
1738 | fgets(str, 100, filep); | |
1739 | ch = strchr(str, character); | |
1740 | while (ch != NULL) { | |
1741 | matches++; | |
1742 | ch = strchr(ch+1, character); | |
1743 | } | |
c98d5d94 LB |
1744 | |
1745 | fclose(filep); | |
e275b388 | 1746 | return matches+1; |
c98d5d94 LB |
1747 | } |
1748 | ||
103a8fea | 1749 | /* |
c98d5d94 LB |
1750 | * run func(thread, core, package) in topology order |
1751 | * skip non-present cpus | |
103a8fea LB |
1752 | */ |
1753 | ||
c98d5d94 LB |
1754 | int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *, |
1755 | struct pkg_data *, struct thread_data *, struct core_data *, | |
1756 | struct pkg_data *), struct thread_data *thread_base, | |
1757 | struct core_data *core_base, struct pkg_data *pkg_base, | |
1758 | struct thread_data *thread_base2, struct core_data *core_base2, | |
1759 | struct pkg_data *pkg_base2) | |
1760 | { | |
1761 | int retval, pkg_no, core_no, thread_no; | |
1762 | ||
1763 | for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) { | |
1764 | for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) { | |
1765 | for (thread_no = 0; thread_no < | |
1766 | topo.num_threads_per_core; ++thread_no) { | |
1767 | struct thread_data *t, *t2; | |
1768 | struct core_data *c, *c2; | |
1769 | struct pkg_data *p, *p2; | |
1770 | ||
1771 | t = GET_THREAD(thread_base, thread_no, core_no, pkg_no); | |
1772 | ||
1773 | if (cpu_is_not_present(t->cpu_id)) | |
1774 | continue; | |
1775 | ||
1776 | t2 = GET_THREAD(thread_base2, thread_no, core_no, pkg_no); | |
1777 | ||
1778 | c = GET_CORE(core_base, core_no, pkg_no); | |
1779 | c2 = GET_CORE(core_base2, core_no, pkg_no); | |
1780 | ||
1781 | p = GET_PKG(pkg_base, pkg_no); | |
1782 | p2 = GET_PKG(pkg_base2, pkg_no); | |
1783 | ||
1784 | retval = func(t, c, p, t2, c2, p2); | |
1785 | if (retval) | |
1786 | return retval; | |
1787 | } | |
1788 | } | |
1789 | } | |
1790 | return 0; | |
1791 | } | |
1792 | ||
1793 | /* | |
1794 | * run func(cpu) on every cpu in /proc/stat | |
1795 | * return max_cpu number | |
1796 | */ | |
1797 | int for_all_proc_cpus(int (func)(int)) | |
103a8fea LB |
1798 | { |
1799 | FILE *fp; | |
c98d5d94 | 1800 | int cpu_num; |
103a8fea LB |
1801 | int retval; |
1802 | ||
57a42a34 | 1803 | fp = fopen_or_die(proc_stat, "r"); |
103a8fea LB |
1804 | |
1805 | retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n"); | |
b2c95d90 JT |
1806 | if (retval != 0) |
1807 | err(1, "%s: failed to parse format", proc_stat); | |
103a8fea | 1808 | |
c98d5d94 LB |
1809 | while (1) { |
1810 | retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num); | |
103a8fea LB |
1811 | if (retval != 1) |
1812 | break; | |
1813 | ||
c98d5d94 LB |
1814 | retval = func(cpu_num); |
1815 | if (retval) { | |
1816 | fclose(fp); | |
1817 | return(retval); | |
1818 | } | |
103a8fea LB |
1819 | } |
1820 | fclose(fp); | |
c98d5d94 | 1821 | return 0; |
103a8fea LB |
1822 | } |
1823 | ||
1824 | void re_initialize(void) | |
1825 | { | |
c98d5d94 LB |
1826 | free_all_buffers(); |
1827 | setup_all_buffers(); | |
1828 | printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus); | |
103a8fea LB |
1829 | } |
1830 | ||
c98d5d94 | 1831 | |
103a8fea | 1832 | /* |
c98d5d94 LB |
1833 | * count_cpus() |
1834 | * remember the last one seen, it will be the max | |
103a8fea | 1835 | */ |
c98d5d94 | 1836 | int count_cpus(int cpu) |
103a8fea | 1837 | { |
c98d5d94 LB |
1838 | if (topo.max_cpu_num < cpu) |
1839 | topo.max_cpu_num = cpu; | |
103a8fea | 1840 | |
c98d5d94 LB |
1841 | topo.num_cpus += 1; |
1842 | return 0; | |
1843 | } | |
1844 | int mark_cpu_present(int cpu) | |
1845 | { | |
1846 | CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set); | |
15aaa346 | 1847 | return 0; |
103a8fea LB |
1848 | } |
1849 | ||
562a2d37 LB |
1850 | /* |
1851 | * snapshot_proc_interrupts() | |
1852 | * | |
1853 | * read and record summary of /proc/interrupts | |
1854 | * | |
1855 | * return 1 if config change requires a restart, else return 0 | |
1856 | */ | |
1857 | int snapshot_proc_interrupts(void) | |
1858 | { | |
1859 | static FILE *fp; | |
1860 | int column, retval; | |
1861 | ||
1862 | if (fp == NULL) | |
1863 | fp = fopen_or_die("/proc/interrupts", "r"); | |
1864 | else | |
1865 | rewind(fp); | |
1866 | ||
1867 | /* read 1st line of /proc/interrupts to get cpu* name for each column */ | |
1868 | for (column = 0; column < topo.num_cpus; ++column) { | |
1869 | int cpu_number; | |
1870 | ||
1871 | retval = fscanf(fp, " CPU%d", &cpu_number); | |
1872 | if (retval != 1) | |
1873 | break; | |
1874 | ||
1875 | if (cpu_number > topo.max_cpu_num) { | |
1876 | warn("/proc/interrupts: cpu%d: > %d", cpu_number, topo.max_cpu_num); | |
1877 | return 1; | |
1878 | } | |
1879 | ||
1880 | irq_column_2_cpu[column] = cpu_number; | |
1881 | irqs_per_cpu[cpu_number] = 0; | |
1882 | } | |
1883 | ||
1884 | /* read /proc/interrupt count lines and sum up irqs per cpu */ | |
1885 | while (1) { | |
1886 | int column; | |
1887 | char buf[64]; | |
1888 | ||
1889 | retval = fscanf(fp, " %s:", buf); /* flush irq# "N:" */ | |
1890 | if (retval != 1) | |
1891 | break; | |
1892 | ||
1893 | /* read the count per cpu */ | |
1894 | for (column = 0; column < topo.num_cpus; ++column) { | |
1895 | ||
1896 | int cpu_number, irq_count; | |
1897 | ||
1898 | retval = fscanf(fp, " %d", &irq_count); | |
1899 | if (retval != 1) | |
1900 | break; | |
1901 | ||
1902 | cpu_number = irq_column_2_cpu[column]; | |
1903 | irqs_per_cpu[cpu_number] += irq_count; | |
1904 | ||
1905 | } | |
1906 | ||
1907 | while (getc(fp) != '\n') | |
1908 | ; /* flush interrupt description */ | |
1909 | ||
1910 | } | |
1911 | return 0; | |
1912 | } | |
fdf676e5 LB |
1913 | /* |
1914 | * snapshot_gfx_rc6_ms() | |
1915 | * | |
1916 | * record snapshot of | |
1917 | * /sys/class/drm/card0/power/rc6_residency_ms | |
1918 | * | |
1919 | * return 1 if config change requires a restart, else return 0 | |
1920 | */ | |
1921 | int snapshot_gfx_rc6_ms(void) | |
1922 | { | |
1923 | FILE *fp; | |
1924 | int retval; | |
1925 | ||
1926 | fp = fopen_or_die("/sys/class/drm/card0/power/rc6_residency_ms", "r"); | |
1927 | ||
1928 | retval = fscanf(fp, "%lld", &gfx_cur_rc6_ms); | |
1929 | if (retval != 1) | |
1930 | err(1, "GFX rc6"); | |
1931 | ||
1932 | fclose(fp); | |
1933 | ||
1934 | return 0; | |
1935 | } | |
27d47356 LB |
1936 | /* |
1937 | * snapshot_gfx_mhz() | |
1938 | * | |
1939 | * record snapshot of | |
1940 | * /sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz | |
1941 | * | |
1942 | * return 1 if config change requires a restart, else return 0 | |
1943 | */ | |
1944 | int snapshot_gfx_mhz(void) | |
1945 | { | |
1946 | static FILE *fp; | |
1947 | int retval; | |
1948 | ||
1949 | if (fp == NULL) | |
1950 | fp = fopen_or_die("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", "r"); | |
1951 | else | |
1952 | rewind(fp); | |
1953 | ||
1954 | retval = fscanf(fp, "%d", &gfx_cur_mhz); | |
1955 | if (retval != 1) | |
1956 | err(1, "GFX MHz"); | |
1957 | ||
1958 | return 0; | |
1959 | } | |
562a2d37 LB |
1960 | |
1961 | /* | |
1962 | * snapshot /proc and /sys files | |
1963 | * | |
1964 | * return 1 if configuration restart needed, else return 0 | |
1965 | */ | |
1966 | int snapshot_proc_sysfs_files(void) | |
1967 | { | |
1968 | if (snapshot_proc_interrupts()) | |
1969 | return 1; | |
1970 | ||
fdf676e5 LB |
1971 | if (do_gfx_rc6_ms) |
1972 | snapshot_gfx_rc6_ms(); | |
1973 | ||
27d47356 LB |
1974 | if (do_gfx_mhz) |
1975 | snapshot_gfx_mhz(); | |
1976 | ||
562a2d37 LB |
1977 | return 0; |
1978 | } | |
1979 | ||
103a8fea LB |
1980 | void turbostat_loop() |
1981 | { | |
c98d5d94 | 1982 | int retval; |
e52966c0 | 1983 | int restarted = 0; |
c98d5d94 | 1984 | |
103a8fea | 1985 | restart: |
e52966c0 LB |
1986 | restarted++; |
1987 | ||
562a2d37 | 1988 | snapshot_proc_sysfs_files(); |
c98d5d94 | 1989 | retval = for_all_cpus(get_counters, EVEN_COUNTERS); |
d91bb17c LB |
1990 | if (retval < -1) { |
1991 | exit(retval); | |
1992 | } else if (retval == -1) { | |
e52966c0 LB |
1993 | if (restarted > 1) { |
1994 | exit(retval); | |
1995 | } | |
c98d5d94 LB |
1996 | re_initialize(); |
1997 | goto restart; | |
1998 | } | |
e52966c0 | 1999 | restarted = 0; |
103a8fea LB |
2000 | gettimeofday(&tv_even, (struct timezone *)NULL); |
2001 | ||
2002 | while (1) { | |
c98d5d94 | 2003 | if (for_all_proc_cpus(cpu_is_not_present)) { |
103a8fea LB |
2004 | re_initialize(); |
2005 | goto restart; | |
2006 | } | |
2a0609c0 | 2007 | nanosleep(&interval_ts, NULL); |
562a2d37 LB |
2008 | if (snapshot_proc_sysfs_files()) |
2009 | goto restart; | |
c98d5d94 | 2010 | retval = for_all_cpus(get_counters, ODD_COUNTERS); |
d91bb17c LB |
2011 | if (retval < -1) { |
2012 | exit(retval); | |
2013 | } else if (retval == -1) { | |
15aaa346 LB |
2014 | re_initialize(); |
2015 | goto restart; | |
2016 | } | |
103a8fea | 2017 | gettimeofday(&tv_odd, (struct timezone *)NULL); |
103a8fea | 2018 | timersub(&tv_odd, &tv_even, &tv_delta); |
c98d5d94 LB |
2019 | for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS); |
2020 | compute_average(EVEN_COUNTERS); | |
2021 | format_all_counters(EVEN_COUNTERS); | |
b7d8c148 | 2022 | flush_output_stdout(); |
2a0609c0 | 2023 | nanosleep(&interval_ts, NULL); |
562a2d37 LB |
2024 | if (snapshot_proc_sysfs_files()) |
2025 | goto restart; | |
c98d5d94 | 2026 | retval = for_all_cpus(get_counters, EVEN_COUNTERS); |
d91bb17c LB |
2027 | if (retval < -1) { |
2028 | exit(retval); | |
2029 | } else if (retval == -1) { | |
103a8fea LB |
2030 | re_initialize(); |
2031 | goto restart; | |
2032 | } | |
103a8fea | 2033 | gettimeofday(&tv_even, (struct timezone *)NULL); |
103a8fea | 2034 | timersub(&tv_even, &tv_odd, &tv_delta); |
c98d5d94 LB |
2035 | for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS); |
2036 | compute_average(ODD_COUNTERS); | |
2037 | format_all_counters(ODD_COUNTERS); | |
b7d8c148 | 2038 | flush_output_stdout(); |
103a8fea LB |
2039 | } |
2040 | } | |
2041 | ||
2042 | void check_dev_msr() | |
2043 | { | |
2044 | struct stat sb; | |
7ce7d5de | 2045 | char pathname[32]; |
103a8fea | 2046 | |
7ce7d5de PB |
2047 | sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); |
2048 | if (stat(pathname, &sb)) | |
a21d38c8 LB |
2049 | if (system("/sbin/modprobe msr > /dev/null 2>&1")) |
2050 | err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" "); | |
103a8fea LB |
2051 | } |
2052 | ||
98481e79 | 2053 | void check_permissions() |
103a8fea | 2054 | { |
98481e79 LB |
2055 | struct __user_cap_header_struct cap_header_data; |
2056 | cap_user_header_t cap_header = &cap_header_data; | |
2057 | struct __user_cap_data_struct cap_data_data; | |
2058 | cap_user_data_t cap_data = &cap_data_data; | |
2059 | extern int capget(cap_user_header_t hdrp, cap_user_data_t datap); | |
2060 | int do_exit = 0; | |
7ce7d5de | 2061 | char pathname[32]; |
98481e79 LB |
2062 | |
2063 | /* check for CAP_SYS_RAWIO */ | |
2064 | cap_header->pid = getpid(); | |
2065 | cap_header->version = _LINUX_CAPABILITY_VERSION; | |
2066 | if (capget(cap_header, cap_data) < 0) | |
2067 | err(-6, "capget(2) failed"); | |
2068 | ||
2069 | if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) { | |
2070 | do_exit++; | |
2071 | warnx("capget(CAP_SYS_RAWIO) failed," | |
2072 | " try \"# setcap cap_sys_rawio=ep %s\"", progname); | |
2073 | } | |
2074 | ||
2075 | /* test file permissions */ | |
7ce7d5de PB |
2076 | sprintf(pathname, "/dev/cpu/%d/msr", base_cpu); |
2077 | if (euidaccess(pathname, R_OK)) { | |
98481e79 LB |
2078 | do_exit++; |
2079 | warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr"); | |
2080 | } | |
2081 | ||
2082 | /* if all else fails, thell them to be root */ | |
2083 | if (do_exit) | |
2084 | if (getuid() != 0) | |
d7899447 | 2085 | warnx("... or simply run as root"); |
98481e79 LB |
2086 | |
2087 | if (do_exit) | |
2088 | exit(-6); | |
103a8fea LB |
2089 | } |
2090 | ||
d7899447 LB |
2091 | /* |
2092 | * NHM adds support for additional MSRs: | |
2093 | * | |
2094 | * MSR_SMI_COUNT 0x00000034 | |
2095 | * | |
ec0adc53 | 2096 | * MSR_PLATFORM_INFO 0x000000ce |
d7899447 LB |
2097 | * MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 |
2098 | * | |
2099 | * MSR_PKG_C3_RESIDENCY 0x000003f8 | |
2100 | * MSR_PKG_C6_RESIDENCY 0x000003f9 | |
2101 | * MSR_CORE_C3_RESIDENCY 0x000003fc | |
2102 | * MSR_CORE_C6_RESIDENCY 0x000003fd | |
2103 | * | |
ee7e38e3 LB |
2104 | * Side effect: |
2105 | * sets global pkg_cstate_limit to decode MSR_NHM_SNB_PKG_CST_CFG_CTL | |
d7899447 | 2106 | */ |
ee7e38e3 | 2107 | int probe_nhm_msrs(unsigned int family, unsigned int model) |
103a8fea | 2108 | { |
ee7e38e3 | 2109 | unsigned long long msr; |
21ed5574 | 2110 | unsigned int base_ratio; |
ee7e38e3 LB |
2111 | int *pkg_cstate_limits; |
2112 | ||
103a8fea LB |
2113 | if (!genuine_intel) |
2114 | return 0; | |
2115 | ||
2116 | if (family != 6) | |
2117 | return 0; | |
2118 | ||
21ed5574 LB |
2119 | bclk = discover_bclk(family, model); |
2120 | ||
103a8fea LB |
2121 | switch (model) { |
2122 | case 0x1A: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */ | |
2123 | case 0x1E: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */ | |
2124 | case 0x1F: /* Core i7 and i5 Processor - Nehalem */ | |
2125 | case 0x25: /* Westmere Client - Clarkdale, Arrandale */ | |
2126 | case 0x2C: /* Westmere EP - Gulftown */ | |
ee7e38e3 LB |
2127 | case 0x2E: /* Nehalem-EX Xeon - Beckton */ |
2128 | case 0x2F: /* Westmere-EX Xeon - Eagleton */ | |
2129 | pkg_cstate_limits = nhm_pkg_cstate_limits; | |
2130 | break; | |
103a8fea LB |
2131 | case 0x2A: /* SNB */ |
2132 | case 0x2D: /* SNB Xeon */ | |
553575f1 | 2133 | case 0x3A: /* IVB */ |
1300651b | 2134 | case 0x3E: /* IVB Xeon */ |
ee7e38e3 LB |
2135 | pkg_cstate_limits = snb_pkg_cstate_limits; |
2136 | break; | |
70b43400 | 2137 | case 0x3C: /* HSW */ |
e6f9bb3c | 2138 | case 0x3F: /* HSX */ |
70b43400 | 2139 | case 0x45: /* HSW */ |
149c2319 | 2140 | case 0x46: /* HSW */ |
4e8e863f | 2141 | case 0x3D: /* BDW */ |
48a0631c | 2142 | case 0x47: /* BDW */ |
4e8e863f LB |
2143 | case 0x4F: /* BDX */ |
2144 | case 0x56: /* BDX-DE */ | |
0b2bb692 LB |
2145 | case 0x4E: /* SKL */ |
2146 | case 0x5E: /* SKL */ | |
ee7e38e3 LB |
2147 | pkg_cstate_limits = hsw_pkg_cstate_limits; |
2148 | break; | |
2149 | case 0x37: /* BYT */ | |
2150 | case 0x4D: /* AVN */ | |
2151 | pkg_cstate_limits = slv_pkg_cstate_limits; | |
2152 | break; | |
2153 | case 0x4C: /* AMT */ | |
2154 | pkg_cstate_limits = amt_pkg_cstate_limits; | |
2155 | break; | |
2156 | case 0x57: /* PHI */ | |
2157 | pkg_cstate_limits = phi_pkg_cstate_limits; | |
2158 | break; | |
103a8fea LB |
2159 | default: |
2160 | return 0; | |
2161 | } | |
7ce7d5de | 2162 | get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr); |
e9257f5f | 2163 | pkg_cstate_limit = pkg_cstate_limits[msr & 0xF]; |
ee7e38e3 | 2164 | |
ec0adc53 | 2165 | get_msr(base_cpu, MSR_PLATFORM_INFO, &msr); |
21ed5574 LB |
2166 | base_ratio = (msr >> 8) & 0xFF; |
2167 | ||
2168 | base_hz = base_ratio * bclk * 1000000; | |
2169 | has_base_hz = 1; | |
ee7e38e3 | 2170 | return 1; |
103a8fea | 2171 | } |
d7899447 LB |
2172 | int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model) |
2173 | { | |
d7899447 LB |
2174 | switch (model) { |
2175 | /* Nehalem compatible, but do not include turbo-ratio limit support */ | |
2176 | case 0x2E: /* Nehalem-EX Xeon - Beckton */ | |
2177 | case 0x2F: /* Westmere-EX Xeon - Eagleton */ | |
cbf97aba | 2178 | case 0x57: /* PHI - Knights Landing (different MSR definition) */ |
d7899447 LB |
2179 | return 0; |
2180 | default: | |
2181 | return 1; | |
2182 | } | |
2183 | } | |
6574a5d5 LB |
2184 | int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model) |
2185 | { | |
2186 | if (!genuine_intel) | |
2187 | return 0; | |
2188 | ||
2189 | if (family != 6) | |
2190 | return 0; | |
2191 | ||
2192 | switch (model) { | |
2193 | case 0x3E: /* IVB Xeon */ | |
fcd17211 LB |
2194 | case 0x3F: /* HSW Xeon */ |
2195 | return 1; | |
2196 | default: | |
2197 | return 0; | |
2198 | } | |
2199 | } | |
2200 | int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model) | |
2201 | { | |
2202 | if (!genuine_intel) | |
2203 | return 0; | |
2204 | ||
2205 | if (family != 6) | |
2206 | return 0; | |
2207 | ||
2208 | switch (model) { | |
2209 | case 0x3F: /* HSW Xeon */ | |
6574a5d5 LB |
2210 | return 1; |
2211 | default: | |
2212 | return 0; | |
2213 | } | |
2214 | } | |
2215 | ||
fb5d4327 DC |
2216 | int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model) |
2217 | { | |
2218 | if (!genuine_intel) | |
2219 | return 0; | |
2220 | ||
2221 | if (family != 6) | |
2222 | return 0; | |
2223 | ||
2224 | switch (model) { | |
2225 | case 0x57: /* Knights Landing */ | |
2226 | return 1; | |
2227 | default: | |
2228 | return 0; | |
2229 | } | |
2230 | } | |
6fb3143b LB |
2231 | int has_config_tdp(unsigned int family, unsigned int model) |
2232 | { | |
2233 | if (!genuine_intel) | |
2234 | return 0; | |
2235 | ||
2236 | if (family != 6) | |
2237 | return 0; | |
2238 | ||
2239 | switch (model) { | |
2240 | case 0x3A: /* IVB */ | |
6fb3143b LB |
2241 | case 0x3C: /* HSW */ |
2242 | case 0x3F: /* HSX */ | |
2243 | case 0x45: /* HSW */ | |
2244 | case 0x46: /* HSW */ | |
2245 | case 0x3D: /* BDW */ | |
2246 | case 0x47: /* BDW */ | |
2247 | case 0x4F: /* BDX */ | |
2248 | case 0x56: /* BDX-DE */ | |
2249 | case 0x4E: /* SKL */ | |
2250 | case 0x5E: /* SKL */ | |
2251 | ||
2252 | case 0x57: /* Knights Landing */ | |
2253 | return 1; | |
2254 | default: | |
2255 | return 0; | |
2256 | } | |
2257 | } | |
2258 | ||
fcd17211 | 2259 | static void |
1b69317d | 2260 | dump_cstate_pstate_config_info(unsigned int family, unsigned int model) |
fcd17211 LB |
2261 | { |
2262 | if (!do_nhm_platform_info) | |
2263 | return; | |
2264 | ||
2265 | dump_nhm_platform_info(); | |
2266 | ||
2267 | if (has_hsw_turbo_ratio_limit(family, model)) | |
2268 | dump_hsw_turbo_ratio_limits(); | |
2269 | ||
2270 | if (has_ivt_turbo_ratio_limit(family, model)) | |
2271 | dump_ivt_turbo_ratio_limits(); | |
2272 | ||
2273 | if (has_nhm_turbo_ratio_limit(family, model)) | |
2274 | dump_nhm_turbo_ratio_limits(); | |
2275 | ||
fb5d4327 DC |
2276 | if (has_knl_turbo_ratio_limit(family, model)) |
2277 | dump_knl_turbo_ratio_limits(); | |
2278 | ||
6fb3143b LB |
2279 | if (has_config_tdp(family, model)) |
2280 | dump_config_tdp(); | |
2281 | ||
fcd17211 LB |
2282 | dump_nhm_cst_cfg(); |
2283 | } | |
2284 | ||
2285 | ||
889facbe LB |
2286 | /* |
2287 | * print_epb() | |
2288 | * Decode the ENERGY_PERF_BIAS MSR | |
2289 | */ | |
2290 | int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
2291 | { | |
2292 | unsigned long long msr; | |
2293 | char *epb_string; | |
2294 | int cpu; | |
2295 | ||
2296 | if (!has_epb) | |
2297 | return 0; | |
2298 | ||
2299 | cpu = t->cpu_id; | |
2300 | ||
2301 | /* EPB is per-package */ | |
2302 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
2303 | return 0; | |
2304 | ||
2305 | if (cpu_migrate(cpu)) { | |
b7d8c148 | 2306 | fprintf(outf, "Could not migrate to CPU %d\n", cpu); |
889facbe LB |
2307 | return -1; |
2308 | } | |
2309 | ||
2310 | if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr)) | |
2311 | return 0; | |
2312 | ||
e9be7dd6 | 2313 | switch (msr & 0xF) { |
889facbe LB |
2314 | case ENERGY_PERF_BIAS_PERFORMANCE: |
2315 | epb_string = "performance"; | |
2316 | break; | |
2317 | case ENERGY_PERF_BIAS_NORMAL: | |
2318 | epb_string = "balanced"; | |
2319 | break; | |
2320 | case ENERGY_PERF_BIAS_POWERSAVE: | |
2321 | epb_string = "powersave"; | |
2322 | break; | |
2323 | default: | |
2324 | epb_string = "custom"; | |
2325 | break; | |
2326 | } | |
b7d8c148 | 2327 | fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string); |
889facbe LB |
2328 | |
2329 | return 0; | |
2330 | } | |
7f5c258e LB |
2331 | /* |
2332 | * print_hwp() | |
2333 | * Decode the MSR_HWP_CAPABILITIES | |
2334 | */ | |
2335 | int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
2336 | { | |
2337 | unsigned long long msr; | |
2338 | int cpu; | |
2339 | ||
2340 | if (!has_hwp) | |
2341 | return 0; | |
2342 | ||
2343 | cpu = t->cpu_id; | |
2344 | ||
2345 | /* MSR_HWP_CAPABILITIES is per-package */ | |
2346 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
2347 | return 0; | |
2348 | ||
2349 | if (cpu_migrate(cpu)) { | |
b7d8c148 | 2350 | fprintf(outf, "Could not migrate to CPU %d\n", cpu); |
7f5c258e LB |
2351 | return -1; |
2352 | } | |
2353 | ||
2354 | if (get_msr(cpu, MSR_PM_ENABLE, &msr)) | |
2355 | return 0; | |
2356 | ||
b7d8c148 | 2357 | fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n", |
7f5c258e LB |
2358 | cpu, msr, (msr & (1 << 0)) ? "" : "No-"); |
2359 | ||
2360 | /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */ | |
2361 | if ((msr & (1 << 0)) == 0) | |
2362 | return 0; | |
2363 | ||
2364 | if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr)) | |
2365 | return 0; | |
2366 | ||
b7d8c148 | 2367 | fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx " |
7f5c258e LB |
2368 | "(high 0x%x guar 0x%x eff 0x%x low 0x%x)\n", |
2369 | cpu, msr, | |
2370 | (unsigned int)HWP_HIGHEST_PERF(msr), | |
2371 | (unsigned int)HWP_GUARANTEED_PERF(msr), | |
2372 | (unsigned int)HWP_MOSTEFFICIENT_PERF(msr), | |
2373 | (unsigned int)HWP_LOWEST_PERF(msr)); | |
2374 | ||
2375 | if (get_msr(cpu, MSR_HWP_REQUEST, &msr)) | |
2376 | return 0; | |
2377 | ||
b7d8c148 | 2378 | fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx " |
7f5c258e LB |
2379 | "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x pkg 0x%x)\n", |
2380 | cpu, msr, | |
2381 | (unsigned int)(((msr) >> 0) & 0xff), | |
2382 | (unsigned int)(((msr) >> 8) & 0xff), | |
2383 | (unsigned int)(((msr) >> 16) & 0xff), | |
2384 | (unsigned int)(((msr) >> 24) & 0xff), | |
2385 | (unsigned int)(((msr) >> 32) & 0xff3), | |
2386 | (unsigned int)(((msr) >> 42) & 0x1)); | |
2387 | ||
2388 | if (has_hwp_pkg) { | |
2389 | if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr)) | |
2390 | return 0; | |
2391 | ||
b7d8c148 | 2392 | fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx " |
7f5c258e LB |
2393 | "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x)\n", |
2394 | cpu, msr, | |
2395 | (unsigned int)(((msr) >> 0) & 0xff), | |
2396 | (unsigned int)(((msr) >> 8) & 0xff), | |
2397 | (unsigned int)(((msr) >> 16) & 0xff), | |
2398 | (unsigned int)(((msr) >> 24) & 0xff), | |
2399 | (unsigned int)(((msr) >> 32) & 0xff3)); | |
2400 | } | |
2401 | if (has_hwp_notify) { | |
2402 | if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr)) | |
2403 | return 0; | |
2404 | ||
b7d8c148 | 2405 | fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx " |
7f5c258e LB |
2406 | "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n", |
2407 | cpu, msr, | |
2408 | ((msr) & 0x1) ? "EN" : "Dis", | |
2409 | ((msr) & 0x2) ? "EN" : "Dis"); | |
2410 | } | |
2411 | if (get_msr(cpu, MSR_HWP_STATUS, &msr)) | |
2412 | return 0; | |
2413 | ||
b7d8c148 | 2414 | fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx " |
7f5c258e LB |
2415 | "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n", |
2416 | cpu, msr, | |
2417 | ((msr) & 0x1) ? "" : "No-", | |
2418 | ((msr) & 0x2) ? "" : "No-"); | |
889facbe LB |
2419 | |
2420 | return 0; | |
2421 | } | |
2422 | ||
3a9a941d LB |
2423 | /* |
2424 | * print_perf_limit() | |
2425 | */ | |
2426 | int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
2427 | { | |
2428 | unsigned long long msr; | |
2429 | int cpu; | |
2430 | ||
2431 | cpu = t->cpu_id; | |
2432 | ||
2433 | /* per-package */ | |
2434 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
2435 | return 0; | |
2436 | ||
2437 | if (cpu_migrate(cpu)) { | |
b7d8c148 | 2438 | fprintf(outf, "Could not migrate to CPU %d\n", cpu); |
3a9a941d LB |
2439 | return -1; |
2440 | } | |
2441 | ||
2442 | if (do_core_perf_limit_reasons) { | |
2443 | get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr); | |
b7d8c148 LB |
2444 | fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); |
2445 | fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)", | |
e33cbe85 | 2446 | (msr & 1 << 15) ? "bit15, " : "", |
3a9a941d | 2447 | (msr & 1 << 14) ? "bit14, " : "", |
e33cbe85 LB |
2448 | (msr & 1 << 13) ? "Transitions, " : "", |
2449 | (msr & 1 << 12) ? "MultiCoreTurbo, " : "", | |
2450 | (msr & 1 << 11) ? "PkgPwrL2, " : "", | |
2451 | (msr & 1 << 10) ? "PkgPwrL1, " : "", | |
2452 | (msr & 1 << 9) ? "CorePwr, " : "", | |
2453 | (msr & 1 << 8) ? "Amps, " : "", | |
2454 | (msr & 1 << 6) ? "VR-Therm, " : "", | |
2455 | (msr & 1 << 5) ? "Auto-HWP, " : "", | |
2456 | (msr & 1 << 4) ? "Graphics, " : "", | |
2457 | (msr & 1 << 2) ? "bit2, " : "", | |
2458 | (msr & 1 << 1) ? "ThermStatus, " : "", | |
2459 | (msr & 1 << 0) ? "PROCHOT, " : ""); | |
b7d8c148 | 2460 | fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n", |
e33cbe85 | 2461 | (msr & 1 << 31) ? "bit31, " : "", |
3a9a941d | 2462 | (msr & 1 << 30) ? "bit30, " : "", |
e33cbe85 LB |
2463 | (msr & 1 << 29) ? "Transitions, " : "", |
2464 | (msr & 1 << 28) ? "MultiCoreTurbo, " : "", | |
2465 | (msr & 1 << 27) ? "PkgPwrL2, " : "", | |
2466 | (msr & 1 << 26) ? "PkgPwrL1, " : "", | |
2467 | (msr & 1 << 25) ? "CorePwr, " : "", | |
2468 | (msr & 1 << 24) ? "Amps, " : "", | |
2469 | (msr & 1 << 22) ? "VR-Therm, " : "", | |
2470 | (msr & 1 << 21) ? "Auto-HWP, " : "", | |
2471 | (msr & 1 << 20) ? "Graphics, " : "", | |
2472 | (msr & 1 << 18) ? "bit18, " : "", | |
2473 | (msr & 1 << 17) ? "ThermStatus, " : "", | |
2474 | (msr & 1 << 16) ? "PROCHOT, " : ""); | |
3a9a941d LB |
2475 | |
2476 | } | |
2477 | if (do_gfx_perf_limit_reasons) { | |
2478 | get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr); | |
b7d8c148 LB |
2479 | fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); |
2480 | fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)", | |
3a9a941d LB |
2481 | (msr & 1 << 0) ? "PROCHOT, " : "", |
2482 | (msr & 1 << 1) ? "ThermStatus, " : "", | |
2483 | (msr & 1 << 4) ? "Graphics, " : "", | |
2484 | (msr & 1 << 6) ? "VR-Therm, " : "", | |
2485 | (msr & 1 << 8) ? "Amps, " : "", | |
2486 | (msr & 1 << 9) ? "GFXPwr, " : "", | |
2487 | (msr & 1 << 10) ? "PkgPwrL1, " : "", | |
2488 | (msr & 1 << 11) ? "PkgPwrL2, " : ""); | |
b7d8c148 | 2489 | fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n", |
3a9a941d LB |
2490 | (msr & 1 << 16) ? "PROCHOT, " : "", |
2491 | (msr & 1 << 17) ? "ThermStatus, " : "", | |
2492 | (msr & 1 << 20) ? "Graphics, " : "", | |
2493 | (msr & 1 << 22) ? "VR-Therm, " : "", | |
2494 | (msr & 1 << 24) ? "Amps, " : "", | |
2495 | (msr & 1 << 25) ? "GFXPwr, " : "", | |
2496 | (msr & 1 << 26) ? "PkgPwrL1, " : "", | |
2497 | (msr & 1 << 27) ? "PkgPwrL2, " : ""); | |
2498 | } | |
2499 | if (do_ring_perf_limit_reasons) { | |
2500 | get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr); | |
b7d8c148 LB |
2501 | fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr); |
2502 | fprintf(outf, " (Active: %s%s%s%s%s%s)", | |
3a9a941d LB |
2503 | (msr & 1 << 0) ? "PROCHOT, " : "", |
2504 | (msr & 1 << 1) ? "ThermStatus, " : "", | |
2505 | (msr & 1 << 6) ? "VR-Therm, " : "", | |
2506 | (msr & 1 << 8) ? "Amps, " : "", | |
2507 | (msr & 1 << 10) ? "PkgPwrL1, " : "", | |
2508 | (msr & 1 << 11) ? "PkgPwrL2, " : ""); | |
b7d8c148 | 2509 | fprintf(outf, " (Logged: %s%s%s%s%s%s)\n", |
3a9a941d LB |
2510 | (msr & 1 << 16) ? "PROCHOT, " : "", |
2511 | (msr & 1 << 17) ? "ThermStatus, " : "", | |
2512 | (msr & 1 << 22) ? "VR-Therm, " : "", | |
2513 | (msr & 1 << 24) ? "Amps, " : "", | |
2514 | (msr & 1 << 26) ? "PkgPwrL1, " : "", | |
2515 | (msr & 1 << 27) ? "PkgPwrL2, " : ""); | |
2516 | } | |
2517 | return 0; | |
2518 | } | |
2519 | ||
889facbe LB |
2520 | #define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */ |
2521 | #define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */ | |
2522 | ||
1b69317d | 2523 | double get_tdp(unsigned int model) |
144b44b1 LB |
2524 | { |
2525 | unsigned long long msr; | |
2526 | ||
2527 | if (do_rapl & RAPL_PKG_POWER_INFO) | |
7ce7d5de | 2528 | if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr)) |
144b44b1 LB |
2529 | return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units; |
2530 | ||
2531 | switch (model) { | |
2532 | case 0x37: | |
2533 | case 0x4D: | |
2534 | return 30.0; | |
2535 | default: | |
2536 | return 135.0; | |
2537 | } | |
2538 | } | |
2539 | ||
40ee8e3b AS |
2540 | /* |
2541 | * rapl_dram_energy_units_probe() | |
2542 | * Energy units are either hard-coded, or come from RAPL Energy Unit MSR. | |
2543 | */ | |
2544 | static double | |
2545 | rapl_dram_energy_units_probe(int model, double rapl_energy_units) | |
2546 | { | |
2547 | /* only called for genuine_intel, family 6 */ | |
2548 | ||
2549 | switch (model) { | |
2550 | case 0x3F: /* HSX */ | |
2551 | case 0x4F: /* BDX */ | |
2552 | case 0x56: /* BDX-DE */ | |
fb5d4327 | 2553 | case 0x57: /* KNL */ |
40ee8e3b AS |
2554 | return (rapl_dram_energy_units = 15.3 / 1000000); |
2555 | default: | |
2556 | return (rapl_energy_units); | |
2557 | } | |
2558 | } | |
2559 | ||
144b44b1 | 2560 | |
889facbe LB |
2561 | /* |
2562 | * rapl_probe() | |
2563 | * | |
144b44b1 | 2564 | * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units |
889facbe LB |
2565 | */ |
2566 | void rapl_probe(unsigned int family, unsigned int model) | |
2567 | { | |
2568 | unsigned long long msr; | |
144b44b1 | 2569 | unsigned int time_unit; |
889facbe LB |
2570 | double tdp; |
2571 | ||
2572 | if (!genuine_intel) | |
2573 | return; | |
2574 | ||
2575 | if (family != 6) | |
2576 | return; | |
2577 | ||
2578 | switch (model) { | |
2579 | case 0x2A: | |
2580 | case 0x3A: | |
70b43400 | 2581 | case 0x3C: /* HSW */ |
70b43400 | 2582 | case 0x45: /* HSW */ |
149c2319 | 2583 | case 0x46: /* HSW */ |
4e8e863f | 2584 | case 0x3D: /* BDW */ |
48a0631c | 2585 | case 0x47: /* BDW */ |
144b44b1 | 2586 | do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO; |
889facbe | 2587 | break; |
0b2bb692 LB |
2588 | case 0x4E: /* SKL */ |
2589 | case 0x5E: /* SKL */ | |
2590 | do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; | |
2591 | break; | |
e6f9bb3c | 2592 | case 0x3F: /* HSX */ |
4e8e863f LB |
2593 | case 0x4F: /* BDX */ |
2594 | case 0x56: /* BDX-DE */ | |
fb5d4327 | 2595 | case 0x57: /* KNL */ |
0b2bb692 | 2596 | do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO; |
e6f9bb3c | 2597 | break; |
889facbe LB |
2598 | case 0x2D: |
2599 | case 0x3E: | |
0b2bb692 | 2600 | do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO; |
144b44b1 LB |
2601 | break; |
2602 | case 0x37: /* BYT */ | |
2603 | case 0x4D: /* AVN */ | |
2604 | do_rapl = RAPL_PKG | RAPL_CORES ; | |
889facbe LB |
2605 | break; |
2606 | default: | |
2607 | return; | |
2608 | } | |
2609 | ||
2610 | /* units on package 0, verify later other packages match */ | |
7ce7d5de | 2611 | if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr)) |
889facbe LB |
2612 | return; |
2613 | ||
2614 | rapl_power_units = 1.0 / (1 << (msr & 0xF)); | |
144b44b1 LB |
2615 | if (model == 0x37) |
2616 | rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000; | |
2617 | else | |
2618 | rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F)); | |
889facbe | 2619 | |
40ee8e3b AS |
2620 | rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units); |
2621 | ||
144b44b1 LB |
2622 | time_unit = msr >> 16 & 0xF; |
2623 | if (time_unit == 0) | |
2624 | time_unit = 0xA; | |
889facbe | 2625 | |
144b44b1 | 2626 | rapl_time_units = 1.0 / (1 << (time_unit)); |
889facbe | 2627 | |
144b44b1 | 2628 | tdp = get_tdp(model); |
889facbe | 2629 | |
144b44b1 | 2630 | rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp; |
d8af6f5f | 2631 | if (debug) |
b7d8c148 | 2632 | fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp); |
889facbe LB |
2633 | |
2634 | return; | |
2635 | } | |
2636 | ||
1b69317d | 2637 | void perf_limit_reasons_probe(unsigned int family, unsigned int model) |
3a9a941d LB |
2638 | { |
2639 | if (!genuine_intel) | |
2640 | return; | |
2641 | ||
2642 | if (family != 6) | |
2643 | return; | |
2644 | ||
2645 | switch (model) { | |
2646 | case 0x3C: /* HSW */ | |
2647 | case 0x45: /* HSW */ | |
2648 | case 0x46: /* HSW */ | |
2649 | do_gfx_perf_limit_reasons = 1; | |
2650 | case 0x3F: /* HSX */ | |
2651 | do_core_perf_limit_reasons = 1; | |
2652 | do_ring_perf_limit_reasons = 1; | |
2653 | default: | |
2654 | return; | |
2655 | } | |
2656 | } | |
2657 | ||
889facbe LB |
2658 | int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p) |
2659 | { | |
2660 | unsigned long long msr; | |
2661 | unsigned int dts; | |
2662 | int cpu; | |
2663 | ||
2664 | if (!(do_dts || do_ptm)) | |
2665 | return 0; | |
2666 | ||
2667 | cpu = t->cpu_id; | |
2668 | ||
2669 | /* DTS is per-core, no need to print for each thread */ | |
2670 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE)) | |
2671 | return 0; | |
2672 | ||
2673 | if (cpu_migrate(cpu)) { | |
b7d8c148 | 2674 | fprintf(outf, "Could not migrate to CPU %d\n", cpu); |
889facbe LB |
2675 | return -1; |
2676 | } | |
2677 | ||
2678 | if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) { | |
2679 | if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr)) | |
2680 | return 0; | |
2681 | ||
2682 | dts = (msr >> 16) & 0x7F; | |
b7d8c148 | 2683 | fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n", |
889facbe LB |
2684 | cpu, msr, tcc_activation_temp - dts); |
2685 | ||
2686 | #ifdef THERM_DEBUG | |
2687 | if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr)) | |
2688 | return 0; | |
2689 | ||
2690 | dts = (msr >> 16) & 0x7F; | |
2691 | dts2 = (msr >> 8) & 0x7F; | |
b7d8c148 | 2692 | fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", |
889facbe LB |
2693 | cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); |
2694 | #endif | |
2695 | } | |
2696 | ||
2697 | ||
2698 | if (do_dts) { | |
2699 | unsigned int resolution; | |
2700 | ||
2701 | if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr)) | |
2702 | return 0; | |
2703 | ||
2704 | dts = (msr >> 16) & 0x7F; | |
2705 | resolution = (msr >> 27) & 0xF; | |
b7d8c148 | 2706 | fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n", |
889facbe LB |
2707 | cpu, msr, tcc_activation_temp - dts, resolution); |
2708 | ||
2709 | #ifdef THERM_DEBUG | |
2710 | if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr)) | |
2711 | return 0; | |
2712 | ||
2713 | dts = (msr >> 16) & 0x7F; | |
2714 | dts2 = (msr >> 8) & 0x7F; | |
b7d8c148 | 2715 | fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n", |
889facbe LB |
2716 | cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2); |
2717 | #endif | |
2718 | } | |
2719 | ||
2720 | return 0; | |
2721 | } | |
36229897 | 2722 | |
889facbe LB |
2723 | void print_power_limit_msr(int cpu, unsigned long long msr, char *label) |
2724 | { | |
b7d8c148 | 2725 | fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n", |
889facbe LB |
2726 | cpu, label, |
2727 | ((msr >> 15) & 1) ? "EN" : "DIS", | |
2728 | ((msr >> 0) & 0x7FFF) * rapl_power_units, | |
2729 | (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units, | |
2730 | (((msr >> 16) & 1) ? "EN" : "DIS")); | |
2731 | ||
2732 | return; | |
2733 | } | |
2734 | ||
2735 | int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
2736 | { | |
2737 | unsigned long long msr; | |
2738 | int cpu; | |
889facbe LB |
2739 | |
2740 | if (!do_rapl) | |
2741 | return 0; | |
2742 | ||
2743 | /* RAPL counters are per package, so print only for 1st thread/package */ | |
2744 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
2745 | return 0; | |
2746 | ||
2747 | cpu = t->cpu_id; | |
2748 | if (cpu_migrate(cpu)) { | |
b7d8c148 | 2749 | fprintf(outf, "Could not migrate to CPU %d\n", cpu); |
889facbe LB |
2750 | return -1; |
2751 | } | |
2752 | ||
2753 | if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr)) | |
2754 | return -1; | |
2755 | ||
d8af6f5f | 2756 | if (debug) { |
b7d8c148 | 2757 | fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx " |
889facbe | 2758 | "(%f Watts, %f Joules, %f sec.)\n", cpu, msr, |
144b44b1 | 2759 | rapl_power_units, rapl_energy_units, rapl_time_units); |
889facbe | 2760 | } |
144b44b1 LB |
2761 | if (do_rapl & RAPL_PKG_POWER_INFO) { |
2762 | ||
889facbe LB |
2763 | if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr)) |
2764 | return -5; | |
2765 | ||
2766 | ||
b7d8c148 | 2767 | fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", |
889facbe LB |
2768 | cpu, msr, |
2769 | ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
2770 | ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
2771 | ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
2772 | ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); | |
2773 | ||
144b44b1 LB |
2774 | } |
2775 | if (do_rapl & RAPL_PKG) { | |
2776 | ||
889facbe LB |
2777 | if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr)) |
2778 | return -9; | |
2779 | ||
b7d8c148 | 2780 | fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n", |
889facbe LB |
2781 | cpu, msr, (msr >> 63) & 1 ? "": "UN"); |
2782 | ||
2783 | print_power_limit_msr(cpu, msr, "PKG Limit #1"); | |
b7d8c148 | 2784 | fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n", |
889facbe LB |
2785 | cpu, |
2786 | ((msr >> 47) & 1) ? "EN" : "DIS", | |
2787 | ((msr >> 32) & 0x7FFF) * rapl_power_units, | |
2788 | (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units, | |
2789 | ((msr >> 48) & 1) ? "EN" : "DIS"); | |
2790 | } | |
2791 | ||
0b2bb692 | 2792 | if (do_rapl & RAPL_DRAM_POWER_INFO) { |
889facbe LB |
2793 | if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr)) |
2794 | return -6; | |
2795 | ||
b7d8c148 | 2796 | fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n", |
889facbe LB |
2797 | cpu, msr, |
2798 | ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
2799 | ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
2800 | ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units, | |
2801 | ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units); | |
0b2bb692 LB |
2802 | } |
2803 | if (do_rapl & RAPL_DRAM) { | |
889facbe LB |
2804 | if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr)) |
2805 | return -9; | |
b7d8c148 | 2806 | fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n", |
889facbe LB |
2807 | cpu, msr, (msr >> 31) & 1 ? "": "UN"); |
2808 | ||
2809 | print_power_limit_msr(cpu, msr, "DRAM Limit"); | |
2810 | } | |
144b44b1 | 2811 | if (do_rapl & RAPL_CORE_POLICY) { |
d8af6f5f | 2812 | if (debug) { |
889facbe LB |
2813 | if (get_msr(cpu, MSR_PP0_POLICY, &msr)) |
2814 | return -7; | |
2815 | ||
b7d8c148 | 2816 | fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF); |
144b44b1 LB |
2817 | } |
2818 | } | |
2819 | if (do_rapl & RAPL_CORES) { | |
d8af6f5f | 2820 | if (debug) { |
889facbe LB |
2821 | |
2822 | if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr)) | |
2823 | return -9; | |
b7d8c148 | 2824 | fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n", |
889facbe LB |
2825 | cpu, msr, (msr >> 31) & 1 ? "": "UN"); |
2826 | print_power_limit_msr(cpu, msr, "Cores Limit"); | |
2827 | } | |
2828 | } | |
2829 | if (do_rapl & RAPL_GFX) { | |
d8af6f5f | 2830 | if (debug) { |
889facbe LB |
2831 | if (get_msr(cpu, MSR_PP1_POLICY, &msr)) |
2832 | return -8; | |
2833 | ||
b7d8c148 | 2834 | fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF); |
889facbe LB |
2835 | |
2836 | if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr)) | |
2837 | return -9; | |
b7d8c148 | 2838 | fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n", |
889facbe LB |
2839 | cpu, msr, (msr >> 31) & 1 ? "": "UN"); |
2840 | print_power_limit_msr(cpu, msr, "GFX Limit"); | |
2841 | } | |
2842 | } | |
2843 | return 0; | |
2844 | } | |
2845 | ||
d7899447 LB |
2846 | /* |
2847 | * SNB adds support for additional MSRs: | |
2848 | * | |
2849 | * MSR_PKG_C7_RESIDENCY 0x000003fa | |
2850 | * MSR_CORE_C7_RESIDENCY 0x000003fe | |
2851 | * MSR_PKG_C2_RESIDENCY 0x0000060d | |
2852 | */ | |
103a8fea | 2853 | |
d7899447 | 2854 | int has_snb_msrs(unsigned int family, unsigned int model) |
103a8fea LB |
2855 | { |
2856 | if (!genuine_intel) | |
2857 | return 0; | |
2858 | ||
2859 | switch (model) { | |
2860 | case 0x2A: | |
2861 | case 0x2D: | |
650a37f3 | 2862 | case 0x3A: /* IVB */ |
1300651b | 2863 | case 0x3E: /* IVB Xeon */ |
70b43400 LB |
2864 | case 0x3C: /* HSW */ |
2865 | case 0x3F: /* HSW */ | |
2866 | case 0x45: /* HSW */ | |
149c2319 | 2867 | case 0x46: /* HSW */ |
4e8e863f | 2868 | case 0x3D: /* BDW */ |
48a0631c | 2869 | case 0x47: /* BDW */ |
4e8e863f LB |
2870 | case 0x4F: /* BDX */ |
2871 | case 0x56: /* BDX-DE */ | |
0b2bb692 LB |
2872 | case 0x4E: /* SKL */ |
2873 | case 0x5E: /* SKL */ | |
103a8fea LB |
2874 | return 1; |
2875 | } | |
2876 | return 0; | |
2877 | } | |
2878 | ||
d7899447 LB |
2879 | /* |
2880 | * HSW adds support for additional MSRs: | |
2881 | * | |
2882 | * MSR_PKG_C8_RESIDENCY 0x00000630 | |
2883 | * MSR_PKG_C9_RESIDENCY 0x00000631 | |
2884 | * MSR_PKG_C10_RESIDENCY 0x00000632 | |
2885 | */ | |
2886 | int has_hsw_msrs(unsigned int family, unsigned int model) | |
ca58710f KCA |
2887 | { |
2888 | if (!genuine_intel) | |
2889 | return 0; | |
2890 | ||
2891 | switch (model) { | |
4e8e863f LB |
2892 | case 0x45: /* HSW */ |
2893 | case 0x3D: /* BDW */ | |
0b2bb692 LB |
2894 | case 0x4E: /* SKL */ |
2895 | case 0x5E: /* SKL */ | |
2896 | return 1; | |
2897 | } | |
2898 | return 0; | |
2899 | } | |
2900 | ||
2901 | /* | |
2902 | * SKL adds support for additional MSRS: | |
2903 | * | |
2904 | * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658 | |
2905 | * MSR_PKG_ANY_CORE_C0_RES 0x00000659 | |
2906 | * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A | |
2907 | * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B | |
2908 | */ | |
2909 | int has_skl_msrs(unsigned int family, unsigned int model) | |
2910 | { | |
2911 | if (!genuine_intel) | |
2912 | return 0; | |
2913 | ||
2914 | switch (model) { | |
2915 | case 0x4E: /* SKL */ | |
2916 | case 0x5E: /* SKL */ | |
ca58710f KCA |
2917 | return 1; |
2918 | } | |
2919 | return 0; | |
2920 | } | |
2921 | ||
2922 | ||
0b2bb692 | 2923 | |
144b44b1 LB |
2924 | int is_slm(unsigned int family, unsigned int model) |
2925 | { | |
2926 | if (!genuine_intel) | |
2927 | return 0; | |
2928 | switch (model) { | |
2929 | case 0x37: /* BYT */ | |
2930 | case 0x4D: /* AVN */ | |
2931 | return 1; | |
2932 | } | |
2933 | return 0; | |
2934 | } | |
2935 | ||
fb5d4327 DC |
2936 | int is_knl(unsigned int family, unsigned int model) |
2937 | { | |
2938 | if (!genuine_intel) | |
2939 | return 0; | |
2940 | switch (model) { | |
2941 | case 0x57: /* KNL */ | |
2942 | return 1; | |
2943 | } | |
2944 | return 0; | |
2945 | } | |
2946 | ||
b2b34dfe HC |
2947 | unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model) |
2948 | { | |
2949 | if (is_knl(family, model)) | |
2950 | return 1024; | |
2951 | return 1; | |
2952 | } | |
2953 | ||
144b44b1 LB |
2954 | #define SLM_BCLK_FREQS 5 |
2955 | double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0}; | |
2956 | ||
2957 | double slm_bclk(void) | |
2958 | { | |
2959 | unsigned long long msr = 3; | |
2960 | unsigned int i; | |
2961 | double freq; | |
2962 | ||
7ce7d5de | 2963 | if (get_msr(base_cpu, MSR_FSB_FREQ, &msr)) |
b7d8c148 | 2964 | fprintf(outf, "SLM BCLK: unknown\n"); |
144b44b1 LB |
2965 | |
2966 | i = msr & 0xf; | |
2967 | if (i >= SLM_BCLK_FREQS) { | |
b7d8c148 | 2968 | fprintf(outf, "SLM BCLK[%d] invalid\n", i); |
144b44b1 LB |
2969 | msr = 3; |
2970 | } | |
2971 | freq = slm_freq_table[i]; | |
2972 | ||
b7d8c148 | 2973 | fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq); |
144b44b1 LB |
2974 | |
2975 | return freq; | |
2976 | } | |
2977 | ||
103a8fea LB |
2978 | double discover_bclk(unsigned int family, unsigned int model) |
2979 | { | |
121b48bb | 2980 | if (has_snb_msrs(family, model) || is_knl(family, model)) |
103a8fea | 2981 | return 100.00; |
144b44b1 LB |
2982 | else if (is_slm(family, model)) |
2983 | return slm_bclk(); | |
103a8fea LB |
2984 | else |
2985 | return 133.33; | |
2986 | } | |
2987 | ||
889facbe LB |
2988 | /* |
2989 | * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where | |
2990 | * the Thermal Control Circuit (TCC) activates. | |
2991 | * This is usually equal to tjMax. | |
2992 | * | |
2993 | * Older processors do not have this MSR, so there we guess, | |
2994 | * but also allow cmdline over-ride with -T. | |
2995 | * | |
2996 | * Several MSR temperature values are in units of degrees-C | |
2997 | * below this value, including the Digital Thermal Sensor (DTS), | |
2998 | * Package Thermal Management Sensor (PTM), and thermal event thresholds. | |
2999 | */ | |
3000 | int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p) | |
3001 | { | |
3002 | unsigned long long msr; | |
3003 | unsigned int target_c_local; | |
3004 | int cpu; | |
3005 | ||
3006 | /* tcc_activation_temp is used only for dts or ptm */ | |
3007 | if (!(do_dts || do_ptm)) | |
3008 | return 0; | |
3009 | ||
3010 | /* this is a per-package concept */ | |
3011 | if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) | |
3012 | return 0; | |
3013 | ||
3014 | cpu = t->cpu_id; | |
3015 | if (cpu_migrate(cpu)) { | |
b7d8c148 | 3016 | fprintf(outf, "Could not migrate to CPU %d\n", cpu); |
889facbe LB |
3017 | return -1; |
3018 | } | |
3019 | ||
3020 | if (tcc_activation_temp_override != 0) { | |
3021 | tcc_activation_temp = tcc_activation_temp_override; | |
b7d8c148 | 3022 | fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n", |
889facbe LB |
3023 | cpu, tcc_activation_temp); |
3024 | return 0; | |
3025 | } | |
3026 | ||
3027 | /* Temperature Target MSR is Nehalem and newer only */ | |
d7899447 | 3028 | if (!do_nhm_platform_info) |
889facbe LB |
3029 | goto guess; |
3030 | ||
7ce7d5de | 3031 | if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr)) |
889facbe LB |
3032 | goto guess; |
3033 | ||
3482124a | 3034 | target_c_local = (msr >> 16) & 0xFF; |
889facbe | 3035 | |
d8af6f5f | 3036 | if (debug) |
b7d8c148 | 3037 | fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n", |
889facbe LB |
3038 | cpu, msr, target_c_local); |
3039 | ||
3482124a | 3040 | if (!target_c_local) |
889facbe LB |
3041 | goto guess; |
3042 | ||
3043 | tcc_activation_temp = target_c_local; | |
3044 | ||
3045 | return 0; | |
3046 | ||
3047 | guess: | |
3048 | tcc_activation_temp = TJMAX_DEFAULT; | |
b7d8c148 | 3049 | fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n", |
889facbe LB |
3050 | cpu, tcc_activation_temp); |
3051 | ||
3052 | return 0; | |
3053 | } | |
69807a63 | 3054 | |
aa8d8cc7 LB |
3055 | void decode_feature_control_msr(void) |
3056 | { | |
3057 | unsigned long long msr; | |
3058 | ||
3059 | if (!get_msr(base_cpu, MSR_IA32_FEATURE_CONTROL, &msr)) | |
3060 | fprintf(outf, "cpu%d: MSR_IA32_FEATURE_CONTROL: 0x%08llx (%sLocked %s)\n", | |
3061 | base_cpu, msr, | |
3062 | msr & FEATURE_CONTROL_LOCKED ? "" : "UN-", | |
3063 | msr & (1 << 18) ? "SGX" : ""); | |
3064 | } | |
3065 | ||
69807a63 LB |
3066 | void decode_misc_enable_msr(void) |
3067 | { | |
3068 | unsigned long long msr; | |
3069 | ||
3070 | if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr)) | |
b7d8c148 | 3071 | fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%s %s %s)\n", |
69807a63 LB |
3072 | base_cpu, msr, |
3073 | msr & (1 << 3) ? "TCC" : "", | |
3074 | msr & (1 << 16) ? "EIST" : "", | |
3075 | msr & (1 << 18) ? "MONITOR" : ""); | |
3076 | } | |
3077 | ||
f0057310 LB |
3078 | /* |
3079 | * Decode MSR_MISC_PWR_MGMT | |
3080 | * | |
3081 | * Decode the bits according to the Nehalem documentation | |
3082 | * bit[0] seems to continue to have same meaning going forward | |
3083 | * bit[1] less so... | |
3084 | */ | |
3085 | void decode_misc_pwr_mgmt_msr(void) | |
3086 | { | |
3087 | unsigned long long msr; | |
3088 | ||
3089 | if (!do_nhm_platform_info) | |
3090 | return; | |
3091 | ||
3092 | if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr)) | |
b7d8c148 | 3093 | fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB)\n", |
f0057310 LB |
3094 | base_cpu, msr, |
3095 | msr & (1 << 0) ? "DIS" : "EN", | |
3096 | msr & (1 << 1) ? "EN" : "DIS"); | |
3097 | } | |
7f5c258e | 3098 | |
fcd17211 | 3099 | void process_cpuid() |
103a8fea | 3100 | { |
61a87ba7 | 3101 | unsigned int eax, ebx, ecx, edx, max_level, max_extended_level; |
103a8fea LB |
3102 | unsigned int fms, family, model, stepping; |
3103 | ||
3104 | eax = ebx = ecx = edx = 0; | |
3105 | ||
5aea2f7f | 3106 | __cpuid(0, max_level, ebx, ecx, edx); |
103a8fea LB |
3107 | |
3108 | if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e) | |
3109 | genuine_intel = 1; | |
3110 | ||
d8af6f5f | 3111 | if (debug) |
b7d8c148 | 3112 | fprintf(outf, "CPUID(0): %.4s%.4s%.4s ", |
103a8fea LB |
3113 | (char *)&ebx, (char *)&edx, (char *)&ecx); |
3114 | ||
5aea2f7f | 3115 | __cpuid(1, fms, ebx, ecx, edx); |
103a8fea LB |
3116 | family = (fms >> 8) & 0xf; |
3117 | model = (fms >> 4) & 0xf; | |
3118 | stepping = fms & 0xf; | |
3119 | if (family == 6 || family == 0xf) | |
3120 | model += ((fms >> 16) & 0xf) << 4; | |
3121 | ||
69807a63 | 3122 | if (debug) { |
b7d8c148 | 3123 | fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n", |
103a8fea | 3124 | max_level, family, model, stepping, family, model, stepping); |
aa8d8cc7 | 3125 | fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s %s\n", |
69807a63 LB |
3126 | ecx & (1 << 0) ? "SSE3" : "-", |
3127 | ecx & (1 << 3) ? "MONITOR" : "-", | |
aa8d8cc7 | 3128 | ecx & (1 << 6) ? "SMX" : "-", |
69807a63 LB |
3129 | ecx & (1 << 7) ? "EIST" : "-", |
3130 | ecx & (1 << 8) ? "TM2" : "-", | |
3131 | edx & (1 << 4) ? "TSC" : "-", | |
3132 | edx & (1 << 5) ? "MSR" : "-", | |
3133 | edx & (1 << 22) ? "ACPI-TM" : "-", | |
3134 | edx & (1 << 29) ? "TM" : "-"); | |
3135 | } | |
103a8fea | 3136 | |
b2c95d90 JT |
3137 | if (!(edx & (1 << 5))) |
3138 | errx(1, "CPUID: no MSR"); | |
103a8fea LB |
3139 | |
3140 | /* | |
3141 | * check max extended function levels of CPUID. | |
3142 | * This is needed to check for invariant TSC. | |
3143 | * This check is valid for both Intel and AMD. | |
3144 | */ | |
3145 | ebx = ecx = edx = 0; | |
5aea2f7f | 3146 | __cpuid(0x80000000, max_extended_level, ebx, ecx, edx); |
103a8fea | 3147 | |
61a87ba7 | 3148 | if (max_extended_level >= 0x80000007) { |
103a8fea | 3149 | |
d7899447 LB |
3150 | /* |
3151 | * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8 | |
3152 | * this check is valid for both Intel and AMD | |
3153 | */ | |
5aea2f7f | 3154 | __cpuid(0x80000007, eax, ebx, ecx, edx); |
d7899447 LB |
3155 | has_invariant_tsc = edx & (1 << 8); |
3156 | } | |
103a8fea LB |
3157 | |
3158 | /* | |
3159 | * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0 | |
3160 | * this check is valid for both Intel and AMD | |
3161 | */ | |
3162 | ||
5aea2f7f | 3163 | __cpuid(0x6, eax, ebx, ecx, edx); |
8209e054 | 3164 | has_aperf = ecx & (1 << 0); |
889facbe LB |
3165 | do_dts = eax & (1 << 0); |
3166 | do_ptm = eax & (1 << 6); | |
7f5c258e LB |
3167 | has_hwp = eax & (1 << 7); |
3168 | has_hwp_notify = eax & (1 << 8); | |
3169 | has_hwp_activity_window = eax & (1 << 9); | |
3170 | has_hwp_epp = eax & (1 << 10); | |
3171 | has_hwp_pkg = eax & (1 << 11); | |
889facbe LB |
3172 | has_epb = ecx & (1 << 3); |
3173 | ||
d8af6f5f | 3174 | if (debug) |
b7d8c148 | 3175 | fprintf(outf, "CPUID(6): %sAPERF, %sDTS, %sPTM, %sHWP, " |
7f5c258e LB |
3176 | "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n", |
3177 | has_aperf ? "" : "No-", | |
3178 | do_dts ? "" : "No-", | |
3179 | do_ptm ? "" : "No-", | |
3180 | has_hwp ? "" : "No-", | |
3181 | has_hwp_notify ? "" : "No-", | |
3182 | has_hwp_activity_window ? "" : "No-", | |
3183 | has_hwp_epp ? "" : "No-", | |
3184 | has_hwp_pkg ? "" : "No-", | |
3185 | has_epb ? "" : "No-"); | |
103a8fea | 3186 | |
69807a63 LB |
3187 | if (debug) |
3188 | decode_misc_enable_msr(); | |
3189 | ||
aa8d8cc7 LB |
3190 | if (max_level >= 0x7) { |
3191 | int has_sgx; | |
103a8fea | 3192 | |
aa8d8cc7 LB |
3193 | ecx = 0; |
3194 | ||
3195 | __cpuid_count(0x7, 0, eax, ebx, ecx, edx); | |
3196 | ||
3197 | has_sgx = ebx & (1 << 2); | |
3198 | fprintf(outf, "CPUID(7): %sSGX\n", has_sgx ? "" : "No-"); | |
3199 | ||
3200 | if (has_sgx) | |
3201 | decode_feature_control_msr(); | |
3202 | } | |
3203 | ||
61a87ba7 | 3204 | if (max_level >= 0x15) { |
8a5bdf41 LB |
3205 | unsigned int eax_crystal; |
3206 | unsigned int ebx_tsc; | |
3207 | ||
3208 | /* | |
3209 | * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz | |
3210 | */ | |
3211 | eax_crystal = ebx_tsc = crystal_hz = edx = 0; | |
5aea2f7f | 3212 | __cpuid(0x15, eax_crystal, ebx_tsc, crystal_hz, edx); |
8a5bdf41 LB |
3213 | |
3214 | if (ebx_tsc != 0) { | |
3215 | ||
3216 | if (debug && (ebx != 0)) | |
b7d8c148 | 3217 | fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n", |
8a5bdf41 LB |
3218 | eax_crystal, ebx_tsc, crystal_hz); |
3219 | ||
3220 | if (crystal_hz == 0) | |
3221 | switch(model) { | |
3222 | case 0x4E: /* SKL */ | |
3223 | case 0x5E: /* SKL */ | |
3224 | crystal_hz = 24000000; /* 24 MHz */ | |
3225 | break; | |
3226 | default: | |
3227 | crystal_hz = 0; | |
3228 | } | |
3229 | ||
3230 | if (crystal_hz) { | |
3231 | tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal; | |
3232 | if (debug) | |
b7d8c148 | 3233 | fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n", |
8a5bdf41 LB |
3234 | tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal); |
3235 | } | |
3236 | } | |
3237 | } | |
61a87ba7 LB |
3238 | if (max_level >= 0x16) { |
3239 | unsigned int base_mhz, max_mhz, bus_mhz, edx; | |
3240 | ||
3241 | /* | |
3242 | * CPUID 16H Base MHz, Max MHz, Bus MHz | |
3243 | */ | |
3244 | base_mhz = max_mhz = bus_mhz = edx = 0; | |
3245 | ||
5aea2f7f | 3246 | __cpuid(0x16, base_mhz, max_mhz, bus_mhz, edx); |
61a87ba7 | 3247 | if (debug) |
b7d8c148 | 3248 | fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n", |
61a87ba7 LB |
3249 | base_mhz, max_mhz, bus_mhz); |
3250 | } | |
8a5bdf41 | 3251 | |
b2b34dfe HC |
3252 | if (has_aperf) |
3253 | aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model); | |
3254 | ||
ee7e38e3 | 3255 | do_nhm_platform_info = do_nhm_cstates = do_smi = probe_nhm_msrs(family, model); |
d7899447 | 3256 | do_snb_cstates = has_snb_msrs(family, model); |
ee7e38e3 LB |
3257 | do_pc2 = do_snb_cstates && (pkg_cstate_limit >= PCL__2); |
3258 | do_pc3 = (pkg_cstate_limit >= PCL__3); | |
3259 | do_pc6 = (pkg_cstate_limit >= PCL__6); | |
3260 | do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7); | |
d7899447 | 3261 | do_c8_c9_c10 = has_hsw_msrs(family, model); |
0b2bb692 | 3262 | do_skl_residency = has_skl_msrs(family, model); |
144b44b1 | 3263 | do_slm_cstates = is_slm(family, model); |
fb5d4327 | 3264 | do_knl_cstates = is_knl(family, model); |
103a8fea | 3265 | |
f0057310 LB |
3266 | if (debug) |
3267 | decode_misc_pwr_mgmt_msr(); | |
3268 | ||
889facbe | 3269 | rapl_probe(family, model); |
3a9a941d | 3270 | perf_limit_reasons_probe(family, model); |
889facbe | 3271 | |
fcd17211 | 3272 | if (debug) |
1b69317d | 3273 | dump_cstate_pstate_config_info(family, model); |
fcd17211 | 3274 | |
a2b7b749 LB |
3275 | if (has_skl_msrs(family, model)) |
3276 | calculate_tsc_tweak(); | |
3277 | ||
fdf676e5 LB |
3278 | do_gfx_rc6_ms = !access("/sys/class/drm/card0/power/rc6_residency_ms", R_OK); |
3279 | ||
27d47356 LB |
3280 | do_gfx_mhz = !access("/sys/class/graphics/fb0/device/drm/card0/gt_cur_freq_mhz", R_OK); |
3281 | ||
889facbe | 3282 | return; |
103a8fea LB |
3283 | } |
3284 | ||
d8af6f5f | 3285 | void help() |
103a8fea | 3286 | { |
b7d8c148 | 3287 | fprintf(outf, |
d8af6f5f LB |
3288 | "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n" |
3289 | "\n" | |
3290 | "Turbostat forks the specified COMMAND and prints statistics\n" | |
3291 | "when COMMAND completes.\n" | |
3292 | "If no COMMAND is specified, turbostat wakes every 5-seconds\n" | |
3293 | "to print statistics, until interrupted.\n" | |
3294 | "--debug run in \"debug\" mode\n" | |
3295 | "--interval sec Override default 5-second measurement interval\n" | |
3296 | "--help print this help message\n" | |
3297 | "--counter msr print 32-bit counter at address \"msr\"\n" | |
3298 | "--Counter msr print 64-bit Counter at address \"msr\"\n" | |
b7d8c148 | 3299 | "--out file create or truncate \"file\" for all output\n" |
d8af6f5f LB |
3300 | "--msr msr print 32-bit value at address \"msr\"\n" |
3301 | "--MSR msr print 64-bit Value at address \"msr\"\n" | |
3302 | "--version print version information\n" | |
3303 | "\n" | |
3304 | "For more help, run \"man turbostat\"\n"); | |
103a8fea LB |
3305 | } |
3306 | ||
3307 | ||
3308 | /* | |
3309 | * in /dev/cpu/ return success for names that are numbers | |
3310 | * ie. filter out ".", "..", "microcode". | |
3311 | */ | |
3312 | int dir_filter(const struct dirent *dirp) | |
3313 | { | |
3314 | if (isdigit(dirp->d_name[0])) | |
3315 | return 1; | |
3316 | else | |
3317 | return 0; | |
3318 | } | |
3319 | ||
3320 | int open_dev_cpu_msr(int dummy1) | |
3321 | { | |
3322 | return 0; | |
3323 | } | |
3324 | ||
c98d5d94 LB |
3325 | void topology_probe() |
3326 | { | |
3327 | int i; | |
3328 | int max_core_id = 0; | |
3329 | int max_package_id = 0; | |
3330 | int max_siblings = 0; | |
3331 | struct cpu_topology { | |
3332 | int core_id; | |
3333 | int physical_package_id; | |
3334 | } *cpus; | |
3335 | ||
3336 | /* Initialize num_cpus, max_cpu_num */ | |
3337 | topo.num_cpus = 0; | |
3338 | topo.max_cpu_num = 0; | |
3339 | for_all_proc_cpus(count_cpus); | |
3340 | if (!summary_only && topo.num_cpus > 1) | |
3341 | show_cpu = 1; | |
3342 | ||
d8af6f5f | 3343 | if (debug > 1) |
b7d8c148 | 3344 | fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num); |
c98d5d94 LB |
3345 | |
3346 | cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology)); | |
b2c95d90 JT |
3347 | if (cpus == NULL) |
3348 | err(1, "calloc cpus"); | |
c98d5d94 LB |
3349 | |
3350 | /* | |
3351 | * Allocate and initialize cpu_present_set | |
3352 | */ | |
3353 | cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1)); | |
b2c95d90 JT |
3354 | if (cpu_present_set == NULL) |
3355 | err(3, "CPU_ALLOC"); | |
c98d5d94 LB |
3356 | cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); |
3357 | CPU_ZERO_S(cpu_present_setsize, cpu_present_set); | |
3358 | for_all_proc_cpus(mark_cpu_present); | |
3359 | ||
3360 | /* | |
3361 | * Allocate and initialize cpu_affinity_set | |
3362 | */ | |
3363 | cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1)); | |
b2c95d90 JT |
3364 | if (cpu_affinity_set == NULL) |
3365 | err(3, "CPU_ALLOC"); | |
c98d5d94 LB |
3366 | cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1)); |
3367 | CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set); | |
3368 | ||
3369 | ||
3370 | /* | |
3371 | * For online cpus | |
3372 | * find max_core_id, max_package_id | |
3373 | */ | |
3374 | for (i = 0; i <= topo.max_cpu_num; ++i) { | |
3375 | int siblings; | |
3376 | ||
3377 | if (cpu_is_not_present(i)) { | |
d8af6f5f | 3378 | if (debug > 1) |
b7d8c148 | 3379 | fprintf(outf, "cpu%d NOT PRESENT\n", i); |
c98d5d94 LB |
3380 | continue; |
3381 | } | |
3382 | cpus[i].core_id = get_core_id(i); | |
3383 | if (cpus[i].core_id > max_core_id) | |
3384 | max_core_id = cpus[i].core_id; | |
3385 | ||
3386 | cpus[i].physical_package_id = get_physical_package_id(i); | |
3387 | if (cpus[i].physical_package_id > max_package_id) | |
3388 | max_package_id = cpus[i].physical_package_id; | |
3389 | ||
3390 | siblings = get_num_ht_siblings(i); | |
3391 | if (siblings > max_siblings) | |
3392 | max_siblings = siblings; | |
d8af6f5f | 3393 | if (debug > 1) |
b7d8c148 | 3394 | fprintf(outf, "cpu %d pkg %d core %d\n", |
c98d5d94 LB |
3395 | i, cpus[i].physical_package_id, cpus[i].core_id); |
3396 | } | |
3397 | topo.num_cores_per_pkg = max_core_id + 1; | |
d8af6f5f | 3398 | if (debug > 1) |
b7d8c148 | 3399 | fprintf(outf, "max_core_id %d, sizing for %d cores per package\n", |
c98d5d94 | 3400 | max_core_id, topo.num_cores_per_pkg); |
1cc21f7b | 3401 | if (debug && !summary_only && topo.num_cores_per_pkg > 1) |
c98d5d94 LB |
3402 | show_core = 1; |
3403 | ||
3404 | topo.num_packages = max_package_id + 1; | |
d8af6f5f | 3405 | if (debug > 1) |
b7d8c148 | 3406 | fprintf(outf, "max_package_id %d, sizing for %d packages\n", |
c98d5d94 | 3407 | max_package_id, topo.num_packages); |
1cc21f7b | 3408 | if (debug && !summary_only && topo.num_packages > 1) |
c98d5d94 LB |
3409 | show_pkg = 1; |
3410 | ||
3411 | topo.num_threads_per_core = max_siblings; | |
d8af6f5f | 3412 | if (debug > 1) |
b7d8c148 | 3413 | fprintf(outf, "max_siblings %d\n", max_siblings); |
c98d5d94 LB |
3414 | |
3415 | free(cpus); | |
3416 | } | |
3417 | ||
3418 | void | |
3419 | allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p) | |
3420 | { | |
3421 | int i; | |
3422 | ||
3423 | *t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg * | |
3424 | topo.num_packages, sizeof(struct thread_data)); | |
3425 | if (*t == NULL) | |
3426 | goto error; | |
3427 | ||
3428 | for (i = 0; i < topo.num_threads_per_core * | |
3429 | topo.num_cores_per_pkg * topo.num_packages; i++) | |
3430 | (*t)[i].cpu_id = -1; | |
3431 | ||
3432 | *c = calloc(topo.num_cores_per_pkg * topo.num_packages, | |
3433 | sizeof(struct core_data)); | |
3434 | if (*c == NULL) | |
3435 | goto error; | |
3436 | ||
3437 | for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++) | |
3438 | (*c)[i].core_id = -1; | |
3439 | ||
3440 | *p = calloc(topo.num_packages, sizeof(struct pkg_data)); | |
3441 | if (*p == NULL) | |
3442 | goto error; | |
3443 | ||
3444 | for (i = 0; i < topo.num_packages; i++) | |
3445 | (*p)[i].package_id = i; | |
3446 | ||
3447 | return; | |
3448 | error: | |
b2c95d90 | 3449 | err(1, "calloc counters"); |
c98d5d94 LB |
3450 | } |
3451 | /* | |
3452 | * init_counter() | |
3453 | * | |
3454 | * set cpu_id, core_num, pkg_num | |
3455 | * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE | |
3456 | * | |
3457 | * increment topo.num_cores when 1st core in pkg seen | |
3458 | */ | |
3459 | void init_counter(struct thread_data *thread_base, struct core_data *core_base, | |
3460 | struct pkg_data *pkg_base, int thread_num, int core_num, | |
3461 | int pkg_num, int cpu_id) | |
3462 | { | |
3463 | struct thread_data *t; | |
3464 | struct core_data *c; | |
3465 | struct pkg_data *p; | |
3466 | ||
3467 | t = GET_THREAD(thread_base, thread_num, core_num, pkg_num); | |
3468 | c = GET_CORE(core_base, core_num, pkg_num); | |
3469 | p = GET_PKG(pkg_base, pkg_num); | |
3470 | ||
3471 | t->cpu_id = cpu_id; | |
3472 | if (thread_num == 0) { | |
3473 | t->flags |= CPU_IS_FIRST_THREAD_IN_CORE; | |
3474 | if (cpu_is_first_core_in_package(cpu_id)) | |
3475 | t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE; | |
3476 | } | |
3477 | ||
3478 | c->core_id = core_num; | |
3479 | p->package_id = pkg_num; | |
3480 | } | |
3481 | ||
3482 | ||
3483 | int initialize_counters(int cpu_id) | |
3484 | { | |
3485 | int my_thread_id, my_core_id, my_package_id; | |
3486 | ||
3487 | my_package_id = get_physical_package_id(cpu_id); | |
3488 | my_core_id = get_core_id(cpu_id); | |
e275b388 DC |
3489 | my_thread_id = get_cpu_position_in_core(cpu_id); |
3490 | if (!my_thread_id) | |
c98d5d94 | 3491 | topo.num_cores++; |
c98d5d94 LB |
3492 | |
3493 | init_counter(EVEN_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); | |
3494 | init_counter(ODD_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id); | |
3495 | return 0; | |
3496 | } | |
3497 | ||
3498 | void allocate_output_buffer() | |
3499 | { | |
3b4d5c7f | 3500 | output_buffer = calloc(1, (1 + topo.num_cpus) * 1024); |
c98d5d94 | 3501 | outp = output_buffer; |
b2c95d90 JT |
3502 | if (outp == NULL) |
3503 | err(-1, "calloc output buffer"); | |
c98d5d94 | 3504 | } |
36229897 LB |
3505 | void allocate_fd_percpu(void) |
3506 | { | |
3507 | fd_percpu = calloc(topo.max_cpu_num, sizeof(int)); | |
3508 | if (fd_percpu == NULL) | |
3509 | err(-1, "calloc fd_percpu"); | |
3510 | } | |
562a2d37 LB |
3511 | void allocate_irq_buffers(void) |
3512 | { | |
3513 | irq_column_2_cpu = calloc(topo.num_cpus, sizeof(int)); | |
3514 | if (irq_column_2_cpu == NULL) | |
3515 | err(-1, "calloc %d", topo.num_cpus); | |
c98d5d94 | 3516 | |
562a2d37 LB |
3517 | irqs_per_cpu = calloc(topo.max_cpu_num, sizeof(int)); |
3518 | if (irqs_per_cpu == NULL) | |
3519 | err(-1, "calloc %d", topo.max_cpu_num); | |
3520 | } | |
c98d5d94 LB |
3521 | void setup_all_buffers(void) |
3522 | { | |
3523 | topology_probe(); | |
562a2d37 | 3524 | allocate_irq_buffers(); |
36229897 | 3525 | allocate_fd_percpu(); |
c98d5d94 LB |
3526 | allocate_counters(&thread_even, &core_even, &package_even); |
3527 | allocate_counters(&thread_odd, &core_odd, &package_odd); | |
3528 | allocate_output_buffer(); | |
3529 | for_all_proc_cpus(initialize_counters); | |
3530 | } | |
3b4d5c7f | 3531 | |
7ce7d5de PB |
3532 | void set_base_cpu(void) |
3533 | { | |
3534 | base_cpu = sched_getcpu(); | |
3535 | if (base_cpu < 0) | |
3536 | err(-ENODEV, "No valid cpus found"); | |
3537 | ||
3538 | if (debug > 1) | |
b7d8c148 | 3539 | fprintf(outf, "base_cpu = %d\n", base_cpu); |
7ce7d5de PB |
3540 | } |
3541 | ||
103a8fea LB |
3542 | void turbostat_init() |
3543 | { | |
7ce7d5de PB |
3544 | setup_all_buffers(); |
3545 | set_base_cpu(); | |
103a8fea | 3546 | check_dev_msr(); |
98481e79 | 3547 | check_permissions(); |
fcd17211 | 3548 | process_cpuid(); |
103a8fea | 3549 | |
103a8fea | 3550 | |
7f5c258e LB |
3551 | if (debug) |
3552 | for_all_cpus(print_hwp, ODD_COUNTERS); | |
3553 | ||
d8af6f5f | 3554 | if (debug) |
889facbe LB |
3555 | for_all_cpus(print_epb, ODD_COUNTERS); |
3556 | ||
d8af6f5f | 3557 | if (debug) |
3a9a941d LB |
3558 | for_all_cpus(print_perf_limit, ODD_COUNTERS); |
3559 | ||
d8af6f5f | 3560 | if (debug) |
889facbe LB |
3561 | for_all_cpus(print_rapl, ODD_COUNTERS); |
3562 | ||
3563 | for_all_cpus(set_temperature_target, ODD_COUNTERS); | |
3564 | ||
d8af6f5f | 3565 | if (debug) |
889facbe | 3566 | for_all_cpus(print_thermal, ODD_COUNTERS); |
103a8fea LB |
3567 | } |
3568 | ||
3569 | int fork_it(char **argv) | |
3570 | { | |
103a8fea | 3571 | pid_t child_pid; |
d91bb17c | 3572 | int status; |
d15cf7c1 | 3573 | |
d91bb17c LB |
3574 | status = for_all_cpus(get_counters, EVEN_COUNTERS); |
3575 | if (status) | |
3576 | exit(status); | |
c98d5d94 LB |
3577 | /* clear affinity side-effect of get_counters() */ |
3578 | sched_setaffinity(0, cpu_present_setsize, cpu_present_set); | |
103a8fea LB |
3579 | gettimeofday(&tv_even, (struct timezone *)NULL); |
3580 | ||
3581 | child_pid = fork(); | |
3582 | if (!child_pid) { | |
3583 | /* child */ | |
3584 | execvp(argv[0], argv); | |
3585 | } else { | |
103a8fea LB |
3586 | |
3587 | /* parent */ | |
b2c95d90 JT |
3588 | if (child_pid == -1) |
3589 | err(1, "fork"); | |
103a8fea LB |
3590 | |
3591 | signal(SIGINT, SIG_IGN); | |
3592 | signal(SIGQUIT, SIG_IGN); | |
b2c95d90 JT |
3593 | if (waitpid(child_pid, &status, 0) == -1) |
3594 | err(status, "waitpid"); | |
103a8fea | 3595 | } |
c98d5d94 LB |
3596 | /* |
3597 | * n.b. fork_it() does not check for errors from for_all_cpus() | |
3598 | * because re-starting is problematic when forking | |
3599 | */ | |
3600 | for_all_cpus(get_counters, ODD_COUNTERS); | |
103a8fea | 3601 | gettimeofday(&tv_odd, (struct timezone *)NULL); |
103a8fea | 3602 | timersub(&tv_odd, &tv_even, &tv_delta); |
c98d5d94 LB |
3603 | for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS); |
3604 | compute_average(EVEN_COUNTERS); | |
3605 | format_all_counters(EVEN_COUNTERS); | |
103a8fea | 3606 | |
b7d8c148 LB |
3607 | fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0); |
3608 | ||
3609 | flush_output_stderr(); | |
103a8fea | 3610 | |
d91bb17c | 3611 | return status; |
103a8fea LB |
3612 | } |
3613 | ||
3b4d5c7f AS |
3614 | int get_and_dump_counters(void) |
3615 | { | |
3616 | int status; | |
3617 | ||
3618 | status = for_all_cpus(get_counters, ODD_COUNTERS); | |
3619 | if (status) | |
3620 | return status; | |
3621 | ||
3622 | status = for_all_cpus(dump_counters, ODD_COUNTERS); | |
3623 | if (status) | |
3624 | return status; | |
3625 | ||
b7d8c148 | 3626 | flush_output_stdout(); |
3b4d5c7f AS |
3627 | |
3628 | return status; | |
3629 | } | |
3630 | ||
d8af6f5f | 3631 | void print_version() { |
0102b067 | 3632 | fprintf(outf, "turbostat version 4.11 27 Feb 2016" |
d8af6f5f LB |
3633 | " - Len Brown <lenb@kernel.org>\n"); |
3634 | } | |
3635 | ||
103a8fea LB |
3636 | void cmdline(int argc, char **argv) |
3637 | { | |
3638 | int opt; | |
d8af6f5f LB |
3639 | int option_index = 0; |
3640 | static struct option long_options[] = { | |
3641 | {"Counter", required_argument, 0, 'C'}, | |
3642 | {"counter", required_argument, 0, 'c'}, | |
3643 | {"Dump", no_argument, 0, 'D'}, | |
3644 | {"debug", no_argument, 0, 'd'}, | |
3645 | {"interval", required_argument, 0, 'i'}, | |
3646 | {"help", no_argument, 0, 'h'}, | |
3647 | {"Joules", no_argument, 0, 'J'}, | |
3648 | {"MSR", required_argument, 0, 'M'}, | |
3649 | {"msr", required_argument, 0, 'm'}, | |
b7d8c148 | 3650 | {"out", required_argument, 0, 'o'}, |
d8af6f5f LB |
3651 | {"Package", no_argument, 0, 'p'}, |
3652 | {"processor", no_argument, 0, 'p'}, | |
3653 | {"Summary", no_argument, 0, 'S'}, | |
3654 | {"TCC", required_argument, 0, 'T'}, | |
3655 | {"version", no_argument, 0, 'v' }, | |
3656 | {0, 0, 0, 0 } | |
3657 | }; | |
103a8fea LB |
3658 | |
3659 | progname = argv[0]; | |
3660 | ||
b7d8c148 | 3661 | while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:o:PpST:v", |
d8af6f5f | 3662 | long_options, &option_index)) != -1) { |
103a8fea | 3663 | switch (opt) { |
d8af6f5f LB |
3664 | case 'C': |
3665 | sscanf(optarg, "%x", &extra_delta_offset64); | |
c98d5d94 | 3666 | break; |
d8af6f5f LB |
3667 | case 'c': |
3668 | sscanf(optarg, "%x", &extra_delta_offset32); | |
c98d5d94 | 3669 | break; |
d8af6f5f | 3670 | case 'D': |
3b4d5c7f AS |
3671 | dump_only++; |
3672 | break; | |
d8af6f5f LB |
3673 | case 'd': |
3674 | debug++; | |
103a8fea | 3675 | break; |
d8af6f5f LB |
3676 | case 'h': |
3677 | default: | |
3678 | help(); | |
3679 | exit(1); | |
103a8fea | 3680 | case 'i': |
2a0609c0 LB |
3681 | { |
3682 | double interval = strtod(optarg, NULL); | |
3683 | ||
3684 | if (interval < 0.001) { | |
b7d8c148 | 3685 | fprintf(outf, "interval %f seconds is too small\n", |
2a0609c0 LB |
3686 | interval); |
3687 | exit(2); | |
3688 | } | |
3689 | ||
3690 | interval_ts.tv_sec = interval; | |
3691 | interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000; | |
3692 | } | |
103a8fea | 3693 | break; |
d8af6f5f LB |
3694 | case 'J': |
3695 | rapl_joules++; | |
8e180f3c | 3696 | break; |
d8af6f5f LB |
3697 | case 'M': |
3698 | sscanf(optarg, "%x", &extra_msr_offset64); | |
8e180f3c | 3699 | break; |
2f32edf1 LB |
3700 | case 'm': |
3701 | sscanf(optarg, "%x", &extra_msr_offset32); | |
2f32edf1 | 3702 | break; |
b7d8c148 LB |
3703 | case 'o': |
3704 | outf = fopen_or_die(optarg, "w"); | |
3705 | break; | |
d8af6f5f LB |
3706 | case 'P': |
3707 | show_pkg_only++; | |
3708 | break; | |
3709 | case 'p': | |
3710 | show_core_only++; | |
103a8fea | 3711 | break; |
d8af6f5f LB |
3712 | case 'S': |
3713 | summary_only++; | |
889facbe LB |
3714 | break; |
3715 | case 'T': | |
3716 | tcc_activation_temp_override = atoi(optarg); | |
3717 | break; | |
d8af6f5f LB |
3718 | case 'v': |
3719 | print_version(); | |
3720 | exit(0); | |
5c56be9a | 3721 | break; |
103a8fea LB |
3722 | } |
3723 | } | |
3724 | } | |
3725 | ||
3726 | int main(int argc, char **argv) | |
3727 | { | |
b7d8c148 LB |
3728 | outf = stderr; |
3729 | ||
103a8fea LB |
3730 | cmdline(argc, argv); |
3731 | ||
d8af6f5f LB |
3732 | if (debug) |
3733 | print_version(); | |
103a8fea LB |
3734 | |
3735 | turbostat_init(); | |
3736 | ||
3b4d5c7f AS |
3737 | /* dump counters and exit */ |
3738 | if (dump_only) | |
3739 | return get_and_dump_counters(); | |
3740 | ||
103a8fea LB |
3741 | /* |
3742 | * if any params left, it must be a command to fork | |
3743 | */ | |
3744 | if (argc - optind) | |
3745 | return fork_it(argv + optind); | |
3746 | else | |
3747 | turbostat_loop(); | |
3748 | ||
3749 | return 0; | |
3750 | } |