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tools/power turbostat: add --out option for saving output in a file
[mirror_ubuntu-zesty-kernel.git] / tools / power / x86 / turbostat / turbostat.c
CommitLineData
103a8fea
LB		 1/*
2 * turbostat -- show CPU frequency and C-state residency
3 * on modern Intel turbo-capable processors.
4 *
144b44b1 5 * Copyright (c) 2013 Intel Corporation.
103a8fea
LB		 6 * Len Brown <len.brown@intel.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
88c3281f 22#define _GNU_SOURCE
b731f311 23#include MSRHEADER
95aebc44 24#include <stdarg.h>
103a8fea 25#include <stdio.h>
b2c95d90 26#include <err.h>
103a8fea
LB		 27#include <unistd.h>
28#include <sys/types.h>
29#include <sys/wait.h>
30#include <sys/stat.h>
31#include <sys/resource.h>
32#include <fcntl.h>
33#include <signal.h>
34#include <sys/time.h>
35#include <stdlib.h>
d8af6f5f 36#include <getopt.h>
103a8fea
LB		 37#include <dirent.h>
38#include <string.h>
39#include <ctype.h>
88c3281f 40#include <sched.h>
2a0609c0 41#include <time.h>
2b92865e 42#include <cpuid.h>
98481e79
LB		 43#include <linux/capability.h>
44#include <errno.h>
103a8fea 45
103a8fea 46char *proc_stat = "/proc/stat";
b7d8c148 47FILE *outf;
2a0609c0 48struct timespec interval_ts = {5, 0};
d8af6f5f
LB		 49unsigned int debug;
50unsigned int rapl_joules;
51unsigned int summary_only;
52unsigned int dump_only;
103a8fea
LB		 53unsigned int skip_c0;
54unsigned int skip_c1;
55unsigned int do_nhm_cstates;
56unsigned int do_snb_cstates;
fb5d4327 57unsigned int do_knl_cstates;
ee7e38e3
LB		 58unsigned int do_pc2;
59unsigned int do_pc3;
60unsigned int do_pc6;
61unsigned int do_pc7;
ca58710f 62unsigned int do_c8_c9_c10;
0b2bb692 63unsigned int do_skl_residency;
144b44b1
LB		 64unsigned int do_slm_cstates;
65unsigned int use_c1_residency_msr;
103a8fea 66unsigned int has_aperf;
889facbe 67unsigned int has_epb;
fc04cc67 68unsigned int units = 1000000; /* MHz etc */
103a8fea
LB		 69unsigned int genuine_intel;
70unsigned int has_invariant_tsc;
d7899447 71unsigned int do_nhm_platform_info;
2f32edf1
LB		 72unsigned int extra_msr_offset32;
73unsigned int extra_msr_offset64;
8e180f3c
LB		 74unsigned int extra_delta_offset32;
75unsigned int extra_delta_offset64;
b2b34dfe 76unsigned int aperf_mperf_multiplier = 1;
1ed51011 77int do_smi;
103a8fea 78double bclk;
a2b7b749 79double base_hz;
21ed5574 80unsigned int has_base_hz;
a2b7b749 81double tsc_tweak = 1.0;
103a8fea
LB		 82unsigned int show_pkg;
83unsigned int show_core;
84unsigned int show_cpu;
c98d5d94
LB		 85unsigned int show_pkg_only;
86unsigned int show_core_only;
87char *output_buffer, *outp;
889facbe
LB		 88unsigned int do_rapl;
89unsigned int do_dts;
90unsigned int do_ptm;
91unsigned int tcc_activation_temp;
92unsigned int tcc_activation_temp_override;
40ee8e3b
AS		 93double rapl_power_units, rapl_time_units;
94double rapl_dram_energy_units, rapl_energy_units;
889facbe 95double rapl_joule_counter_range;
3a9a941d
LB		 96unsigned int do_core_perf_limit_reasons;
97unsigned int do_gfx_perf_limit_reasons;
98unsigned int do_ring_perf_limit_reasons;
8a5bdf41
LB		 99unsigned int crystal_hz;
100unsigned long long tsc_hz;
7ce7d5de 101int base_cpu;
21ed5574 102double discover_bclk(unsigned int family, unsigned int model);
7f5c258e
LB		 103unsigned int has_hwp; /* IA32_PM_ENABLE, IA32_HWP_CAPABILITIES */
104 /* IA32_HWP_REQUEST, IA32_HWP_STATUS */
105unsigned int has_hwp_notify; /* IA32_HWP_INTERRUPT */
106unsigned int has_hwp_activity_window; /* IA32_HWP_REQUEST[bits 41:32] */
107unsigned int has_hwp_epp; /* IA32_HWP_REQUEST[bits 31:24] */
108unsigned int has_hwp_pkg; /* IA32_HWP_REQUEST_PKG */
889facbe 109
e6f9bb3c
LB		 110#define RAPL_PKG (1 << 0)
111 /* 0x610 MSR_PKG_POWER_LIMIT */
112 /* 0x611 MSR_PKG_ENERGY_STATUS */
113#define RAPL_PKG_PERF_STATUS (1 << 1)
114 /* 0x613 MSR_PKG_PERF_STATUS */
115#define RAPL_PKG_POWER_INFO (1 << 2)
116 /* 0x614 MSR_PKG_POWER_INFO */
117
118#define RAPL_DRAM (1 << 3)
119 /* 0x618 MSR_DRAM_POWER_LIMIT */
120 /* 0x619 MSR_DRAM_ENERGY_STATUS */
e6f9bb3c
LB		 121#define RAPL_DRAM_PERF_STATUS (1 << 4)
122 /* 0x61b MSR_DRAM_PERF_STATUS */
0b2bb692
LB		 123#define RAPL_DRAM_POWER_INFO (1 << 5)
124 /* 0x61c MSR_DRAM_POWER_INFO */
e6f9bb3c 125
0b2bb692 126#define RAPL_CORES (1 << 6)
e6f9bb3c
LB		 127 /* 0x638 MSR_PP0_POWER_LIMIT */
128 /* 0x639 MSR_PP0_ENERGY_STATUS */
0b2bb692 129#define RAPL_CORE_POLICY (1 << 7)
e6f9bb3c
LB		 130 /* 0x63a MSR_PP0_POLICY */
131
0b2bb692 132#define RAPL_GFX (1 << 8)
e6f9bb3c
LB		 133 /* 0x640 MSR_PP1_POWER_LIMIT */
134 /* 0x641 MSR_PP1_ENERGY_STATUS */
135 /* 0x642 MSR_PP1_POLICY */
889facbe
LB		 136#define TJMAX_DEFAULT 100
137
138#define MAX(a, b) ((a) > (b) ? (a) : (b))
103a8fea
LB		 139
140int aperf_mperf_unstable;
141int backwards_count;
142char *progname;
103a8fea 143
c98d5d94
LB		 144cpu_set_t *cpu_present_set, *cpu_affinity_set;
145size_t cpu_present_setsize, cpu_affinity_setsize;
146
147struct thread_data {
148 unsigned long long tsc;
149 unsigned long long aperf;
150 unsigned long long mperf;
144b44b1 151 unsigned long long c1;
2f32edf1 152 unsigned long long extra_msr64;
8e180f3c
LB		 153 unsigned long long extra_delta64;
154 unsigned long long extra_msr32;
155 unsigned long long extra_delta32;
1ed51011 156 unsigned int smi_count;
c98d5d94
LB		 157 unsigned int cpu_id;
158 unsigned int flags;
159#define CPU_IS_FIRST_THREAD_IN_CORE 0x2
160#define CPU_IS_FIRST_CORE_IN_PACKAGE 0x4
161} *thread_even, *thread_odd;
162
163struct core_data {
164 unsigned long long c3;
165 unsigned long long c6;
166 unsigned long long c7;
889facbe 167 unsigned int core_temp_c;
c98d5d94
LB		 168 unsigned int core_id;
169} *core_even, *core_odd;
170
171struct pkg_data {
172 unsigned long long pc2;
173 unsigned long long pc3;
174 unsigned long long pc6;
175 unsigned long long pc7;
ca58710f
KCA		 176 unsigned long long pc8;
177 unsigned long long pc9;
178 unsigned long long pc10;
0b2bb692
LB		 179 unsigned long long pkg_wtd_core_c0;
180 unsigned long long pkg_any_core_c0;
181 unsigned long long pkg_any_gfxe_c0;
182 unsigned long long pkg_both_core_gfxe_c0;
c98d5d94 183 unsigned int package_id;
889facbe
LB		 184 unsigned int energy_pkg; /* MSR_PKG_ENERGY_STATUS */
185 unsigned int energy_dram; /* MSR_DRAM_ENERGY_STATUS */
186 unsigned int energy_cores; /* MSR_PP0_ENERGY_STATUS */
187 unsigned int energy_gfx; /* MSR_PP1_ENERGY_STATUS */
188 unsigned int rapl_pkg_perf_status; /* MSR_PKG_PERF_STATUS */
189 unsigned int rapl_dram_perf_status; /* MSR_DRAM_PERF_STATUS */
190 unsigned int pkg_temp_c;
191
c98d5d94
LB		 192} *package_even, *package_odd;
193
194#define ODD_COUNTERS thread_odd, core_odd, package_odd
195#define EVEN_COUNTERS thread_even, core_even, package_even
196
197#define GET_THREAD(thread_base, thread_no, core_no, pkg_no) \
198 (thread_base + (pkg_no) * topo.num_cores_per_pkg * \
199 topo.num_threads_per_core + \
200 (core_no) * topo.num_threads_per_core + (thread_no))
201#define GET_CORE(core_base, core_no, pkg_no) \
202 (core_base + (pkg_no) * topo.num_cores_per_pkg + (core_no))
203#define GET_PKG(pkg_base, pkg_no) (pkg_base + pkg_no)
204
205struct system_summary {
206 struct thread_data threads;
207 struct core_data cores;
208 struct pkg_data packages;
209} sum, average;
210
211
212struct topo_params {
213 int num_packages;
214 int num_cpus;
215 int num_cores;
216 int max_cpu_num;
217 int num_cores_per_pkg;
218 int num_threads_per_core;
219} topo;
220
221struct timeval tv_even, tv_odd, tv_delta;
222
223void setup_all_buffers(void);
224
225int cpu_is_not_present(int cpu)
d15cf7c1 226{
c98d5d94 227 return !CPU_ISSET_S(cpu, cpu_present_setsize, cpu_present_set);
d15cf7c1 228}
88c3281f 229/*
c98d5d94
LB		 230 * run func(thread, core, package) in topology order
231 * skip non-present cpus
88c3281f 232 */
c98d5d94
LB		 233
234int for_all_cpus(int (func)(struct thread_data *, struct core_data *, struct pkg_data *),
235 struct thread_data *thread_base, struct core_data *core_base, struct pkg_data *pkg_base)
88c3281f 236{
c98d5d94 237 int retval, pkg_no, core_no, thread_no;
d15cf7c1 238
c98d5d94
LB		 239 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
240 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) {
241 for (thread_no = 0; thread_no <
242 topo.num_threads_per_core; ++thread_no) {
243 struct thread_data *t;
244 struct core_data *c;
245 struct pkg_data *p;
88c3281f 246
c98d5d94
LB		 247 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no);
248
249 if (cpu_is_not_present(t->cpu_id))
250 continue;
251
252 c = GET_CORE(core_base, core_no, pkg_no);
253 p = GET_PKG(pkg_base, pkg_no);
254
255 retval = func(t, c, p);
256 if (retval)
257 return retval;
258 }
259 }
260 }
261 return 0;
88c3281f
LB		 262}
263
264int cpu_migrate(int cpu)
265{
c98d5d94
LB		 266 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
267 CPU_SET_S(cpu, cpu_affinity_setsize, cpu_affinity_set);
268 if (sched_setaffinity(0, cpu_affinity_setsize, cpu_affinity_set) == -1)
88c3281f
LB		 269 return -1;
270 else
271 return 0;
272}
273
15aaa346 274int get_msr(int cpu, off_t offset, unsigned long long *msr)
103a8fea
LB		 275{
276 ssize_t retval;
103a8fea
LB		 277 char pathname[32];
278 int fd;
279
280 sprintf(pathname, "/dev/cpu/%d/msr", cpu);
281 fd = open(pathname, O_RDONLY);
15aaa346 282 if (fd < 0)
98481e79 283 err(-1, "%s open failed, try chown or chmod +r /dev/cpu/*/msr, or run as root", pathname);
103a8fea 284
15aaa346 285 retval = pread(fd, msr, sizeof *msr, offset);
103a8fea 286 close(fd);
15aaa346 287
98481e79
LB		 288 if (retval != sizeof *msr)
289 err(-1, "%s offset 0x%llx read failed", pathname, (unsigned long long)offset);
15aaa346
LB		 290
291 return 0;
103a8fea
LB		 292}
293
fc04cc67
LB		 294/*
295 * Example Format w/ field column widths:
296 *
75d2e44e 297 * Package Core CPU Avg_MHz Bzy_MHz TSC_MHz SMI Busy% CPU_%c1 CPU_%c3 CPU_%c6 CPU_%c7 CoreTmp PkgTmp Pkg%pc2 Pkg%pc3 Pkg%pc6 Pkg%pc7 PkgWatt CorWatt GFXWatt
e7c95ff3 298 * 123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678123456781234567812345678
fc04cc67
LB		 299 */
300
a829eb4d 301void print_header(void)
103a8fea
LB		 302{
303 if (show_pkg)
e7c95ff3 304 outp += sprintf(outp, " Package");
103a8fea 305 if (show_core)
e7c95ff3 306 outp += sprintf(outp, " Core");
103a8fea 307 if (show_cpu)
e7c95ff3 308 outp += sprintf(outp, " CPU");
fc04cc67 309 if (has_aperf)
e7c95ff3 310 outp += sprintf(outp, " Avg_MHz");
d7899447 311 if (has_aperf)
75d2e44e 312 outp += sprintf(outp, " Busy%%");
103a8fea 313 if (has_aperf)
e7c95ff3
LB		 314 outp += sprintf(outp, " Bzy_MHz");
315 outp += sprintf(outp, " TSC_MHz");
1cc21f7b 316
8e180f3c 317 if (extra_delta_offset32)
e7c95ff3 318 outp += sprintf(outp, " count 0x%03X", extra_delta_offset32);
8e180f3c 319 if (extra_delta_offset64)
e7c95ff3 320 outp += sprintf(outp, " COUNT 0x%03X", extra_delta_offset64);
2f32edf1 321 if (extra_msr_offset32)
e7c95ff3 322 outp += sprintf(outp, " MSR 0x%03X", extra_msr_offset32);
2f32edf1 323 if (extra_msr_offset64)
e7c95ff3 324 outp += sprintf(outp, " MSR 0x%03X", extra_msr_offset64);
1cc21f7b
LB		 325
326 if (!debug)
327 goto done;
328
329 if (do_smi)
330 outp += sprintf(outp, " SMI");
331
103a8fea 332 if (do_nhm_cstates)
e7c95ff3 333 outp += sprintf(outp, " CPU%%c1");
fb5d4327 334 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates)
e7c95ff3 335 outp += sprintf(outp, " CPU%%c3");
103a8fea 336 if (do_nhm_cstates)
e7c95ff3 337 outp += sprintf(outp, " CPU%%c6");
103a8fea 338 if (do_snb_cstates)
e7c95ff3 339 outp += sprintf(outp, " CPU%%c7");
889facbe
LB		 340
341 if (do_dts)
e7c95ff3 342 outp += sprintf(outp, " CoreTmp");
889facbe 343 if (do_ptm)
e7c95ff3 344 outp += sprintf(outp, " PkgTmp");
889facbe 345
0b2bb692
LB		 346 if (do_skl_residency) {
347 outp += sprintf(outp, " Totl%%C0");
348 outp += sprintf(outp, " Any%%C0");
349 outp += sprintf(outp, " GFX%%C0");
350 outp += sprintf(outp, " CPUGFX%%");
351 }
352
ee7e38e3 353 if (do_pc2)
e7c95ff3 354 outp += sprintf(outp, " Pkg%%pc2");
ee7e38e3 355 if (do_pc3)
e7c95ff3 356 outp += sprintf(outp, " Pkg%%pc3");
ee7e38e3 357 if (do_pc6)
e7c95ff3 358 outp += sprintf(outp, " Pkg%%pc6");
ee7e38e3 359 if (do_pc7)
e7c95ff3 360 outp += sprintf(outp, " Pkg%%pc7");
ca58710f 361 if (do_c8_c9_c10) {
e7c95ff3
LB		 362 outp += sprintf(outp, " Pkg%%pc8");
363 outp += sprintf(outp, " Pkg%%pc9");
364 outp += sprintf(outp, " Pk%%pc10");
ca58710f 365 }
103a8fea 366
5c56be9a
DB		 367 if (do_rapl && !rapl_joules) {
368 if (do_rapl & RAPL_PKG)
e7c95ff3 369 outp += sprintf(outp, " PkgWatt");
5c56be9a 370 if (do_rapl & RAPL_CORES)
e7c95ff3 371 outp += sprintf(outp, " CorWatt");
5c56be9a 372 if (do_rapl & RAPL_GFX)
e7c95ff3 373 outp += sprintf(outp, " GFXWatt");
5c56be9a 374 if (do_rapl & RAPL_DRAM)
e7c95ff3 375 outp += sprintf(outp, " RAMWatt");
5c56be9a 376 if (do_rapl & RAPL_PKG_PERF_STATUS)
e7c95ff3 377 outp += sprintf(outp, " PKG_%%");
5c56be9a 378 if (do_rapl & RAPL_DRAM_PERF_STATUS)
e7c95ff3 379 outp += sprintf(outp, " RAM_%%");
d7899447 380 } else if (do_rapl && rapl_joules) {
5c56be9a 381 if (do_rapl & RAPL_PKG)
e7c95ff3 382 outp += sprintf(outp, " Pkg_J");
5c56be9a 383 if (do_rapl & RAPL_CORES)
e7c95ff3 384 outp += sprintf(outp, " Cor_J");
5c56be9a 385 if (do_rapl & RAPL_GFX)
e7c95ff3 386 outp += sprintf(outp, " GFX_J");
5c56be9a 387 if (do_rapl & RAPL_DRAM)
bd6906ed 388 outp += sprintf(outp, " RAM_J");
5c56be9a 389 if (do_rapl & RAPL_PKG_PERF_STATUS)
e7c95ff3 390 outp += sprintf(outp, " PKG_%%");
5c56be9a 391 if (do_rapl & RAPL_DRAM_PERF_STATUS)
e7c95ff3
LB		 392 outp += sprintf(outp, " RAM_%%");
393 outp += sprintf(outp, " time");
889facbe 394
5c56be9a 395 }
1cc21f7b 396 done:
c98d5d94 397 outp += sprintf(outp, "\n");
103a8fea
LB		 398}
399
c98d5d94
LB		 400int dump_counters(struct thread_data *t, struct core_data *c,
401 struct pkg_data *p)
103a8fea 402{
3b4d5c7f 403 outp += sprintf(outp, "t %p, c %p, p %p\n", t, c, p);
c98d5d94
LB		 404
405 if (t) {
3b4d5c7f
AS		 406 outp += sprintf(outp, "CPU: %d flags 0x%x\n",
407 t->cpu_id, t->flags);
408 outp += sprintf(outp, "TSC: %016llX\n", t->tsc);
409 outp += sprintf(outp, "aperf: %016llX\n", t->aperf);
410 outp += sprintf(outp, "mperf: %016llX\n", t->mperf);
411 outp += sprintf(outp, "c1: %016llX\n", t->c1);
412 outp += sprintf(outp, "msr0x%x: %08llX\n",
8e180f3c 413 extra_delta_offset32, t->extra_delta32);
3b4d5c7f 414 outp += sprintf(outp, "msr0x%x: %016llX\n",
8e180f3c 415 extra_delta_offset64, t->extra_delta64);
3b4d5c7f 416 outp += sprintf(outp, "msr0x%x: %08llX\n",
2f32edf1 417 extra_msr_offset32, t->extra_msr32);
3b4d5c7f 418 outp += sprintf(outp, "msr0x%x: %016llX\n",
2f32edf1 419 extra_msr_offset64, t->extra_msr64);
1ed51011 420 if (do_smi)
3b4d5c7f 421 outp += sprintf(outp, "SMI: %08X\n", t->smi_count);
c98d5d94 422 }
103a8fea 423
c98d5d94 424 if (c) {
3b4d5c7f
AS		 425 outp += sprintf(outp, "core: %d\n", c->core_id);
426 outp += sprintf(outp, "c3: %016llX\n", c->c3);
427 outp += sprintf(outp, "c6: %016llX\n", c->c6);
428 outp += sprintf(outp, "c7: %016llX\n", c->c7);
429 outp += sprintf(outp, "DTS: %dC\n", c->core_temp_c);
c98d5d94 430 }
103a8fea 431
c98d5d94 432 if (p) {
3b4d5c7f 433 outp += sprintf(outp, "package: %d\n", p->package_id);
0b2bb692
LB		 434
435 outp += sprintf(outp, "Weighted cores: %016llX\n", p->pkg_wtd_core_c0);
436 outp += sprintf(outp, "Any cores: %016llX\n", p->pkg_any_core_c0);
437 outp += sprintf(outp, "Any GFX: %016llX\n", p->pkg_any_gfxe_c0);
438 outp += sprintf(outp, "CPU + GFX: %016llX\n", p->pkg_both_core_gfxe_c0);
439
3b4d5c7f 440 outp += sprintf(outp, "pc2: %016llX\n", p->pc2);
ee7e38e3
LB		 441 if (do_pc3)
442 outp += sprintf(outp, "pc3: %016llX\n", p->pc3);
443 if (do_pc6)
444 outp += sprintf(outp, "pc6: %016llX\n", p->pc6);
445 if (do_pc7)
446 outp += sprintf(outp, "pc7: %016llX\n", p->pc7);
3b4d5c7f
AS		 447 outp += sprintf(outp, "pc8: %016llX\n", p->pc8);
448 outp += sprintf(outp, "pc9: %016llX\n", p->pc9);
449 outp += sprintf(outp, "pc10: %016llX\n", p->pc10);
450 outp += sprintf(outp, "Joules PKG: %0X\n", p->energy_pkg);
451 outp += sprintf(outp, "Joules COR: %0X\n", p->energy_cores);
452 outp += sprintf(outp, "Joules GFX: %0X\n", p->energy_gfx);
453 outp += sprintf(outp, "Joules RAM: %0X\n", p->energy_dram);
454 outp += sprintf(outp, "Throttle PKG: %0X\n",
455 p->rapl_pkg_perf_status);
456 outp += sprintf(outp, "Throttle RAM: %0X\n",
457 p->rapl_dram_perf_status);
458 outp += sprintf(outp, "PTM: %dC\n", p->pkg_temp_c);
c98d5d94 459 }
3b4d5c7f
AS		 460
461 outp += sprintf(outp, "\n");
462
c98d5d94 463 return 0;
103a8fea
LB		 464}
465
e23da037
LB		 466/*
467 * column formatting convention & formats
e23da037 468 */
c98d5d94
LB		 469int format_counters(struct thread_data *t, struct core_data *c,
470 struct pkg_data *p)
103a8fea
LB		 471{
472 double interval_float;
fc04cc67 473 char *fmt8;
103a8fea 474
c98d5d94
LB		 475 /* if showing only 1st thread in core and this isn't one, bail out */
476 if (show_core_only && !(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
477 return 0;
478
479 /* if showing only 1st thread in pkg and this isn't one, bail out */
480 if (show_pkg_only && !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
481 return 0;
482
103a8fea
LB		 483 interval_float = tv_delta.tv_sec + tv_delta.tv_usec/1000000.0;
484
c98d5d94
LB		 485 /* topo columns, print blanks on 1st (average) line */
486 if (t == &average.threads) {
103a8fea 487 if (show_pkg)
fc04cc67 488 outp += sprintf(outp, " -");
103a8fea 489 if (show_core)
fc04cc67 490 outp += sprintf(outp, " -");
103a8fea 491 if (show_cpu)
fc04cc67 492 outp += sprintf(outp, " -");
103a8fea 493 } else {
c98d5d94
LB		 494 if (show_pkg) {
495 if (p)
fc04cc67 496 outp += sprintf(outp, "%8d", p->package_id);
c98d5d94 497 else
fc04cc67 498 outp += sprintf(outp, " -");
c98d5d94 499 }
c98d5d94
LB		 500 if (show_core) {
501 if (c)
fc04cc67 502 outp += sprintf(outp, "%8d", c->core_id);
c98d5d94 503 else
fc04cc67 504 outp += sprintf(outp, " -");
c98d5d94 505 }
103a8fea 506 if (show_cpu)
fc04cc67 507 outp += sprintf(outp, "%8d", t->cpu_id);
103a8fea 508 }
fc04cc67 509
d7899447 510 /* Avg_MHz */
fc04cc67
LB		 511 if (has_aperf)
512 outp += sprintf(outp, "%8.0f",
513 1.0 / units * t->aperf / interval_float);
514
75d2e44e 515 /* Busy% */
d7899447 516 if (has_aperf) {
103a8fea 517 if (!skip_c0)
a2b7b749 518 outp += sprintf(outp, "%8.2f", 100.0 * t->mperf/t->tsc/tsc_tweak);
103a8fea 519 else
fc04cc67 520 outp += sprintf(outp, "********");
103a8fea
LB		 521 }
522
d7899447 523 /* Bzy_MHz */
21ed5574
LB		 524 if (has_aperf) {
525 if (has_base_hz)
526 outp += sprintf(outp, "%8.0f", base_hz / units * t->aperf / t->mperf);
527 else
528 outp += sprintf(outp, "%8.0f",
529 1.0 * t->tsc / units * t->aperf / t->mperf / interval_float);
530 }
103a8fea 531
d7899447 532 /* TSC_MHz */
fc04cc67 533 outp += sprintf(outp, "%8.0f", 1.0 * t->tsc/units/interval_float);
103a8fea 534
8e180f3c
LB		 535 /* delta */
536 if (extra_delta_offset32)
537 outp += sprintf(outp, " %11llu", t->extra_delta32);
538
539 /* DELTA */
540 if (extra_delta_offset64)
541 outp += sprintf(outp, " %11llu", t->extra_delta64);
2f32edf1
LB		 542 /* msr */
543 if (extra_msr_offset32)
8e180f3c 544 outp += sprintf(outp, " 0x%08llx", t->extra_msr32);
2f32edf1 545
130ff304 546 /* MSR */
2f32edf1
LB		 547 if (extra_msr_offset64)
548 outp += sprintf(outp, " 0x%016llx", t->extra_msr64);
130ff304 549
1cc21f7b
LB		 550 if (!debug)
551 goto done;
552
553 /* SMI */
554 if (do_smi)
555 outp += sprintf(outp, "%8d", t->smi_count);
556
103a8fea
LB		 557 if (do_nhm_cstates) {
558 if (!skip_c1)
fc04cc67 559 outp += sprintf(outp, "%8.2f", 100.0 * t->c1/t->tsc);
103a8fea 560 else
fc04cc67 561 outp += sprintf(outp, "********");
103a8fea 562 }
c98d5d94
LB		 563
564 /* print per-core data only for 1st thread in core */
565 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
566 goto done;
567
fb5d4327 568 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates)
fc04cc67 569 outp += sprintf(outp, "%8.2f", 100.0 * c->c3/t->tsc);
103a8fea 570 if (do_nhm_cstates)
fc04cc67 571 outp += sprintf(outp, "%8.2f", 100.0 * c->c6/t->tsc);
103a8fea 572 if (do_snb_cstates)
fc04cc67 573 outp += sprintf(outp, "%8.2f", 100.0 * c->c7/t->tsc);
c98d5d94 574
889facbe 575 if (do_dts)
fc04cc67 576 outp += sprintf(outp, "%8d", c->core_temp_c);
889facbe 577
c98d5d94
LB		 578 /* print per-package data only for 1st core in package */
579 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
580 goto done;
581
0b2bb692 582 /* PkgTmp */
889facbe 583 if (do_ptm)
fc04cc67 584 outp += sprintf(outp, "%8d", p->pkg_temp_c);
889facbe 585
0b2bb692
LB		 586 /* Totl%C0, Any%C0 GFX%C0 CPUGFX% */
587 if (do_skl_residency) {
588 outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_wtd_core_c0/t->tsc);
589 outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_any_core_c0/t->tsc);
590 outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_any_gfxe_c0/t->tsc);
591 outp += sprintf(outp, "%8.2f", 100.0 * p->pkg_both_core_gfxe_c0/t->tsc);
592 }
593
ee7e38e3 594 if (do_pc2)
fc04cc67 595 outp += sprintf(outp, "%8.2f", 100.0 * p->pc2/t->tsc);
ee7e38e3 596 if (do_pc3)
fc04cc67 597 outp += sprintf(outp, "%8.2f", 100.0 * p->pc3/t->tsc);
ee7e38e3 598 if (do_pc6)
fc04cc67 599 outp += sprintf(outp, "%8.2f", 100.0 * p->pc6/t->tsc);
ee7e38e3 600 if (do_pc7)
fc04cc67 601 outp += sprintf(outp, "%8.2f", 100.0 * p->pc7/t->tsc);
ca58710f 602 if (do_c8_c9_c10) {
fc04cc67
LB		 603 outp += sprintf(outp, "%8.2f", 100.0 * p->pc8/t->tsc);
604 outp += sprintf(outp, "%8.2f", 100.0 * p->pc9/t->tsc);
605 outp += sprintf(outp, "%8.2f", 100.0 * p->pc10/t->tsc);
ca58710f 606 }
889facbe
LB		 607
608 /*
609 * If measurement interval exceeds minimum RAPL Joule Counter range,
610 * indicate that results are suspect by printing "**" in fraction place.
611 */
fc04cc67
LB		 612 if (interval_float < rapl_joule_counter_range)
613 fmt8 = "%8.2f";
614 else
615 fmt8 = " %6.0f**";
889facbe 616
5c56be9a
DB		 617 if (do_rapl && !rapl_joules) {
618 if (do_rapl & RAPL_PKG)
fc04cc67 619 outp += sprintf(outp, fmt8, p->energy_pkg * rapl_energy_units / interval_float);
5c56be9a 620 if (do_rapl & RAPL_CORES)
fc04cc67 621 outp += sprintf(outp, fmt8, p->energy_cores * rapl_energy_units / interval_float);
5c56be9a 622 if (do_rapl & RAPL_GFX)
fc04cc67 623 outp += sprintf(outp, fmt8, p->energy_gfx * rapl_energy_units / interval_float);
5c56be9a 624 if (do_rapl & RAPL_DRAM)
40ee8e3b 625 outp += sprintf(outp, fmt8, p->energy_dram * rapl_dram_energy_units / interval_float);
5c56be9a 626 if (do_rapl & RAPL_PKG_PERF_STATUS)
fc04cc67 627 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
5c56be9a 628 if (do_rapl & RAPL_DRAM_PERF_STATUS)
fc04cc67 629 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
d7899447 630 } else if (do_rapl && rapl_joules) {
5c56be9a 631 if (do_rapl & RAPL_PKG)
fc04cc67 632 outp += sprintf(outp, fmt8,
5c56be9a
DB		 633 p->energy_pkg * rapl_energy_units);
634 if (do_rapl & RAPL_CORES)
fc04cc67 635 outp += sprintf(outp, fmt8,
5c56be9a
DB		 636 p->energy_cores * rapl_energy_units);
637 if (do_rapl & RAPL_GFX)
fc04cc67 638 outp += sprintf(outp, fmt8,
5c56be9a
DB		 639 p->energy_gfx * rapl_energy_units);
640 if (do_rapl & RAPL_DRAM)
fc04cc67 641 outp += sprintf(outp, fmt8,
40ee8e3b 642 p->energy_dram * rapl_dram_energy_units);
5c56be9a 643 if (do_rapl & RAPL_PKG_PERF_STATUS)
fc04cc67 644 outp += sprintf(outp, fmt8, 100.0 * p->rapl_pkg_perf_status * rapl_time_units / interval_float);
5c56be9a 645 if (do_rapl & RAPL_DRAM_PERF_STATUS)
fc04cc67 646 outp += sprintf(outp, fmt8, 100.0 * p->rapl_dram_perf_status * rapl_time_units / interval_float);
889facbe 647
d7899447 648 outp += sprintf(outp, fmt8, interval_float);
5c56be9a 649 }
c98d5d94 650done:
c98d5d94
LB		 651 outp += sprintf(outp, "\n");
652
653 return 0;
103a8fea
LB		 654}
655
b7d8c148 656void flush_output_stdout(void)
c98d5d94 657{
b7d8c148
LB		 658 FILE *filep;
659
660 if (outf == stderr)
661 filep = stdout;
662 else
663 filep = outf;
664
665 fputs(output_buffer, filep);
666 fflush(filep);
667
c98d5d94
LB		 668 outp = output_buffer;
669}
b7d8c148 670void flush_output_stderr(void)
c98d5d94 671{
b7d8c148
LB		 672 fputs(output_buffer, outf);
673 fflush(outf);
c98d5d94
LB		 674 outp = output_buffer;
675}
676void format_all_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
103a8fea 677{
e23da037 678 static int printed;
103a8fea 679
e23da037
LB		 680 if (!printed || !summary_only)
681 print_header();
103a8fea 682
c98d5d94
LB		 683 if (topo.num_cpus > 1)
684 format_counters(&average.threads, &average.cores,
685 &average.packages);
103a8fea 686
e23da037
LB		 687 printed = 1;
688
689 if (summary_only)
690 return;
691
c98d5d94 692 for_all_cpus(format_counters, t, c, p);
103a8fea
LB		 693}
694
889facbe
LB		 695#define DELTA_WRAP32(new, old) \
696 if (new > old) { \
697 old = new - old; \
698 } else { \
699 old = 0x100000000 + new - old; \
700 }
701
c98d5d94
LB		 702void
703delta_package(struct pkg_data *new, struct pkg_data *old)
704{
0b2bb692
LB		 705
706 if (do_skl_residency) {
707 old->pkg_wtd_core_c0 = new->pkg_wtd_core_c0 - old->pkg_wtd_core_c0;
708 old->pkg_any_core_c0 = new->pkg_any_core_c0 - old->pkg_any_core_c0;
709 old->pkg_any_gfxe_c0 = new->pkg_any_gfxe_c0 - old->pkg_any_gfxe_c0;
710 old->pkg_both_core_gfxe_c0 = new->pkg_both_core_gfxe_c0 - old->pkg_both_core_gfxe_c0;
711 }
c98d5d94 712 old->pc2 = new->pc2 - old->pc2;
ee7e38e3
LB		 713 if (do_pc3)
714 old->pc3 = new->pc3 - old->pc3;
715 if (do_pc6)
716 old->pc6 = new->pc6 - old->pc6;
717 if (do_pc7)
718 old->pc7 = new->pc7 - old->pc7;
ca58710f
KCA		 719 old->pc8 = new->pc8 - old->pc8;
720 old->pc9 = new->pc9 - old->pc9;
721 old->pc10 = new->pc10 - old->pc10;
889facbe
LB		 722 old->pkg_temp_c = new->pkg_temp_c;
723
724 DELTA_WRAP32(new->energy_pkg, old->energy_pkg);
725 DELTA_WRAP32(new->energy_cores, old->energy_cores);
726 DELTA_WRAP32(new->energy_gfx, old->energy_gfx);
727 DELTA_WRAP32(new->energy_dram, old->energy_dram);
728 DELTA_WRAP32(new->rapl_pkg_perf_status, old->rapl_pkg_perf_status);
729 DELTA_WRAP32(new->rapl_dram_perf_status, old->rapl_dram_perf_status);
c98d5d94 730}
103a8fea 731
c98d5d94
LB		 732void
733delta_core(struct core_data *new, struct core_data *old)
103a8fea 734{
c98d5d94
LB		 735 old->c3 = new->c3 - old->c3;
736 old->c6 = new->c6 - old->c6;
737 old->c7 = new->c7 - old->c7;
889facbe 738 old->core_temp_c = new->core_temp_c;
c98d5d94 739}
103a8fea 740
c3ae331d
LB		 741/*
742 * old = new - old
743 */
c98d5d94
LB		 744void
745delta_thread(struct thread_data *new, struct thread_data *old,
746 struct core_data *core_delta)
747{
748 old->tsc = new->tsc - old->tsc;
749
750 /* check for TSC < 1 Mcycles over interval */
b2c95d90
JT		 751 if (old->tsc < (1000 * 1000))
752 errx(-3, "Insanely slow TSC rate, TSC stops in idle?\n"
753 "You can disable all c-states by booting with \"idle=poll\"\n"
754 "or just the deep ones with \"processor.max_cstate=1\"");
103a8fea 755
c98d5d94 756 old->c1 = new->c1 - old->c1;
103a8fea 757
a729617c
LB		 758 if (has_aperf) {
759 if ((new->aperf > old->aperf) && (new->mperf > old->mperf)) {
760 old->aperf = new->aperf - old->aperf;
761 old->mperf = new->mperf - old->mperf;
762 } else {
103a8fea 763
a729617c 764 if (!aperf_mperf_unstable) {
b7d8c148
LB		 765 fprintf(outf, "%s: APERF or MPERF went backwards *\n", progname);
766 fprintf(outf, "* Frequency results do not cover entire interval *\n");
767 fprintf(outf, "* fix this by running Linux-2.6.30 or later *\n");
103a8fea 768
a729617c
LB		 769 aperf_mperf_unstable = 1;
770 }
771 /*
772 * mperf delta is likely a huge "positive" number
773 * can not use it for calculating c0 time
774 */
775 skip_c0 = 1;
776 skip_c1 = 1;
103a8fea 777 }
c98d5d94 778 }
103a8fea 779
103a8fea 780
144b44b1
LB		 781 if (use_c1_residency_msr) {
782 /*
783 * Some models have a dedicated C1 residency MSR,
784 * which should be more accurate than the derivation below.
785 */
786 } else {
787 /*
788 * As counter collection is not atomic,
789 * it is possible for mperf's non-halted cycles + idle states
790 * to exceed TSC's all cycles: show c1 = 0% in that case.
791 */
792 if ((old->mperf + core_delta->c3 + core_delta->c6 + core_delta->c7) > old->tsc)
793 old->c1 = 0;
794 else {
795 /* normal case, derive c1 */
796 old->c1 = old->tsc - old->mperf - core_delta->c3
c98d5d94 797 - core_delta->c6 - core_delta->c7;
144b44b1 798 }
c98d5d94 799 }
c3ae331d 800
c98d5d94 801 if (old->mperf == 0) {
b7d8c148
LB		 802 if (debug > 1)
803 fprintf(outf, "cpu%d MPERF 0!\n", old->cpu_id);
c98d5d94 804 old->mperf = 1; /* divide by 0 protection */
103a8fea 805 }
c98d5d94 806
8e180f3c
LB		 807 old->extra_delta32 = new->extra_delta32 - old->extra_delta32;
808 old->extra_delta32 &= 0xFFFFFFFF;
809
810 old->extra_delta64 = new->extra_delta64 - old->extra_delta64;
811
c98d5d94 812 /*
8e180f3c 813 * Extra MSR is just a snapshot, simply copy latest w/o subtracting
c98d5d94 814 */
2f32edf1
LB		 815 old->extra_msr32 = new->extra_msr32;
816 old->extra_msr64 = new->extra_msr64;
1ed51011
LB		 817
818 if (do_smi)
819 old->smi_count = new->smi_count - old->smi_count;
c98d5d94
LB		 820}
821
822int delta_cpu(struct thread_data *t, struct core_data *c,
823 struct pkg_data *p, struct thread_data *t2,
824 struct core_data *c2, struct pkg_data *p2)
825{
826 /* calculate core delta only for 1st thread in core */
827 if (t->flags & CPU_IS_FIRST_THREAD_IN_CORE)
828 delta_core(c, c2);
829
830 /* always calculate thread delta */
831 delta_thread(t, t2, c2); /* c2 is core delta */
832
833 /* calculate package delta only for 1st core in package */
834 if (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)
835 delta_package(p, p2);
836
103a8fea
LB		 837 return 0;
838}
839
c98d5d94
LB		 840void clear_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
841{
842 t->tsc = 0;
843 t->aperf = 0;
844 t->mperf = 0;
845 t->c1 = 0;
846
1ed51011 847 t->smi_count = 0;
8e180f3c
LB		 848 t->extra_delta32 = 0;
849 t->extra_delta64 = 0;
850
c98d5d94
LB		 851 /* tells format_counters to dump all fields from this set */
852 t->flags = CPU_IS_FIRST_THREAD_IN_CORE | CPU_IS_FIRST_CORE_IN_PACKAGE;
853
854 c->c3 = 0;
855 c->c6 = 0;
856 c->c7 = 0;
889facbe 857 c->core_temp_c = 0;
c98d5d94 858
0b2bb692
LB		 859 p->pkg_wtd_core_c0 = 0;
860 p->pkg_any_core_c0 = 0;
861 p->pkg_any_gfxe_c0 = 0;
862 p->pkg_both_core_gfxe_c0 = 0;
863
c98d5d94 864 p->pc2 = 0;
ee7e38e3
LB		 865 if (do_pc3)
866 p->pc3 = 0;
867 if (do_pc6)
868 p->pc6 = 0;
869 if (do_pc7)
870 p->pc7 = 0;
ca58710f
KCA		 871 p->pc8 = 0;
872 p->pc9 = 0;
873 p->pc10 = 0;
889facbe
LB		 874
875 p->energy_pkg = 0;
876 p->energy_dram = 0;
877 p->energy_cores = 0;
878 p->energy_gfx = 0;
879 p->rapl_pkg_perf_status = 0;
880 p->rapl_dram_perf_status = 0;
881 p->pkg_temp_c = 0;
c98d5d94
LB		 882}
883int sum_counters(struct thread_data *t, struct core_data *c,
884 struct pkg_data *p)
103a8fea 885{
c98d5d94
LB		 886 average.threads.tsc += t->tsc;
887 average.threads.aperf += t->aperf;
888 average.threads.mperf += t->mperf;
889 average.threads.c1 += t->c1;
103a8fea 890
8e180f3c
LB		 891 average.threads.extra_delta32 += t->extra_delta32;
892 average.threads.extra_delta64 += t->extra_delta64;
893
c98d5d94
LB		 894 /* sum per-core values only for 1st thread in core */
895 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
896 return 0;
103a8fea 897
c98d5d94
LB		 898 average.cores.c3 += c->c3;
899 average.cores.c6 += c->c6;
900 average.cores.c7 += c->c7;
901
889facbe
LB		 902 average.cores.core_temp_c = MAX(average.cores.core_temp_c, c->core_temp_c);
903
c98d5d94
LB		 904 /* sum per-pkg values only for 1st core in pkg */
905 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
906 return 0;
907
0b2bb692
LB		 908 if (do_skl_residency) {
909 average.packages.pkg_wtd_core_c0 += p->pkg_wtd_core_c0;
910 average.packages.pkg_any_core_c0 += p->pkg_any_core_c0;
911 average.packages.pkg_any_gfxe_c0 += p->pkg_any_gfxe_c0;
912 average.packages.pkg_both_core_gfxe_c0 += p->pkg_both_core_gfxe_c0;
913 }
914
c98d5d94 915 average.packages.pc2 += p->pc2;
ee7e38e3
LB		 916 if (do_pc3)
917 average.packages.pc3 += p->pc3;
918 if (do_pc6)
919 average.packages.pc6 += p->pc6;
920 if (do_pc7)
921 average.packages.pc7 += p->pc7;
ca58710f
KCA		 922 average.packages.pc8 += p->pc8;
923 average.packages.pc9 += p->pc9;
924 average.packages.pc10 += p->pc10;
c98d5d94 925
889facbe
LB		 926 average.packages.energy_pkg += p->energy_pkg;
927 average.packages.energy_dram += p->energy_dram;
928 average.packages.energy_cores += p->energy_cores;
929 average.packages.energy_gfx += p->energy_gfx;
930
931 average.packages.pkg_temp_c = MAX(average.packages.pkg_temp_c, p->pkg_temp_c);
932
933 average.packages.rapl_pkg_perf_status += p->rapl_pkg_perf_status;
934 average.packages.rapl_dram_perf_status += p->rapl_dram_perf_status;
c98d5d94
LB		 935 return 0;
936}
937/*
938 * sum the counters for all cpus in the system
939 * compute the weighted average
940 */
941void compute_average(struct thread_data *t, struct core_data *c,
942 struct pkg_data *p)
943{
944 clear_counters(&average.threads, &average.cores, &average.packages);
945
946 for_all_cpus(sum_counters, t, c, p);
947
948 average.threads.tsc /= topo.num_cpus;
949 average.threads.aperf /= topo.num_cpus;
950 average.threads.mperf /= topo.num_cpus;
951 average.threads.c1 /= topo.num_cpus;
952
8e180f3c
LB		 953 average.threads.extra_delta32 /= topo.num_cpus;
954 average.threads.extra_delta32 &= 0xFFFFFFFF;
955
956 average.threads.extra_delta64 /= topo.num_cpus;
957
c98d5d94
LB		 958 average.cores.c3 /= topo.num_cores;
959 average.cores.c6 /= topo.num_cores;
960 average.cores.c7 /= topo.num_cores;
961
0b2bb692
LB		 962 if (do_skl_residency) {
963 average.packages.pkg_wtd_core_c0 /= topo.num_packages;
964 average.packages.pkg_any_core_c0 /= topo.num_packages;
965 average.packages.pkg_any_gfxe_c0 /= topo.num_packages;
966 average.packages.pkg_both_core_gfxe_c0 /= topo.num_packages;
967 }
968
c98d5d94 969 average.packages.pc2 /= topo.num_packages;
ee7e38e3
LB		 970 if (do_pc3)
971 average.packages.pc3 /= topo.num_packages;
972 if (do_pc6)
973 average.packages.pc6 /= topo.num_packages;
974 if (do_pc7)
975 average.packages.pc7 /= topo.num_packages;
ca58710f
KCA		 976
977 average.packages.pc8 /= topo.num_packages;
978 average.packages.pc9 /= topo.num_packages;
979 average.packages.pc10 /= topo.num_packages;
103a8fea
LB		 980}
981
c98d5d94 982static unsigned long long rdtsc(void)
103a8fea 983{
c98d5d94 984 unsigned int low, high;
15aaa346 985
c98d5d94 986 asm volatile("rdtsc" : "=a" (low), "=d" (high));
15aaa346 987
c98d5d94
LB		 988 return low | ((unsigned long long)high) << 32;
989}
15aaa346 990
15aaa346 991
c98d5d94
LB		 992/*
993 * get_counters(...)
994 * migrate to cpu
995 * acquire and record local counters for that cpu
996 */
997int get_counters(struct thread_data *t, struct core_data *c, struct pkg_data *p)
998{
999 int cpu = t->cpu_id;
889facbe 1000 unsigned long long msr;
88c3281f 1001
e52966c0 1002 if (cpu_migrate(cpu)) {
b7d8c148 1003 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
c98d5d94 1004 return -1;
e52966c0 1005 }
15aaa346 1006
c98d5d94
LB		 1007 t->tsc = rdtsc(); /* we are running on local CPU of interest */
1008
1009 if (has_aperf) {
9c63a650 1010 if (get_msr(cpu, MSR_IA32_APERF, &t->aperf))
c98d5d94 1011 return -3;
9c63a650 1012 if (get_msr(cpu, MSR_IA32_MPERF, &t->mperf))
c98d5d94 1013 return -4;
b2b34dfe
HC		 1014 t->aperf = t->aperf * aperf_mperf_multiplier;
1015 t->mperf = t->mperf * aperf_mperf_multiplier;
c98d5d94
LB		 1016 }
1017
1ed51011
LB		 1018 if (do_smi) {
1019 if (get_msr(cpu, MSR_SMI_COUNT, &msr))
1020 return -5;
1021 t->smi_count = msr & 0xFFFFFFFF;
1022 }
8e180f3c 1023 if (extra_delta_offset32) {
889facbe 1024 if (get_msr(cpu, extra_delta_offset32, &msr))
8e180f3c 1025 return -5;
889facbe 1026 t->extra_delta32 = msr & 0xFFFFFFFF;
8e180f3c
LB		 1027 }
1028
1029 if (extra_delta_offset64)
1030 if (get_msr(cpu, extra_delta_offset64, &t->extra_delta64))
2f32edf1
LB		 1031 return -5;
1032
8e180f3c 1033 if (extra_msr_offset32) {
889facbe 1034 if (get_msr(cpu, extra_msr_offset32, &msr))
8e180f3c 1035 return -5;
889facbe 1036 t->extra_msr32 = msr & 0xFFFFFFFF;
8e180f3c
LB		 1037 }
1038
2f32edf1
LB		 1039 if (extra_msr_offset64)
1040 if (get_msr(cpu, extra_msr_offset64, &t->extra_msr64))
c98d5d94
LB		 1041 return -5;
1042
144b44b1
LB		 1043 if (use_c1_residency_msr) {
1044 if (get_msr(cpu, MSR_CORE_C1_RES, &t->c1))
1045 return -6;
1046 }
1047
c98d5d94
LB		 1048 /* collect core counters only for 1st thread in core */
1049 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
1050 return 0;
1051
fb5d4327 1052 if (do_nhm_cstates && !do_slm_cstates && !do_knl_cstates) {
c98d5d94
LB		 1053 if (get_msr(cpu, MSR_CORE_C3_RESIDENCY, &c->c3))
1054 return -6;
144b44b1
LB		 1055 }
1056
fb5d4327 1057 if (do_nhm_cstates && !do_knl_cstates) {
c98d5d94
LB		 1058 if (get_msr(cpu, MSR_CORE_C6_RESIDENCY, &c->c6))
1059 return -7;
fb5d4327
DC		 1060 } else if (do_knl_cstates) {
1061 if (get_msr(cpu, MSR_KNL_CORE_C6_RESIDENCY, &c->c6))
1062 return -7;
c98d5d94
LB		 1063 }
1064
1065 if (do_snb_cstates)
1066 if (get_msr(cpu, MSR_CORE_C7_RESIDENCY, &c->c7))
1067 return -8;
1068
889facbe
LB		 1069 if (do_dts) {
1070 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
1071 return -9;
1072 c->core_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
1073 }
1074
1075
c98d5d94
LB		 1076 /* collect package counters only for 1st core in package */
1077 if (!(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
1078 return 0;
1079
0b2bb692
LB		 1080 if (do_skl_residency) {
1081 if (get_msr(cpu, MSR_PKG_WEIGHTED_CORE_C0_RES, &p->pkg_wtd_core_c0))
1082 return -10;
1083 if (get_msr(cpu, MSR_PKG_ANY_CORE_C0_RES, &p->pkg_any_core_c0))
1084 return -11;
1085 if (get_msr(cpu, MSR_PKG_ANY_GFXE_C0_RES, &p->pkg_any_gfxe_c0))
1086 return -12;
1087 if (get_msr(cpu, MSR_PKG_BOTH_CORE_GFXE_C0_RES, &p->pkg_both_core_gfxe_c0))
1088 return -13;
1089 }
ee7e38e3 1090 if (do_pc3)
c98d5d94
LB		 1091 if (get_msr(cpu, MSR_PKG_C3_RESIDENCY, &p->pc3))
1092 return -9;
ee7e38e3 1093 if (do_pc6)
c98d5d94
LB		 1094 if (get_msr(cpu, MSR_PKG_C6_RESIDENCY, &p->pc6))
1095 return -10;
ee7e38e3 1096 if (do_pc2)
c98d5d94
LB		 1097 if (get_msr(cpu, MSR_PKG_C2_RESIDENCY, &p->pc2))
1098 return -11;
ee7e38e3 1099 if (do_pc7)
c98d5d94
LB		 1100 if (get_msr(cpu, MSR_PKG_C7_RESIDENCY, &p->pc7))
1101 return -12;
ca58710f
KCA		 1102 if (do_c8_c9_c10) {
1103 if (get_msr(cpu, MSR_PKG_C8_RESIDENCY, &p->pc8))
1104 return -13;
1105 if (get_msr(cpu, MSR_PKG_C9_RESIDENCY, &p->pc9))
1106 return -13;
1107 if (get_msr(cpu, MSR_PKG_C10_RESIDENCY, &p->pc10))
1108 return -13;
1109 }
889facbe
LB		 1110 if (do_rapl & RAPL_PKG) {
1111 if (get_msr(cpu, MSR_PKG_ENERGY_STATUS, &msr))
1112 return -13;
1113 p->energy_pkg = msr & 0xFFFFFFFF;
1114 }
1115 if (do_rapl & RAPL_CORES) {
1116 if (get_msr(cpu, MSR_PP0_ENERGY_STATUS, &msr))
1117 return -14;
1118 p->energy_cores = msr & 0xFFFFFFFF;
1119 }
1120 if (do_rapl & RAPL_DRAM) {
1121 if (get_msr(cpu, MSR_DRAM_ENERGY_STATUS, &msr))
1122 return -15;
1123 p->energy_dram = msr & 0xFFFFFFFF;
1124 }
1125 if (do_rapl & RAPL_GFX) {
1126 if (get_msr(cpu, MSR_PP1_ENERGY_STATUS, &msr))
1127 return -16;
1128 p->energy_gfx = msr & 0xFFFFFFFF;
1129 }
1130 if (do_rapl & RAPL_PKG_PERF_STATUS) {
1131 if (get_msr(cpu, MSR_PKG_PERF_STATUS, &msr))
1132 return -16;
1133 p->rapl_pkg_perf_status = msr & 0xFFFFFFFF;
1134 }
1135 if (do_rapl & RAPL_DRAM_PERF_STATUS) {
1136 if (get_msr(cpu, MSR_DRAM_PERF_STATUS, &msr))
1137 return -16;
1138 p->rapl_dram_perf_status = msr & 0xFFFFFFFF;
1139 }
1140 if (do_ptm) {
1141 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
1142 return -17;
1143 p->pkg_temp_c = tcc_activation_temp - ((msr >> 16) & 0x7F);
1144 }
15aaa346 1145 return 0;
103a8fea
LB		 1146}
1147
ee7e38e3
LB		 1148/*
1149 * MSR_PKG_CST_CONFIG_CONTROL decoding for pkg_cstate_limit:
1150 * If you change the values, note they are used both in comparisons
1151 * (>= PCL__7) and to index pkg_cstate_limit_strings[].
1152 */
1153
1154#define PCLUKN 0 /* Unknown */
1155#define PCLRSV 1 /* Reserved */
1156#define PCL__0 2 /* PC0 */
1157#define PCL__1 3 /* PC1 */
1158#define PCL__2 4 /* PC2 */
1159#define PCL__3 5 /* PC3 */
1160#define PCL__4 6 /* PC4 */
1161#define PCL__6 7 /* PC6 */
1162#define PCL_6N 8 /* PC6 No Retention */
1163#define PCL_6R 9 /* PC6 Retention */
1164#define PCL__7 10 /* PC7 */
1165#define PCL_7S 11 /* PC7 Shrink */
0b2bb692
LB		 1166#define PCL__8 12 /* PC8 */
1167#define PCL__9 13 /* PC9 */
1168#define PCLUNL 14 /* Unlimited */
ee7e38e3
LB		 1169
1170int pkg_cstate_limit = PCLUKN;
1171char *pkg_cstate_limit_strings[] = { "reserved", "unknown", "pc0", "pc1", "pc2",
0b2bb692 1172 "pc3", "pc4", "pc6", "pc6n", "pc6r", "pc7", "pc7s", "pc8", "pc9", "unlimited"};
ee7e38e3 1173
e9257f5f
LB		 1174int nhm_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__3, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1175int snb_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCL__7, PCL_7S, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1176int hsw_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL__3, PCL__6, PCL__7, PCL_7S, PCL__8, PCL__9, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1177int slv_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCLRSV, PCLRSV, PCL__4, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1178int amt_pkg_cstate_limits[16] = {PCL__0, PCL__1, PCL__2, PCLRSV, PCLRSV, PCLRSV, PCL__6, PCL__7, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
1179int phi_pkg_cstate_limits[16] = {PCL__0, PCL__2, PCL_6N, PCL_6R, PCLRSV, PCLRSV, PCLRSV, PCLUNL, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV, PCLRSV};
ee7e38e3 1180
a2b7b749
LB		 1181
1182static void
1183calculate_tsc_tweak()
1184{
a2b7b749
LB		 1185 tsc_tweak = base_hz / tsc_hz;
1186}
1187
fcd17211
LB		 1188static void
1189dump_nhm_platform_info(void)
103a8fea
LB		 1190{
1191 unsigned long long msr;
1192 unsigned int ratio;
1193
ec0adc53 1194 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
103a8fea 1195
b7d8c148 1196 fprintf(outf, "cpu%d: MSR_PLATFORM_INFO: 0x%08llx\n", base_cpu, msr);
6574a5d5 1197
103a8fea 1198 ratio = (msr >> 40) & 0xFF;
b7d8c148 1199 fprintf(outf, "%d * %.0f = %.0f MHz max efficiency frequency\n",
103a8fea
LB		 1200 ratio, bclk, ratio * bclk);
1201
1202 ratio = (msr >> 8) & 0xFF;
b7d8c148 1203 fprintf(outf, "%d * %.0f = %.0f MHz base frequency\n",
103a8fea
LB		 1204 ratio, bclk, ratio * bclk);
1205
7ce7d5de 1206 get_msr(base_cpu, MSR_IA32_POWER_CTL, &msr);
b7d8c148 1207 fprintf(outf, "cpu%d: MSR_IA32_POWER_CTL: 0x%08llx (C1E auto-promotion: %sabled)\n",
bfae2052 1208 base_cpu, msr, msr & 0x2 ? "EN" : "DIS");
67920418 1209
fcd17211
LB		 1210 return;
1211}
1212
1213static void
1214dump_hsw_turbo_ratio_limits(void)
1215{
1216 unsigned long long msr;
1217 unsigned int ratio;
1218
7ce7d5de 1219 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT2, &msr);
fcd17211 1220
b7d8c148 1221 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT2: 0x%08llx\n", base_cpu, msr);
fcd17211
LB		 1222
1223 ratio = (msr >> 8) & 0xFF;
1224 if (ratio)
b7d8c148 1225 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 18 active cores\n",
fcd17211
LB		 1226 ratio, bclk, ratio * bclk);
1227
1228 ratio = (msr >> 0) & 0xFF;
1229 if (ratio)
b7d8c148 1230 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 17 active cores\n",
fcd17211
LB		 1231 ratio, bclk, ratio * bclk);
1232 return;
1233}
1234
1235static void
1236dump_ivt_turbo_ratio_limits(void)
1237{
1238 unsigned long long msr;
1239 unsigned int ratio;
6574a5d5 1240
7ce7d5de 1241 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT1, &msr);
6574a5d5 1242
b7d8c148 1243 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT1: 0x%08llx\n", base_cpu, msr);
6574a5d5
LB		 1244
1245 ratio = (msr >> 56) & 0xFF;
1246 if (ratio)
b7d8c148 1247 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 16 active cores\n",
6574a5d5
LB		 1248 ratio, bclk, ratio * bclk);
1249
1250 ratio = (msr >> 48) & 0xFF;
1251 if (ratio)
b7d8c148 1252 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 15 active cores\n",
6574a5d5
LB		 1253 ratio, bclk, ratio * bclk);
1254
1255 ratio = (msr >> 40) & 0xFF;
1256 if (ratio)
b7d8c148 1257 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 14 active cores\n",
6574a5d5
LB		 1258 ratio, bclk, ratio * bclk);
1259
1260 ratio = (msr >> 32) & 0xFF;
1261 if (ratio)
b7d8c148 1262 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 13 active cores\n",
6574a5d5
LB		 1263 ratio, bclk, ratio * bclk);
1264
1265 ratio = (msr >> 24) & 0xFF;
1266 if (ratio)
b7d8c148 1267 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 12 active cores\n",
6574a5d5
LB		 1268 ratio, bclk, ratio * bclk);
1269
1270 ratio = (msr >> 16) & 0xFF;
1271 if (ratio)
b7d8c148 1272 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 11 active cores\n",
6574a5d5
LB		 1273 ratio, bclk, ratio * bclk);
1274
1275 ratio = (msr >> 8) & 0xFF;
1276 if (ratio)
b7d8c148 1277 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 10 active cores\n",
6574a5d5
LB		 1278 ratio, bclk, ratio * bclk);
1279
1280 ratio = (msr >> 0) & 0xFF;
1281 if (ratio)
b7d8c148 1282 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 9 active cores\n",
6574a5d5 1283 ratio, bclk, ratio * bclk);
fcd17211
LB		 1284 return;
1285}
6574a5d5 1286
fcd17211
LB		 1287static void
1288dump_nhm_turbo_ratio_limits(void)
1289{
1290 unsigned long long msr;
1291 unsigned int ratio;
103a8fea 1292
7ce7d5de 1293 get_msr(base_cpu, MSR_TURBO_RATIO_LIMIT, &msr);
103a8fea 1294
b7d8c148 1295 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n", base_cpu, msr);
6574a5d5
LB		 1296
1297 ratio = (msr >> 56) & 0xFF;
1298 if (ratio)
b7d8c148 1299 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 8 active cores\n",
6574a5d5
LB		 1300 ratio, bclk, ratio * bclk);
1301
1302 ratio = (msr >> 48) & 0xFF;
1303 if (ratio)
b7d8c148 1304 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 7 active cores\n",
6574a5d5
LB		 1305 ratio, bclk, ratio * bclk);
1306
1307 ratio = (msr >> 40) & 0xFF;
1308 if (ratio)
b7d8c148 1309 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 6 active cores\n",
6574a5d5
LB		 1310 ratio, bclk, ratio * bclk);
1311
1312 ratio = (msr >> 32) & 0xFF;
1313 if (ratio)
b7d8c148 1314 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 5 active cores\n",
6574a5d5
LB		 1315 ratio, bclk, ratio * bclk);
1316
103a8fea
LB		 1317 ratio = (msr >> 24) & 0xFF;
1318 if (ratio)
b7d8c148 1319 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 4 active cores\n",
103a8fea
LB		 1320 ratio, bclk, ratio * bclk);
1321
1322 ratio = (msr >> 16) & 0xFF;
1323 if (ratio)
b7d8c148 1324 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 3 active cores\n",
103a8fea
LB		 1325 ratio, bclk, ratio * bclk);
1326
1327 ratio = (msr >> 8) & 0xFF;
1328 if (ratio)
b7d8c148 1329 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 2 active cores\n",
103a8fea
LB		 1330 ratio, bclk, ratio * bclk);
1331
1332 ratio = (msr >> 0) & 0xFF;
1333 if (ratio)
b7d8c148 1334 fprintf(outf, "%d * %.0f = %.0f MHz max turbo 1 active cores\n",
103a8fea 1335 ratio, bclk, ratio * bclk);
fcd17211
LB		 1336 return;
1337}
3a9a941d 1338
fb5d4327
DC		 1339static void
1340dump_knl_turbo_ratio_limits(void)
1341{
cbf97aba
HC		 1342 const unsigned int buckets_no = 7;
1343
fb5d4327 1344 unsigned long long msr;
cbf97aba
HC		 1345 int delta_cores, delta_ratio;
1346 int i, b_nr;
1347 unsigned int cores[buckets_no];
1348 unsigned int ratio[buckets_no];
fb5d4327 1349
7ce7d5de 1350 get_msr(base_cpu, MSR_NHM_TURBO_RATIO_LIMIT, &msr);
fb5d4327 1351
b7d8c148 1352 fprintf(outf, "cpu%d: MSR_TURBO_RATIO_LIMIT: 0x%08llx\n",
bfae2052 1353 base_cpu, msr);
fb5d4327
DC		 1354
1355 /**
1356 * Turbo encoding in KNL is as follows:
cbf97aba
HC		 1357 * [0] -- Reserved
1358 * [7:1] -- Base value of number of active cores of bucket 1.
fb5d4327
DC		 1359 * [15:8] -- Base value of freq ratio of bucket 1.
1360 * [20:16] -- +ve delta of number of active cores of bucket 2.
1361 * i.e. active cores of bucket 2 =
1362 * active cores of bucket 1 + delta
1363 * [23:21] -- Negative delta of freq ratio of bucket 2.
1364 * i.e. freq ratio of bucket 2 =
1365 * freq ratio of bucket 1 - delta
1366 * [28:24]-- +ve delta of number of active cores of bucket 3.
1367 * [31:29]-- -ve delta of freq ratio of bucket 3.
1368 * [36:32]-- +ve delta of number of active cores of bucket 4.
1369 * [39:37]-- -ve delta of freq ratio of bucket 4.
1370 * [44:40]-- +ve delta of number of active cores of bucket 5.
1371 * [47:45]-- -ve delta of freq ratio of bucket 5.
1372 * [52:48]-- +ve delta of number of active cores of bucket 6.
1373 * [55:53]-- -ve delta of freq ratio of bucket 6.
1374 * [60:56]-- +ve delta of number of active cores of bucket 7.
1375 * [63:61]-- -ve delta of freq ratio of bucket 7.
1376 */
cbf97aba
HC		 1377
1378 b_nr = 0;
1379 cores[b_nr] = (msr & 0xFF) >> 1;
1380 ratio[b_nr] = (msr >> 8) & 0xFF;
1381
1382 for (i = 16; i < 64; i += 8) {
fb5d4327 1383 delta_cores = (msr >> i) & 0x1F;
cbf97aba
HC		 1384 delta_ratio = (msr >> (i + 5)) & 0x7;
1385
1386 cores[b_nr + 1] = cores[b_nr] + delta_cores;
1387 ratio[b_nr + 1] = ratio[b_nr] - delta_ratio;
1388 b_nr++;
1389 }
1390
1391 for (i = buckets_no - 1; i >= 0; i--)
1392 if (i > 0 ? ratio[i] != ratio[i - 1] : 1)
b7d8c148 1393 fprintf(outf,
fb5d4327 1394 "%d * %.0f = %.0f MHz max turbo %d active cores\n",
cbf97aba 1395 ratio[i], bclk, ratio[i] * bclk, cores[i]);
fb5d4327
DC		 1396}
1397
fcd17211
LB		 1398static void
1399dump_nhm_cst_cfg(void)
1400{
1401 unsigned long long msr;
1402
7ce7d5de 1403 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr);
fcd17211
LB		 1404
1405#define SNB_C1_AUTO_UNDEMOTE (1UL << 27)
1406#define SNB_C3_AUTO_UNDEMOTE (1UL << 28)
1407
b7d8c148 1408 fprintf(outf, "cpu%d: MSR_NHM_SNB_PKG_CST_CFG_CTL: 0x%08llx", base_cpu, msr);
fcd17211 1409
b7d8c148 1410 fprintf(outf, " (%s%s%s%s%slocked: pkg-cstate-limit=%d: %s)\n",
fcd17211
LB		 1411 (msr & SNB_C3_AUTO_UNDEMOTE) ? "UNdemote-C3, " : "",
1412 (msr & SNB_C1_AUTO_UNDEMOTE) ? "UNdemote-C1, " : "",
1413 (msr & NHM_C3_AUTO_DEMOTE) ? "demote-C3, " : "",
1414 (msr & NHM_C1_AUTO_DEMOTE) ? "demote-C1, " : "",
1415 (msr & (1 << 15)) ? "" : "UN",
1416 (unsigned int)msr & 7,
1417 pkg_cstate_limit_strings[pkg_cstate_limit]);
1418 return;
103a8fea
LB		 1419}
1420
6fb3143b
LB		 1421static void
1422dump_config_tdp(void)
1423{
1424 unsigned long long msr;
1425
1426 get_msr(base_cpu, MSR_CONFIG_TDP_NOMINAL, &msr);
b7d8c148
LB		 1427 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_NOMINAL: 0x%08llx", base_cpu, msr);
1428 fprintf(outf, " (base_ratio=%d)\n", (unsigned int)msr & 0xEF);
6fb3143b
LB		 1429
1430 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_1, &msr);
b7d8c148 1431 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_1: 0x%08llx (", base_cpu, msr);
6fb3143b 1432 if (msr) {
b7d8c148
LB		 1433 fprintf(outf, "PKG_MIN_PWR_LVL1=%d ", (unsigned int)(msr >> 48) & 0xEFFF);
1434 fprintf(outf, "PKG_MAX_PWR_LVL1=%d ", (unsigned int)(msr >> 32) & 0xEFFF);
1435 fprintf(outf, "LVL1_RATIO=%d ", (unsigned int)(msr >> 16) & 0xEF);
1436 fprintf(outf, "PKG_TDP_LVL1=%d", (unsigned int)(msr) & 0xEFFF);
6fb3143b 1437 }
b7d8c148 1438 fprintf(outf, ")\n");
6fb3143b
LB		 1439
1440 get_msr(base_cpu, MSR_CONFIG_TDP_LEVEL_2, &msr);
b7d8c148 1441 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_LEVEL_2: 0x%08llx (", base_cpu, msr);
6fb3143b 1442 if (msr) {
b7d8c148
LB		 1443 fprintf(outf, "PKG_MIN_PWR_LVL2=%d ", (unsigned int)(msr >> 48) & 0xEFFF);
1444 fprintf(outf, "PKG_MAX_PWR_LVL2=%d ", (unsigned int)(msr >> 32) & 0xEFFF);
1445 fprintf(outf, "LVL2_RATIO=%d ", (unsigned int)(msr >> 16) & 0xEF);
1446 fprintf(outf, "PKG_TDP_LVL2=%d", (unsigned int)(msr) & 0xEFFF);
6fb3143b 1447 }
b7d8c148 1448 fprintf(outf, ")\n");
6fb3143b
LB		 1449
1450 get_msr(base_cpu, MSR_CONFIG_TDP_CONTROL, &msr);
b7d8c148 1451 fprintf(outf, "cpu%d: MSR_CONFIG_TDP_CONTROL: 0x%08llx (", base_cpu, msr);
6fb3143b 1452 if ((msr) & 0x3)
b7d8c148
LB		 1453 fprintf(outf, "TDP_LEVEL=%d ", (unsigned int)(msr) & 0x3);
1454 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
1455 fprintf(outf, ")\n");
6fb3143b
LB		 1456
1457 get_msr(base_cpu, MSR_TURBO_ACTIVATION_RATIO, &msr);
b7d8c148
LB		 1458 fprintf(outf, "cpu%d: MSR_TURBO_ACTIVATION_RATIO: 0x%08llx (", base_cpu, msr);
1459 fprintf(outf, "MAX_NON_TURBO_RATIO=%d", (unsigned int)(msr) & 0x7F);
1460 fprintf(outf, " lock=%d", (unsigned int)(msr >> 31) & 1);
1461 fprintf(outf, ")\n");
6fb3143b
LB		 1462}
1463
c98d5d94 1464void free_all_buffers(void)
103a8fea 1465{
c98d5d94
LB		 1466 CPU_FREE(cpu_present_set);
1467 cpu_present_set = NULL;
1468 cpu_present_set = 0;
103a8fea 1469
c98d5d94
LB		 1470 CPU_FREE(cpu_affinity_set);
1471 cpu_affinity_set = NULL;
1472 cpu_affinity_setsize = 0;
103a8fea 1473
c98d5d94
LB		 1474 free(thread_even);
1475 free(core_even);
1476 free(package_even);
103a8fea 1477
c98d5d94
LB		 1478 thread_even = NULL;
1479 core_even = NULL;
1480 package_even = NULL;
103a8fea 1481
c98d5d94
LB		 1482 free(thread_odd);
1483 free(core_odd);
1484 free(package_odd);
103a8fea 1485
c98d5d94
LB		 1486 thread_odd = NULL;
1487 core_odd = NULL;
1488 package_odd = NULL;
103a8fea 1489
c98d5d94
LB		 1490 free(output_buffer);
1491 output_buffer = NULL;
1492 outp = NULL;
103a8fea
LB		 1493}
1494
57a42a34
JT		 1495/*
1496 * Open a file, and exit on failure
1497 */
1498FILE *fopen_or_die(const char *path, const char *mode)
1499{
b7d8c148 1500 FILE *filep = fopen(path, mode);
b2c95d90
JT		 1501 if (!filep)
1502 err(1, "%s: open failed", path);
57a42a34
JT		 1503 return filep;
1504}
1505
c98d5d94 1506/*
95aebc44 1507 * Parse a file containing a single int.
c98d5d94 1508 */
95aebc44 1509int parse_int_file(const char *fmt, ...)
103a8fea 1510{
95aebc44
JT		 1511 va_list args;
1512 char path[PATH_MAX];
c98d5d94 1513 FILE *filep;
95aebc44 1514 int value;
103a8fea 1515
95aebc44
JT		 1516 va_start(args, fmt);
1517 vsnprintf(path, sizeof(path), fmt, args);
1518 va_end(args);
57a42a34 1519 filep = fopen_or_die(path, "r");
b2c95d90
JT		 1520 if (fscanf(filep, "%d", &value) != 1)
1521 err(1, "%s: failed to parse number from file", path);
c98d5d94 1522 fclose(filep);
95aebc44
JT		 1523 return value;
1524}
1525
1526/*
e275b388
DC		 1527 * get_cpu_position_in_core(cpu)
1528 * return the position of the CPU among its HT siblings in the core
1529 * return -1 if the sibling is not in list
95aebc44 1530 */
e275b388 1531int get_cpu_position_in_core(int cpu)
95aebc44 1532{
e275b388
DC		 1533 char path[64];
1534 FILE *filep;
1535 int this_cpu;
1536 char character;
1537 int i;
1538
1539 sprintf(path,
1540 "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list",
1541 cpu);
1542 filep = fopen(path, "r");
1543 if (filep == NULL) {
1544 perror(path);
1545 exit(1);
1546 }
1547
1548 for (i = 0; i < topo.num_threads_per_core; i++) {
1549 fscanf(filep, "%d", &this_cpu);
1550 if (this_cpu == cpu) {
1551 fclose(filep);
1552 return i;
1553 }
1554
1555 /* Account for no separator after last thread*/
1556 if (i != (topo.num_threads_per_core - 1))
1557 fscanf(filep, "%c", &character);
1558 }
1559
1560 fclose(filep);
1561 return -1;
103a8fea
LB		 1562}
1563
c98d5d94
LB		 1564/*
1565 * cpu_is_first_core_in_package(cpu)
1566 * return 1 if given CPU is 1st core in package
1567 */
1568int cpu_is_first_core_in_package(int cpu)
103a8fea 1569{
95aebc44 1570 return cpu == parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_siblings_list", cpu);
103a8fea
LB		 1571}
1572
1573int get_physical_package_id(int cpu)
1574{
95aebc44 1575 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/physical_package_id", cpu);
103a8fea
LB		 1576}
1577
1578int get_core_id(int cpu)
1579{
95aebc44 1580 return parse_int_file("/sys/devices/system/cpu/cpu%d/topology/core_id", cpu);
103a8fea
LB		 1581}
1582
c98d5d94
LB		 1583int get_num_ht_siblings(int cpu)
1584{
1585 char path[80];
1586 FILE *filep;
e275b388
DC		 1587 int sib1;
1588 int matches = 0;
c98d5d94 1589 char character;
e275b388
DC		 1590 char str[100];
1591 char *ch;
c98d5d94
LB		 1592
1593 sprintf(path, "/sys/devices/system/cpu/cpu%d/topology/thread_siblings_list", cpu);
57a42a34 1594 filep = fopen_or_die(path, "r");
e275b388 1595
c98d5d94
LB		 1596 /*
1597 * file format:
e275b388
DC		 1598 * A ',' separated or '-' separated set of numbers
1599 * (eg 1-2 or 1,3,4,5)
c98d5d94 1600 */
e275b388
DC		 1601 fscanf(filep, "%d%c\n", &sib1, &character);
1602 fseek(filep, 0, SEEK_SET);
1603 fgets(str, 100, filep);
1604 ch = strchr(str, character);
1605 while (ch != NULL) {
1606 matches++;
1607 ch = strchr(ch+1, character);
1608 }
c98d5d94
LB		 1609
1610 fclose(filep);
e275b388 1611 return matches+1;
c98d5d94
LB		 1612}
1613
103a8fea 1614/*
c98d5d94
LB		 1615 * run func(thread, core, package) in topology order
1616 * skip non-present cpus
103a8fea
LB		 1617 */
1618
c98d5d94
LB		 1619int for_all_cpus_2(int (func)(struct thread_data *, struct core_data *,
1620 struct pkg_data *, struct thread_data *, struct core_data *,
1621 struct pkg_data *), struct thread_data *thread_base,
1622 struct core_data *core_base, struct pkg_data *pkg_base,
1623 struct thread_data *thread_base2, struct core_data *core_base2,
1624 struct pkg_data *pkg_base2)
1625{
1626 int retval, pkg_no, core_no, thread_no;
1627
1628 for (pkg_no = 0; pkg_no < topo.num_packages; ++pkg_no) {
1629 for (core_no = 0; core_no < topo.num_cores_per_pkg; ++core_no) {
1630 for (thread_no = 0; thread_no <
1631 topo.num_threads_per_core; ++thread_no) {
1632 struct thread_data *t, *t2;
1633 struct core_data *c, *c2;
1634 struct pkg_data *p, *p2;
1635
1636 t = GET_THREAD(thread_base, thread_no, core_no, pkg_no);
1637
1638 if (cpu_is_not_present(t->cpu_id))
1639 continue;
1640
1641 t2 = GET_THREAD(thread_base2, thread_no, core_no, pkg_no);
1642
1643 c = GET_CORE(core_base, core_no, pkg_no);
1644 c2 = GET_CORE(core_base2, core_no, pkg_no);
1645
1646 p = GET_PKG(pkg_base, pkg_no);
1647 p2 = GET_PKG(pkg_base2, pkg_no);
1648
1649 retval = func(t, c, p, t2, c2, p2);
1650 if (retval)
1651 return retval;
1652 }
1653 }
1654 }
1655 return 0;
1656}
1657
1658/*
1659 * run func(cpu) on every cpu in /proc/stat
1660 * return max_cpu number
1661 */
1662int for_all_proc_cpus(int (func)(int))
103a8fea
LB		 1663{
1664 FILE *fp;
c98d5d94 1665 int cpu_num;
103a8fea
LB		 1666 int retval;
1667
57a42a34 1668 fp = fopen_or_die(proc_stat, "r");
103a8fea
LB		 1669
1670 retval = fscanf(fp, "cpu %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n");
b2c95d90
JT		 1671 if (retval != 0)
1672 err(1, "%s: failed to parse format", proc_stat);
103a8fea 1673
c98d5d94
LB		 1674 while (1) {
1675 retval = fscanf(fp, "cpu%u %*d %*d %*d %*d %*d %*d %*d %*d %*d %*d\n", &cpu_num);
103a8fea
LB		 1676 if (retval != 1)
1677 break;
1678
c98d5d94
LB		 1679 retval = func(cpu_num);
1680 if (retval) {
1681 fclose(fp);
1682 return(retval);
1683 }
103a8fea
LB		 1684 }
1685 fclose(fp);
c98d5d94 1686 return 0;
103a8fea
LB		 1687}
1688
1689void re_initialize(void)
1690{
c98d5d94
LB		 1691 free_all_buffers();
1692 setup_all_buffers();
1693 printf("turbostat: re-initialized with num_cpus %d\n", topo.num_cpus);
103a8fea
LB		 1694}
1695
c98d5d94 1696
103a8fea 1697/*
c98d5d94
LB		 1698 * count_cpus()
1699 * remember the last one seen, it will be the max
103a8fea 1700 */
c98d5d94 1701int count_cpus(int cpu)
103a8fea 1702{
c98d5d94
LB		 1703 if (topo.max_cpu_num < cpu)
1704 topo.max_cpu_num = cpu;
103a8fea 1705
c98d5d94
LB		 1706 topo.num_cpus += 1;
1707 return 0;
1708}
1709int mark_cpu_present(int cpu)
1710{
1711 CPU_SET_S(cpu, cpu_present_setsize, cpu_present_set);
15aaa346 1712 return 0;
103a8fea
LB		 1713}
1714
1715void turbostat_loop()
1716{
c98d5d94 1717 int retval;
e52966c0 1718 int restarted = 0;
c98d5d94 1719
103a8fea 1720restart:
e52966c0
LB		 1721 restarted++;
1722
c98d5d94 1723 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
d91bb17c
LB		 1724 if (retval < -1) {
1725 exit(retval);
1726 } else if (retval == -1) {
e52966c0
LB		 1727 if (restarted > 1) {
1728 exit(retval);
1729 }
c98d5d94
LB		 1730 re_initialize();
1731 goto restart;
1732 }
e52966c0 1733 restarted = 0;
103a8fea
LB		 1734 gettimeofday(&tv_even, (struct timezone *)NULL);
1735
1736 while (1) {
c98d5d94 1737 if (for_all_proc_cpus(cpu_is_not_present)) {
103a8fea
LB		 1738 re_initialize();
1739 goto restart;
1740 }
2a0609c0 1741 nanosleep(&interval_ts, NULL);
c98d5d94 1742 retval = for_all_cpus(get_counters, ODD_COUNTERS);
d91bb17c
LB		 1743 if (retval < -1) {
1744 exit(retval);
1745 } else if (retval == -1) {
15aaa346
LB		 1746 re_initialize();
1747 goto restart;
1748 }
103a8fea 1749 gettimeofday(&tv_odd, (struct timezone *)NULL);
103a8fea 1750 timersub(&tv_odd, &tv_even, &tv_delta);
c98d5d94
LB		 1751 for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS);
1752 compute_average(EVEN_COUNTERS);
1753 format_all_counters(EVEN_COUNTERS);
b7d8c148 1754 flush_output_stdout();
2a0609c0 1755 nanosleep(&interval_ts, NULL);
c98d5d94 1756 retval = for_all_cpus(get_counters, EVEN_COUNTERS);
d91bb17c
LB		 1757 if (retval < -1) {
1758 exit(retval);
1759 } else if (retval == -1) {
103a8fea
LB		 1760 re_initialize();
1761 goto restart;
1762 }
103a8fea 1763 gettimeofday(&tv_even, (struct timezone *)NULL);
103a8fea 1764 timersub(&tv_even, &tv_odd, &tv_delta);
c98d5d94
LB		 1765 for_all_cpus_2(delta_cpu, EVEN_COUNTERS, ODD_COUNTERS);
1766 compute_average(ODD_COUNTERS);
1767 format_all_counters(ODD_COUNTERS);
b7d8c148 1768 flush_output_stdout();
103a8fea
LB		 1769 }
1770}
1771
1772void check_dev_msr()
1773{
1774 struct stat sb;
7ce7d5de 1775 char pathname[32];
103a8fea 1776
7ce7d5de
PB		 1777 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
1778 if (stat(pathname, &sb))
a21d38c8
LB		 1779 if (system("/sbin/modprobe msr > /dev/null 2>&1"))
1780 err(-5, "no /dev/cpu/0/msr, Try \"# modprobe msr\" ");
103a8fea
LB		 1781}
1782
98481e79 1783void check_permissions()
103a8fea 1784{
98481e79
LB		 1785 struct __user_cap_header_struct cap_header_data;
1786 cap_user_header_t cap_header = &cap_header_data;
1787 struct __user_cap_data_struct cap_data_data;
1788 cap_user_data_t cap_data = &cap_data_data;
1789 extern int capget(cap_user_header_t hdrp, cap_user_data_t datap);
1790 int do_exit = 0;
7ce7d5de 1791 char pathname[32];
98481e79
LB		 1792
1793 /* check for CAP_SYS_RAWIO */
1794 cap_header->pid = getpid();
1795 cap_header->version = _LINUX_CAPABILITY_VERSION;
1796 if (capget(cap_header, cap_data) < 0)
1797 err(-6, "capget(2) failed");
1798
1799 if ((cap_data->effective & (1 << CAP_SYS_RAWIO)) == 0) {
1800 do_exit++;
1801 warnx("capget(CAP_SYS_RAWIO) failed,"
1802 " try \"# setcap cap_sys_rawio=ep %s\"", progname);
1803 }
1804
1805 /* test file permissions */
7ce7d5de
PB		 1806 sprintf(pathname, "/dev/cpu/%d/msr", base_cpu);
1807 if (euidaccess(pathname, R_OK)) {
98481e79
LB		 1808 do_exit++;
1809 warn("/dev/cpu/0/msr open failed, try chown or chmod +r /dev/cpu/*/msr");
1810 }
1811
1812 /* if all else fails, thell them to be root */
1813 if (do_exit)
1814 if (getuid() != 0)
d7899447 1815 warnx("... or simply run as root");
98481e79
LB		 1816
1817 if (do_exit)
1818 exit(-6);
103a8fea
LB		 1819}
1820
d7899447
LB		 1821/*
1822 * NHM adds support for additional MSRs:
1823 *
1824 * MSR_SMI_COUNT 0x00000034
1825 *
ec0adc53 1826 * MSR_PLATFORM_INFO 0x000000ce
d7899447
LB		 1827 * MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2
1828 *
1829 * MSR_PKG_C3_RESIDENCY 0x000003f8
1830 * MSR_PKG_C6_RESIDENCY 0x000003f9
1831 * MSR_CORE_C3_RESIDENCY 0x000003fc
1832 * MSR_CORE_C6_RESIDENCY 0x000003fd
1833 *
ee7e38e3
LB		 1834 * Side effect:
1835 * sets global pkg_cstate_limit to decode MSR_NHM_SNB_PKG_CST_CFG_CTL
d7899447 1836 */
ee7e38e3 1837int probe_nhm_msrs(unsigned int family, unsigned int model)
103a8fea 1838{
ee7e38e3 1839 unsigned long long msr;
21ed5574 1840 unsigned int base_ratio;
ee7e38e3
LB		 1841 int *pkg_cstate_limits;
1842
103a8fea
LB		 1843 if (!genuine_intel)
1844 return 0;
1845
1846 if (family != 6)
1847 return 0;
1848
21ed5574
LB		 1849 bclk = discover_bclk(family, model);
1850
103a8fea
LB		 1851 switch (model) {
1852 case 0x1A: /* Core i7, Xeon 5500 series - Bloomfield, Gainstown NHM-EP */
1853 case 0x1E: /* Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest */
1854 case 0x1F: /* Core i7 and i5 Processor - Nehalem */
1855 case 0x25: /* Westmere Client - Clarkdale, Arrandale */
1856 case 0x2C: /* Westmere EP - Gulftown */
ee7e38e3
LB		 1857 case 0x2E: /* Nehalem-EX Xeon - Beckton */
1858 case 0x2F: /* Westmere-EX Xeon - Eagleton */
1859 pkg_cstate_limits = nhm_pkg_cstate_limits;
1860 break;
103a8fea
LB		 1861 case 0x2A: /* SNB */
1862 case 0x2D: /* SNB Xeon */
553575f1 1863 case 0x3A: /* IVB */
1300651b 1864 case 0x3E: /* IVB Xeon */
ee7e38e3
LB		 1865 pkg_cstate_limits = snb_pkg_cstate_limits;
1866 break;
70b43400 1867 case 0x3C: /* HSW */
e6f9bb3c 1868 case 0x3F: /* HSX */
70b43400 1869 case 0x45: /* HSW */
149c2319 1870 case 0x46: /* HSW */
4e8e863f 1871 case 0x3D: /* BDW */
48a0631c 1872 case 0x47: /* BDW */
4e8e863f
LB		 1873 case 0x4F: /* BDX */
1874 case 0x56: /* BDX-DE */
0b2bb692
LB		 1875 case 0x4E: /* SKL */
1876 case 0x5E: /* SKL */
ee7e38e3
LB		 1877 pkg_cstate_limits = hsw_pkg_cstate_limits;
1878 break;
1879 case 0x37: /* BYT */
1880 case 0x4D: /* AVN */
1881 pkg_cstate_limits = slv_pkg_cstate_limits;
1882 break;
1883 case 0x4C: /* AMT */
1884 pkg_cstate_limits = amt_pkg_cstate_limits;
1885 break;
1886 case 0x57: /* PHI */
1887 pkg_cstate_limits = phi_pkg_cstate_limits;
1888 break;
103a8fea
LB		 1889 default:
1890 return 0;
1891 }
7ce7d5de 1892 get_msr(base_cpu, MSR_NHM_SNB_PKG_CST_CFG_CTL, &msr);
e9257f5f 1893 pkg_cstate_limit = pkg_cstate_limits[msr & 0xF];
ee7e38e3 1894
ec0adc53 1895 get_msr(base_cpu, MSR_PLATFORM_INFO, &msr);
21ed5574
LB		 1896 base_ratio = (msr >> 8) & 0xFF;
1897
1898 base_hz = base_ratio * bclk * 1000000;
1899 has_base_hz = 1;
ee7e38e3 1900 return 1;
103a8fea 1901}
d7899447
LB		 1902int has_nhm_turbo_ratio_limit(unsigned int family, unsigned int model)
1903{
d7899447
LB		 1904 switch (model) {
1905 /* Nehalem compatible, but do not include turbo-ratio limit support */
1906 case 0x2E: /* Nehalem-EX Xeon - Beckton */
1907 case 0x2F: /* Westmere-EX Xeon - Eagleton */
cbf97aba 1908 case 0x57: /* PHI - Knights Landing (different MSR definition) */
d7899447
LB		 1909 return 0;
1910 default:
1911 return 1;
1912 }
1913}
6574a5d5
LB		 1914int has_ivt_turbo_ratio_limit(unsigned int family, unsigned int model)
1915{
1916 if (!genuine_intel)
1917 return 0;
1918
1919 if (family != 6)
1920 return 0;
1921
1922 switch (model) {
1923 case 0x3E: /* IVB Xeon */
fcd17211
LB		 1924 case 0x3F: /* HSW Xeon */
1925 return 1;
1926 default:
1927 return 0;
1928 }
1929}
1930int has_hsw_turbo_ratio_limit(unsigned int family, unsigned int model)
1931{
1932 if (!genuine_intel)
1933 return 0;
1934
1935 if (family != 6)
1936 return 0;
1937
1938 switch (model) {
1939 case 0x3F: /* HSW Xeon */
6574a5d5
LB		 1940 return 1;
1941 default:
1942 return 0;
1943 }
1944}
1945
fb5d4327
DC		 1946int has_knl_turbo_ratio_limit(unsigned int family, unsigned int model)
1947{
1948 if (!genuine_intel)
1949 return 0;
1950
1951 if (family != 6)
1952 return 0;
1953
1954 switch (model) {
1955 case 0x57: /* Knights Landing */
1956 return 1;
1957 default:
1958 return 0;
1959 }
1960}
6fb3143b
LB		 1961int has_config_tdp(unsigned int family, unsigned int model)
1962{
1963 if (!genuine_intel)
1964 return 0;
1965
1966 if (family != 6)
1967 return 0;
1968
1969 switch (model) {
1970 case 0x3A: /* IVB */
6fb3143b
LB		 1971 case 0x3C: /* HSW */
1972 case 0x3F: /* HSX */
1973 case 0x45: /* HSW */
1974 case 0x46: /* HSW */
1975 case 0x3D: /* BDW */
1976 case 0x47: /* BDW */
1977 case 0x4F: /* BDX */
1978 case 0x56: /* BDX-DE */
1979 case 0x4E: /* SKL */
1980 case 0x5E: /* SKL */
1981
1982 case 0x57: /* Knights Landing */
1983 return 1;
1984 default:
1985 return 0;
1986 }
1987}
1988
fcd17211
LB		 1989static void
1990dump_cstate_pstate_config_info(family, model)
1991{
1992 if (!do_nhm_platform_info)
1993 return;
1994
1995 dump_nhm_platform_info();
1996
1997 if (has_hsw_turbo_ratio_limit(family, model))
1998 dump_hsw_turbo_ratio_limits();
1999
2000 if (has_ivt_turbo_ratio_limit(family, model))
2001 dump_ivt_turbo_ratio_limits();
2002
2003 if (has_nhm_turbo_ratio_limit(family, model))
2004 dump_nhm_turbo_ratio_limits();
2005
fb5d4327
DC		 2006 if (has_knl_turbo_ratio_limit(family, model))
2007 dump_knl_turbo_ratio_limits();
2008
6fb3143b
LB		 2009 if (has_config_tdp(family, model))
2010 dump_config_tdp();
2011
fcd17211
LB		 2012 dump_nhm_cst_cfg();
2013}
2014
2015
889facbe
LB		 2016/*
2017 * print_epb()
2018 * Decode the ENERGY_PERF_BIAS MSR
2019 */
2020int print_epb(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2021{
2022 unsigned long long msr;
2023 char *epb_string;
2024 int cpu;
2025
2026 if (!has_epb)
2027 return 0;
2028
2029 cpu = t->cpu_id;
2030
2031 /* EPB is per-package */
2032 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2033 return 0;
2034
2035 if (cpu_migrate(cpu)) {
b7d8c148 2036 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
889facbe
LB		 2037 return -1;
2038 }
2039
2040 if (get_msr(cpu, MSR_IA32_ENERGY_PERF_BIAS, &msr))
2041 return 0;
2042
e9be7dd6 2043 switch (msr & 0xF) {
889facbe
LB		 2044 case ENERGY_PERF_BIAS_PERFORMANCE:
2045 epb_string = "performance";
2046 break;
2047 case ENERGY_PERF_BIAS_NORMAL:
2048 epb_string = "balanced";
2049 break;
2050 case ENERGY_PERF_BIAS_POWERSAVE:
2051 epb_string = "powersave";
2052 break;
2053 default:
2054 epb_string = "custom";
2055 break;
2056 }
b7d8c148 2057 fprintf(outf, "cpu%d: MSR_IA32_ENERGY_PERF_BIAS: 0x%08llx (%s)\n", cpu, msr, epb_string);
889facbe
LB		 2058
2059 return 0;
2060}
7f5c258e
LB		 2061/*
2062 * print_hwp()
2063 * Decode the MSR_HWP_CAPABILITIES
2064 */
2065int print_hwp(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2066{
2067 unsigned long long msr;
2068 int cpu;
2069
2070 if (!has_hwp)
2071 return 0;
2072
2073 cpu = t->cpu_id;
2074
2075 /* MSR_HWP_CAPABILITIES is per-package */
2076 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2077 return 0;
2078
2079 if (cpu_migrate(cpu)) {
b7d8c148 2080 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
7f5c258e
LB		 2081 return -1;
2082 }
2083
2084 if (get_msr(cpu, MSR_PM_ENABLE, &msr))
2085 return 0;
2086
b7d8c148 2087 fprintf(outf, "cpu%d: MSR_PM_ENABLE: 0x%08llx (%sHWP)\n",
7f5c258e
LB		 2088 cpu, msr, (msr & (1 << 0)) ? "" : "No-");
2089
2090 /* MSR_PM_ENABLE[1] == 1 if HWP is enabled and MSRs visible */
2091 if ((msr & (1 << 0)) == 0)
2092 return 0;
2093
2094 if (get_msr(cpu, MSR_HWP_CAPABILITIES, &msr))
2095 return 0;
2096
b7d8c148 2097 fprintf(outf, "cpu%d: MSR_HWP_CAPABILITIES: 0x%08llx "
7f5c258e
LB		 2098 "(high 0x%x guar 0x%x eff 0x%x low 0x%x)\n",
2099 cpu, msr,
2100 (unsigned int)HWP_HIGHEST_PERF(msr),
2101 (unsigned int)HWP_GUARANTEED_PERF(msr),
2102 (unsigned int)HWP_MOSTEFFICIENT_PERF(msr),
2103 (unsigned int)HWP_LOWEST_PERF(msr));
2104
2105 if (get_msr(cpu, MSR_HWP_REQUEST, &msr))
2106 return 0;
2107
b7d8c148 2108 fprintf(outf, "cpu%d: MSR_HWP_REQUEST: 0x%08llx "
7f5c258e
LB		 2109 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x pkg 0x%x)\n",
2110 cpu, msr,
2111 (unsigned int)(((msr) >> 0) & 0xff),
2112 (unsigned int)(((msr) >> 8) & 0xff),
2113 (unsigned int)(((msr) >> 16) & 0xff),
2114 (unsigned int)(((msr) >> 24) & 0xff),
2115 (unsigned int)(((msr) >> 32) & 0xff3),
2116 (unsigned int)(((msr) >> 42) & 0x1));
2117
2118 if (has_hwp_pkg) {
2119 if (get_msr(cpu, MSR_HWP_REQUEST_PKG, &msr))
2120 return 0;
2121
b7d8c148 2122 fprintf(outf, "cpu%d: MSR_HWP_REQUEST_PKG: 0x%08llx "
7f5c258e
LB		 2123 "(min 0x%x max 0x%x des 0x%x epp 0x%x window 0x%x)\n",
2124 cpu, msr,
2125 (unsigned int)(((msr) >> 0) & 0xff),
2126 (unsigned int)(((msr) >> 8) & 0xff),
2127 (unsigned int)(((msr) >> 16) & 0xff),
2128 (unsigned int)(((msr) >> 24) & 0xff),
2129 (unsigned int)(((msr) >> 32) & 0xff3));
2130 }
2131 if (has_hwp_notify) {
2132 if (get_msr(cpu, MSR_HWP_INTERRUPT, &msr))
2133 return 0;
2134
b7d8c148 2135 fprintf(outf, "cpu%d: MSR_HWP_INTERRUPT: 0x%08llx "
7f5c258e
LB		 2136 "(%s_Guaranteed_Perf_Change, %s_Excursion_Min)\n",
2137 cpu, msr,
2138 ((msr) & 0x1) ? "EN" : "Dis",
2139 ((msr) & 0x2) ? "EN" : "Dis");
2140 }
2141 if (get_msr(cpu, MSR_HWP_STATUS, &msr))
2142 return 0;
2143
b7d8c148 2144 fprintf(outf, "cpu%d: MSR_HWP_STATUS: 0x%08llx "
7f5c258e
LB		 2145 "(%sGuaranteed_Perf_Change, %sExcursion_Min)\n",
2146 cpu, msr,
2147 ((msr) & 0x1) ? "" : "No-",
2148 ((msr) & 0x2) ? "" : "No-");
2149
2150 return 0;
2151}
889facbe 2152
3a9a941d
LB		 2153/*
2154 * print_perf_limit()
2155 */
2156int print_perf_limit(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2157{
2158 unsigned long long msr;
2159 int cpu;
2160
2161 cpu = t->cpu_id;
2162
2163 /* per-package */
2164 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2165 return 0;
2166
2167 if (cpu_migrate(cpu)) {
b7d8c148 2168 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
3a9a941d
LB		 2169 return -1;
2170 }
2171
2172 if (do_core_perf_limit_reasons) {
2173 get_msr(cpu, MSR_CORE_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 2174 fprintf(outf, "cpu%d: MSR_CORE_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2175 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)",
e33cbe85 2176 (msr & 1 << 15) ? "bit15, " : "",
3a9a941d 2177 (msr & 1 << 14) ? "bit14, " : "",
e33cbe85
LB		 2178 (msr & 1 << 13) ? "Transitions, " : "",
2179 (msr & 1 << 12) ? "MultiCoreTurbo, " : "",
2180 (msr & 1 << 11) ? "PkgPwrL2, " : "",
2181 (msr & 1 << 10) ? "PkgPwrL1, " : "",
2182 (msr & 1 << 9) ? "CorePwr, " : "",
2183 (msr & 1 << 8) ? "Amps, " : "",
2184 (msr & 1 << 6) ? "VR-Therm, " : "",
2185 (msr & 1 << 5) ? "Auto-HWP, " : "",
2186 (msr & 1 << 4) ? "Graphics, " : "",
2187 (msr & 1 << 2) ? "bit2, " : "",
2188 (msr & 1 << 1) ? "ThermStatus, " : "",
2189 (msr & 1 << 0) ? "PROCHOT, " : "");
b7d8c148 2190 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s%s%s%s%s%s%s)\n",
e33cbe85 2191 (msr & 1 << 31) ? "bit31, " : "",
3a9a941d 2192 (msr & 1 << 30) ? "bit30, " : "",
e33cbe85
LB		 2193 (msr & 1 << 29) ? "Transitions, " : "",
2194 (msr & 1 << 28) ? "MultiCoreTurbo, " : "",
2195 (msr & 1 << 27) ? "PkgPwrL2, " : "",
2196 (msr & 1 << 26) ? "PkgPwrL1, " : "",
2197 (msr & 1 << 25) ? "CorePwr, " : "",
2198 (msr & 1 << 24) ? "Amps, " : "",
2199 (msr & 1 << 22) ? "VR-Therm, " : "",
2200 (msr & 1 << 21) ? "Auto-HWP, " : "",
2201 (msr & 1 << 20) ? "Graphics, " : "",
2202 (msr & 1 << 18) ? "bit18, " : "",
2203 (msr & 1 << 17) ? "ThermStatus, " : "",
2204 (msr & 1 << 16) ? "PROCHOT, " : "");
3a9a941d
LB		 2205
2206 }
2207 if (do_gfx_perf_limit_reasons) {
2208 get_msr(cpu, MSR_GFX_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 2209 fprintf(outf, "cpu%d: MSR_GFX_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2210 fprintf(outf, " (Active: %s%s%s%s%s%s%s%s)",
3a9a941d
LB		 2211 (msr & 1 << 0) ? "PROCHOT, " : "",
2212 (msr & 1 << 1) ? "ThermStatus, " : "",
2213 (msr & 1 << 4) ? "Graphics, " : "",
2214 (msr & 1 << 6) ? "VR-Therm, " : "",
2215 (msr & 1 << 8) ? "Amps, " : "",
2216 (msr & 1 << 9) ? "GFXPwr, " : "",
2217 (msr & 1 << 10) ? "PkgPwrL1, " : "",
2218 (msr & 1 << 11) ? "PkgPwrL2, " : "");
b7d8c148 2219 fprintf(outf, " (Logged: %s%s%s%s%s%s%s%s)\n",
3a9a941d
LB		 2220 (msr & 1 << 16) ? "PROCHOT, " : "",
2221 (msr & 1 << 17) ? "ThermStatus, " : "",
2222 (msr & 1 << 20) ? "Graphics, " : "",
2223 (msr & 1 << 22) ? "VR-Therm, " : "",
2224 (msr & 1 << 24) ? "Amps, " : "",
2225 (msr & 1 << 25) ? "GFXPwr, " : "",
2226 (msr & 1 << 26) ? "PkgPwrL1, " : "",
2227 (msr & 1 << 27) ? "PkgPwrL2, " : "");
2228 }
2229 if (do_ring_perf_limit_reasons) {
2230 get_msr(cpu, MSR_RING_PERF_LIMIT_REASONS, &msr);
b7d8c148
LB		 2231 fprintf(outf, "cpu%d: MSR_RING_PERF_LIMIT_REASONS, 0x%08llx", cpu, msr);
2232 fprintf(outf, " (Active: %s%s%s%s%s%s)",
3a9a941d
LB		 2233 (msr & 1 << 0) ? "PROCHOT, " : "",
2234 (msr & 1 << 1) ? "ThermStatus, " : "",
2235 (msr & 1 << 6) ? "VR-Therm, " : "",
2236 (msr & 1 << 8) ? "Amps, " : "",
2237 (msr & 1 << 10) ? "PkgPwrL1, " : "",
2238 (msr & 1 << 11) ? "PkgPwrL2, " : "");
b7d8c148 2239 fprintf(outf, " (Logged: %s%s%s%s%s%s)\n",
3a9a941d
LB		 2240 (msr & 1 << 16) ? "PROCHOT, " : "",
2241 (msr & 1 << 17) ? "ThermStatus, " : "",
2242 (msr & 1 << 22) ? "VR-Therm, " : "",
2243 (msr & 1 << 24) ? "Amps, " : "",
2244 (msr & 1 << 26) ? "PkgPwrL1, " : "",
2245 (msr & 1 << 27) ? "PkgPwrL2, " : "");
2246 }
2247 return 0;
2248}
2249
889facbe
LB		 2250#define RAPL_POWER_GRANULARITY 0x7FFF /* 15 bit power granularity */
2251#define RAPL_TIME_GRANULARITY 0x3F /* 6 bit time granularity */
2252
144b44b1
LB		 2253double get_tdp(model)
2254{
2255 unsigned long long msr;
2256
2257 if (do_rapl & RAPL_PKG_POWER_INFO)
7ce7d5de 2258 if (!get_msr(base_cpu, MSR_PKG_POWER_INFO, &msr))
144b44b1
LB		 2259 return ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units;
2260
2261 switch (model) {
2262 case 0x37:
2263 case 0x4D:
2264 return 30.0;
2265 default:
2266 return 135.0;
2267 }
2268}
2269
40ee8e3b
AS		 2270/*
2271 * rapl_dram_energy_units_probe()
2272 * Energy units are either hard-coded, or come from RAPL Energy Unit MSR.
2273 */
2274static double
2275rapl_dram_energy_units_probe(int model, double rapl_energy_units)
2276{
2277 /* only called for genuine_intel, family 6 */
2278
2279 switch (model) {
2280 case 0x3F: /* HSX */
2281 case 0x4F: /* BDX */
2282 case 0x56: /* BDX-DE */
fb5d4327 2283 case 0x57: /* KNL */
40ee8e3b
AS		 2284 return (rapl_dram_energy_units = 15.3 / 1000000);
2285 default:
2286 return (rapl_energy_units);
2287 }
2288}
2289
144b44b1 2290
889facbe
LB		 2291/*
2292 * rapl_probe()
2293 *
144b44b1 2294 * sets do_rapl, rapl_power_units, rapl_energy_units, rapl_time_units
889facbe
LB		 2295 */
2296void rapl_probe(unsigned int family, unsigned int model)
2297{
2298 unsigned long long msr;
144b44b1 2299 unsigned int time_unit;
889facbe
LB		 2300 double tdp;
2301
2302 if (!genuine_intel)
2303 return;
2304
2305 if (family != 6)
2306 return;
2307
2308 switch (model) {
2309 case 0x2A:
2310 case 0x3A:
70b43400 2311 case 0x3C: /* HSW */
70b43400 2312 case 0x45: /* HSW */
149c2319 2313 case 0x46: /* HSW */
4e8e863f 2314 case 0x3D: /* BDW */
48a0631c 2315 case 0x47: /* BDW */
144b44b1 2316 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_GFX | RAPL_PKG_POWER_INFO;
889facbe 2317 break;
0b2bb692
LB		 2318 case 0x4E: /* SKL */
2319 case 0x5E: /* SKL */
2320 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
2321 break;
e6f9bb3c 2322 case 0x3F: /* HSX */
4e8e863f
LB		 2323 case 0x4F: /* BDX */
2324 case 0x56: /* BDX-DE */
fb5d4327 2325 case 0x57: /* KNL */
0b2bb692 2326 do_rapl = RAPL_PKG | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_DRAM_PERF_STATUS | RAPL_PKG_PERF_STATUS | RAPL_PKG_POWER_INFO;
e6f9bb3c 2327 break;
889facbe
LB		 2328 case 0x2D:
2329 case 0x3E:
0b2bb692 2330 do_rapl = RAPL_PKG | RAPL_CORES | RAPL_CORE_POLICY | RAPL_DRAM | RAPL_DRAM_POWER_INFO | RAPL_PKG_PERF_STATUS | RAPL_DRAM_PERF_STATUS | RAPL_PKG_POWER_INFO;
144b44b1
LB		 2331 break;
2332 case 0x37: /* BYT */
2333 case 0x4D: /* AVN */
2334 do_rapl = RAPL_PKG | RAPL_CORES ;
889facbe
LB		 2335 break;
2336 default:
2337 return;
2338 }
2339
2340 /* units on package 0, verify later other packages match */
7ce7d5de 2341 if (get_msr(base_cpu, MSR_RAPL_POWER_UNIT, &msr))
889facbe
LB		 2342 return;
2343
2344 rapl_power_units = 1.0 / (1 << (msr & 0xF));
144b44b1
LB		 2345 if (model == 0x37)
2346 rapl_energy_units = 1.0 * (1 << (msr >> 8 & 0x1F)) / 1000000;
2347 else
2348 rapl_energy_units = 1.0 / (1 << (msr >> 8 & 0x1F));
889facbe 2349
40ee8e3b
AS		 2350 rapl_dram_energy_units = rapl_dram_energy_units_probe(model, rapl_energy_units);
2351
144b44b1
LB		 2352 time_unit = msr >> 16 & 0xF;
2353 if (time_unit == 0)
2354 time_unit = 0xA;
889facbe 2355
144b44b1 2356 rapl_time_units = 1.0 / (1 << (time_unit));
889facbe 2357
144b44b1 2358 tdp = get_tdp(model);
889facbe 2359
144b44b1 2360 rapl_joule_counter_range = 0xFFFFFFFF * rapl_energy_units / tdp;
d8af6f5f 2361 if (debug)
b7d8c148 2362 fprintf(outf, "RAPL: %.0f sec. Joule Counter Range, at %.0f Watts\n", rapl_joule_counter_range, tdp);
889facbe
LB		 2363
2364 return;
2365}
2366
3a9a941d
LB		 2367void perf_limit_reasons_probe(family, model)
2368{
2369 if (!genuine_intel)
2370 return;
2371
2372 if (family != 6)
2373 return;
2374
2375 switch (model) {
2376 case 0x3C: /* HSW */
2377 case 0x45: /* HSW */
2378 case 0x46: /* HSW */
2379 do_gfx_perf_limit_reasons = 1;
2380 case 0x3F: /* HSX */
2381 do_core_perf_limit_reasons = 1;
2382 do_ring_perf_limit_reasons = 1;
2383 default:
2384 return;
2385 }
2386}
2387
889facbe
LB		 2388int print_thermal(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2389{
2390 unsigned long long msr;
2391 unsigned int dts;
2392 int cpu;
2393
2394 if (!(do_dts || do_ptm))
2395 return 0;
2396
2397 cpu = t->cpu_id;
2398
2399 /* DTS is per-core, no need to print for each thread */
2400 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE))
2401 return 0;
2402
2403 if (cpu_migrate(cpu)) {
b7d8c148 2404 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
889facbe
LB		 2405 return -1;
2406 }
2407
2408 if (do_ptm && (t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE)) {
2409 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_STATUS, &msr))
2410 return 0;
2411
2412 dts = (msr >> 16) & 0x7F;
b7d8c148 2413 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_STATUS: 0x%08llx (%d C)\n",
889facbe
LB		 2414 cpu, msr, tcc_activation_temp - dts);
2415
2416#ifdef THERM_DEBUG
2417 if (get_msr(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &msr))
2418 return 0;
2419
2420 dts = (msr >> 16) & 0x7F;
2421 dts2 = (msr >> 8) & 0x7F;
b7d8c148 2422 fprintf(outf, "cpu%d: MSR_IA32_PACKAGE_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
889facbe
LB		 2423 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
2424#endif
2425 }
2426
2427
2428 if (do_dts) {
2429 unsigned int resolution;
2430
2431 if (get_msr(cpu, MSR_IA32_THERM_STATUS, &msr))
2432 return 0;
2433
2434 dts = (msr >> 16) & 0x7F;
2435 resolution = (msr >> 27) & 0xF;
b7d8c148 2436 fprintf(outf, "cpu%d: MSR_IA32_THERM_STATUS: 0x%08llx (%d C +/- %d)\n",
889facbe
LB		 2437 cpu, msr, tcc_activation_temp - dts, resolution);
2438
2439#ifdef THERM_DEBUG
2440 if (get_msr(cpu, MSR_IA32_THERM_INTERRUPT, &msr))
2441 return 0;
2442
2443 dts = (msr >> 16) & 0x7F;
2444 dts2 = (msr >> 8) & 0x7F;
b7d8c148 2445 fprintf(outf, "cpu%d: MSR_IA32_THERM_INTERRUPT: 0x%08llx (%d C, %d C)\n",
889facbe
LB		 2446 cpu, msr, tcc_activation_temp - dts, tcc_activation_temp - dts2);
2447#endif
2448 }
2449
2450 return 0;
2451}
2452
2453void print_power_limit_msr(int cpu, unsigned long long msr, char *label)
2454{
b7d8c148 2455 fprintf(outf, "cpu%d: %s: %sabled (%f Watts, %f sec, clamp %sabled)\n",
889facbe
LB		 2456 cpu, label,
2457 ((msr >> 15) & 1) ? "EN" : "DIS",
2458 ((msr >> 0) & 0x7FFF) * rapl_power_units,
2459 (1.0 + (((msr >> 22) & 0x3)/4.0)) * (1 << ((msr >> 17) & 0x1F)) * rapl_time_units,
2460 (((msr >> 16) & 1) ? "EN" : "DIS"));
2461
2462 return;
2463}
2464
2465int print_rapl(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2466{
2467 unsigned long long msr;
2468 int cpu;
889facbe
LB		 2469
2470 if (!do_rapl)
2471 return 0;
2472
2473 /* RAPL counters are per package, so print only for 1st thread/package */
2474 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2475 return 0;
2476
2477 cpu = t->cpu_id;
2478 if (cpu_migrate(cpu)) {
b7d8c148 2479 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
889facbe
LB		 2480 return -1;
2481 }
2482
2483 if (get_msr(cpu, MSR_RAPL_POWER_UNIT, &msr))
2484 return -1;
2485
d8af6f5f 2486 if (debug) {
b7d8c148 2487 fprintf(outf, "cpu%d: MSR_RAPL_POWER_UNIT: 0x%08llx "
889facbe 2488 "(%f Watts, %f Joules, %f sec.)\n", cpu, msr,
144b44b1 2489 rapl_power_units, rapl_energy_units, rapl_time_units);
889facbe 2490 }
144b44b1
LB		 2491 if (do_rapl & RAPL_PKG_POWER_INFO) {
2492
889facbe
LB		 2493 if (get_msr(cpu, MSR_PKG_POWER_INFO, &msr))
2494 return -5;
2495
2496
b7d8c148 2497 fprintf(outf, "cpu%d: MSR_PKG_POWER_INFO: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
889facbe
LB		 2498 cpu, msr,
2499 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
2500 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
2501 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
2502 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
2503
144b44b1
LB		 2504 }
2505 if (do_rapl & RAPL_PKG) {
2506
889facbe
LB		 2507 if (get_msr(cpu, MSR_PKG_POWER_LIMIT, &msr))
2508 return -9;
2509
b7d8c148 2510 fprintf(outf, "cpu%d: MSR_PKG_POWER_LIMIT: 0x%08llx (%slocked)\n",
889facbe
LB		 2511 cpu, msr, (msr >> 63) & 1 ? "": "UN");
2512
2513 print_power_limit_msr(cpu, msr, "PKG Limit #1");
b7d8c148 2514 fprintf(outf, "cpu%d: PKG Limit #2: %sabled (%f Watts, %f* sec, clamp %sabled)\n",
889facbe
LB		 2515 cpu,
2516 ((msr >> 47) & 1) ? "EN" : "DIS",
2517 ((msr >> 32) & 0x7FFF) * rapl_power_units,
2518 (1.0 + (((msr >> 54) & 0x3)/4.0)) * (1 << ((msr >> 49) & 0x1F)) * rapl_time_units,
2519 ((msr >> 48) & 1) ? "EN" : "DIS");
2520 }
2521
0b2bb692 2522 if (do_rapl & RAPL_DRAM_POWER_INFO) {
889facbe
LB		 2523 if (get_msr(cpu, MSR_DRAM_POWER_INFO, &msr))
2524 return -6;
2525
b7d8c148 2526 fprintf(outf, "cpu%d: MSR_DRAM_POWER_INFO,: 0x%08llx (%.0f W TDP, RAPL %.0f - %.0f W, %f sec.)\n",
889facbe
LB		 2527 cpu, msr,
2528 ((msr >> 0) & RAPL_POWER_GRANULARITY) * rapl_power_units,
2529 ((msr >> 16) & RAPL_POWER_GRANULARITY) * rapl_power_units,
2530 ((msr >> 32) & RAPL_POWER_GRANULARITY) * rapl_power_units,
2531 ((msr >> 48) & RAPL_TIME_GRANULARITY) * rapl_time_units);
0b2bb692
LB		 2532 }
2533 if (do_rapl & RAPL_DRAM) {
889facbe
LB		 2534 if (get_msr(cpu, MSR_DRAM_POWER_LIMIT, &msr))
2535 return -9;
b7d8c148 2536 fprintf(outf, "cpu%d: MSR_DRAM_POWER_LIMIT: 0x%08llx (%slocked)\n",
889facbe
LB		 2537 cpu, msr, (msr >> 31) & 1 ? "": "UN");
2538
2539 print_power_limit_msr(cpu, msr, "DRAM Limit");
2540 }
144b44b1 2541 if (do_rapl & RAPL_CORE_POLICY) {
d8af6f5f 2542 if (debug) {
889facbe
LB		 2543 if (get_msr(cpu, MSR_PP0_POLICY, &msr))
2544 return -7;
2545
b7d8c148 2546 fprintf(outf, "cpu%d: MSR_PP0_POLICY: %lld\n", cpu, msr & 0xF);
144b44b1
LB		 2547 }
2548 }
2549 if (do_rapl & RAPL_CORES) {
d8af6f5f 2550 if (debug) {
889facbe
LB		 2551
2552 if (get_msr(cpu, MSR_PP0_POWER_LIMIT, &msr))
2553 return -9;
b7d8c148 2554 fprintf(outf, "cpu%d: MSR_PP0_POWER_LIMIT: 0x%08llx (%slocked)\n",
889facbe
LB		 2555 cpu, msr, (msr >> 31) & 1 ? "": "UN");
2556 print_power_limit_msr(cpu, msr, "Cores Limit");
2557 }
2558 }
2559 if (do_rapl & RAPL_GFX) {
d8af6f5f 2560 if (debug) {
889facbe
LB		 2561 if (get_msr(cpu, MSR_PP1_POLICY, &msr))
2562 return -8;
2563
b7d8c148 2564 fprintf(outf, "cpu%d: MSR_PP1_POLICY: %lld\n", cpu, msr & 0xF);
889facbe
LB		 2565
2566 if (get_msr(cpu, MSR_PP1_POWER_LIMIT, &msr))
2567 return -9;
b7d8c148 2568 fprintf(outf, "cpu%d: MSR_PP1_POWER_LIMIT: 0x%08llx (%slocked)\n",
889facbe
LB		 2569 cpu, msr, (msr >> 31) & 1 ? "": "UN");
2570 print_power_limit_msr(cpu, msr, "GFX Limit");
2571 }
2572 }
2573 return 0;
2574}
2575
d7899447
LB		 2576/*
2577 * SNB adds support for additional MSRs:
2578 *
2579 * MSR_PKG_C7_RESIDENCY 0x000003fa
2580 * MSR_CORE_C7_RESIDENCY 0x000003fe
2581 * MSR_PKG_C2_RESIDENCY 0x0000060d
2582 */
103a8fea 2583
d7899447 2584int has_snb_msrs(unsigned int family, unsigned int model)
103a8fea
LB		 2585{
2586 if (!genuine_intel)
2587 return 0;
2588
2589 switch (model) {
2590 case 0x2A:
2591 case 0x2D:
650a37f3 2592 case 0x3A: /* IVB */
1300651b 2593 case 0x3E: /* IVB Xeon */
70b43400
LB		 2594 case 0x3C: /* HSW */
2595 case 0x3F: /* HSW */
2596 case 0x45: /* HSW */
149c2319 2597 case 0x46: /* HSW */
4e8e863f 2598 case 0x3D: /* BDW */
48a0631c 2599 case 0x47: /* BDW */
4e8e863f
LB		 2600 case 0x4F: /* BDX */
2601 case 0x56: /* BDX-DE */
0b2bb692
LB		 2602 case 0x4E: /* SKL */
2603 case 0x5E: /* SKL */
103a8fea
LB		 2604 return 1;
2605 }
2606 return 0;
2607}
2608
d7899447
LB		 2609/*
2610 * HSW adds support for additional MSRs:
2611 *
2612 * MSR_PKG_C8_RESIDENCY 0x00000630
2613 * MSR_PKG_C9_RESIDENCY 0x00000631
2614 * MSR_PKG_C10_RESIDENCY 0x00000632
2615 */
2616int has_hsw_msrs(unsigned int family, unsigned int model)
ca58710f
KCA		 2617{
2618 if (!genuine_intel)
2619 return 0;
2620
2621 switch (model) {
4e8e863f
LB		 2622 case 0x45: /* HSW */
2623 case 0x3D: /* BDW */
0b2bb692
LB		 2624 case 0x4E: /* SKL */
2625 case 0x5E: /* SKL */
2626 return 1;
2627 }
2628 return 0;
2629}
2630
2631/*
2632 * SKL adds support for additional MSRS:
2633 *
2634 * MSR_PKG_WEIGHTED_CORE_C0_RES 0x00000658
2635 * MSR_PKG_ANY_CORE_C0_RES 0x00000659
2636 * MSR_PKG_ANY_GFXE_C0_RES 0x0000065A
2637 * MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x0000065B
2638 */
2639int has_skl_msrs(unsigned int family, unsigned int model)
2640{
2641 if (!genuine_intel)
2642 return 0;
2643
2644 switch (model) {
2645 case 0x4E: /* SKL */
2646 case 0x5E: /* SKL */
ca58710f
KCA		 2647 return 1;
2648 }
2649 return 0;
2650}
2651
2652
0b2bb692 2653
144b44b1
LB		 2654int is_slm(unsigned int family, unsigned int model)
2655{
2656 if (!genuine_intel)
2657 return 0;
2658 switch (model) {
2659 case 0x37: /* BYT */
2660 case 0x4D: /* AVN */
2661 return 1;
2662 }
2663 return 0;
2664}
2665
fb5d4327
DC		 2666int is_knl(unsigned int family, unsigned int model)
2667{
2668 if (!genuine_intel)
2669 return 0;
2670 switch (model) {
2671 case 0x57: /* KNL */
2672 return 1;
2673 }
2674 return 0;
2675}
2676
b2b34dfe
HC		 2677unsigned int get_aperf_mperf_multiplier(unsigned int family, unsigned int model)
2678{
2679 if (is_knl(family, model))
2680 return 1024;
2681 return 1;
2682}
2683
144b44b1
LB		 2684#define SLM_BCLK_FREQS 5
2685double slm_freq_table[SLM_BCLK_FREQS] = { 83.3, 100.0, 133.3, 116.7, 80.0};
2686
2687double slm_bclk(void)
2688{
2689 unsigned long long msr = 3;
2690 unsigned int i;
2691 double freq;
2692
7ce7d5de 2693 if (get_msr(base_cpu, MSR_FSB_FREQ, &msr))
b7d8c148 2694 fprintf(outf, "SLM BCLK: unknown\n");
144b44b1
LB		 2695
2696 i = msr & 0xf;
2697 if (i >= SLM_BCLK_FREQS) {
b7d8c148 2698 fprintf(outf, "SLM BCLK[%d] invalid\n", i);
144b44b1
LB		 2699 msr = 3;
2700 }
2701 freq = slm_freq_table[i];
2702
b7d8c148 2703 fprintf(outf, "SLM BCLK: %.1f Mhz\n", freq);
144b44b1
LB		 2704
2705 return freq;
2706}
2707
103a8fea
LB		 2708double discover_bclk(unsigned int family, unsigned int model)
2709{
121b48bb 2710 if (has_snb_msrs(family, model) || is_knl(family, model))
103a8fea 2711 return 100.00;
144b44b1
LB		 2712 else if (is_slm(family, model))
2713 return slm_bclk();
103a8fea
LB		 2714 else
2715 return 133.33;
2716}
2717
889facbe
LB		 2718/*
2719 * MSR_IA32_TEMPERATURE_TARGET indicates the temperature where
2720 * the Thermal Control Circuit (TCC) activates.
2721 * This is usually equal to tjMax.
2722 *
2723 * Older processors do not have this MSR, so there we guess,
2724 * but also allow cmdline over-ride with -T.
2725 *
2726 * Several MSR temperature values are in units of degrees-C
2727 * below this value, including the Digital Thermal Sensor (DTS),
2728 * Package Thermal Management Sensor (PTM), and thermal event thresholds.
2729 */
2730int set_temperature_target(struct thread_data *t, struct core_data *c, struct pkg_data *p)
2731{
2732 unsigned long long msr;
2733 unsigned int target_c_local;
2734 int cpu;
2735
2736 /* tcc_activation_temp is used only for dts or ptm */
2737 if (!(do_dts || do_ptm))
2738 return 0;
2739
2740 /* this is a per-package concept */
2741 if (!(t->flags & CPU_IS_FIRST_THREAD_IN_CORE) || !(t->flags & CPU_IS_FIRST_CORE_IN_PACKAGE))
2742 return 0;
2743
2744 cpu = t->cpu_id;
2745 if (cpu_migrate(cpu)) {
b7d8c148 2746 fprintf(outf, "Could not migrate to CPU %d\n", cpu);
889facbe
LB		 2747 return -1;
2748 }
2749
2750 if (tcc_activation_temp_override != 0) {
2751 tcc_activation_temp = tcc_activation_temp_override;
b7d8c148 2752 fprintf(outf, "cpu%d: Using cmdline TCC Target (%d C)\n",
889facbe
LB		 2753 cpu, tcc_activation_temp);
2754 return 0;
2755 }
2756
2757 /* Temperature Target MSR is Nehalem and newer only */
d7899447 2758 if (!do_nhm_platform_info)
889facbe
LB		 2759 goto guess;
2760
7ce7d5de 2761 if (get_msr(base_cpu, MSR_IA32_TEMPERATURE_TARGET, &msr))
889facbe
LB		 2762 goto guess;
2763
3482124a 2764 target_c_local = (msr >> 16) & 0xFF;
889facbe 2765
d8af6f5f 2766 if (debug)
b7d8c148 2767 fprintf(outf, "cpu%d: MSR_IA32_TEMPERATURE_TARGET: 0x%08llx (%d C)\n",
889facbe
LB		 2768 cpu, msr, target_c_local);
2769
3482124a 2770 if (!target_c_local)
889facbe
LB		 2771 goto guess;
2772
2773 tcc_activation_temp = target_c_local;
2774
2775 return 0;
2776
2777guess:
2778 tcc_activation_temp = TJMAX_DEFAULT;
b7d8c148 2779 fprintf(outf, "cpu%d: Guessing tjMax %d C, Please use -T to specify\n",
889facbe
LB		 2780 cpu, tcc_activation_temp);
2781
2782 return 0;
2783}
69807a63
LB		 2784
2785void decode_misc_enable_msr(void)
2786{
2787 unsigned long long msr;
2788
2789 if (!get_msr(base_cpu, MSR_IA32_MISC_ENABLE, &msr))
b7d8c148 2790 fprintf(outf, "cpu%d: MSR_IA32_MISC_ENABLE: 0x%08llx (%s %s %s)\n",
69807a63
LB		 2791 base_cpu, msr,
2792 msr & (1 << 3) ? "TCC" : "",
2793 msr & (1 << 16) ? "EIST" : "",
2794 msr & (1 << 18) ? "MONITOR" : "");
2795}
2796
f0057310
LB		 2797/*
2798 * Decode MSR_MISC_PWR_MGMT
2799 *
2800 * Decode the bits according to the Nehalem documentation
2801 * bit[0] seems to continue to have same meaning going forward
2802 * bit[1] less so...
2803 */
2804void decode_misc_pwr_mgmt_msr(void)
2805{
2806 unsigned long long msr;
2807
2808 if (!do_nhm_platform_info)
2809 return;
2810
2811 if (!get_msr(base_cpu, MSR_MISC_PWR_MGMT, &msr))
b7d8c148 2812 fprintf(outf, "cpu%d: MSR_MISC_PWR_MGMT: 0x%08llx (%sable-EIST_Coordination %sable-EPB)\n",
f0057310
LB		 2813 base_cpu, msr,
2814 msr & (1 << 0) ? "DIS" : "EN",
2815 msr & (1 << 1) ? "EN" : "DIS");
2816}
7f5c258e 2817
fcd17211 2818void process_cpuid()
103a8fea 2819{
61a87ba7 2820 unsigned int eax, ebx, ecx, edx, max_level, max_extended_level;
103a8fea
LB		 2821 unsigned int fms, family, model, stepping;
2822
2823 eax = ebx = ecx = edx = 0;
2824
2b92865e 2825 __get_cpuid(0, &max_level, &ebx, &ecx, &edx);
103a8fea
LB		 2826
2827 if (ebx == 0x756e6547 && edx == 0x49656e69 && ecx == 0x6c65746e)
2828 genuine_intel = 1;
2829
d8af6f5f 2830 if (debug)
b7d8c148 2831 fprintf(outf, "CPUID(0): %.4s%.4s%.4s ",
103a8fea
LB		 2832 (char *)&ebx, (char *)&edx, (char *)&ecx);
2833
2b92865e 2834 __get_cpuid(1, &fms, &ebx, &ecx, &edx);
103a8fea
LB		 2835 family = (fms >> 8) & 0xf;
2836 model = (fms >> 4) & 0xf;
2837 stepping = fms & 0xf;
2838 if (family == 6 || family == 0xf)
2839 model += ((fms >> 16) & 0xf) << 4;
2840
69807a63 2841 if (debug) {
b7d8c148 2842 fprintf(outf, "%d CPUID levels; family:model:stepping 0x%x:%x:%x (%d:%d:%d)\n",
103a8fea 2843 max_level, family, model, stepping, family, model, stepping);
b7d8c148 2844 fprintf(outf, "CPUID(1): %s %s %s %s %s %s %s %s\n",
69807a63
LB		 2845 ecx & (1 << 0) ? "SSE3" : "-",
2846 ecx & (1 << 3) ? "MONITOR" : "-",
2847 ecx & (1 << 7) ? "EIST" : "-",
2848 ecx & (1 << 8) ? "TM2" : "-",
2849 edx & (1 << 4) ? "TSC" : "-",
2850 edx & (1 << 5) ? "MSR" : "-",
2851 edx & (1 << 22) ? "ACPI-TM" : "-",
2852 edx & (1 << 29) ? "TM" : "-");
2853 }
103a8fea 2854
b2c95d90
JT		 2855 if (!(edx & (1 << 5)))
2856 errx(1, "CPUID: no MSR");
103a8fea
LB		 2857
2858 /*
2859 * check max extended function levels of CPUID.
2860 * This is needed to check for invariant TSC.
2861 * This check is valid for both Intel and AMD.
2862 */
2863 ebx = ecx = edx = 0;
61a87ba7 2864 __get_cpuid(0x80000000, &max_extended_level, &ebx, &ecx, &edx);
103a8fea 2865
61a87ba7 2866 if (max_extended_level >= 0x80000007) {
103a8fea 2867
d7899447
LB		 2868 /*
2869 * Non-Stop TSC is advertised by CPUID.EAX=0x80000007: EDX.bit8
2870 * this check is valid for both Intel and AMD
2871 */
2872 __get_cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
2873 has_invariant_tsc = edx & (1 << 8);
2874 }
103a8fea
LB		 2875
2876 /*
2877 * APERF/MPERF is advertised by CPUID.EAX=0x6: ECX.bit0
2878 * this check is valid for both Intel and AMD
2879 */
2880
2b92865e 2881 __get_cpuid(0x6, &eax, &ebx, &ecx, &edx);
8209e054 2882 has_aperf = ecx & (1 << 0);
889facbe
LB		 2883 do_dts = eax & (1 << 0);
2884 do_ptm = eax & (1 << 6);
7f5c258e
LB		 2885 has_hwp = eax & (1 << 7);
2886 has_hwp_notify = eax & (1 << 8);
2887 has_hwp_activity_window = eax & (1 << 9);
2888 has_hwp_epp = eax & (1 << 10);
2889 has_hwp_pkg = eax & (1 << 11);
889facbe
LB		 2890 has_epb = ecx & (1 << 3);
2891
d8af6f5f 2892 if (debug)
b7d8c148 2893 fprintf(outf, "CPUID(6): %sAPERF, %sDTS, %sPTM, %sHWP, "
7f5c258e
LB		 2894 "%sHWPnotify, %sHWPwindow, %sHWPepp, %sHWPpkg, %sEPB\n",
2895 has_aperf ? "" : "No-",
2896 do_dts ? "" : "No-",
2897 do_ptm ? "" : "No-",
2898 has_hwp ? "" : "No-",
2899 has_hwp_notify ? "" : "No-",
2900 has_hwp_activity_window ? "" : "No-",
2901 has_hwp_epp ? "" : "No-",
2902 has_hwp_pkg ? "" : "No-",
2903 has_epb ? "" : "No-");
103a8fea 2904
69807a63
LB		 2905 if (debug)
2906 decode_misc_enable_msr();
2907
61a87ba7 2908 if (max_level >= 0x15) {
8a5bdf41
LB		 2909 unsigned int eax_crystal;
2910 unsigned int ebx_tsc;
2911
2912 /*
2913 * CPUID 15H TSC/Crystal ratio, possibly Crystal Hz
2914 */
2915 eax_crystal = ebx_tsc = crystal_hz = edx = 0;
2916 __get_cpuid(0x15, &eax_crystal, &ebx_tsc, &crystal_hz, &edx);
2917
2918 if (ebx_tsc != 0) {
2919
2920 if (debug && (ebx != 0))
b7d8c148 2921 fprintf(outf, "CPUID(0x15): eax_crystal: %d ebx_tsc: %d ecx_crystal_hz: %d\n",
8a5bdf41
LB		 2922 eax_crystal, ebx_tsc, crystal_hz);
2923
2924 if (crystal_hz == 0)
2925 switch(model) {
2926 case 0x4E: /* SKL */
2927 case 0x5E: /* SKL */
2928 crystal_hz = 24000000; /* 24 MHz */
2929 break;
2930 default:
2931 crystal_hz = 0;
2932 }
2933
2934 if (crystal_hz) {
2935 tsc_hz = (unsigned long long) crystal_hz * ebx_tsc / eax_crystal;
2936 if (debug)
b7d8c148 2937 fprintf(outf, "TSC: %lld MHz (%d Hz * %d / %d / 1000000)\n",
8a5bdf41
LB		 2938 tsc_hz / 1000000, crystal_hz, ebx_tsc, eax_crystal);
2939 }
2940 }
2941 }
61a87ba7
LB		 2942 if (max_level >= 0x16) {
2943 unsigned int base_mhz, max_mhz, bus_mhz, edx;
2944
2945 /*
2946 * CPUID 16H Base MHz, Max MHz, Bus MHz
2947 */
2948 base_mhz = max_mhz = bus_mhz = edx = 0;
2949
2950 __get_cpuid(0x16, &base_mhz, &max_mhz, &bus_mhz, &edx);
2951 if (debug)
b7d8c148 2952 fprintf(outf, "CPUID(0x16): base_mhz: %d max_mhz: %d bus_mhz: %d\n",
61a87ba7
LB		 2953 base_mhz, max_mhz, bus_mhz);
2954 }
8a5bdf41 2955
b2b34dfe
HC		 2956 if (has_aperf)
2957 aperf_mperf_multiplier = get_aperf_mperf_multiplier(family, model);
2958
ee7e38e3 2959 do_nhm_platform_info = do_nhm_cstates = do_smi = probe_nhm_msrs(family, model);
d7899447 2960 do_snb_cstates = has_snb_msrs(family, model);
ee7e38e3
LB		 2961 do_pc2 = do_snb_cstates && (pkg_cstate_limit >= PCL__2);
2962 do_pc3 = (pkg_cstate_limit >= PCL__3);
2963 do_pc6 = (pkg_cstate_limit >= PCL__6);
2964 do_pc7 = do_snb_cstates && (pkg_cstate_limit >= PCL__7);
d7899447 2965 do_c8_c9_c10 = has_hsw_msrs(family, model);
0b2bb692 2966 do_skl_residency = has_skl_msrs(family, model);
144b44b1 2967 do_slm_cstates = is_slm(family, model);
fb5d4327 2968 do_knl_cstates = is_knl(family, model);
103a8fea 2969
f0057310
LB		 2970 if (debug)
2971 decode_misc_pwr_mgmt_msr();
2972
889facbe 2973 rapl_probe(family, model);
3a9a941d 2974 perf_limit_reasons_probe(family, model);
889facbe 2975
fcd17211
LB		 2976 if (debug)
2977 dump_cstate_pstate_config_info();
2978
a2b7b749
LB		 2979 if (has_skl_msrs(family, model))
2980 calculate_tsc_tweak();
2981
889facbe 2982 return;
103a8fea
LB		 2983}
2984
d8af6f5f 2985void help()
103a8fea 2986{
b7d8c148 2987 fprintf(outf,
d8af6f5f
LB		 2988 "Usage: turbostat [OPTIONS][(--interval seconds) | COMMAND ...]\n"
2989 "\n"
2990 "Turbostat forks the specified COMMAND and prints statistics\n"
2991 "when COMMAND completes.\n"
2992 "If no COMMAND is specified, turbostat wakes every 5-seconds\n"
2993 "to print statistics, until interrupted.\n"
2994 "--debug run in \"debug\" mode\n"
2995 "--interval sec Override default 5-second measurement interval\n"
2996 "--help print this help message\n"
2997 "--counter msr print 32-bit counter at address \"msr\"\n"
2998 "--Counter msr print 64-bit Counter at address \"msr\"\n"
b7d8c148 2999 "--out file create or truncate \"file\" for all output\n"
d8af6f5f
LB		 3000 "--msr msr print 32-bit value at address \"msr\"\n"
3001 "--MSR msr print 64-bit Value at address \"msr\"\n"
3002 "--version print version information\n"
3003 "\n"
3004 "For more help, run \"man turbostat\"\n");
103a8fea
LB		 3005}
3006
3007
3008/*
3009 * in /dev/cpu/ return success for names that are numbers
3010 * ie. filter out ".", "..", "microcode".
3011 */
3012int dir_filter(const struct dirent *dirp)
3013{
3014 if (isdigit(dirp->d_name[0]))
3015 return 1;
3016 else
3017 return 0;
3018}
3019
3020int open_dev_cpu_msr(int dummy1)
3021{
3022 return 0;
3023}
3024
c98d5d94
LB		 3025void topology_probe()
3026{
3027 int i;
3028 int max_core_id = 0;
3029 int max_package_id = 0;
3030 int max_siblings = 0;
3031 struct cpu_topology {
3032 int core_id;
3033 int physical_package_id;
3034 } *cpus;
3035
3036 /* Initialize num_cpus, max_cpu_num */
3037 topo.num_cpus = 0;
3038 topo.max_cpu_num = 0;
3039 for_all_proc_cpus(count_cpus);
3040 if (!summary_only && topo.num_cpus > 1)
3041 show_cpu = 1;
3042
d8af6f5f 3043 if (debug > 1)
b7d8c148 3044 fprintf(outf, "num_cpus %d max_cpu_num %d\n", topo.num_cpus, topo.max_cpu_num);
c98d5d94
LB		 3045
3046 cpus = calloc(1, (topo.max_cpu_num + 1) * sizeof(struct cpu_topology));
b2c95d90
JT		 3047 if (cpus == NULL)
3048 err(1, "calloc cpus");
c98d5d94
LB		 3049
3050 /*
3051 * Allocate and initialize cpu_present_set
3052 */
3053 cpu_present_set = CPU_ALLOC((topo.max_cpu_num + 1));
b2c95d90
JT		 3054 if (cpu_present_set == NULL)
3055 err(3, "CPU_ALLOC");
c98d5d94
LB		 3056 cpu_present_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
3057 CPU_ZERO_S(cpu_present_setsize, cpu_present_set);
3058 for_all_proc_cpus(mark_cpu_present);
3059
3060 /*
3061 * Allocate and initialize cpu_affinity_set
3062 */
3063 cpu_affinity_set = CPU_ALLOC((topo.max_cpu_num + 1));
b2c95d90
JT		 3064 if (cpu_affinity_set == NULL)
3065 err(3, "CPU_ALLOC");
c98d5d94
LB		 3066 cpu_affinity_setsize = CPU_ALLOC_SIZE((topo.max_cpu_num + 1));
3067 CPU_ZERO_S(cpu_affinity_setsize, cpu_affinity_set);
3068
3069
3070 /*
3071 * For online cpus
3072 * find max_core_id, max_package_id
3073 */
3074 for (i = 0; i <= topo.max_cpu_num; ++i) {
3075 int siblings;
3076
3077 if (cpu_is_not_present(i)) {
d8af6f5f 3078 if (debug > 1)
b7d8c148 3079 fprintf(outf, "cpu%d NOT PRESENT\n", i);
c98d5d94
LB		 3080 continue;
3081 }
3082 cpus[i].core_id = get_core_id(i);
3083 if (cpus[i].core_id > max_core_id)
3084 max_core_id = cpus[i].core_id;
3085
3086 cpus[i].physical_package_id = get_physical_package_id(i);
3087 if (cpus[i].physical_package_id > max_package_id)
3088 max_package_id = cpus[i].physical_package_id;
3089
3090 siblings = get_num_ht_siblings(i);
3091 if (siblings > max_siblings)
3092 max_siblings = siblings;
d8af6f5f 3093 if (debug > 1)
b7d8c148 3094 fprintf(outf, "cpu %d pkg %d core %d\n",
c98d5d94
LB		 3095 i, cpus[i].physical_package_id, cpus[i].core_id);
3096 }
3097 topo.num_cores_per_pkg = max_core_id + 1;
d8af6f5f 3098 if (debug > 1)
b7d8c148 3099 fprintf(outf, "max_core_id %d, sizing for %d cores per package\n",
c98d5d94 3100 max_core_id, topo.num_cores_per_pkg);
1cc21f7b 3101 if (debug && !summary_only && topo.num_cores_per_pkg > 1)
c98d5d94
LB		 3102 show_core = 1;
3103
3104 topo.num_packages = max_package_id + 1;
d8af6f5f 3105 if (debug > 1)
b7d8c148 3106 fprintf(outf, "max_package_id %d, sizing for %d packages\n",
c98d5d94 3107 max_package_id, topo.num_packages);
1cc21f7b 3108 if (debug && !summary_only && topo.num_packages > 1)
c98d5d94
LB		 3109 show_pkg = 1;
3110
3111 topo.num_threads_per_core = max_siblings;
d8af6f5f 3112 if (debug > 1)
b7d8c148 3113 fprintf(outf, "max_siblings %d\n", max_siblings);
c98d5d94
LB		 3114
3115 free(cpus);
3116}
3117
3118void
3119allocate_counters(struct thread_data **t, struct core_data **c, struct pkg_data **p)
3120{
3121 int i;
3122
3123 *t = calloc(topo.num_threads_per_core * topo.num_cores_per_pkg *
3124 topo.num_packages, sizeof(struct thread_data));
3125 if (*t == NULL)
3126 goto error;
3127
3128 for (i = 0; i < topo.num_threads_per_core *
3129 topo.num_cores_per_pkg * topo.num_packages; i++)
3130 (*t)[i].cpu_id = -1;
3131
3132 *c = calloc(topo.num_cores_per_pkg * topo.num_packages,
3133 sizeof(struct core_data));
3134 if (*c == NULL)
3135 goto error;
3136
3137 for (i = 0; i < topo.num_cores_per_pkg * topo.num_packages; i++)
3138 (*c)[i].core_id = -1;
3139
3140 *p = calloc(topo.num_packages, sizeof(struct pkg_data));
3141 if (*p == NULL)
3142 goto error;
3143
3144 for (i = 0; i < topo.num_packages; i++)
3145 (*p)[i].package_id = i;
3146
3147 return;
3148error:
b2c95d90 3149 err(1, "calloc counters");
c98d5d94
LB		 3150}
3151/*
3152 * init_counter()
3153 *
3154 * set cpu_id, core_num, pkg_num
3155 * set FIRST_THREAD_IN_CORE and FIRST_CORE_IN_PACKAGE
3156 *
3157 * increment topo.num_cores when 1st core in pkg seen
3158 */
3159void init_counter(struct thread_data *thread_base, struct core_data *core_base,
3160 struct pkg_data *pkg_base, int thread_num, int core_num,
3161 int pkg_num, int cpu_id)
3162{
3163 struct thread_data *t;
3164 struct core_data *c;
3165 struct pkg_data *p;
3166
3167 t = GET_THREAD(thread_base, thread_num, core_num, pkg_num);
3168 c = GET_CORE(core_base, core_num, pkg_num);
3169 p = GET_PKG(pkg_base, pkg_num);
3170
3171 t->cpu_id = cpu_id;
3172 if (thread_num == 0) {
3173 t->flags |= CPU_IS_FIRST_THREAD_IN_CORE;
3174 if (cpu_is_first_core_in_package(cpu_id))
3175 t->flags |= CPU_IS_FIRST_CORE_IN_PACKAGE;
3176 }
3177
3178 c->core_id = core_num;
3179 p->package_id = pkg_num;
3180}
3181
3182
3183int initialize_counters(int cpu_id)
3184{
3185 int my_thread_id, my_core_id, my_package_id;
3186
3187 my_package_id = get_physical_package_id(cpu_id);
3188 my_core_id = get_core_id(cpu_id);
e275b388
DC		 3189 my_thread_id = get_cpu_position_in_core(cpu_id);
3190 if (!my_thread_id)
c98d5d94 3191 topo.num_cores++;
c98d5d94
LB		 3192
3193 init_counter(EVEN_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id);
3194 init_counter(ODD_COUNTERS, my_thread_id, my_core_id, my_package_id, cpu_id);
3195 return 0;
3196}
3197
3198void allocate_output_buffer()
3199{
3b4d5c7f 3200 output_buffer = calloc(1, (1 + topo.num_cpus) * 1024);
c98d5d94 3201 outp = output_buffer;
b2c95d90
JT		 3202 if (outp == NULL)
3203 err(-1, "calloc output buffer");
c98d5d94
LB		 3204}
3205
3206void setup_all_buffers(void)
3207{
3208 topology_probe();
3209 allocate_counters(&thread_even, &core_even, &package_even);
3210 allocate_counters(&thread_odd, &core_odd, &package_odd);
3211 allocate_output_buffer();
3212 for_all_proc_cpus(initialize_counters);
3213}
3b4d5c7f 3214
7ce7d5de
PB		 3215void set_base_cpu(void)
3216{
3217 base_cpu = sched_getcpu();
3218 if (base_cpu < 0)
3219 err(-ENODEV, "No valid cpus found");
3220
3221 if (debug > 1)
b7d8c148 3222 fprintf(outf, "base_cpu = %d\n", base_cpu);
7ce7d5de
PB		 3223}
3224
103a8fea
LB		 3225void turbostat_init()
3226{
7ce7d5de
PB		 3227 setup_all_buffers();
3228 set_base_cpu();
103a8fea 3229 check_dev_msr();
98481e79 3230 check_permissions();
fcd17211 3231 process_cpuid();
103a8fea 3232
103a8fea 3233
7f5c258e
LB		 3234 if (debug)
3235 for_all_cpus(print_hwp, ODD_COUNTERS);
3236
d8af6f5f 3237 if (debug)
889facbe
LB		 3238 for_all_cpus(print_epb, ODD_COUNTERS);
3239
d8af6f5f 3240 if (debug)
3a9a941d
LB		 3241 for_all_cpus(print_perf_limit, ODD_COUNTERS);
3242
d8af6f5f 3243 if (debug)
889facbe
LB		 3244 for_all_cpus(print_rapl, ODD_COUNTERS);
3245
3246 for_all_cpus(set_temperature_target, ODD_COUNTERS);
3247
d8af6f5f 3248 if (debug)
889facbe 3249 for_all_cpus(print_thermal, ODD_COUNTERS);
103a8fea
LB		 3250}
3251
3252int fork_it(char **argv)
3253{
103a8fea 3254 pid_t child_pid;
d91bb17c 3255 int status;
d15cf7c1 3256
d91bb17c
LB		 3257 status = for_all_cpus(get_counters, EVEN_COUNTERS);
3258 if (status)
3259 exit(status);
c98d5d94
LB		 3260 /* clear affinity side-effect of get_counters() */
3261 sched_setaffinity(0, cpu_present_setsize, cpu_present_set);
103a8fea
LB		 3262 gettimeofday(&tv_even, (struct timezone *)NULL);
3263
3264 child_pid = fork();
3265 if (!child_pid) {
3266 /* child */
3267 execvp(argv[0], argv);
3268 } else {
103a8fea
LB		 3269
3270 /* parent */
b2c95d90
JT		 3271 if (child_pid == -1)
3272 err(1, "fork");
103a8fea
LB		 3273
3274 signal(SIGINT, SIG_IGN);
3275 signal(SIGQUIT, SIG_IGN);
b2c95d90
JT		 3276 if (waitpid(child_pid, &status, 0) == -1)
3277 err(status, "waitpid");
103a8fea 3278 }
c98d5d94
LB		 3279 /*
3280 * n.b. fork_it() does not check for errors from for_all_cpus()
3281 * because re-starting is problematic when forking
3282 */
3283 for_all_cpus(get_counters, ODD_COUNTERS);
103a8fea 3284 gettimeofday(&tv_odd, (struct timezone *)NULL);
103a8fea 3285 timersub(&tv_odd, &tv_even, &tv_delta);
c98d5d94
LB		 3286 for_all_cpus_2(delta_cpu, ODD_COUNTERS, EVEN_COUNTERS);
3287 compute_average(EVEN_COUNTERS);
3288 format_all_counters(EVEN_COUNTERS);
103a8fea 3289
b7d8c148
LB		 3290 fprintf(outf, "%.6f sec\n", tv_delta.tv_sec + tv_delta.tv_usec/1000000.0);
3291
3292 flush_output_stderr();
103a8fea 3293
d91bb17c 3294 return status;
103a8fea
LB		 3295}
3296
3b4d5c7f
AS		 3297int get_and_dump_counters(void)
3298{
3299 int status;
3300
3301 status = for_all_cpus(get_counters, ODD_COUNTERS);
3302 if (status)
3303 return status;
3304
3305 status = for_all_cpus(dump_counters, ODD_COUNTERS);
3306 if (status)
3307 return status;
3308
b7d8c148 3309 flush_output_stdout();
3b4d5c7f
AS		 3310
3311 return status;
3312}
3313
d8af6f5f 3314void print_version() {
b7d8c148 3315 fprintf(outf, "turbostat version 4.10 10 Dec, 2015"
d8af6f5f
LB		 3316 " - Len Brown <lenb@kernel.org>\n");
3317}
3318
103a8fea
LB		 3319void cmdline(int argc, char **argv)
3320{
3321 int opt;
d8af6f5f
LB		 3322 int option_index = 0;
3323 static struct option long_options[] = {
3324 {"Counter", required_argument, 0, 'C'},
3325 {"counter", required_argument, 0, 'c'},
3326 {"Dump", no_argument, 0, 'D'},
3327 {"debug", no_argument, 0, 'd'},
3328 {"interval", required_argument, 0, 'i'},
3329 {"help", no_argument, 0, 'h'},
3330 {"Joules", no_argument, 0, 'J'},
3331 {"MSR", required_argument, 0, 'M'},
3332 {"msr", required_argument, 0, 'm'},
b7d8c148 3333 {"out", required_argument, 0, 'o'},
d8af6f5f
LB		 3334 {"Package", no_argument, 0, 'p'},
3335 {"processor", no_argument, 0, 'p'},
3336 {"Summary", no_argument, 0, 'S'},
3337 {"TCC", required_argument, 0, 'T'},
3338 {"version", no_argument, 0, 'v' },
3339 {0, 0, 0, 0 }
3340 };
103a8fea
LB		 3341
3342 progname = argv[0];
3343
b7d8c148 3344 while ((opt = getopt_long_only(argc, argv, "+C:c:Ddhi:JM:m:o:PpST:v",
d8af6f5f 3345 long_options, &option_index)) != -1) {
103a8fea 3346 switch (opt) {
d8af6f5f
LB		 3347 case 'C':
3348 sscanf(optarg, "%x", &extra_delta_offset64);
c98d5d94 3349 break;
d8af6f5f
LB		 3350 case 'c':
3351 sscanf(optarg, "%x", &extra_delta_offset32);
c98d5d94 3352 break;
d8af6f5f 3353 case 'D':
3b4d5c7f
AS		 3354 dump_only++;
3355 break;
d8af6f5f
LB		 3356 case 'd':
3357 debug++;
103a8fea 3358 break;
d8af6f5f
LB		 3359 case 'h':
3360 default:
3361 help();
3362 exit(1);
103a8fea 3363 case 'i':
2a0609c0
LB		 3364 {
3365 double interval = strtod(optarg, NULL);
3366
3367 if (interval < 0.001) {
b7d8c148 3368 fprintf(outf, "interval %f seconds is too small\n",
2a0609c0
LB		 3369 interval);
3370 exit(2);
3371 }
3372
3373 interval_ts.tv_sec = interval;
3374 interval_ts.tv_nsec = (interval - interval_ts.tv_sec) * 1000000000;
3375 }
103a8fea 3376 break;
d8af6f5f
LB		 3377 case 'J':
3378 rapl_joules++;
8e180f3c 3379 break;
d8af6f5f
LB		 3380 case 'M':
3381 sscanf(optarg, "%x", &extra_msr_offset64);
8e180f3c 3382 break;
2f32edf1
LB		 3383 case 'm':
3384 sscanf(optarg, "%x", &extra_msr_offset32);
2f32edf1 3385 break;
b7d8c148
LB		 3386 case 'o':
3387 outf = fopen_or_die(optarg, "w");
3388 break;
d8af6f5f
LB		 3389 case 'P':
3390 show_pkg_only++;
3391 break;
3392 case 'p':
3393 show_core_only++;
103a8fea 3394 break;
d8af6f5f
LB		 3395 case 'S':
3396 summary_only++;
889facbe
LB		 3397 break;
3398 case 'T':
3399 tcc_activation_temp_override = atoi(optarg);
3400 break;
d8af6f5f
LB		 3401 case 'v':
3402 print_version();
3403 exit(0);
5c56be9a 3404 break;
103a8fea
LB		 3405 }
3406 }
3407}
3408
3409int main(int argc, char **argv)
3410{
b7d8c148
LB		 3411 outf = stderr;
3412
103a8fea
LB		 3413 cmdline(argc, argv);
3414
d8af6f5f
LB		 3415 if (debug)
3416 print_version();
103a8fea
LB		 3417
3418 turbostat_init();
3419
3b4d5c7f
AS		 3420 /* dump counters and exit */
3421 if (dump_only)
3422 return get_and_dump_counters();
3423
103a8fea
LB		 3424 /*
3425 * if any params left, it must be a command to fork
3426 */
3427 if (argc - optind)
3428 return fork_it(argv + optind);
3429 else
3430 turbostat_loop();
3431
3432 return 0;
3433}
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