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Commit | Line | Data |
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d19893da FB |
1 | /* |
2 | * Host code generation | |
5fafdf24 | 3 | * |
d19893da FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
d19893da | 18 | */ |
5b6dd868 BS |
19 | #ifdef _WIN32 |
20 | #include <windows.h> | |
21 | #else | |
22 | #include <sys/types.h> | |
23 | #include <sys/mman.h> | |
24 | #endif | |
d19893da FB |
25 | #include <stdarg.h> |
26 | #include <stdlib.h> | |
27 | #include <stdio.h> | |
28 | #include <string.h> | |
29 | #include <inttypes.h> | |
30 | ||
31 | #include "config.h" | |
2054396a | 32 | |
5b6dd868 | 33 | #include "qemu-common.h" |
af5ad107 | 34 | #define NO_CPU_IO_DEFS |
d3eead2e | 35 | #include "cpu.h" |
6db8b538 | 36 | #include "trace.h" |
76cad711 | 37 | #include "disas/disas.h" |
57fec1fe | 38 | #include "tcg.h" |
5b6dd868 BS |
39 | #if defined(CONFIG_USER_ONLY) |
40 | #include "qemu.h" | |
41 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) | |
42 | #include <sys/param.h> | |
43 | #if __FreeBSD_version >= 700104 | |
44 | #define HAVE_KINFO_GETVMMAP | |
45 | #define sigqueue sigqueue_freebsd /* avoid redefinition */ | |
46 | #include <sys/time.h> | |
47 | #include <sys/proc.h> | |
48 | #include <machine/profile.h> | |
49 | #define _KERNEL | |
50 | #include <sys/user.h> | |
51 | #undef _KERNEL | |
52 | #undef sigqueue | |
53 | #include <libutil.h> | |
54 | #endif | |
55 | #endif | |
0bc3cd62 PB |
56 | #else |
57 | #include "exec/address-spaces.h" | |
5b6dd868 BS |
58 | #endif |
59 | ||
022c62cb | 60 | #include "exec/cputlb.h" |
e1b89321 | 61 | #include "exec/tb-hash.h" |
5b6dd868 | 62 | #include "translate-all.h" |
510a647f | 63 | #include "qemu/bitmap.h" |
0aa09897 | 64 | #include "qemu/timer.h" |
5b6dd868 BS |
65 | |
66 | //#define DEBUG_TB_INVALIDATE | |
67 | //#define DEBUG_FLUSH | |
68 | /* make various TB consistency checks */ | |
69 | //#define DEBUG_TB_CHECK | |
70 | ||
71 | #if !defined(CONFIG_USER_ONLY) | |
72 | /* TB consistency checks only implemented for usermode emulation. */ | |
73 | #undef DEBUG_TB_CHECK | |
74 | #endif | |
75 | ||
76 | #define SMC_BITMAP_USE_THRESHOLD 10 | |
77 | ||
5b6dd868 BS |
78 | typedef struct PageDesc { |
79 | /* list of TBs intersecting this ram page */ | |
80 | TranslationBlock *first_tb; | |
81 | /* in order to optimize self modifying code, we count the number | |
82 | of lookups we do to a given page to use a bitmap */ | |
83 | unsigned int code_write_count; | |
510a647f | 84 | unsigned long *code_bitmap; |
5b6dd868 BS |
85 | #if defined(CONFIG_USER_ONLY) |
86 | unsigned long flags; | |
87 | #endif | |
88 | } PageDesc; | |
89 | ||
90 | /* In system mode we want L1_MAP to be based on ram offsets, | |
91 | while in user mode we want it to be based on virtual addresses. */ | |
92 | #if !defined(CONFIG_USER_ONLY) | |
93 | #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS | |
94 | # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS | |
95 | #else | |
96 | # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS | |
97 | #endif | |
98 | #else | |
99 | # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS | |
100 | #endif | |
101 | ||
03f49957 PB |
102 | /* Size of the L2 (and L3, etc) page tables. */ |
103 | #define V_L2_BITS 10 | |
104 | #define V_L2_SIZE (1 << V_L2_BITS) | |
105 | ||
5b6dd868 BS |
106 | /* The bits remaining after N lower levels of page tables. */ |
107 | #define V_L1_BITS_REM \ | |
03f49957 | 108 | ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % V_L2_BITS) |
5b6dd868 BS |
109 | |
110 | #if V_L1_BITS_REM < 4 | |
03f49957 | 111 | #define V_L1_BITS (V_L1_BITS_REM + V_L2_BITS) |
5b6dd868 BS |
112 | #else |
113 | #define V_L1_BITS V_L1_BITS_REM | |
114 | #endif | |
115 | ||
116 | #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS) | |
117 | ||
118 | #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS) | |
119 | ||
120 | uintptr_t qemu_real_host_page_size; | |
4e51361d | 121 | uintptr_t qemu_real_host_page_mask; |
5b6dd868 BS |
122 | uintptr_t qemu_host_page_size; |
123 | uintptr_t qemu_host_page_mask; | |
124 | ||
125 | /* This is a multi-level map on the virtual address space. | |
126 | The bottom level has pointers to PageDesc. */ | |
127 | static void *l1_map[V_L1_SIZE]; | |
128 | ||
57fec1fe FB |
129 | /* code generation context */ |
130 | TCGContext tcg_ctx; | |
d19893da | 131 | |
5b6dd868 BS |
132 | static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, |
133 | tb_page_addr_t phys_page2); | |
a8a826a3 | 134 | static TranslationBlock *tb_find_pc(uintptr_t tc_ptr); |
5b6dd868 | 135 | |
57fec1fe FB |
136 | void cpu_gen_init(void) |
137 | { | |
138 | tcg_context_init(&tcg_ctx); | |
57fec1fe FB |
139 | } |
140 | ||
d19893da | 141 | /* return non zero if the very first instruction is invalid so that |
5fafdf24 | 142 | the virtual CPU can trigger an exception. |
d19893da FB |
143 | |
144 | '*gen_code_size_ptr' contains the size of the generated code (host | |
145 | code). | |
146 | */ | |
9349b4f9 | 147 | int cpu_gen_code(CPUArchState *env, TranslationBlock *tb, int *gen_code_size_ptr) |
d19893da | 148 | { |
57fec1fe | 149 | TCGContext *s = &tcg_ctx; |
1813e175 | 150 | tcg_insn_unit *gen_code_buf; |
d19893da | 151 | int gen_code_size; |
57fec1fe FB |
152 | #ifdef CONFIG_PROFILER |
153 | int64_t ti; | |
154 | #endif | |
155 | ||
156 | #ifdef CONFIG_PROFILER | |
b67d9a52 FB |
157 | s->tb_count1++; /* includes aborted translations because of |
158 | exceptions */ | |
57fec1fe FB |
159 | ti = profile_getclock(); |
160 | #endif | |
161 | tcg_func_start(s); | |
d19893da | 162 | |
2cfc5f17 TS |
163 | gen_intermediate_code(env, tb); |
164 | ||
6db8b538 AB |
165 | trace_translate_block(tb, tb->pc, tb->tc_ptr); |
166 | ||
ec6338ba | 167 | /* generate machine code */ |
57fec1fe | 168 | gen_code_buf = tb->tc_ptr; |
ec6338ba FB |
169 | tb->tb_next_offset[0] = 0xffff; |
170 | tb->tb_next_offset[1] = 0xffff; | |
57fec1fe | 171 | s->tb_next_offset = tb->tb_next_offset; |
4cbb86e1 | 172 | #ifdef USE_DIRECT_JUMP |
57fec1fe FB |
173 | s->tb_jmp_offset = tb->tb_jmp_offset; |
174 | s->tb_next = NULL; | |
d19893da | 175 | #else |
57fec1fe FB |
176 | s->tb_jmp_offset = NULL; |
177 | s->tb_next = tb->tb_next; | |
d19893da | 178 | #endif |
57fec1fe FB |
179 | |
180 | #ifdef CONFIG_PROFILER | |
b67d9a52 FB |
181 | s->tb_count++; |
182 | s->interm_time += profile_getclock() - ti; | |
183 | s->code_time -= profile_getclock(); | |
57fec1fe | 184 | #endif |
54604f74 | 185 | gen_code_size = tcg_gen_code(s, gen_code_buf); |
d19893da | 186 | *gen_code_size_ptr = gen_code_size; |
57fec1fe | 187 | #ifdef CONFIG_PROFILER |
b67d9a52 FB |
188 | s->code_time += profile_getclock(); |
189 | s->code_in_len += tb->size; | |
190 | s->code_out_len += gen_code_size; | |
57fec1fe FB |
191 | #endif |
192 | ||
d19893da | 193 | #ifdef DEBUG_DISAS |
8fec2b8c | 194 | if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) { |
1813e175 RH |
195 | qemu_log("OUT: [size=%d]\n", gen_code_size); |
196 | log_disas(tb->tc_ptr, gen_code_size); | |
93fcfe39 | 197 | qemu_log("\n"); |
31b1a7b4 | 198 | qemu_log_flush(); |
d19893da FB |
199 | } |
200 | #endif | |
201 | return 0; | |
202 | } | |
203 | ||
5fafdf24 | 204 | /* The cpu state corresponding to 'searched_pc' is restored. |
d19893da | 205 | */ |
74f10515 | 206 | static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, |
a8a826a3 | 207 | uintptr_t searched_pc) |
d19893da | 208 | { |
74f10515 | 209 | CPUArchState *env = cpu->env_ptr; |
57fec1fe FB |
210 | TCGContext *s = &tcg_ctx; |
211 | int j; | |
6375e09e | 212 | uintptr_t tc_ptr; |
57fec1fe FB |
213 | #ifdef CONFIG_PROFILER |
214 | int64_t ti; | |
215 | #endif | |
216 | ||
217 | #ifdef CONFIG_PROFILER | |
218 | ti = profile_getclock(); | |
219 | #endif | |
220 | tcg_func_start(s); | |
d19893da | 221 | |
2cfc5f17 | 222 | gen_intermediate_code_pc(env, tb); |
3b46e624 | 223 | |
bd79255d | 224 | if (tb->cflags & CF_USE_ICOUNT) { |
2e70f6ef | 225 | /* Reset the cycle counter to the start of the block. */ |
28ecfd7a | 226 | cpu->icount_decr.u16.low += tb->icount; |
2e70f6ef | 227 | /* Clear the IO flag. */ |
99df7dce | 228 | cpu->can_do_io = 0; |
2e70f6ef PB |
229 | } |
230 | ||
d19893da | 231 | /* find opc index corresponding to search_pc */ |
6375e09e | 232 | tc_ptr = (uintptr_t)tb->tc_ptr; |
d19893da FB |
233 | if (searched_pc < tc_ptr) |
234 | return -1; | |
57fec1fe FB |
235 | |
236 | s->tb_next_offset = tb->tb_next_offset; | |
237 | #ifdef USE_DIRECT_JUMP | |
238 | s->tb_jmp_offset = tb->tb_jmp_offset; | |
239 | s->tb_next = NULL; | |
240 | #else | |
241 | s->tb_jmp_offset = NULL; | |
242 | s->tb_next = tb->tb_next; | |
243 | #endif | |
1813e175 RH |
244 | j = tcg_gen_code_search_pc(s, (tcg_insn_unit *)tc_ptr, |
245 | searched_pc - tc_ptr); | |
57fec1fe FB |
246 | if (j < 0) |
247 | return -1; | |
d19893da | 248 | /* now find start of instruction before */ |
ab1103de | 249 | while (s->gen_opc_instr_start[j] == 0) { |
d19893da | 250 | j--; |
ab1103de | 251 | } |
28ecfd7a | 252 | cpu->icount_decr.u16.low -= s->gen_opc_icount[j]; |
3b46e624 | 253 | |
e87b7cb0 | 254 | restore_state_to_opc(env, tb, j); |
57fec1fe FB |
255 | |
256 | #ifdef CONFIG_PROFILER | |
b67d9a52 FB |
257 | s->restore_time += profile_getclock() - ti; |
258 | s->restore_count++; | |
57fec1fe | 259 | #endif |
d19893da FB |
260 | return 0; |
261 | } | |
5b6dd868 | 262 | |
3f38f309 | 263 | bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr) |
a8a826a3 BS |
264 | { |
265 | TranslationBlock *tb; | |
266 | ||
267 | tb = tb_find_pc(retaddr); | |
268 | if (tb) { | |
74f10515 | 269 | cpu_restore_state_from_tb(cpu, tb, retaddr); |
d8a499f1 PD |
270 | if (tb->cflags & CF_NOCACHE) { |
271 | /* one-shot translation, invalidate it immediately */ | |
272 | cpu->current_tb = NULL; | |
273 | tb_phys_invalidate(tb, -1); | |
274 | tb_free(tb); | |
275 | } | |
a8a826a3 BS |
276 | return true; |
277 | } | |
278 | return false; | |
279 | } | |
280 | ||
5b6dd868 | 281 | #ifdef _WIN32 |
2d8ac5eb | 282 | static __attribute__((unused)) void map_exec(void *addr, long size) |
5b6dd868 BS |
283 | { |
284 | DWORD old_protect; | |
285 | VirtualProtect(addr, size, | |
286 | PAGE_EXECUTE_READWRITE, &old_protect); | |
287 | } | |
288 | #else | |
2d8ac5eb | 289 | static __attribute__((unused)) void map_exec(void *addr, long size) |
5b6dd868 BS |
290 | { |
291 | unsigned long start, end, page_size; | |
292 | ||
293 | page_size = getpagesize(); | |
294 | start = (unsigned long)addr; | |
295 | start &= ~(page_size - 1); | |
296 | ||
297 | end = (unsigned long)addr + size; | |
298 | end += page_size - 1; | |
299 | end &= ~(page_size - 1); | |
300 | ||
301 | mprotect((void *)start, end - start, | |
302 | PROT_READ | PROT_WRITE | PROT_EXEC); | |
303 | } | |
304 | #endif | |
305 | ||
47c16ed5 | 306 | void page_size_init(void) |
5b6dd868 BS |
307 | { |
308 | /* NOTE: we can always suppose that qemu_host_page_size >= | |
309 | TARGET_PAGE_SIZE */ | |
5b6dd868 | 310 | qemu_real_host_page_size = getpagesize(); |
4e51361d | 311 | qemu_real_host_page_mask = ~(qemu_real_host_page_size - 1); |
5b6dd868 BS |
312 | if (qemu_host_page_size == 0) { |
313 | qemu_host_page_size = qemu_real_host_page_size; | |
314 | } | |
315 | if (qemu_host_page_size < TARGET_PAGE_SIZE) { | |
316 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
317 | } | |
318 | qemu_host_page_mask = ~(qemu_host_page_size - 1); | |
47c16ed5 | 319 | } |
5b6dd868 | 320 | |
47c16ed5 AK |
321 | static void page_init(void) |
322 | { | |
323 | page_size_init(); | |
5b6dd868 BS |
324 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
325 | { | |
326 | #ifdef HAVE_KINFO_GETVMMAP | |
327 | struct kinfo_vmentry *freep; | |
328 | int i, cnt; | |
329 | ||
330 | freep = kinfo_getvmmap(getpid(), &cnt); | |
331 | if (freep) { | |
332 | mmap_lock(); | |
333 | for (i = 0; i < cnt; i++) { | |
334 | unsigned long startaddr, endaddr; | |
335 | ||
336 | startaddr = freep[i].kve_start; | |
337 | endaddr = freep[i].kve_end; | |
338 | if (h2g_valid(startaddr)) { | |
339 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
340 | ||
341 | if (h2g_valid(endaddr)) { | |
342 | endaddr = h2g(endaddr); | |
343 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
344 | } else { | |
345 | #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS | |
346 | endaddr = ~0ul; | |
347 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
348 | #endif | |
349 | } | |
350 | } | |
351 | } | |
352 | free(freep); | |
353 | mmap_unlock(); | |
354 | } | |
355 | #else | |
356 | FILE *f; | |
357 | ||
358 | last_brk = (unsigned long)sbrk(0); | |
359 | ||
360 | f = fopen("/compat/linux/proc/self/maps", "r"); | |
361 | if (f) { | |
362 | mmap_lock(); | |
363 | ||
364 | do { | |
365 | unsigned long startaddr, endaddr; | |
366 | int n; | |
367 | ||
368 | n = fscanf(f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr); | |
369 | ||
370 | if (n == 2 && h2g_valid(startaddr)) { | |
371 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
372 | ||
373 | if (h2g_valid(endaddr)) { | |
374 | endaddr = h2g(endaddr); | |
375 | } else { | |
376 | endaddr = ~0ul; | |
377 | } | |
378 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
379 | } | |
380 | } while (!feof(f)); | |
381 | ||
382 | fclose(f); | |
383 | mmap_unlock(); | |
384 | } | |
385 | #endif | |
386 | } | |
387 | #endif | |
388 | } | |
389 | ||
390 | static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) | |
391 | { | |
392 | PageDesc *pd; | |
393 | void **lp; | |
394 | int i; | |
395 | ||
5b6dd868 BS |
396 | /* Level 1. Always allocated. */ |
397 | lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1)); | |
398 | ||
399 | /* Level 2..N-1. */ | |
03f49957 | 400 | for (i = V_L1_SHIFT / V_L2_BITS - 1; i > 0; i--) { |
5b6dd868 BS |
401 | void **p = *lp; |
402 | ||
403 | if (p == NULL) { | |
404 | if (!alloc) { | |
405 | return NULL; | |
406 | } | |
e3a0abfd | 407 | p = g_new0(void *, V_L2_SIZE); |
5b6dd868 BS |
408 | *lp = p; |
409 | } | |
410 | ||
03f49957 | 411 | lp = p + ((index >> (i * V_L2_BITS)) & (V_L2_SIZE - 1)); |
5b6dd868 BS |
412 | } |
413 | ||
414 | pd = *lp; | |
415 | if (pd == NULL) { | |
416 | if (!alloc) { | |
417 | return NULL; | |
418 | } | |
e3a0abfd | 419 | pd = g_new0(PageDesc, V_L2_SIZE); |
5b6dd868 BS |
420 | *lp = pd; |
421 | } | |
422 | ||
03f49957 | 423 | return pd + (index & (V_L2_SIZE - 1)); |
5b6dd868 BS |
424 | } |
425 | ||
426 | static inline PageDesc *page_find(tb_page_addr_t index) | |
427 | { | |
428 | return page_find_alloc(index, 0); | |
429 | } | |
430 | ||
431 | #if !defined(CONFIG_USER_ONLY) | |
432 | #define mmap_lock() do { } while (0) | |
433 | #define mmap_unlock() do { } while (0) | |
434 | #endif | |
435 | ||
436 | #if defined(CONFIG_USER_ONLY) | |
437 | /* Currently it is not recommended to allocate big chunks of data in | |
438 | user mode. It will change when a dedicated libc will be used. */ | |
439 | /* ??? 64-bit hosts ought to have no problem mmaping data outside the | |
440 | region in which the guest needs to run. Revisit this. */ | |
441 | #define USE_STATIC_CODE_GEN_BUFFER | |
442 | #endif | |
443 | ||
444 | /* ??? Should configure for this, not list operating systems here. */ | |
445 | #if (defined(__linux__) \ | |
446 | || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \ | |
447 | || defined(__DragonFly__) || defined(__OpenBSD__) \ | |
448 | || defined(__NetBSD__)) | |
449 | # define USE_MMAP | |
450 | #endif | |
451 | ||
452 | /* Minimum size of the code gen buffer. This number is randomly chosen, | |
453 | but not so small that we can't have a fair number of TB's live. */ | |
454 | #define MIN_CODE_GEN_BUFFER_SIZE (1024u * 1024) | |
455 | ||
456 | /* Maximum size of the code gen buffer we'd like to use. Unless otherwise | |
457 | indicated, this is constrained by the range of direct branches on the | |
458 | host cpu, as used by the TCG implementation of goto_tb. */ | |
459 | #if defined(__x86_64__) | |
460 | # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024) | |
461 | #elif defined(__sparc__) | |
462 | # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024) | |
4a136e0a CF |
463 | #elif defined(__aarch64__) |
464 | # define MAX_CODE_GEN_BUFFER_SIZE (128ul * 1024 * 1024) | |
5b6dd868 BS |
465 | #elif defined(__arm__) |
466 | # define MAX_CODE_GEN_BUFFER_SIZE (16u * 1024 * 1024) | |
467 | #elif defined(__s390x__) | |
468 | /* We have a +- 4GB range on the branches; leave some slop. */ | |
469 | # define MAX_CODE_GEN_BUFFER_SIZE (3ul * 1024 * 1024 * 1024) | |
479eb121 RH |
470 | #elif defined(__mips__) |
471 | /* We have a 256MB branch region, but leave room to make sure the | |
472 | main executable is also within that region. */ | |
473 | # define MAX_CODE_GEN_BUFFER_SIZE (128ul * 1024 * 1024) | |
5b6dd868 BS |
474 | #else |
475 | # define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) | |
476 | #endif | |
477 | ||
478 | #define DEFAULT_CODE_GEN_BUFFER_SIZE_1 (32u * 1024 * 1024) | |
479 | ||
480 | #define DEFAULT_CODE_GEN_BUFFER_SIZE \ | |
481 | (DEFAULT_CODE_GEN_BUFFER_SIZE_1 < MAX_CODE_GEN_BUFFER_SIZE \ | |
482 | ? DEFAULT_CODE_GEN_BUFFER_SIZE_1 : MAX_CODE_GEN_BUFFER_SIZE) | |
483 | ||
484 | static inline size_t size_code_gen_buffer(size_t tb_size) | |
485 | { | |
486 | /* Size the buffer. */ | |
487 | if (tb_size == 0) { | |
488 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
489 | tb_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
490 | #else | |
491 | /* ??? Needs adjustments. */ | |
492 | /* ??? If we relax the requirement that CONFIG_USER_ONLY use the | |
493 | static buffer, we could size this on RESERVED_VA, on the text | |
494 | segment size of the executable, or continue to use the default. */ | |
495 | tb_size = (unsigned long)(ram_size / 4); | |
496 | #endif | |
497 | } | |
498 | if (tb_size < MIN_CODE_GEN_BUFFER_SIZE) { | |
499 | tb_size = MIN_CODE_GEN_BUFFER_SIZE; | |
500 | } | |
501 | if (tb_size > MAX_CODE_GEN_BUFFER_SIZE) { | |
502 | tb_size = MAX_CODE_GEN_BUFFER_SIZE; | |
503 | } | |
0b0d3320 | 504 | tcg_ctx.code_gen_buffer_size = tb_size; |
5b6dd868 BS |
505 | return tb_size; |
506 | } | |
507 | ||
483c76e1 RH |
508 | #ifdef __mips__ |
509 | /* In order to use J and JAL within the code_gen_buffer, we require | |
510 | that the buffer not cross a 256MB boundary. */ | |
511 | static inline bool cross_256mb(void *addr, size_t size) | |
512 | { | |
513 | return ((uintptr_t)addr ^ ((uintptr_t)addr + size)) & 0xf0000000; | |
514 | } | |
515 | ||
516 | /* We weren't able to allocate a buffer without crossing that boundary, | |
517 | so make do with the larger portion of the buffer that doesn't cross. | |
518 | Returns the new base of the buffer, and adjusts code_gen_buffer_size. */ | |
519 | static inline void *split_cross_256mb(void *buf1, size_t size1) | |
520 | { | |
521 | void *buf2 = (void *)(((uintptr_t)buf1 + size1) & 0xf0000000); | |
522 | size_t size2 = buf1 + size1 - buf2; | |
523 | ||
524 | size1 = buf2 - buf1; | |
525 | if (size1 < size2) { | |
526 | size1 = size2; | |
527 | buf1 = buf2; | |
528 | } | |
529 | ||
530 | tcg_ctx.code_gen_buffer_size = size1; | |
531 | return buf1; | |
532 | } | |
533 | #endif | |
534 | ||
5b6dd868 BS |
535 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
536 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] | |
537 | __attribute__((aligned(CODE_GEN_ALIGN))); | |
538 | ||
539 | static inline void *alloc_code_gen_buffer(void) | |
540 | { | |
483c76e1 RH |
541 | void *buf = static_code_gen_buffer; |
542 | #ifdef __mips__ | |
543 | if (cross_256mb(buf, tcg_ctx.code_gen_buffer_size)) { | |
544 | buf = split_cross_256mb(buf, tcg_ctx.code_gen_buffer_size); | |
545 | } | |
546 | #endif | |
547 | map_exec(buf, tcg_ctx.code_gen_buffer_size); | |
548 | return buf; | |
5b6dd868 BS |
549 | } |
550 | #elif defined(USE_MMAP) | |
551 | static inline void *alloc_code_gen_buffer(void) | |
552 | { | |
553 | int flags = MAP_PRIVATE | MAP_ANONYMOUS; | |
554 | uintptr_t start = 0; | |
555 | void *buf; | |
556 | ||
557 | /* Constrain the position of the buffer based on the host cpu. | |
558 | Note that these addresses are chosen in concert with the | |
559 | addresses assigned in the relevant linker script file. */ | |
560 | # if defined(__PIE__) || defined(__PIC__) | |
561 | /* Don't bother setting a preferred location if we're building | |
562 | a position-independent executable. We're more likely to get | |
563 | an address near the main executable if we let the kernel | |
564 | choose the address. */ | |
565 | # elif defined(__x86_64__) && defined(MAP_32BIT) | |
566 | /* Force the memory down into low memory with the executable. | |
567 | Leave the choice of exact location with the kernel. */ | |
568 | flags |= MAP_32BIT; | |
569 | /* Cannot expect to map more than 800MB in low memory. */ | |
0b0d3320 EV |
570 | if (tcg_ctx.code_gen_buffer_size > 800u * 1024 * 1024) { |
571 | tcg_ctx.code_gen_buffer_size = 800u * 1024 * 1024; | |
5b6dd868 BS |
572 | } |
573 | # elif defined(__sparc__) | |
574 | start = 0x40000000ul; | |
575 | # elif defined(__s390x__) | |
576 | start = 0x90000000ul; | |
479eb121 RH |
577 | # elif defined(__mips__) |
578 | /* ??? We ought to more explicitly manage layout for softmmu too. */ | |
579 | # ifdef CONFIG_USER_ONLY | |
580 | start = 0x68000000ul; | |
581 | # elif _MIPS_SIM == _ABI64 | |
582 | start = 0x128000000ul; | |
583 | # else | |
584 | start = 0x08000000ul; | |
585 | # endif | |
5b6dd868 BS |
586 | # endif |
587 | ||
0b0d3320 | 588 | buf = mmap((void *)start, tcg_ctx.code_gen_buffer_size, |
5b6dd868 | 589 | PROT_WRITE | PROT_READ | PROT_EXEC, flags, -1, 0); |
483c76e1 RH |
590 | if (buf == MAP_FAILED) { |
591 | return NULL; | |
592 | } | |
593 | ||
594 | #ifdef __mips__ | |
595 | if (cross_256mb(buf, tcg_ctx.code_gen_buffer_size)) { | |
5d831be2 | 596 | /* Try again, with the original still mapped, to avoid re-acquiring |
483c76e1 RH |
597 | that 256mb crossing. This time don't specify an address. */ |
598 | size_t size2, size1 = tcg_ctx.code_gen_buffer_size; | |
599 | void *buf2 = mmap(NULL, size1, PROT_WRITE | PROT_READ | PROT_EXEC, | |
600 | flags, -1, 0); | |
601 | if (buf2 != MAP_FAILED) { | |
602 | if (!cross_256mb(buf2, size1)) { | |
603 | /* Success! Use the new buffer. */ | |
604 | munmap(buf, size1); | |
605 | return buf2; | |
606 | } | |
607 | /* Failure. Work with what we had. */ | |
608 | munmap(buf2, size1); | |
609 | } | |
610 | ||
611 | /* Split the original buffer. Free the smaller half. */ | |
612 | buf2 = split_cross_256mb(buf, size1); | |
613 | size2 = tcg_ctx.code_gen_buffer_size; | |
614 | munmap(buf + (buf == buf2 ? size2 : 0), size1 - size2); | |
615 | return buf2; | |
616 | } | |
617 | #endif | |
618 | ||
619 | return buf; | |
5b6dd868 BS |
620 | } |
621 | #else | |
622 | static inline void *alloc_code_gen_buffer(void) | |
623 | { | |
8b98ade3 | 624 | void *buf = g_try_malloc(tcg_ctx.code_gen_buffer_size); |
5b6dd868 | 625 | |
483c76e1 RH |
626 | if (buf == NULL) { |
627 | return NULL; | |
628 | } | |
629 | ||
630 | #ifdef __mips__ | |
631 | if (cross_256mb(buf, tcg_ctx.code_gen_buffer_size)) { | |
632 | void *buf2 = g_malloc(tcg_ctx.code_gen_buffer_size); | |
633 | if (buf2 != NULL && !cross_256mb(buf2, size1)) { | |
634 | /* Success! Use the new buffer. */ | |
635 | free(buf); | |
636 | buf = buf2; | |
637 | } else { | |
638 | /* Failure. Work with what we had. Since this is malloc | |
639 | and not mmap, we can't free the other half. */ | |
640 | free(buf2); | |
641 | buf = split_cross_256mb(buf, tcg_ctx.code_gen_buffer_size); | |
642 | } | |
5b6dd868 | 643 | } |
483c76e1 RH |
644 | #endif |
645 | ||
646 | map_exec(buf, tcg_ctx.code_gen_buffer_size); | |
5b6dd868 BS |
647 | return buf; |
648 | } | |
649 | #endif /* USE_STATIC_CODE_GEN_BUFFER, USE_MMAP */ | |
650 | ||
651 | static inline void code_gen_alloc(size_t tb_size) | |
652 | { | |
0b0d3320 EV |
653 | tcg_ctx.code_gen_buffer_size = size_code_gen_buffer(tb_size); |
654 | tcg_ctx.code_gen_buffer = alloc_code_gen_buffer(); | |
655 | if (tcg_ctx.code_gen_buffer == NULL) { | |
5b6dd868 BS |
656 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); |
657 | exit(1); | |
658 | } | |
659 | ||
0b0d3320 EV |
660 | qemu_madvise(tcg_ctx.code_gen_buffer, tcg_ctx.code_gen_buffer_size, |
661 | QEMU_MADV_HUGEPAGE); | |
5b6dd868 BS |
662 | |
663 | /* Steal room for the prologue at the end of the buffer. This ensures | |
664 | (via the MAX_CODE_GEN_BUFFER_SIZE limits above) that direct branches | |
665 | from TB's to the prologue are going to be in range. It also means | |
666 | that we don't need to mark (additional) portions of the data segment | |
667 | as executable. */ | |
0b0d3320 EV |
668 | tcg_ctx.code_gen_prologue = tcg_ctx.code_gen_buffer + |
669 | tcg_ctx.code_gen_buffer_size - 1024; | |
670 | tcg_ctx.code_gen_buffer_size -= 1024; | |
5b6dd868 | 671 | |
0b0d3320 | 672 | tcg_ctx.code_gen_buffer_max_size = tcg_ctx.code_gen_buffer_size - |
5b6dd868 | 673 | (TCG_MAX_OP_SIZE * OPC_BUF_SIZE); |
0b0d3320 EV |
674 | tcg_ctx.code_gen_max_blocks = tcg_ctx.code_gen_buffer_size / |
675 | CODE_GEN_AVG_BLOCK_SIZE; | |
5e5f07e0 EV |
676 | tcg_ctx.tb_ctx.tbs = |
677 | g_malloc(tcg_ctx.code_gen_max_blocks * sizeof(TranslationBlock)); | |
5b6dd868 BS |
678 | } |
679 | ||
680 | /* Must be called before using the QEMU cpus. 'tb_size' is the size | |
681 | (in bytes) allocated to the translation buffer. Zero means default | |
682 | size. */ | |
683 | void tcg_exec_init(unsigned long tb_size) | |
684 | { | |
685 | cpu_gen_init(); | |
686 | code_gen_alloc(tb_size); | |
0b0d3320 EV |
687 | tcg_ctx.code_gen_ptr = tcg_ctx.code_gen_buffer; |
688 | tcg_register_jit(tcg_ctx.code_gen_buffer, tcg_ctx.code_gen_buffer_size); | |
5b6dd868 BS |
689 | page_init(); |
690 | #if !defined(CONFIG_USER_ONLY) || !defined(CONFIG_USE_GUEST_BASE) | |
691 | /* There's no guest base to take into account, so go ahead and | |
692 | initialize the prologue now. */ | |
693 | tcg_prologue_init(&tcg_ctx); | |
694 | #endif | |
695 | } | |
696 | ||
697 | bool tcg_enabled(void) | |
698 | { | |
0b0d3320 | 699 | return tcg_ctx.code_gen_buffer != NULL; |
5b6dd868 BS |
700 | } |
701 | ||
702 | /* Allocate a new translation block. Flush the translation buffer if | |
703 | too many translation blocks or too much generated code. */ | |
704 | static TranslationBlock *tb_alloc(target_ulong pc) | |
705 | { | |
706 | TranslationBlock *tb; | |
707 | ||
5e5f07e0 | 708 | if (tcg_ctx.tb_ctx.nb_tbs >= tcg_ctx.code_gen_max_blocks || |
0b0d3320 EV |
709 | (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) >= |
710 | tcg_ctx.code_gen_buffer_max_size) { | |
5b6dd868 BS |
711 | return NULL; |
712 | } | |
5e5f07e0 | 713 | tb = &tcg_ctx.tb_ctx.tbs[tcg_ctx.tb_ctx.nb_tbs++]; |
5b6dd868 BS |
714 | tb->pc = pc; |
715 | tb->cflags = 0; | |
716 | return tb; | |
717 | } | |
718 | ||
719 | void tb_free(TranslationBlock *tb) | |
720 | { | |
721 | /* In practice this is mostly used for single use temporary TB | |
722 | Ignore the hard cases and just back up if this TB happens to | |
723 | be the last one generated. */ | |
5e5f07e0 EV |
724 | if (tcg_ctx.tb_ctx.nb_tbs > 0 && |
725 | tb == &tcg_ctx.tb_ctx.tbs[tcg_ctx.tb_ctx.nb_tbs - 1]) { | |
0b0d3320 | 726 | tcg_ctx.code_gen_ptr = tb->tc_ptr; |
5e5f07e0 | 727 | tcg_ctx.tb_ctx.nb_tbs--; |
5b6dd868 BS |
728 | } |
729 | } | |
730 | ||
731 | static inline void invalidate_page_bitmap(PageDesc *p) | |
732 | { | |
733 | if (p->code_bitmap) { | |
734 | g_free(p->code_bitmap); | |
735 | p->code_bitmap = NULL; | |
736 | } | |
737 | p->code_write_count = 0; | |
738 | } | |
739 | ||
740 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */ | |
741 | static void page_flush_tb_1(int level, void **lp) | |
742 | { | |
743 | int i; | |
744 | ||
745 | if (*lp == NULL) { | |
746 | return; | |
747 | } | |
748 | if (level == 0) { | |
749 | PageDesc *pd = *lp; | |
750 | ||
03f49957 | 751 | for (i = 0; i < V_L2_SIZE; ++i) { |
5b6dd868 BS |
752 | pd[i].first_tb = NULL; |
753 | invalidate_page_bitmap(pd + i); | |
754 | } | |
755 | } else { | |
756 | void **pp = *lp; | |
757 | ||
03f49957 | 758 | for (i = 0; i < V_L2_SIZE; ++i) { |
5b6dd868 BS |
759 | page_flush_tb_1(level - 1, pp + i); |
760 | } | |
761 | } | |
762 | } | |
763 | ||
764 | static void page_flush_tb(void) | |
765 | { | |
766 | int i; | |
767 | ||
768 | for (i = 0; i < V_L1_SIZE; i++) { | |
03f49957 | 769 | page_flush_tb_1(V_L1_SHIFT / V_L2_BITS - 1, l1_map + i); |
5b6dd868 BS |
770 | } |
771 | } | |
772 | ||
773 | /* flush all the translation blocks */ | |
774 | /* XXX: tb_flush is currently not thread safe */ | |
775 | void tb_flush(CPUArchState *env1) | |
776 | { | |
a47dddd7 | 777 | CPUState *cpu = ENV_GET_CPU(env1); |
5b6dd868 BS |
778 | |
779 | #if defined(DEBUG_FLUSH) | |
780 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", | |
0b0d3320 | 781 | (unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer), |
5e5f07e0 | 782 | tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ? |
0b0d3320 | 783 | ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer)) / |
5e5f07e0 | 784 | tcg_ctx.tb_ctx.nb_tbs : 0); |
5b6dd868 | 785 | #endif |
0b0d3320 EV |
786 | if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) |
787 | > tcg_ctx.code_gen_buffer_size) { | |
a47dddd7 | 788 | cpu_abort(cpu, "Internal error: code buffer overflow\n"); |
5b6dd868 | 789 | } |
5e5f07e0 | 790 | tcg_ctx.tb_ctx.nb_tbs = 0; |
5b6dd868 | 791 | |
bdc44640 | 792 | CPU_FOREACH(cpu) { |
8cd70437 | 793 | memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache)); |
5b6dd868 BS |
794 | } |
795 | ||
eb2535f4 | 796 | memset(tcg_ctx.tb_ctx.tb_phys_hash, 0, sizeof(tcg_ctx.tb_ctx.tb_phys_hash)); |
5b6dd868 BS |
797 | page_flush_tb(); |
798 | ||
0b0d3320 | 799 | tcg_ctx.code_gen_ptr = tcg_ctx.code_gen_buffer; |
5b6dd868 BS |
800 | /* XXX: flush processor icache at this point if cache flush is |
801 | expensive */ | |
5e5f07e0 | 802 | tcg_ctx.tb_ctx.tb_flush_count++; |
5b6dd868 BS |
803 | } |
804 | ||
805 | #ifdef DEBUG_TB_CHECK | |
806 | ||
807 | static void tb_invalidate_check(target_ulong address) | |
808 | { | |
809 | TranslationBlock *tb; | |
810 | int i; | |
811 | ||
812 | address &= TARGET_PAGE_MASK; | |
813 | for (i = 0; i < CODE_GEN_PHYS_HASH_SIZE; i++) { | |
5e5f07e0 | 814 | for (tb = tb_ctx.tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { |
5b6dd868 BS |
815 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
816 | address >= tb->pc + tb->size)) { | |
817 | printf("ERROR invalidate: address=" TARGET_FMT_lx | |
818 | " PC=%08lx size=%04x\n", | |
819 | address, (long)tb->pc, tb->size); | |
820 | } | |
821 | } | |
822 | } | |
823 | } | |
824 | ||
825 | /* verify that all the pages have correct rights for code */ | |
826 | static void tb_page_check(void) | |
827 | { | |
828 | TranslationBlock *tb; | |
829 | int i, flags1, flags2; | |
830 | ||
831 | for (i = 0; i < CODE_GEN_PHYS_HASH_SIZE; i++) { | |
5e5f07e0 EV |
832 | for (tb = tcg_ctx.tb_ctx.tb_phys_hash[i]; tb != NULL; |
833 | tb = tb->phys_hash_next) { | |
5b6dd868 BS |
834 | flags1 = page_get_flags(tb->pc); |
835 | flags2 = page_get_flags(tb->pc + tb->size - 1); | |
836 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | |
837 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | |
838 | (long)tb->pc, tb->size, flags1, flags2); | |
839 | } | |
840 | } | |
841 | } | |
842 | } | |
843 | ||
844 | #endif | |
845 | ||
0c884d16 | 846 | static inline void tb_hash_remove(TranslationBlock **ptb, TranslationBlock *tb) |
5b6dd868 BS |
847 | { |
848 | TranslationBlock *tb1; | |
849 | ||
850 | for (;;) { | |
851 | tb1 = *ptb; | |
852 | if (tb1 == tb) { | |
0c884d16 | 853 | *ptb = tb1->phys_hash_next; |
5b6dd868 BS |
854 | break; |
855 | } | |
0c884d16 | 856 | ptb = &tb1->phys_hash_next; |
5b6dd868 BS |
857 | } |
858 | } | |
859 | ||
860 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) | |
861 | { | |
862 | TranslationBlock *tb1; | |
863 | unsigned int n1; | |
864 | ||
865 | for (;;) { | |
866 | tb1 = *ptb; | |
867 | n1 = (uintptr_t)tb1 & 3; | |
868 | tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3); | |
869 | if (tb1 == tb) { | |
870 | *ptb = tb1->page_next[n1]; | |
871 | break; | |
872 | } | |
873 | ptb = &tb1->page_next[n1]; | |
874 | } | |
875 | } | |
876 | ||
877 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) | |
878 | { | |
879 | TranslationBlock *tb1, **ptb; | |
880 | unsigned int n1; | |
881 | ||
882 | ptb = &tb->jmp_next[n]; | |
883 | tb1 = *ptb; | |
884 | if (tb1) { | |
885 | /* find tb(n) in circular list */ | |
886 | for (;;) { | |
887 | tb1 = *ptb; | |
888 | n1 = (uintptr_t)tb1 & 3; | |
889 | tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3); | |
890 | if (n1 == n && tb1 == tb) { | |
891 | break; | |
892 | } | |
893 | if (n1 == 2) { | |
894 | ptb = &tb1->jmp_first; | |
895 | } else { | |
896 | ptb = &tb1->jmp_next[n1]; | |
897 | } | |
898 | } | |
899 | /* now we can suppress tb(n) from the list */ | |
900 | *ptb = tb->jmp_next[n]; | |
901 | ||
902 | tb->jmp_next[n] = NULL; | |
903 | } | |
904 | } | |
905 | ||
906 | /* reset the jump entry 'n' of a TB so that it is not chained to | |
907 | another TB */ | |
908 | static inline void tb_reset_jump(TranslationBlock *tb, int n) | |
909 | { | |
910 | tb_set_jmp_target(tb, n, (uintptr_t)(tb->tc_ptr + tb->tb_next_offset[n])); | |
911 | } | |
912 | ||
0c884d16 | 913 | /* invalidate one TB */ |
5b6dd868 BS |
914 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) |
915 | { | |
182735ef | 916 | CPUState *cpu; |
5b6dd868 BS |
917 | PageDesc *p; |
918 | unsigned int h, n1; | |
919 | tb_page_addr_t phys_pc; | |
920 | TranslationBlock *tb1, *tb2; | |
921 | ||
922 | /* remove the TB from the hash list */ | |
923 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
924 | h = tb_phys_hash_func(phys_pc); | |
5e5f07e0 | 925 | tb_hash_remove(&tcg_ctx.tb_ctx.tb_phys_hash[h], tb); |
5b6dd868 BS |
926 | |
927 | /* remove the TB from the page list */ | |
928 | if (tb->page_addr[0] != page_addr) { | |
929 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | |
930 | tb_page_remove(&p->first_tb, tb); | |
931 | invalidate_page_bitmap(p); | |
932 | } | |
933 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { | |
934 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | |
935 | tb_page_remove(&p->first_tb, tb); | |
936 | invalidate_page_bitmap(p); | |
937 | } | |
938 | ||
5e5f07e0 | 939 | tcg_ctx.tb_ctx.tb_invalidated_flag = 1; |
5b6dd868 BS |
940 | |
941 | /* remove the TB from the hash list */ | |
942 | h = tb_jmp_cache_hash_func(tb->pc); | |
bdc44640 | 943 | CPU_FOREACH(cpu) { |
8cd70437 AF |
944 | if (cpu->tb_jmp_cache[h] == tb) { |
945 | cpu->tb_jmp_cache[h] = NULL; | |
5b6dd868 BS |
946 | } |
947 | } | |
948 | ||
949 | /* suppress this TB from the two jump lists */ | |
950 | tb_jmp_remove(tb, 0); | |
951 | tb_jmp_remove(tb, 1); | |
952 | ||
953 | /* suppress any remaining jumps to this TB */ | |
954 | tb1 = tb->jmp_first; | |
955 | for (;;) { | |
956 | n1 = (uintptr_t)tb1 & 3; | |
957 | if (n1 == 2) { | |
958 | break; | |
959 | } | |
960 | tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3); | |
961 | tb2 = tb1->jmp_next[n1]; | |
962 | tb_reset_jump(tb1, n1); | |
963 | tb1->jmp_next[n1] = NULL; | |
964 | tb1 = tb2; | |
965 | } | |
966 | tb->jmp_first = (TranslationBlock *)((uintptr_t)tb | 2); /* fail safe */ | |
967 | ||
5e5f07e0 | 968 | tcg_ctx.tb_ctx.tb_phys_invalidate_count++; |
5b6dd868 BS |
969 | } |
970 | ||
5b6dd868 BS |
971 | static void build_page_bitmap(PageDesc *p) |
972 | { | |
973 | int n, tb_start, tb_end; | |
974 | TranslationBlock *tb; | |
975 | ||
510a647f | 976 | p->code_bitmap = bitmap_new(TARGET_PAGE_SIZE); |
5b6dd868 BS |
977 | |
978 | tb = p->first_tb; | |
979 | while (tb != NULL) { | |
980 | n = (uintptr_t)tb & 3; | |
981 | tb = (TranslationBlock *)((uintptr_t)tb & ~3); | |
982 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
983 | if (n == 0) { | |
984 | /* NOTE: tb_end may be after the end of the page, but | |
985 | it is not a problem */ | |
986 | tb_start = tb->pc & ~TARGET_PAGE_MASK; | |
987 | tb_end = tb_start + tb->size; | |
988 | if (tb_end > TARGET_PAGE_SIZE) { | |
989 | tb_end = TARGET_PAGE_SIZE; | |
990 | } | |
991 | } else { | |
992 | tb_start = 0; | |
993 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
994 | } | |
510a647f | 995 | bitmap_set(p->code_bitmap, tb_start, tb_end - tb_start); |
5b6dd868 BS |
996 | tb = tb->page_next[n]; |
997 | } | |
998 | } | |
999 | ||
648f034c | 1000 | TranslationBlock *tb_gen_code(CPUState *cpu, |
5b6dd868 BS |
1001 | target_ulong pc, target_ulong cs_base, |
1002 | int flags, int cflags) | |
1003 | { | |
648f034c | 1004 | CPUArchState *env = cpu->env_ptr; |
5b6dd868 | 1005 | TranslationBlock *tb; |
5b6dd868 BS |
1006 | tb_page_addr_t phys_pc, phys_page2; |
1007 | target_ulong virt_page2; | |
1008 | int code_gen_size; | |
1009 | ||
1010 | phys_pc = get_page_addr_code(env, pc); | |
0266359e PB |
1011 | if (use_icount) { |
1012 | cflags |= CF_USE_ICOUNT; | |
1013 | } | |
5b6dd868 BS |
1014 | tb = tb_alloc(pc); |
1015 | if (!tb) { | |
1016 | /* flush must be done */ | |
1017 | tb_flush(env); | |
1018 | /* cannot fail at this point */ | |
1019 | tb = tb_alloc(pc); | |
1020 | /* Don't forget to invalidate previous TB info. */ | |
5e5f07e0 | 1021 | tcg_ctx.tb_ctx.tb_invalidated_flag = 1; |
5b6dd868 | 1022 | } |
1813e175 | 1023 | tb->tc_ptr = tcg_ctx.code_gen_ptr; |
5b6dd868 BS |
1024 | tb->cs_base = cs_base; |
1025 | tb->flags = flags; | |
1026 | tb->cflags = cflags; | |
1027 | cpu_gen_code(env, tb, &code_gen_size); | |
0b0d3320 EV |
1028 | tcg_ctx.code_gen_ptr = (void *)(((uintptr_t)tcg_ctx.code_gen_ptr + |
1029 | code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); | |
5b6dd868 BS |
1030 | |
1031 | /* check next page if needed */ | |
1032 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; | |
1033 | phys_page2 = -1; | |
1034 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { | |
1035 | phys_page2 = get_page_addr_code(env, virt_page2); | |
1036 | } | |
1037 | tb_link_page(tb, phys_pc, phys_page2); | |
1038 | return tb; | |
1039 | } | |
1040 | ||
1041 | /* | |
1042 | * Invalidate all TBs which intersect with the target physical address range | |
1043 | * [start;end[. NOTE: start and end may refer to *different* physical pages. | |
1044 | * 'is_cpu_write_access' should be true if called from a real cpu write | |
1045 | * access: the virtual CPU will exit the current TB if code is modified inside | |
1046 | * this TB. | |
1047 | */ | |
35865339 | 1048 | void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end) |
5b6dd868 BS |
1049 | { |
1050 | while (start < end) { | |
35865339 | 1051 | tb_invalidate_phys_page_range(start, end, 0); |
5b6dd868 BS |
1052 | start &= TARGET_PAGE_MASK; |
1053 | start += TARGET_PAGE_SIZE; | |
1054 | } | |
1055 | } | |
1056 | ||
1057 | /* | |
1058 | * Invalidate all TBs which intersect with the target physical address range | |
1059 | * [start;end[. NOTE: start and end must refer to the *same* physical page. | |
1060 | * 'is_cpu_write_access' should be true if called from a real cpu write | |
1061 | * access: the virtual CPU will exit the current TB if code is modified inside | |
1062 | * this TB. | |
1063 | */ | |
1064 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, | |
1065 | int is_cpu_write_access) | |
1066 | { | |
1067 | TranslationBlock *tb, *tb_next, *saved_tb; | |
4917cf44 | 1068 | CPUState *cpu = current_cpu; |
baea4fae | 1069 | #if defined(TARGET_HAS_PRECISE_SMC) |
4917cf44 AF |
1070 | CPUArchState *env = NULL; |
1071 | #endif | |
5b6dd868 BS |
1072 | tb_page_addr_t tb_start, tb_end; |
1073 | PageDesc *p; | |
1074 | int n; | |
1075 | #ifdef TARGET_HAS_PRECISE_SMC | |
1076 | int current_tb_not_found = is_cpu_write_access; | |
1077 | TranslationBlock *current_tb = NULL; | |
1078 | int current_tb_modified = 0; | |
1079 | target_ulong current_pc = 0; | |
1080 | target_ulong current_cs_base = 0; | |
1081 | int current_flags = 0; | |
1082 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
1083 | ||
1084 | p = page_find(start >> TARGET_PAGE_BITS); | |
1085 | if (!p) { | |
1086 | return; | |
1087 | } | |
baea4fae | 1088 | #if defined(TARGET_HAS_PRECISE_SMC) |
4917cf44 AF |
1089 | if (cpu != NULL) { |
1090 | env = cpu->env_ptr; | |
d77953b9 | 1091 | } |
4917cf44 | 1092 | #endif |
5b6dd868 BS |
1093 | |
1094 | /* we remove all the TBs in the range [start, end[ */ | |
1095 | /* XXX: see if in some cases it could be faster to invalidate all | |
1096 | the code */ | |
1097 | tb = p->first_tb; | |
1098 | while (tb != NULL) { | |
1099 | n = (uintptr_t)tb & 3; | |
1100 | tb = (TranslationBlock *)((uintptr_t)tb & ~3); | |
1101 | tb_next = tb->page_next[n]; | |
1102 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
1103 | if (n == 0) { | |
1104 | /* NOTE: tb_end may be after the end of the page, but | |
1105 | it is not a problem */ | |
1106 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
1107 | tb_end = tb_start + tb->size; | |
1108 | } else { | |
1109 | tb_start = tb->page_addr[1]; | |
1110 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
1111 | } | |
1112 | if (!(tb_end <= start || tb_start >= end)) { | |
1113 | #ifdef TARGET_HAS_PRECISE_SMC | |
1114 | if (current_tb_not_found) { | |
1115 | current_tb_not_found = 0; | |
1116 | current_tb = NULL; | |
93afeade | 1117 | if (cpu->mem_io_pc) { |
5b6dd868 | 1118 | /* now we have a real cpu fault */ |
93afeade | 1119 | current_tb = tb_find_pc(cpu->mem_io_pc); |
5b6dd868 BS |
1120 | } |
1121 | } | |
1122 | if (current_tb == tb && | |
1123 | (current_tb->cflags & CF_COUNT_MASK) != 1) { | |
1124 | /* If we are modifying the current TB, we must stop | |
1125 | its execution. We could be more precise by checking | |
1126 | that the modification is after the current PC, but it | |
1127 | would require a specialized function to partially | |
1128 | restore the CPU state */ | |
1129 | ||
1130 | current_tb_modified = 1; | |
74f10515 | 1131 | cpu_restore_state_from_tb(cpu, current_tb, cpu->mem_io_pc); |
5b6dd868 BS |
1132 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1133 | ¤t_flags); | |
1134 | } | |
1135 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
1136 | /* we need to do that to handle the case where a signal | |
1137 | occurs while doing tb_phys_invalidate() */ | |
1138 | saved_tb = NULL; | |
d77953b9 AF |
1139 | if (cpu != NULL) { |
1140 | saved_tb = cpu->current_tb; | |
1141 | cpu->current_tb = NULL; | |
5b6dd868 BS |
1142 | } |
1143 | tb_phys_invalidate(tb, -1); | |
d77953b9 AF |
1144 | if (cpu != NULL) { |
1145 | cpu->current_tb = saved_tb; | |
c3affe56 AF |
1146 | if (cpu->interrupt_request && cpu->current_tb) { |
1147 | cpu_interrupt(cpu, cpu->interrupt_request); | |
5b6dd868 BS |
1148 | } |
1149 | } | |
1150 | } | |
1151 | tb = tb_next; | |
1152 | } | |
1153 | #if !defined(CONFIG_USER_ONLY) | |
1154 | /* if no code remaining, no need to continue to use slow writes */ | |
1155 | if (!p->first_tb) { | |
1156 | invalidate_page_bitmap(p); | |
fc377bcf | 1157 | tlb_unprotect_code(start); |
5b6dd868 BS |
1158 | } |
1159 | #endif | |
1160 | #ifdef TARGET_HAS_PRECISE_SMC | |
1161 | if (current_tb_modified) { | |
1162 | /* we generate a block containing just the instruction | |
1163 | modifying the memory. It will ensure that it cannot modify | |
1164 | itself */ | |
d77953b9 | 1165 | cpu->current_tb = NULL; |
648f034c | 1166 | tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); |
0ea8cb88 | 1167 | cpu_resume_from_signal(cpu, NULL); |
5b6dd868 BS |
1168 | } |
1169 | #endif | |
1170 | } | |
1171 | ||
1172 | /* len must be <= 8 and start must be a multiple of len */ | |
1173 | void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len) | |
1174 | { | |
1175 | PageDesc *p; | |
5b6dd868 BS |
1176 | |
1177 | #if 0 | |
1178 | if (1) { | |
1179 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", | |
1180 | cpu_single_env->mem_io_vaddr, len, | |
1181 | cpu_single_env->eip, | |
1182 | cpu_single_env->eip + | |
1183 | (intptr_t)cpu_single_env->segs[R_CS].base); | |
1184 | } | |
1185 | #endif | |
1186 | p = page_find(start >> TARGET_PAGE_BITS); | |
1187 | if (!p) { | |
1188 | return; | |
1189 | } | |
fc377bcf PB |
1190 | if (!p->code_bitmap && |
1191 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD) { | |
1192 | /* build code bitmap */ | |
1193 | build_page_bitmap(p); | |
1194 | } | |
5b6dd868 | 1195 | if (p->code_bitmap) { |
510a647f EC |
1196 | unsigned int nr; |
1197 | unsigned long b; | |
1198 | ||
1199 | nr = start & ~TARGET_PAGE_MASK; | |
1200 | b = p->code_bitmap[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG - 1)); | |
5b6dd868 BS |
1201 | if (b & ((1 << len) - 1)) { |
1202 | goto do_invalidate; | |
1203 | } | |
1204 | } else { | |
1205 | do_invalidate: | |
1206 | tb_invalidate_phys_page_range(start, start + len, 1); | |
1207 | } | |
1208 | } | |
1209 | ||
1210 | #if !defined(CONFIG_SOFTMMU) | |
1211 | static void tb_invalidate_phys_page(tb_page_addr_t addr, | |
d02532f0 AG |
1212 | uintptr_t pc, void *puc, |
1213 | bool locked) | |
5b6dd868 BS |
1214 | { |
1215 | TranslationBlock *tb; | |
1216 | PageDesc *p; | |
1217 | int n; | |
1218 | #ifdef TARGET_HAS_PRECISE_SMC | |
1219 | TranslationBlock *current_tb = NULL; | |
4917cf44 AF |
1220 | CPUState *cpu = current_cpu; |
1221 | CPUArchState *env = NULL; | |
5b6dd868 BS |
1222 | int current_tb_modified = 0; |
1223 | target_ulong current_pc = 0; | |
1224 | target_ulong current_cs_base = 0; | |
1225 | int current_flags = 0; | |
1226 | #endif | |
1227 | ||
1228 | addr &= TARGET_PAGE_MASK; | |
1229 | p = page_find(addr >> TARGET_PAGE_BITS); | |
1230 | if (!p) { | |
1231 | return; | |
1232 | } | |
1233 | tb = p->first_tb; | |
1234 | #ifdef TARGET_HAS_PRECISE_SMC | |
1235 | if (tb && pc != 0) { | |
1236 | current_tb = tb_find_pc(pc); | |
1237 | } | |
4917cf44 AF |
1238 | if (cpu != NULL) { |
1239 | env = cpu->env_ptr; | |
d77953b9 | 1240 | } |
5b6dd868 BS |
1241 | #endif |
1242 | while (tb != NULL) { | |
1243 | n = (uintptr_t)tb & 3; | |
1244 | tb = (TranslationBlock *)((uintptr_t)tb & ~3); | |
1245 | #ifdef TARGET_HAS_PRECISE_SMC | |
1246 | if (current_tb == tb && | |
1247 | (current_tb->cflags & CF_COUNT_MASK) != 1) { | |
1248 | /* If we are modifying the current TB, we must stop | |
1249 | its execution. We could be more precise by checking | |
1250 | that the modification is after the current PC, but it | |
1251 | would require a specialized function to partially | |
1252 | restore the CPU state */ | |
1253 | ||
1254 | current_tb_modified = 1; | |
74f10515 | 1255 | cpu_restore_state_from_tb(cpu, current_tb, pc); |
5b6dd868 BS |
1256 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1257 | ¤t_flags); | |
1258 | } | |
1259 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
1260 | tb_phys_invalidate(tb, addr); | |
1261 | tb = tb->page_next[n]; | |
1262 | } | |
1263 | p->first_tb = NULL; | |
1264 | #ifdef TARGET_HAS_PRECISE_SMC | |
1265 | if (current_tb_modified) { | |
1266 | /* we generate a block containing just the instruction | |
1267 | modifying the memory. It will ensure that it cannot modify | |
1268 | itself */ | |
d77953b9 | 1269 | cpu->current_tb = NULL; |
648f034c | 1270 | tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); |
d02532f0 AG |
1271 | if (locked) { |
1272 | mmap_unlock(); | |
1273 | } | |
0ea8cb88 | 1274 | cpu_resume_from_signal(cpu, puc); |
5b6dd868 BS |
1275 | } |
1276 | #endif | |
1277 | } | |
1278 | #endif | |
1279 | ||
1280 | /* add the tb in the target page and protect it if necessary */ | |
1281 | static inline void tb_alloc_page(TranslationBlock *tb, | |
1282 | unsigned int n, tb_page_addr_t page_addr) | |
1283 | { | |
1284 | PageDesc *p; | |
1285 | #ifndef CONFIG_USER_ONLY | |
1286 | bool page_already_protected; | |
1287 | #endif | |
1288 | ||
1289 | tb->page_addr[n] = page_addr; | |
1290 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1); | |
1291 | tb->page_next[n] = p->first_tb; | |
1292 | #ifndef CONFIG_USER_ONLY | |
1293 | page_already_protected = p->first_tb != NULL; | |
1294 | #endif | |
1295 | p->first_tb = (TranslationBlock *)((uintptr_t)tb | n); | |
1296 | invalidate_page_bitmap(p); | |
1297 | ||
5b6dd868 BS |
1298 | #if defined(CONFIG_USER_ONLY) |
1299 | if (p->flags & PAGE_WRITE) { | |
1300 | target_ulong addr; | |
1301 | PageDesc *p2; | |
1302 | int prot; | |
1303 | ||
1304 | /* force the host page as non writable (writes will have a | |
1305 | page fault + mprotect overhead) */ | |
1306 | page_addr &= qemu_host_page_mask; | |
1307 | prot = 0; | |
1308 | for (addr = page_addr; addr < page_addr + qemu_host_page_size; | |
1309 | addr += TARGET_PAGE_SIZE) { | |
1310 | ||
1311 | p2 = page_find(addr >> TARGET_PAGE_BITS); | |
1312 | if (!p2) { | |
1313 | continue; | |
1314 | } | |
1315 | prot |= p2->flags; | |
1316 | p2->flags &= ~PAGE_WRITE; | |
1317 | } | |
1318 | mprotect(g2h(page_addr), qemu_host_page_size, | |
1319 | (prot & PAGE_BITS) & ~PAGE_WRITE); | |
1320 | #ifdef DEBUG_TB_INVALIDATE | |
1321 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", | |
1322 | page_addr); | |
1323 | #endif | |
1324 | } | |
1325 | #else | |
1326 | /* if some code is already present, then the pages are already | |
1327 | protected. So we handle the case where only the first TB is | |
1328 | allocated in a physical page */ | |
1329 | if (!page_already_protected) { | |
1330 | tlb_protect_code(page_addr); | |
1331 | } | |
1332 | #endif | |
5b6dd868 BS |
1333 | } |
1334 | ||
1335 | /* add a new TB and link it to the physical page tables. phys_page2 is | |
1336 | (-1) to indicate that only one page contains the TB. */ | |
1337 | static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, | |
1338 | tb_page_addr_t phys_page2) | |
1339 | { | |
1340 | unsigned int h; | |
1341 | TranslationBlock **ptb; | |
1342 | ||
1343 | /* Grab the mmap lock to stop another thread invalidating this TB | |
1344 | before we are done. */ | |
1345 | mmap_lock(); | |
1346 | /* add in the physical hash table */ | |
1347 | h = tb_phys_hash_func(phys_pc); | |
5e5f07e0 | 1348 | ptb = &tcg_ctx.tb_ctx.tb_phys_hash[h]; |
5b6dd868 BS |
1349 | tb->phys_hash_next = *ptb; |
1350 | *ptb = tb; | |
1351 | ||
1352 | /* add in the page list */ | |
1353 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); | |
1354 | if (phys_page2 != -1) { | |
1355 | tb_alloc_page(tb, 1, phys_page2); | |
1356 | } else { | |
1357 | tb->page_addr[1] = -1; | |
1358 | } | |
1359 | ||
1360 | tb->jmp_first = (TranslationBlock *)((uintptr_t)tb | 2); | |
1361 | tb->jmp_next[0] = NULL; | |
1362 | tb->jmp_next[1] = NULL; | |
1363 | ||
1364 | /* init original jump addresses */ | |
1365 | if (tb->tb_next_offset[0] != 0xffff) { | |
1366 | tb_reset_jump(tb, 0); | |
1367 | } | |
1368 | if (tb->tb_next_offset[1] != 0xffff) { | |
1369 | tb_reset_jump(tb, 1); | |
1370 | } | |
1371 | ||
1372 | #ifdef DEBUG_TB_CHECK | |
1373 | tb_page_check(); | |
1374 | #endif | |
1375 | mmap_unlock(); | |
1376 | } | |
1377 | ||
5b6dd868 BS |
1378 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
1379 | tb[1].tc_ptr. Return NULL if not found */ | |
a8a826a3 | 1380 | static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) |
5b6dd868 BS |
1381 | { |
1382 | int m_min, m_max, m; | |
1383 | uintptr_t v; | |
1384 | TranslationBlock *tb; | |
1385 | ||
5e5f07e0 | 1386 | if (tcg_ctx.tb_ctx.nb_tbs <= 0) { |
5b6dd868 BS |
1387 | return NULL; |
1388 | } | |
0b0d3320 EV |
1389 | if (tc_ptr < (uintptr_t)tcg_ctx.code_gen_buffer || |
1390 | tc_ptr >= (uintptr_t)tcg_ctx.code_gen_ptr) { | |
5b6dd868 BS |
1391 | return NULL; |
1392 | } | |
1393 | /* binary search (cf Knuth) */ | |
1394 | m_min = 0; | |
5e5f07e0 | 1395 | m_max = tcg_ctx.tb_ctx.nb_tbs - 1; |
5b6dd868 BS |
1396 | while (m_min <= m_max) { |
1397 | m = (m_min + m_max) >> 1; | |
5e5f07e0 | 1398 | tb = &tcg_ctx.tb_ctx.tbs[m]; |
5b6dd868 BS |
1399 | v = (uintptr_t)tb->tc_ptr; |
1400 | if (v == tc_ptr) { | |
1401 | return tb; | |
1402 | } else if (tc_ptr < v) { | |
1403 | m_max = m - 1; | |
1404 | } else { | |
1405 | m_min = m + 1; | |
1406 | } | |
1407 | } | |
5e5f07e0 | 1408 | return &tcg_ctx.tb_ctx.tbs[m_max]; |
5b6dd868 BS |
1409 | } |
1410 | ||
ec53b45b | 1411 | #if !defined(CONFIG_USER_ONLY) |
29d8ec7b | 1412 | void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) |
5b6dd868 BS |
1413 | { |
1414 | ram_addr_t ram_addr; | |
5c8a00ce | 1415 | MemoryRegion *mr; |
149f54b5 | 1416 | hwaddr l = 1; |
5b6dd868 | 1417 | |
41063e1e | 1418 | rcu_read_lock(); |
29d8ec7b | 1419 | mr = address_space_translate(as, addr, &addr, &l, false); |
5c8a00ce PB |
1420 | if (!(memory_region_is_ram(mr) |
1421 | || memory_region_is_romd(mr))) { | |
41063e1e | 1422 | rcu_read_unlock(); |
5b6dd868 BS |
1423 | return; |
1424 | } | |
5c8a00ce | 1425 | ram_addr = (memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK) |
149f54b5 | 1426 | + addr; |
5b6dd868 | 1427 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
41063e1e | 1428 | rcu_read_unlock(); |
5b6dd868 | 1429 | } |
ec53b45b | 1430 | #endif /* !defined(CONFIG_USER_ONLY) */ |
5b6dd868 | 1431 | |
239c51a5 | 1432 | void tb_check_watchpoint(CPUState *cpu) |
5b6dd868 BS |
1433 | { |
1434 | TranslationBlock *tb; | |
1435 | ||
93afeade | 1436 | tb = tb_find_pc(cpu->mem_io_pc); |
8d302e76 AJ |
1437 | if (tb) { |
1438 | /* We can use retranslation to find the PC. */ | |
1439 | cpu_restore_state_from_tb(cpu, tb, cpu->mem_io_pc); | |
1440 | tb_phys_invalidate(tb, -1); | |
1441 | } else { | |
1442 | /* The exception probably happened in a helper. The CPU state should | |
1443 | have been saved before calling it. Fetch the PC from there. */ | |
1444 | CPUArchState *env = cpu->env_ptr; | |
1445 | target_ulong pc, cs_base; | |
1446 | tb_page_addr_t addr; | |
1447 | int flags; | |
1448 | ||
1449 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); | |
1450 | addr = get_page_addr_code(env, pc); | |
1451 | tb_invalidate_phys_range(addr, addr + 1); | |
5b6dd868 | 1452 | } |
5b6dd868 BS |
1453 | } |
1454 | ||
1455 | #ifndef CONFIG_USER_ONLY | |
1456 | /* mask must never be zero, except for A20 change call */ | |
c3affe56 | 1457 | static void tcg_handle_interrupt(CPUState *cpu, int mask) |
5b6dd868 | 1458 | { |
5b6dd868 BS |
1459 | int old_mask; |
1460 | ||
259186a7 AF |
1461 | old_mask = cpu->interrupt_request; |
1462 | cpu->interrupt_request |= mask; | |
5b6dd868 BS |
1463 | |
1464 | /* | |
1465 | * If called from iothread context, wake the target cpu in | |
1466 | * case its halted. | |
1467 | */ | |
1468 | if (!qemu_cpu_is_self(cpu)) { | |
1469 | qemu_cpu_kick(cpu); | |
1470 | return; | |
1471 | } | |
1472 | ||
1473 | if (use_icount) { | |
28ecfd7a | 1474 | cpu->icount_decr.u16.high = 0xffff; |
99df7dce | 1475 | if (!cpu_can_do_io(cpu) |
5b6dd868 | 1476 | && (mask & ~old_mask) != 0) { |
a47dddd7 | 1477 | cpu_abort(cpu, "Raised interrupt while not in I/O function"); |
5b6dd868 BS |
1478 | } |
1479 | } else { | |
378df4b2 | 1480 | cpu->tcg_exit_req = 1; |
5b6dd868 BS |
1481 | } |
1482 | } | |
1483 | ||
1484 | CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt; | |
1485 | ||
1486 | /* in deterministic execution mode, instructions doing device I/Os | |
1487 | must be at the end of the TB */ | |
90b40a69 | 1488 | void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) |
5b6dd868 | 1489 | { |
a47dddd7 | 1490 | #if defined(TARGET_MIPS) || defined(TARGET_SH4) |
90b40a69 | 1491 | CPUArchState *env = cpu->env_ptr; |
a47dddd7 | 1492 | #endif |
5b6dd868 BS |
1493 | TranslationBlock *tb; |
1494 | uint32_t n, cflags; | |
1495 | target_ulong pc, cs_base; | |
1496 | uint64_t flags; | |
1497 | ||
1498 | tb = tb_find_pc(retaddr); | |
1499 | if (!tb) { | |
a47dddd7 | 1500 | cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p", |
5b6dd868 BS |
1501 | (void *)retaddr); |
1502 | } | |
28ecfd7a | 1503 | n = cpu->icount_decr.u16.low + tb->icount; |
74f10515 | 1504 | cpu_restore_state_from_tb(cpu, tb, retaddr); |
5b6dd868 BS |
1505 | /* Calculate how many instructions had been executed before the fault |
1506 | occurred. */ | |
28ecfd7a | 1507 | n = n - cpu->icount_decr.u16.low; |
5b6dd868 BS |
1508 | /* Generate a new TB ending on the I/O insn. */ |
1509 | n++; | |
1510 | /* On MIPS and SH, delay slot instructions can only be restarted if | |
1511 | they were already the first instruction in the TB. If this is not | |
1512 | the first instruction in a TB then re-execute the preceding | |
1513 | branch. */ | |
1514 | #if defined(TARGET_MIPS) | |
1515 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { | |
c3577479 | 1516 | env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); |
28ecfd7a | 1517 | cpu->icount_decr.u16.low++; |
5b6dd868 BS |
1518 | env->hflags &= ~MIPS_HFLAG_BMASK; |
1519 | } | |
1520 | #elif defined(TARGET_SH4) | |
1521 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 | |
1522 | && n > 1) { | |
1523 | env->pc -= 2; | |
28ecfd7a | 1524 | cpu->icount_decr.u16.low++; |
5b6dd868 BS |
1525 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
1526 | } | |
1527 | #endif | |
1528 | /* This should never happen. */ | |
1529 | if (n > CF_COUNT_MASK) { | |
a47dddd7 | 1530 | cpu_abort(cpu, "TB too big during recompile"); |
5b6dd868 BS |
1531 | } |
1532 | ||
1533 | cflags = n | CF_LAST_IO; | |
1534 | pc = tb->pc; | |
1535 | cs_base = tb->cs_base; | |
1536 | flags = tb->flags; | |
1537 | tb_phys_invalidate(tb, -1); | |
1538 | /* FIXME: In theory this could raise an exception. In practice | |
1539 | we have already translated the block once so it's probably ok. */ | |
648f034c | 1540 | tb_gen_code(cpu, pc, cs_base, flags, cflags); |
5b6dd868 BS |
1541 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
1542 | the first in the TB) then we end up generating a whole new TB and | |
1543 | repeating the fault, which is horribly inefficient. | |
1544 | Better would be to execute just this insn uncached, or generate a | |
1545 | second new TB. */ | |
0ea8cb88 | 1546 | cpu_resume_from_signal(cpu, NULL); |
5b6dd868 BS |
1547 | } |
1548 | ||
611d4f99 | 1549 | void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr) |
5b6dd868 BS |
1550 | { |
1551 | unsigned int i; | |
1552 | ||
1553 | /* Discard jump cache entries for any tb which might potentially | |
1554 | overlap the flushed page. */ | |
1555 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); | |
8cd70437 | 1556 | memset(&cpu->tb_jmp_cache[i], 0, |
5b6dd868 BS |
1557 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
1558 | ||
1559 | i = tb_jmp_cache_hash_page(addr); | |
8cd70437 | 1560 | memset(&cpu->tb_jmp_cache[i], 0, |
5b6dd868 BS |
1561 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
1562 | } | |
1563 | ||
1564 | void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) | |
1565 | { | |
1566 | int i, target_code_size, max_target_code_size; | |
1567 | int direct_jmp_count, direct_jmp2_count, cross_page; | |
1568 | TranslationBlock *tb; | |
1569 | ||
1570 | target_code_size = 0; | |
1571 | max_target_code_size = 0; | |
1572 | cross_page = 0; | |
1573 | direct_jmp_count = 0; | |
1574 | direct_jmp2_count = 0; | |
5e5f07e0 EV |
1575 | for (i = 0; i < tcg_ctx.tb_ctx.nb_tbs; i++) { |
1576 | tb = &tcg_ctx.tb_ctx.tbs[i]; | |
5b6dd868 BS |
1577 | target_code_size += tb->size; |
1578 | if (tb->size > max_target_code_size) { | |
1579 | max_target_code_size = tb->size; | |
1580 | } | |
1581 | if (tb->page_addr[1] != -1) { | |
1582 | cross_page++; | |
1583 | } | |
1584 | if (tb->tb_next_offset[0] != 0xffff) { | |
1585 | direct_jmp_count++; | |
1586 | if (tb->tb_next_offset[1] != 0xffff) { | |
1587 | direct_jmp2_count++; | |
1588 | } | |
1589 | } | |
1590 | } | |
1591 | /* XXX: avoid using doubles ? */ | |
1592 | cpu_fprintf(f, "Translation buffer state:\n"); | |
1593 | cpu_fprintf(f, "gen code size %td/%zd\n", | |
0b0d3320 EV |
1594 | tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, |
1595 | tcg_ctx.code_gen_buffer_max_size); | |
5b6dd868 | 1596 | cpu_fprintf(f, "TB count %d/%d\n", |
5e5f07e0 | 1597 | tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.code_gen_max_blocks); |
5b6dd868 | 1598 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
5e5f07e0 EV |
1599 | tcg_ctx.tb_ctx.nb_tbs ? target_code_size / |
1600 | tcg_ctx.tb_ctx.nb_tbs : 0, | |
1601 | max_target_code_size); | |
5b6dd868 | 1602 | cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)\n", |
5e5f07e0 EV |
1603 | tcg_ctx.tb_ctx.nb_tbs ? (tcg_ctx.code_gen_ptr - |
1604 | tcg_ctx.code_gen_buffer) / | |
1605 | tcg_ctx.tb_ctx.nb_tbs : 0, | |
1606 | target_code_size ? (double) (tcg_ctx.code_gen_ptr - | |
1607 | tcg_ctx.code_gen_buffer) / | |
1608 | target_code_size : 0); | |
1609 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", cross_page, | |
1610 | tcg_ctx.tb_ctx.nb_tbs ? (cross_page * 100) / | |
1611 | tcg_ctx.tb_ctx.nb_tbs : 0); | |
5b6dd868 BS |
1612 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", |
1613 | direct_jmp_count, | |
5e5f07e0 EV |
1614 | tcg_ctx.tb_ctx.nb_tbs ? (direct_jmp_count * 100) / |
1615 | tcg_ctx.tb_ctx.nb_tbs : 0, | |
5b6dd868 | 1616 | direct_jmp2_count, |
5e5f07e0 EV |
1617 | tcg_ctx.tb_ctx.nb_tbs ? (direct_jmp2_count * 100) / |
1618 | tcg_ctx.tb_ctx.nb_tbs : 0); | |
5b6dd868 | 1619 | cpu_fprintf(f, "\nStatistics:\n"); |
5e5f07e0 EV |
1620 | cpu_fprintf(f, "TB flush count %d\n", tcg_ctx.tb_ctx.tb_flush_count); |
1621 | cpu_fprintf(f, "TB invalidate count %d\n", | |
1622 | tcg_ctx.tb_ctx.tb_phys_invalidate_count); | |
5b6dd868 BS |
1623 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); |
1624 | tcg_dump_info(f, cpu_fprintf); | |
1625 | } | |
1626 | ||
246ae24d MF |
1627 | void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf) |
1628 | { | |
1629 | tcg_dump_op_count(f, cpu_fprintf); | |
1630 | } | |
1631 | ||
5b6dd868 BS |
1632 | #else /* CONFIG_USER_ONLY */ |
1633 | ||
c3affe56 | 1634 | void cpu_interrupt(CPUState *cpu, int mask) |
5b6dd868 | 1635 | { |
259186a7 | 1636 | cpu->interrupt_request |= mask; |
378df4b2 | 1637 | cpu->tcg_exit_req = 1; |
5b6dd868 BS |
1638 | } |
1639 | ||
1640 | /* | |
1641 | * Walks guest process memory "regions" one by one | |
1642 | * and calls callback function 'fn' for each region. | |
1643 | */ | |
1644 | struct walk_memory_regions_data { | |
1645 | walk_memory_regions_fn fn; | |
1646 | void *priv; | |
1a1c4db9 | 1647 | target_ulong start; |
5b6dd868 BS |
1648 | int prot; |
1649 | }; | |
1650 | ||
1651 | static int walk_memory_regions_end(struct walk_memory_regions_data *data, | |
1a1c4db9 | 1652 | target_ulong end, int new_prot) |
5b6dd868 | 1653 | { |
1a1c4db9 | 1654 | if (data->start != -1u) { |
5b6dd868 BS |
1655 | int rc = data->fn(data->priv, data->start, end, data->prot); |
1656 | if (rc != 0) { | |
1657 | return rc; | |
1658 | } | |
1659 | } | |
1660 | ||
1a1c4db9 | 1661 | data->start = (new_prot ? end : -1u); |
5b6dd868 BS |
1662 | data->prot = new_prot; |
1663 | ||
1664 | return 0; | |
1665 | } | |
1666 | ||
1667 | static int walk_memory_regions_1(struct walk_memory_regions_data *data, | |
1a1c4db9 | 1668 | target_ulong base, int level, void **lp) |
5b6dd868 | 1669 | { |
1a1c4db9 | 1670 | target_ulong pa; |
5b6dd868 BS |
1671 | int i, rc; |
1672 | ||
1673 | if (*lp == NULL) { | |
1674 | return walk_memory_regions_end(data, base, 0); | |
1675 | } | |
1676 | ||
1677 | if (level == 0) { | |
1678 | PageDesc *pd = *lp; | |
1679 | ||
03f49957 | 1680 | for (i = 0; i < V_L2_SIZE; ++i) { |
5b6dd868 BS |
1681 | int prot = pd[i].flags; |
1682 | ||
1683 | pa = base | (i << TARGET_PAGE_BITS); | |
1684 | if (prot != data->prot) { | |
1685 | rc = walk_memory_regions_end(data, pa, prot); | |
1686 | if (rc != 0) { | |
1687 | return rc; | |
1688 | } | |
1689 | } | |
1690 | } | |
1691 | } else { | |
1692 | void **pp = *lp; | |
1693 | ||
03f49957 | 1694 | for (i = 0; i < V_L2_SIZE; ++i) { |
1a1c4db9 | 1695 | pa = base | ((target_ulong)i << |
03f49957 | 1696 | (TARGET_PAGE_BITS + V_L2_BITS * level)); |
5b6dd868 BS |
1697 | rc = walk_memory_regions_1(data, pa, level - 1, pp + i); |
1698 | if (rc != 0) { | |
1699 | return rc; | |
1700 | } | |
1701 | } | |
1702 | } | |
1703 | ||
1704 | return 0; | |
1705 | } | |
1706 | ||
1707 | int walk_memory_regions(void *priv, walk_memory_regions_fn fn) | |
1708 | { | |
1709 | struct walk_memory_regions_data data; | |
1710 | uintptr_t i; | |
1711 | ||
1712 | data.fn = fn; | |
1713 | data.priv = priv; | |
1a1c4db9 | 1714 | data.start = -1u; |
5b6dd868 BS |
1715 | data.prot = 0; |
1716 | ||
1717 | for (i = 0; i < V_L1_SIZE; i++) { | |
1a1c4db9 | 1718 | int rc = walk_memory_regions_1(&data, (target_ulong)i << (V_L1_SHIFT + TARGET_PAGE_BITS), |
03f49957 | 1719 | V_L1_SHIFT / V_L2_BITS - 1, l1_map + i); |
5b6dd868 BS |
1720 | if (rc != 0) { |
1721 | return rc; | |
1722 | } | |
1723 | } | |
1724 | ||
1725 | return walk_memory_regions_end(&data, 0, 0); | |
1726 | } | |
1727 | ||
1a1c4db9 MI |
1728 | static int dump_region(void *priv, target_ulong start, |
1729 | target_ulong end, unsigned long prot) | |
5b6dd868 BS |
1730 | { |
1731 | FILE *f = (FILE *)priv; | |
1732 | ||
1a1c4db9 MI |
1733 | (void) fprintf(f, TARGET_FMT_lx"-"TARGET_FMT_lx |
1734 | " "TARGET_FMT_lx" %c%c%c\n", | |
5b6dd868 BS |
1735 | start, end, end - start, |
1736 | ((prot & PAGE_READ) ? 'r' : '-'), | |
1737 | ((prot & PAGE_WRITE) ? 'w' : '-'), | |
1738 | ((prot & PAGE_EXEC) ? 'x' : '-')); | |
1739 | ||
1740 | return 0; | |
1741 | } | |
1742 | ||
1743 | /* dump memory mappings */ | |
1744 | void page_dump(FILE *f) | |
1745 | { | |
1a1c4db9 | 1746 | const int length = sizeof(target_ulong) * 2; |
227b8175 SW |
1747 | (void) fprintf(f, "%-*s %-*s %-*s %s\n", |
1748 | length, "start", length, "end", length, "size", "prot"); | |
5b6dd868 BS |
1749 | walk_memory_regions(f, dump_region); |
1750 | } | |
1751 | ||
1752 | int page_get_flags(target_ulong address) | |
1753 | { | |
1754 | PageDesc *p; | |
1755 | ||
1756 | p = page_find(address >> TARGET_PAGE_BITS); | |
1757 | if (!p) { | |
1758 | return 0; | |
1759 | } | |
1760 | return p->flags; | |
1761 | } | |
1762 | ||
1763 | /* Modify the flags of a page and invalidate the code if necessary. | |
1764 | The flag PAGE_WRITE_ORG is positioned automatically depending | |
1765 | on PAGE_WRITE. The mmap_lock should already be held. */ | |
1766 | void page_set_flags(target_ulong start, target_ulong end, int flags) | |
1767 | { | |
1768 | target_ulong addr, len; | |
1769 | ||
1770 | /* This function should never be called with addresses outside the | |
1771 | guest address space. If this assert fires, it probably indicates | |
1772 | a missing call to h2g_valid. */ | |
1773 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS | |
1a1c4db9 | 1774 | assert(end < ((target_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); |
5b6dd868 BS |
1775 | #endif |
1776 | assert(start < end); | |
1777 | ||
1778 | start = start & TARGET_PAGE_MASK; | |
1779 | end = TARGET_PAGE_ALIGN(end); | |
1780 | ||
1781 | if (flags & PAGE_WRITE) { | |
1782 | flags |= PAGE_WRITE_ORG; | |
1783 | } | |
1784 | ||
1785 | for (addr = start, len = end - start; | |
1786 | len != 0; | |
1787 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
1788 | PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
1789 | ||
1790 | /* If the write protection bit is set, then we invalidate | |
1791 | the code inside. */ | |
1792 | if (!(p->flags & PAGE_WRITE) && | |
1793 | (flags & PAGE_WRITE) && | |
1794 | p->first_tb) { | |
d02532f0 | 1795 | tb_invalidate_phys_page(addr, 0, NULL, false); |
5b6dd868 BS |
1796 | } |
1797 | p->flags = flags; | |
1798 | } | |
1799 | } | |
1800 | ||
1801 | int page_check_range(target_ulong start, target_ulong len, int flags) | |
1802 | { | |
1803 | PageDesc *p; | |
1804 | target_ulong end; | |
1805 | target_ulong addr; | |
1806 | ||
1807 | /* This function should never be called with addresses outside the | |
1808 | guest address space. If this assert fires, it probably indicates | |
1809 | a missing call to h2g_valid. */ | |
1810 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS | |
1a1c4db9 | 1811 | assert(start < ((target_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); |
5b6dd868 BS |
1812 | #endif |
1813 | ||
1814 | if (len == 0) { | |
1815 | return 0; | |
1816 | } | |
1817 | if (start + len - 1 < start) { | |
1818 | /* We've wrapped around. */ | |
1819 | return -1; | |
1820 | } | |
1821 | ||
1822 | /* must do before we loose bits in the next step */ | |
1823 | end = TARGET_PAGE_ALIGN(start + len); | |
1824 | start = start & TARGET_PAGE_MASK; | |
1825 | ||
1826 | for (addr = start, len = end - start; | |
1827 | len != 0; | |
1828 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
1829 | p = page_find(addr >> TARGET_PAGE_BITS); | |
1830 | if (!p) { | |
1831 | return -1; | |
1832 | } | |
1833 | if (!(p->flags & PAGE_VALID)) { | |
1834 | return -1; | |
1835 | } | |
1836 | ||
1837 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) { | |
1838 | return -1; | |
1839 | } | |
1840 | if (flags & PAGE_WRITE) { | |
1841 | if (!(p->flags & PAGE_WRITE_ORG)) { | |
1842 | return -1; | |
1843 | } | |
1844 | /* unprotect the page if it was put read-only because it | |
1845 | contains translated code */ | |
1846 | if (!(p->flags & PAGE_WRITE)) { | |
1847 | if (!page_unprotect(addr, 0, NULL)) { | |
1848 | return -1; | |
1849 | } | |
1850 | } | |
5b6dd868 BS |
1851 | } |
1852 | } | |
1853 | return 0; | |
1854 | } | |
1855 | ||
1856 | /* called from signal handler: invalidate the code and unprotect the | |
1857 | page. Return TRUE if the fault was successfully handled. */ | |
1858 | int page_unprotect(target_ulong address, uintptr_t pc, void *puc) | |
1859 | { | |
1860 | unsigned int prot; | |
1861 | PageDesc *p; | |
1862 | target_ulong host_start, host_end, addr; | |
1863 | ||
1864 | /* Technically this isn't safe inside a signal handler. However we | |
1865 | know this only ever happens in a synchronous SEGV handler, so in | |
1866 | practice it seems to be ok. */ | |
1867 | mmap_lock(); | |
1868 | ||
1869 | p = page_find(address >> TARGET_PAGE_BITS); | |
1870 | if (!p) { | |
1871 | mmap_unlock(); | |
1872 | return 0; | |
1873 | } | |
1874 | ||
1875 | /* if the page was really writable, then we change its | |
1876 | protection back to writable */ | |
1877 | if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) { | |
1878 | host_start = address & qemu_host_page_mask; | |
1879 | host_end = host_start + qemu_host_page_size; | |
1880 | ||
1881 | prot = 0; | |
1882 | for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) { | |
1883 | p = page_find(addr >> TARGET_PAGE_BITS); | |
1884 | p->flags |= PAGE_WRITE; | |
1885 | prot |= p->flags; | |
1886 | ||
1887 | /* and since the content will be modified, we must invalidate | |
1888 | the corresponding translated code. */ | |
d02532f0 | 1889 | tb_invalidate_phys_page(addr, pc, puc, true); |
5b6dd868 BS |
1890 | #ifdef DEBUG_TB_CHECK |
1891 | tb_invalidate_check(addr); | |
1892 | #endif | |
1893 | } | |
1894 | mprotect((void *)g2h(host_start), qemu_host_page_size, | |
1895 | prot & PAGE_BITS); | |
1896 | ||
1897 | mmap_unlock(); | |
1898 | return 1; | |
1899 | } | |
1900 | mmap_unlock(); | |
1901 | return 0; | |
1902 | } | |
1903 | #endif /* CONFIG_USER_ONLY */ |