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Commit | Line | Data |
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d19893da FB |
1 | /* |
2 | * Host code generation | |
5fafdf24 | 3 | * |
d19893da FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
d19893da | 18 | */ |
5b6dd868 BS |
19 | #ifdef _WIN32 |
20 | #include <windows.h> | |
21 | #else | |
5b6dd868 BS |
22 | #include <sys/mman.h> |
23 | #endif | |
7b31bbc2 | 24 | #include "qemu/osdep.h" |
d19893da | 25 | |
2054396a | 26 | |
5b6dd868 | 27 | #include "qemu-common.h" |
af5ad107 | 28 | #define NO_CPU_IO_DEFS |
d3eead2e | 29 | #include "cpu.h" |
6db8b538 | 30 | #include "trace.h" |
76cad711 | 31 | #include "disas/disas.h" |
57fec1fe | 32 | #include "tcg.h" |
5b6dd868 BS |
33 | #if defined(CONFIG_USER_ONLY) |
34 | #include "qemu.h" | |
35 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) | |
36 | #include <sys/param.h> | |
37 | #if __FreeBSD_version >= 700104 | |
38 | #define HAVE_KINFO_GETVMMAP | |
39 | #define sigqueue sigqueue_freebsd /* avoid redefinition */ | |
5b6dd868 BS |
40 | #include <sys/proc.h> |
41 | #include <machine/profile.h> | |
42 | #define _KERNEL | |
43 | #include <sys/user.h> | |
44 | #undef _KERNEL | |
45 | #undef sigqueue | |
46 | #include <libutil.h> | |
47 | #endif | |
48 | #endif | |
0bc3cd62 PB |
49 | #else |
50 | #include "exec/address-spaces.h" | |
5b6dd868 BS |
51 | #endif |
52 | ||
022c62cb | 53 | #include "exec/cputlb.h" |
e1b89321 | 54 | #include "exec/tb-hash.h" |
5b6dd868 | 55 | #include "translate-all.h" |
510a647f | 56 | #include "qemu/bitmap.h" |
0aa09897 | 57 | #include "qemu/timer.h" |
508127e2 | 58 | #include "exec/log.h" |
5b6dd868 BS |
59 | |
60 | //#define DEBUG_TB_INVALIDATE | |
61 | //#define DEBUG_FLUSH | |
62 | /* make various TB consistency checks */ | |
63 | //#define DEBUG_TB_CHECK | |
64 | ||
65 | #if !defined(CONFIG_USER_ONLY) | |
66 | /* TB consistency checks only implemented for usermode emulation. */ | |
67 | #undef DEBUG_TB_CHECK | |
68 | #endif | |
69 | ||
70 | #define SMC_BITMAP_USE_THRESHOLD 10 | |
71 | ||
5b6dd868 BS |
72 | typedef struct PageDesc { |
73 | /* list of TBs intersecting this ram page */ | |
74 | TranslationBlock *first_tb; | |
75 | /* in order to optimize self modifying code, we count the number | |
76 | of lookups we do to a given page to use a bitmap */ | |
77 | unsigned int code_write_count; | |
510a647f | 78 | unsigned long *code_bitmap; |
5b6dd868 BS |
79 | #if defined(CONFIG_USER_ONLY) |
80 | unsigned long flags; | |
81 | #endif | |
82 | } PageDesc; | |
83 | ||
84 | /* In system mode we want L1_MAP to be based on ram offsets, | |
85 | while in user mode we want it to be based on virtual addresses. */ | |
86 | #if !defined(CONFIG_USER_ONLY) | |
87 | #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS | |
88 | # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS | |
89 | #else | |
90 | # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS | |
91 | #endif | |
92 | #else | |
93 | # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS | |
94 | #endif | |
95 | ||
03f49957 PB |
96 | /* Size of the L2 (and L3, etc) page tables. */ |
97 | #define V_L2_BITS 10 | |
98 | #define V_L2_SIZE (1 << V_L2_BITS) | |
99 | ||
5b6dd868 BS |
100 | /* The bits remaining after N lower levels of page tables. */ |
101 | #define V_L1_BITS_REM \ | |
03f49957 | 102 | ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % V_L2_BITS) |
5b6dd868 BS |
103 | |
104 | #if V_L1_BITS_REM < 4 | |
03f49957 | 105 | #define V_L1_BITS (V_L1_BITS_REM + V_L2_BITS) |
5b6dd868 BS |
106 | #else |
107 | #define V_L1_BITS V_L1_BITS_REM | |
108 | #endif | |
109 | ||
110 | #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS) | |
111 | ||
112 | #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS) | |
113 | ||
5b6dd868 | 114 | uintptr_t qemu_host_page_size; |
0c2d70c4 | 115 | intptr_t qemu_host_page_mask; |
5b6dd868 | 116 | |
d1142fb8 | 117 | /* The bottom level has pointers to PageDesc */ |
5b6dd868 BS |
118 | static void *l1_map[V_L1_SIZE]; |
119 | ||
57fec1fe FB |
120 | /* code generation context */ |
121 | TCGContext tcg_ctx; | |
d19893da | 122 | |
677ef623 FK |
123 | /* translation block context */ |
124 | #ifdef CONFIG_USER_ONLY | |
125 | __thread int have_tb_lock; | |
126 | #endif | |
127 | ||
128 | void tb_lock(void) | |
129 | { | |
130 | #ifdef CONFIG_USER_ONLY | |
131 | assert(!have_tb_lock); | |
132 | qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); | |
133 | have_tb_lock++; | |
134 | #endif | |
135 | } | |
136 | ||
137 | void tb_unlock(void) | |
138 | { | |
139 | #ifdef CONFIG_USER_ONLY | |
140 | assert(have_tb_lock); | |
141 | have_tb_lock--; | |
142 | qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); | |
143 | #endif | |
144 | } | |
145 | ||
146 | void tb_lock_reset(void) | |
147 | { | |
148 | #ifdef CONFIG_USER_ONLY | |
149 | if (have_tb_lock) { | |
150 | qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); | |
151 | have_tb_lock = 0; | |
152 | } | |
153 | #endif | |
154 | } | |
155 | ||
5b6dd868 BS |
156 | static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, |
157 | tb_page_addr_t phys_page2); | |
a8a826a3 | 158 | static TranslationBlock *tb_find_pc(uintptr_t tc_ptr); |
5b6dd868 | 159 | |
57fec1fe FB |
160 | void cpu_gen_init(void) |
161 | { | |
162 | tcg_context_init(&tcg_ctx); | |
57fec1fe FB |
163 | } |
164 | ||
fca8a500 RH |
165 | /* Encode VAL as a signed leb128 sequence at P. |
166 | Return P incremented past the encoded value. */ | |
167 | static uint8_t *encode_sleb128(uint8_t *p, target_long val) | |
168 | { | |
169 | int more, byte; | |
170 | ||
171 | do { | |
172 | byte = val & 0x7f; | |
173 | val >>= 7; | |
174 | more = !((val == 0 && (byte & 0x40) == 0) | |
175 | || (val == -1 && (byte & 0x40) != 0)); | |
176 | if (more) { | |
177 | byte |= 0x80; | |
178 | } | |
179 | *p++ = byte; | |
180 | } while (more); | |
181 | ||
182 | return p; | |
183 | } | |
184 | ||
185 | /* Decode a signed leb128 sequence at *PP; increment *PP past the | |
186 | decoded value. Return the decoded value. */ | |
187 | static target_long decode_sleb128(uint8_t **pp) | |
188 | { | |
189 | uint8_t *p = *pp; | |
190 | target_long val = 0; | |
191 | int byte, shift = 0; | |
192 | ||
193 | do { | |
194 | byte = *p++; | |
195 | val |= (target_ulong)(byte & 0x7f) << shift; | |
196 | shift += 7; | |
197 | } while (byte & 0x80); | |
198 | if (shift < TARGET_LONG_BITS && (byte & 0x40)) { | |
199 | val |= -(target_ulong)1 << shift; | |
200 | } | |
201 | ||
202 | *pp = p; | |
203 | return val; | |
204 | } | |
205 | ||
206 | /* Encode the data collected about the instructions while compiling TB. | |
207 | Place the data at BLOCK, and return the number of bytes consumed. | |
208 | ||
209 | The logical table consisits of TARGET_INSN_START_WORDS target_ulong's, | |
210 | which come from the target's insn_start data, followed by a uintptr_t | |
211 | which comes from the host pc of the end of the code implementing the insn. | |
212 | ||
213 | Each line of the table is encoded as sleb128 deltas from the previous | |
214 | line. The seed for the first line is { tb->pc, 0..., tb->tc_ptr }. | |
215 | That is, the first column is seeded with the guest pc, the last column | |
216 | with the host pc, and the middle columns with zeros. */ | |
217 | ||
218 | static int encode_search(TranslationBlock *tb, uint8_t *block) | |
219 | { | |
b125f9dc | 220 | uint8_t *highwater = tcg_ctx.code_gen_highwater; |
fca8a500 RH |
221 | uint8_t *p = block; |
222 | int i, j, n; | |
223 | ||
224 | tb->tc_search = block; | |
225 | ||
226 | for (i = 0, n = tb->icount; i < n; ++i) { | |
227 | target_ulong prev; | |
228 | ||
229 | for (j = 0; j < TARGET_INSN_START_WORDS; ++j) { | |
230 | if (i == 0) { | |
231 | prev = (j == 0 ? tb->pc : 0); | |
232 | } else { | |
233 | prev = tcg_ctx.gen_insn_data[i - 1][j]; | |
234 | } | |
235 | p = encode_sleb128(p, tcg_ctx.gen_insn_data[i][j] - prev); | |
236 | } | |
237 | prev = (i == 0 ? 0 : tcg_ctx.gen_insn_end_off[i - 1]); | |
238 | p = encode_sleb128(p, tcg_ctx.gen_insn_end_off[i] - prev); | |
b125f9dc RH |
239 | |
240 | /* Test for (pending) buffer overflow. The assumption is that any | |
241 | one row beginning below the high water mark cannot overrun | |
242 | the buffer completely. Thus we can test for overflow after | |
243 | encoding a row without having to check during encoding. */ | |
244 | if (unlikely(p > highwater)) { | |
245 | return -1; | |
246 | } | |
fca8a500 RH |
247 | } |
248 | ||
249 | return p - block; | |
250 | } | |
251 | ||
fec88f64 | 252 | /* The cpu state corresponding to 'searched_pc' is restored. */ |
74f10515 | 253 | static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, |
a8a826a3 | 254 | uintptr_t searched_pc) |
d19893da | 255 | { |
fca8a500 RH |
256 | target_ulong data[TARGET_INSN_START_WORDS] = { tb->pc }; |
257 | uintptr_t host_pc = (uintptr_t)tb->tc_ptr; | |
74f10515 | 258 | CPUArchState *env = cpu->env_ptr; |
fca8a500 RH |
259 | uint8_t *p = tb->tc_search; |
260 | int i, j, num_insns = tb->icount; | |
57fec1fe | 261 | #ifdef CONFIG_PROFILER |
fca8a500 | 262 | int64_t ti = profile_getclock(); |
57fec1fe FB |
263 | #endif |
264 | ||
fca8a500 RH |
265 | if (searched_pc < host_pc) { |
266 | return -1; | |
267 | } | |
d19893da | 268 | |
fca8a500 RH |
269 | /* Reconstruct the stored insn data while looking for the point at |
270 | which the end of the insn exceeds the searched_pc. */ | |
271 | for (i = 0; i < num_insns; ++i) { | |
272 | for (j = 0; j < TARGET_INSN_START_WORDS; ++j) { | |
273 | data[j] += decode_sleb128(&p); | |
274 | } | |
275 | host_pc += decode_sleb128(&p); | |
276 | if (host_pc > searched_pc) { | |
277 | goto found; | |
278 | } | |
279 | } | |
280 | return -1; | |
3b46e624 | 281 | |
fca8a500 | 282 | found: |
bd79255d | 283 | if (tb->cflags & CF_USE_ICOUNT) { |
414b15c9 | 284 | assert(use_icount); |
2e70f6ef | 285 | /* Reset the cycle counter to the start of the block. */ |
fca8a500 | 286 | cpu->icount_decr.u16.low += num_insns; |
2e70f6ef | 287 | /* Clear the IO flag. */ |
99df7dce | 288 | cpu->can_do_io = 0; |
2e70f6ef | 289 | } |
fca8a500 RH |
290 | cpu->icount_decr.u16.low -= i; |
291 | restore_state_to_opc(env, tb, data); | |
57fec1fe FB |
292 | |
293 | #ifdef CONFIG_PROFILER | |
fca8a500 RH |
294 | tcg_ctx.restore_time += profile_getclock() - ti; |
295 | tcg_ctx.restore_count++; | |
57fec1fe | 296 | #endif |
d19893da FB |
297 | return 0; |
298 | } | |
5b6dd868 | 299 | |
3f38f309 | 300 | bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr) |
a8a826a3 BS |
301 | { |
302 | TranslationBlock *tb; | |
303 | ||
304 | tb = tb_find_pc(retaddr); | |
305 | if (tb) { | |
74f10515 | 306 | cpu_restore_state_from_tb(cpu, tb, retaddr); |
d8a499f1 PD |
307 | if (tb->cflags & CF_NOCACHE) { |
308 | /* one-shot translation, invalidate it immediately */ | |
309 | cpu->current_tb = NULL; | |
310 | tb_phys_invalidate(tb, -1); | |
311 | tb_free(tb); | |
312 | } | |
a8a826a3 BS |
313 | return true; |
314 | } | |
315 | return false; | |
316 | } | |
317 | ||
47c16ed5 | 318 | void page_size_init(void) |
5b6dd868 BS |
319 | { |
320 | /* NOTE: we can always suppose that qemu_host_page_size >= | |
321 | TARGET_PAGE_SIZE */ | |
5b6dd868 | 322 | qemu_real_host_page_size = getpagesize(); |
0c2d70c4 | 323 | qemu_real_host_page_mask = -(intptr_t)qemu_real_host_page_size; |
5b6dd868 BS |
324 | if (qemu_host_page_size == 0) { |
325 | qemu_host_page_size = qemu_real_host_page_size; | |
326 | } | |
327 | if (qemu_host_page_size < TARGET_PAGE_SIZE) { | |
328 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
329 | } | |
0c2d70c4 | 330 | qemu_host_page_mask = -(intptr_t)qemu_host_page_size; |
47c16ed5 | 331 | } |
5b6dd868 | 332 | |
47c16ed5 AK |
333 | static void page_init(void) |
334 | { | |
335 | page_size_init(); | |
5b6dd868 BS |
336 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
337 | { | |
338 | #ifdef HAVE_KINFO_GETVMMAP | |
339 | struct kinfo_vmentry *freep; | |
340 | int i, cnt; | |
341 | ||
342 | freep = kinfo_getvmmap(getpid(), &cnt); | |
343 | if (freep) { | |
344 | mmap_lock(); | |
345 | for (i = 0; i < cnt; i++) { | |
346 | unsigned long startaddr, endaddr; | |
347 | ||
348 | startaddr = freep[i].kve_start; | |
349 | endaddr = freep[i].kve_end; | |
350 | if (h2g_valid(startaddr)) { | |
351 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
352 | ||
353 | if (h2g_valid(endaddr)) { | |
354 | endaddr = h2g(endaddr); | |
355 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
356 | } else { | |
357 | #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS | |
358 | endaddr = ~0ul; | |
359 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
360 | #endif | |
361 | } | |
362 | } | |
363 | } | |
364 | free(freep); | |
365 | mmap_unlock(); | |
366 | } | |
367 | #else | |
368 | FILE *f; | |
369 | ||
370 | last_brk = (unsigned long)sbrk(0); | |
371 | ||
372 | f = fopen("/compat/linux/proc/self/maps", "r"); | |
373 | if (f) { | |
374 | mmap_lock(); | |
375 | ||
376 | do { | |
377 | unsigned long startaddr, endaddr; | |
378 | int n; | |
379 | ||
380 | n = fscanf(f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr); | |
381 | ||
382 | if (n == 2 && h2g_valid(startaddr)) { | |
383 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
384 | ||
385 | if (h2g_valid(endaddr)) { | |
386 | endaddr = h2g(endaddr); | |
387 | } else { | |
388 | endaddr = ~0ul; | |
389 | } | |
390 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
391 | } | |
392 | } while (!feof(f)); | |
393 | ||
394 | fclose(f); | |
395 | mmap_unlock(); | |
396 | } | |
397 | #endif | |
398 | } | |
399 | #endif | |
400 | } | |
401 | ||
75692087 PB |
402 | /* If alloc=1: |
403 | * Called with mmap_lock held for user-mode emulation. | |
404 | */ | |
5b6dd868 BS |
405 | static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) |
406 | { | |
407 | PageDesc *pd; | |
408 | void **lp; | |
409 | int i; | |
410 | ||
5b6dd868 BS |
411 | /* Level 1. Always allocated. */ |
412 | lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1)); | |
413 | ||
414 | /* Level 2..N-1. */ | |
03f49957 | 415 | for (i = V_L1_SHIFT / V_L2_BITS - 1; i > 0; i--) { |
6940fab8 | 416 | void **p = atomic_rcu_read(lp); |
5b6dd868 BS |
417 | |
418 | if (p == NULL) { | |
419 | if (!alloc) { | |
420 | return NULL; | |
421 | } | |
e3a0abfd | 422 | p = g_new0(void *, V_L2_SIZE); |
6940fab8 | 423 | atomic_rcu_set(lp, p); |
5b6dd868 BS |
424 | } |
425 | ||
03f49957 | 426 | lp = p + ((index >> (i * V_L2_BITS)) & (V_L2_SIZE - 1)); |
5b6dd868 BS |
427 | } |
428 | ||
6940fab8 | 429 | pd = atomic_rcu_read(lp); |
5b6dd868 BS |
430 | if (pd == NULL) { |
431 | if (!alloc) { | |
432 | return NULL; | |
433 | } | |
e3a0abfd | 434 | pd = g_new0(PageDesc, V_L2_SIZE); |
6940fab8 | 435 | atomic_rcu_set(lp, pd); |
5b6dd868 BS |
436 | } |
437 | ||
03f49957 | 438 | return pd + (index & (V_L2_SIZE - 1)); |
5b6dd868 BS |
439 | } |
440 | ||
441 | static inline PageDesc *page_find(tb_page_addr_t index) | |
442 | { | |
443 | return page_find_alloc(index, 0); | |
444 | } | |
445 | ||
5b6dd868 BS |
446 | #if defined(CONFIG_USER_ONLY) |
447 | /* Currently it is not recommended to allocate big chunks of data in | |
448 | user mode. It will change when a dedicated libc will be used. */ | |
449 | /* ??? 64-bit hosts ought to have no problem mmaping data outside the | |
450 | region in which the guest needs to run. Revisit this. */ | |
451 | #define USE_STATIC_CODE_GEN_BUFFER | |
452 | #endif | |
453 | ||
5b6dd868 BS |
454 | /* Minimum size of the code gen buffer. This number is randomly chosen, |
455 | but not so small that we can't have a fair number of TB's live. */ | |
456 | #define MIN_CODE_GEN_BUFFER_SIZE (1024u * 1024) | |
457 | ||
458 | /* Maximum size of the code gen buffer we'd like to use. Unless otherwise | |
459 | indicated, this is constrained by the range of direct branches on the | |
460 | host cpu, as used by the TCG implementation of goto_tb. */ | |
461 | #if defined(__x86_64__) | |
462 | # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024) | |
463 | #elif defined(__sparc__) | |
464 | # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024) | |
5bfd75a3 RH |
465 | #elif defined(__powerpc64__) |
466 | # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024) | |
399f1648 SF |
467 | #elif defined(__powerpc__) |
468 | # define MAX_CODE_GEN_BUFFER_SIZE (32u * 1024 * 1024) | |
4a136e0a CF |
469 | #elif defined(__aarch64__) |
470 | # define MAX_CODE_GEN_BUFFER_SIZE (128ul * 1024 * 1024) | |
5b6dd868 BS |
471 | #elif defined(__arm__) |
472 | # define MAX_CODE_GEN_BUFFER_SIZE (16u * 1024 * 1024) | |
473 | #elif defined(__s390x__) | |
474 | /* We have a +- 4GB range on the branches; leave some slop. */ | |
475 | # define MAX_CODE_GEN_BUFFER_SIZE (3ul * 1024 * 1024 * 1024) | |
479eb121 RH |
476 | #elif defined(__mips__) |
477 | /* We have a 256MB branch region, but leave room to make sure the | |
478 | main executable is also within that region. */ | |
479 | # define MAX_CODE_GEN_BUFFER_SIZE (128ul * 1024 * 1024) | |
5b6dd868 BS |
480 | #else |
481 | # define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) | |
482 | #endif | |
483 | ||
484 | #define DEFAULT_CODE_GEN_BUFFER_SIZE_1 (32u * 1024 * 1024) | |
485 | ||
486 | #define DEFAULT_CODE_GEN_BUFFER_SIZE \ | |
487 | (DEFAULT_CODE_GEN_BUFFER_SIZE_1 < MAX_CODE_GEN_BUFFER_SIZE \ | |
488 | ? DEFAULT_CODE_GEN_BUFFER_SIZE_1 : MAX_CODE_GEN_BUFFER_SIZE) | |
489 | ||
490 | static inline size_t size_code_gen_buffer(size_t tb_size) | |
491 | { | |
492 | /* Size the buffer. */ | |
493 | if (tb_size == 0) { | |
494 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
495 | tb_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
496 | #else | |
497 | /* ??? Needs adjustments. */ | |
498 | /* ??? If we relax the requirement that CONFIG_USER_ONLY use the | |
499 | static buffer, we could size this on RESERVED_VA, on the text | |
500 | segment size of the executable, or continue to use the default. */ | |
501 | tb_size = (unsigned long)(ram_size / 4); | |
502 | #endif | |
503 | } | |
504 | if (tb_size < MIN_CODE_GEN_BUFFER_SIZE) { | |
505 | tb_size = MIN_CODE_GEN_BUFFER_SIZE; | |
506 | } | |
507 | if (tb_size > MAX_CODE_GEN_BUFFER_SIZE) { | |
508 | tb_size = MAX_CODE_GEN_BUFFER_SIZE; | |
509 | } | |
0b0d3320 | 510 | tcg_ctx.code_gen_buffer_size = tb_size; |
5b6dd868 BS |
511 | return tb_size; |
512 | } | |
513 | ||
483c76e1 RH |
514 | #ifdef __mips__ |
515 | /* In order to use J and JAL within the code_gen_buffer, we require | |
516 | that the buffer not cross a 256MB boundary. */ | |
517 | static inline bool cross_256mb(void *addr, size_t size) | |
518 | { | |
519 | return ((uintptr_t)addr ^ ((uintptr_t)addr + size)) & 0xf0000000; | |
520 | } | |
521 | ||
522 | /* We weren't able to allocate a buffer without crossing that boundary, | |
523 | so make do with the larger portion of the buffer that doesn't cross. | |
524 | Returns the new base of the buffer, and adjusts code_gen_buffer_size. */ | |
525 | static inline void *split_cross_256mb(void *buf1, size_t size1) | |
526 | { | |
527 | void *buf2 = (void *)(((uintptr_t)buf1 + size1) & 0xf0000000); | |
528 | size_t size2 = buf1 + size1 - buf2; | |
529 | ||
530 | size1 = buf2 - buf1; | |
531 | if (size1 < size2) { | |
532 | size1 = size2; | |
533 | buf1 = buf2; | |
534 | } | |
535 | ||
536 | tcg_ctx.code_gen_buffer_size = size1; | |
537 | return buf1; | |
538 | } | |
539 | #endif | |
540 | ||
5b6dd868 BS |
541 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
542 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] | |
543 | __attribute__((aligned(CODE_GEN_ALIGN))); | |
544 | ||
f293709c RH |
545 | # ifdef _WIN32 |
546 | static inline void do_protect(void *addr, long size, int prot) | |
547 | { | |
548 | DWORD old_protect; | |
549 | VirtualProtect(addr, size, prot, &old_protect); | |
550 | } | |
551 | ||
552 | static inline void map_exec(void *addr, long size) | |
553 | { | |
554 | do_protect(addr, size, PAGE_EXECUTE_READWRITE); | |
555 | } | |
556 | ||
557 | static inline void map_none(void *addr, long size) | |
558 | { | |
559 | do_protect(addr, size, PAGE_NOACCESS); | |
560 | } | |
561 | # else | |
562 | static inline void do_protect(void *addr, long size, int prot) | |
563 | { | |
564 | uintptr_t start, end; | |
565 | ||
566 | start = (uintptr_t)addr; | |
567 | start &= qemu_real_host_page_mask; | |
568 | ||
569 | end = (uintptr_t)addr + size; | |
570 | end = ROUND_UP(end, qemu_real_host_page_size); | |
571 | ||
572 | mprotect((void *)start, end - start, prot); | |
573 | } | |
574 | ||
575 | static inline void map_exec(void *addr, long size) | |
576 | { | |
577 | do_protect(addr, size, PROT_READ | PROT_WRITE | PROT_EXEC); | |
578 | } | |
579 | ||
580 | static inline void map_none(void *addr, long size) | |
581 | { | |
582 | do_protect(addr, size, PROT_NONE); | |
583 | } | |
584 | # endif /* WIN32 */ | |
585 | ||
5b6dd868 BS |
586 | static inline void *alloc_code_gen_buffer(void) |
587 | { | |
483c76e1 | 588 | void *buf = static_code_gen_buffer; |
f293709c RH |
589 | size_t full_size, size; |
590 | ||
591 | /* The size of the buffer, rounded down to end on a page boundary. */ | |
592 | full_size = (((uintptr_t)buf + sizeof(static_code_gen_buffer)) | |
593 | & qemu_real_host_page_mask) - (uintptr_t)buf; | |
594 | ||
595 | /* Reserve a guard page. */ | |
596 | size = full_size - qemu_real_host_page_size; | |
597 | ||
598 | /* Honor a command-line option limiting the size of the buffer. */ | |
599 | if (size > tcg_ctx.code_gen_buffer_size) { | |
600 | size = (((uintptr_t)buf + tcg_ctx.code_gen_buffer_size) | |
601 | & qemu_real_host_page_mask) - (uintptr_t)buf; | |
602 | } | |
603 | tcg_ctx.code_gen_buffer_size = size; | |
604 | ||
483c76e1 | 605 | #ifdef __mips__ |
f293709c RH |
606 | if (cross_256mb(buf, size)) { |
607 | buf = split_cross_256mb(buf, size); | |
608 | size = tcg_ctx.code_gen_buffer_size; | |
483c76e1 RH |
609 | } |
610 | #endif | |
f293709c RH |
611 | |
612 | map_exec(buf, size); | |
613 | map_none(buf + size, qemu_real_host_page_size); | |
614 | qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); | |
615 | ||
483c76e1 | 616 | return buf; |
5b6dd868 | 617 | } |
f293709c RH |
618 | #elif defined(_WIN32) |
619 | static inline void *alloc_code_gen_buffer(void) | |
620 | { | |
621 | size_t size = tcg_ctx.code_gen_buffer_size; | |
622 | void *buf1, *buf2; | |
623 | ||
624 | /* Perform the allocation in two steps, so that the guard page | |
625 | is reserved but uncommitted. */ | |
626 | buf1 = VirtualAlloc(NULL, size + qemu_real_host_page_size, | |
627 | MEM_RESERVE, PAGE_NOACCESS); | |
628 | if (buf1 != NULL) { | |
629 | buf2 = VirtualAlloc(buf1, size, MEM_COMMIT, PAGE_EXECUTE_READWRITE); | |
630 | assert(buf1 == buf2); | |
631 | } | |
632 | ||
633 | return buf1; | |
634 | } | |
635 | #else | |
5b6dd868 BS |
636 | static inline void *alloc_code_gen_buffer(void) |
637 | { | |
638 | int flags = MAP_PRIVATE | MAP_ANONYMOUS; | |
639 | uintptr_t start = 0; | |
f293709c | 640 | size_t size = tcg_ctx.code_gen_buffer_size; |
5b6dd868 BS |
641 | void *buf; |
642 | ||
643 | /* Constrain the position of the buffer based on the host cpu. | |
644 | Note that these addresses are chosen in concert with the | |
645 | addresses assigned in the relevant linker script file. */ | |
646 | # if defined(__PIE__) || defined(__PIC__) | |
647 | /* Don't bother setting a preferred location if we're building | |
648 | a position-independent executable. We're more likely to get | |
649 | an address near the main executable if we let the kernel | |
650 | choose the address. */ | |
651 | # elif defined(__x86_64__) && defined(MAP_32BIT) | |
652 | /* Force the memory down into low memory with the executable. | |
653 | Leave the choice of exact location with the kernel. */ | |
654 | flags |= MAP_32BIT; | |
655 | /* Cannot expect to map more than 800MB in low memory. */ | |
f293709c RH |
656 | if (size > 800u * 1024 * 1024) { |
657 | tcg_ctx.code_gen_buffer_size = size = 800u * 1024 * 1024; | |
5b6dd868 BS |
658 | } |
659 | # elif defined(__sparc__) | |
660 | start = 0x40000000ul; | |
661 | # elif defined(__s390x__) | |
662 | start = 0x90000000ul; | |
479eb121 | 663 | # elif defined(__mips__) |
f293709c | 664 | # if _MIPS_SIM == _ABI64 |
479eb121 RH |
665 | start = 0x128000000ul; |
666 | # else | |
667 | start = 0x08000000ul; | |
668 | # endif | |
5b6dd868 BS |
669 | # endif |
670 | ||
f293709c RH |
671 | buf = mmap((void *)start, size + qemu_real_host_page_size, |
672 | PROT_NONE, flags, -1, 0); | |
483c76e1 RH |
673 | if (buf == MAP_FAILED) { |
674 | return NULL; | |
675 | } | |
676 | ||
677 | #ifdef __mips__ | |
f293709c | 678 | if (cross_256mb(buf, size)) { |
5d831be2 | 679 | /* Try again, with the original still mapped, to avoid re-acquiring |
483c76e1 | 680 | that 256mb crossing. This time don't specify an address. */ |
f293709c RH |
681 | size_t size2; |
682 | void *buf2 = mmap(NULL, size + qemu_real_host_page_size, | |
683 | PROT_NONE, flags, -1, 0); | |
684 | switch (buf2 != MAP_FAILED) { | |
685 | case 1: | |
686 | if (!cross_256mb(buf2, size)) { | |
483c76e1 | 687 | /* Success! Use the new buffer. */ |
f293709c RH |
688 | munmap(buf, size); |
689 | break; | |
483c76e1 RH |
690 | } |
691 | /* Failure. Work with what we had. */ | |
f293709c RH |
692 | munmap(buf2, size); |
693 | /* fallthru */ | |
694 | default: | |
695 | /* Split the original buffer. Free the smaller half. */ | |
696 | buf2 = split_cross_256mb(buf, size); | |
697 | size2 = tcg_ctx.code_gen_buffer_size; | |
698 | if (buf == buf2) { | |
699 | munmap(buf + size2 + qemu_real_host_page_size, size - size2); | |
700 | } else { | |
701 | munmap(buf, size - size2); | |
702 | } | |
703 | size = size2; | |
704 | break; | |
483c76e1 | 705 | } |
f293709c | 706 | buf = buf2; |
483c76e1 RH |
707 | } |
708 | #endif | |
709 | ||
f293709c RH |
710 | /* Make the final buffer accessible. The guard page at the end |
711 | will remain inaccessible with PROT_NONE. */ | |
712 | mprotect(buf, size, PROT_WRITE | PROT_READ | PROT_EXEC); | |
483c76e1 | 713 | |
f293709c RH |
714 | /* Request large pages for the buffer. */ |
715 | qemu_madvise(buf, size, QEMU_MADV_HUGEPAGE); | |
483c76e1 | 716 | |
5b6dd868 BS |
717 | return buf; |
718 | } | |
f293709c | 719 | #endif /* USE_STATIC_CODE_GEN_BUFFER, WIN32, POSIX */ |
5b6dd868 BS |
720 | |
721 | static inline void code_gen_alloc(size_t tb_size) | |
722 | { | |
0b0d3320 EV |
723 | tcg_ctx.code_gen_buffer_size = size_code_gen_buffer(tb_size); |
724 | tcg_ctx.code_gen_buffer = alloc_code_gen_buffer(); | |
725 | if (tcg_ctx.code_gen_buffer == NULL) { | |
5b6dd868 BS |
726 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); |
727 | exit(1); | |
728 | } | |
729 | ||
8163b749 RH |
730 | /* Estimate a good size for the number of TBs we can support. We |
731 | still haven't deducted the prologue from the buffer size here, | |
732 | but that's minimal and won't affect the estimate much. */ | |
733 | tcg_ctx.code_gen_max_blocks | |
734 | = tcg_ctx.code_gen_buffer_size / CODE_GEN_AVG_BLOCK_SIZE; | |
735 | tcg_ctx.tb_ctx.tbs = g_new(TranslationBlock, tcg_ctx.code_gen_max_blocks); | |
736 | ||
677ef623 | 737 | qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock); |
5b6dd868 BS |
738 | } |
739 | ||
740 | /* Must be called before using the QEMU cpus. 'tb_size' is the size | |
741 | (in bytes) allocated to the translation buffer. Zero means default | |
742 | size. */ | |
743 | void tcg_exec_init(unsigned long tb_size) | |
744 | { | |
745 | cpu_gen_init(); | |
5b6dd868 | 746 | page_init(); |
f293709c | 747 | code_gen_alloc(tb_size); |
4cbea598 | 748 | #if defined(CONFIG_SOFTMMU) |
5b6dd868 BS |
749 | /* There's no guest base to take into account, so go ahead and |
750 | initialize the prologue now. */ | |
751 | tcg_prologue_init(&tcg_ctx); | |
752 | #endif | |
753 | } | |
754 | ||
755 | bool tcg_enabled(void) | |
756 | { | |
0b0d3320 | 757 | return tcg_ctx.code_gen_buffer != NULL; |
5b6dd868 BS |
758 | } |
759 | ||
760 | /* Allocate a new translation block. Flush the translation buffer if | |
761 | too many translation blocks or too much generated code. */ | |
762 | static TranslationBlock *tb_alloc(target_ulong pc) | |
763 | { | |
764 | TranslationBlock *tb; | |
765 | ||
b125f9dc | 766 | if (tcg_ctx.tb_ctx.nb_tbs >= tcg_ctx.code_gen_max_blocks) { |
5b6dd868 BS |
767 | return NULL; |
768 | } | |
5e5f07e0 | 769 | tb = &tcg_ctx.tb_ctx.tbs[tcg_ctx.tb_ctx.nb_tbs++]; |
5b6dd868 BS |
770 | tb->pc = pc; |
771 | tb->cflags = 0; | |
772 | return tb; | |
773 | } | |
774 | ||
775 | void tb_free(TranslationBlock *tb) | |
776 | { | |
777 | /* In practice this is mostly used for single use temporary TB | |
778 | Ignore the hard cases and just back up if this TB happens to | |
779 | be the last one generated. */ | |
5e5f07e0 EV |
780 | if (tcg_ctx.tb_ctx.nb_tbs > 0 && |
781 | tb == &tcg_ctx.tb_ctx.tbs[tcg_ctx.tb_ctx.nb_tbs - 1]) { | |
0b0d3320 | 782 | tcg_ctx.code_gen_ptr = tb->tc_ptr; |
5e5f07e0 | 783 | tcg_ctx.tb_ctx.nb_tbs--; |
5b6dd868 BS |
784 | } |
785 | } | |
786 | ||
787 | static inline void invalidate_page_bitmap(PageDesc *p) | |
788 | { | |
012aef07 MA |
789 | g_free(p->code_bitmap); |
790 | p->code_bitmap = NULL; | |
5b6dd868 BS |
791 | p->code_write_count = 0; |
792 | } | |
793 | ||
794 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */ | |
795 | static void page_flush_tb_1(int level, void **lp) | |
796 | { | |
797 | int i; | |
798 | ||
799 | if (*lp == NULL) { | |
800 | return; | |
801 | } | |
802 | if (level == 0) { | |
803 | PageDesc *pd = *lp; | |
804 | ||
03f49957 | 805 | for (i = 0; i < V_L2_SIZE; ++i) { |
5b6dd868 BS |
806 | pd[i].first_tb = NULL; |
807 | invalidate_page_bitmap(pd + i); | |
808 | } | |
809 | } else { | |
810 | void **pp = *lp; | |
811 | ||
03f49957 | 812 | for (i = 0; i < V_L2_SIZE; ++i) { |
5b6dd868 BS |
813 | page_flush_tb_1(level - 1, pp + i); |
814 | } | |
815 | } | |
816 | } | |
817 | ||
818 | static void page_flush_tb(void) | |
819 | { | |
820 | int i; | |
821 | ||
822 | for (i = 0; i < V_L1_SIZE; i++) { | |
03f49957 | 823 | page_flush_tb_1(V_L1_SHIFT / V_L2_BITS - 1, l1_map + i); |
5b6dd868 BS |
824 | } |
825 | } | |
826 | ||
827 | /* flush all the translation blocks */ | |
828 | /* XXX: tb_flush is currently not thread safe */ | |
bbd77c18 | 829 | void tb_flush(CPUState *cpu) |
5b6dd868 | 830 | { |
5b6dd868 BS |
831 | #if defined(DEBUG_FLUSH) |
832 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", | |
0b0d3320 | 833 | (unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer), |
5e5f07e0 | 834 | tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ? |
0b0d3320 | 835 | ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer)) / |
5e5f07e0 | 836 | tcg_ctx.tb_ctx.nb_tbs : 0); |
5b6dd868 | 837 | #endif |
0b0d3320 EV |
838 | if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) |
839 | > tcg_ctx.code_gen_buffer_size) { | |
a47dddd7 | 840 | cpu_abort(cpu, "Internal error: code buffer overflow\n"); |
5b6dd868 | 841 | } |
5e5f07e0 | 842 | tcg_ctx.tb_ctx.nb_tbs = 0; |
5b6dd868 | 843 | |
bdc44640 | 844 | CPU_FOREACH(cpu) { |
8cd70437 | 845 | memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache)); |
5b6dd868 BS |
846 | } |
847 | ||
eb2535f4 | 848 | memset(tcg_ctx.tb_ctx.tb_phys_hash, 0, sizeof(tcg_ctx.tb_ctx.tb_phys_hash)); |
5b6dd868 BS |
849 | page_flush_tb(); |
850 | ||
0b0d3320 | 851 | tcg_ctx.code_gen_ptr = tcg_ctx.code_gen_buffer; |
5b6dd868 BS |
852 | /* XXX: flush processor icache at this point if cache flush is |
853 | expensive */ | |
5e5f07e0 | 854 | tcg_ctx.tb_ctx.tb_flush_count++; |
5b6dd868 BS |
855 | } |
856 | ||
857 | #ifdef DEBUG_TB_CHECK | |
858 | ||
859 | static void tb_invalidate_check(target_ulong address) | |
860 | { | |
861 | TranslationBlock *tb; | |
862 | int i; | |
863 | ||
864 | address &= TARGET_PAGE_MASK; | |
865 | for (i = 0; i < CODE_GEN_PHYS_HASH_SIZE; i++) { | |
7e6bd36d EC |
866 | for (tb = tcg_ctx.tb_ctx.tb_phys_hash[i]; tb != NULL; |
867 | tb = tb->phys_hash_next) { | |
5b6dd868 BS |
868 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
869 | address >= tb->pc + tb->size)) { | |
870 | printf("ERROR invalidate: address=" TARGET_FMT_lx | |
871 | " PC=%08lx size=%04x\n", | |
872 | address, (long)tb->pc, tb->size); | |
873 | } | |
874 | } | |
875 | } | |
876 | } | |
877 | ||
878 | /* verify that all the pages have correct rights for code */ | |
879 | static void tb_page_check(void) | |
880 | { | |
881 | TranslationBlock *tb; | |
882 | int i, flags1, flags2; | |
883 | ||
884 | for (i = 0; i < CODE_GEN_PHYS_HASH_SIZE; i++) { | |
5e5f07e0 EV |
885 | for (tb = tcg_ctx.tb_ctx.tb_phys_hash[i]; tb != NULL; |
886 | tb = tb->phys_hash_next) { | |
5b6dd868 BS |
887 | flags1 = page_get_flags(tb->pc); |
888 | flags2 = page_get_flags(tb->pc + tb->size - 1); | |
889 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | |
890 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | |
891 | (long)tb->pc, tb->size, flags1, flags2); | |
892 | } | |
893 | } | |
894 | } | |
895 | } | |
896 | ||
897 | #endif | |
898 | ||
0c884d16 | 899 | static inline void tb_hash_remove(TranslationBlock **ptb, TranslationBlock *tb) |
5b6dd868 BS |
900 | { |
901 | TranslationBlock *tb1; | |
902 | ||
903 | for (;;) { | |
904 | tb1 = *ptb; | |
905 | if (tb1 == tb) { | |
0c884d16 | 906 | *ptb = tb1->phys_hash_next; |
5b6dd868 BS |
907 | break; |
908 | } | |
0c884d16 | 909 | ptb = &tb1->phys_hash_next; |
5b6dd868 BS |
910 | } |
911 | } | |
912 | ||
913 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) | |
914 | { | |
915 | TranslationBlock *tb1; | |
916 | unsigned int n1; | |
917 | ||
918 | for (;;) { | |
919 | tb1 = *ptb; | |
920 | n1 = (uintptr_t)tb1 & 3; | |
921 | tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3); | |
922 | if (tb1 == tb) { | |
923 | *ptb = tb1->page_next[n1]; | |
924 | break; | |
925 | } | |
926 | ptb = &tb1->page_next[n1]; | |
927 | } | |
928 | } | |
929 | ||
930 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) | |
931 | { | |
932 | TranslationBlock *tb1, **ptb; | |
933 | unsigned int n1; | |
934 | ||
935 | ptb = &tb->jmp_next[n]; | |
936 | tb1 = *ptb; | |
937 | if (tb1) { | |
938 | /* find tb(n) in circular list */ | |
939 | for (;;) { | |
940 | tb1 = *ptb; | |
941 | n1 = (uintptr_t)tb1 & 3; | |
942 | tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3); | |
943 | if (n1 == n && tb1 == tb) { | |
944 | break; | |
945 | } | |
946 | if (n1 == 2) { | |
947 | ptb = &tb1->jmp_first; | |
948 | } else { | |
949 | ptb = &tb1->jmp_next[n1]; | |
950 | } | |
951 | } | |
952 | /* now we can suppress tb(n) from the list */ | |
953 | *ptb = tb->jmp_next[n]; | |
954 | ||
955 | tb->jmp_next[n] = NULL; | |
956 | } | |
957 | } | |
958 | ||
959 | /* reset the jump entry 'n' of a TB so that it is not chained to | |
960 | another TB */ | |
961 | static inline void tb_reset_jump(TranslationBlock *tb, int n) | |
962 | { | |
963 | tb_set_jmp_target(tb, n, (uintptr_t)(tb->tc_ptr + tb->tb_next_offset[n])); | |
964 | } | |
965 | ||
0c884d16 | 966 | /* invalidate one TB */ |
5b6dd868 BS |
967 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) |
968 | { | |
182735ef | 969 | CPUState *cpu; |
5b6dd868 BS |
970 | PageDesc *p; |
971 | unsigned int h, n1; | |
972 | tb_page_addr_t phys_pc; | |
973 | TranslationBlock *tb1, *tb2; | |
974 | ||
975 | /* remove the TB from the hash list */ | |
976 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
977 | h = tb_phys_hash_func(phys_pc); | |
5e5f07e0 | 978 | tb_hash_remove(&tcg_ctx.tb_ctx.tb_phys_hash[h], tb); |
5b6dd868 BS |
979 | |
980 | /* remove the TB from the page list */ | |
981 | if (tb->page_addr[0] != page_addr) { | |
982 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | |
983 | tb_page_remove(&p->first_tb, tb); | |
984 | invalidate_page_bitmap(p); | |
985 | } | |
986 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { | |
987 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | |
988 | tb_page_remove(&p->first_tb, tb); | |
989 | invalidate_page_bitmap(p); | |
990 | } | |
991 | ||
5e5f07e0 | 992 | tcg_ctx.tb_ctx.tb_invalidated_flag = 1; |
5b6dd868 BS |
993 | |
994 | /* remove the TB from the hash list */ | |
995 | h = tb_jmp_cache_hash_func(tb->pc); | |
bdc44640 | 996 | CPU_FOREACH(cpu) { |
8cd70437 AF |
997 | if (cpu->tb_jmp_cache[h] == tb) { |
998 | cpu->tb_jmp_cache[h] = NULL; | |
5b6dd868 BS |
999 | } |
1000 | } | |
1001 | ||
1002 | /* suppress this TB from the two jump lists */ | |
1003 | tb_jmp_remove(tb, 0); | |
1004 | tb_jmp_remove(tb, 1); | |
1005 | ||
1006 | /* suppress any remaining jumps to this TB */ | |
1007 | tb1 = tb->jmp_first; | |
1008 | for (;;) { | |
1009 | n1 = (uintptr_t)tb1 & 3; | |
1010 | if (n1 == 2) { | |
1011 | break; | |
1012 | } | |
1013 | tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3); | |
1014 | tb2 = tb1->jmp_next[n1]; | |
1015 | tb_reset_jump(tb1, n1); | |
1016 | tb1->jmp_next[n1] = NULL; | |
1017 | tb1 = tb2; | |
1018 | } | |
1019 | tb->jmp_first = (TranslationBlock *)((uintptr_t)tb | 2); /* fail safe */ | |
1020 | ||
5e5f07e0 | 1021 | tcg_ctx.tb_ctx.tb_phys_invalidate_count++; |
5b6dd868 BS |
1022 | } |
1023 | ||
5b6dd868 BS |
1024 | static void build_page_bitmap(PageDesc *p) |
1025 | { | |
1026 | int n, tb_start, tb_end; | |
1027 | TranslationBlock *tb; | |
1028 | ||
510a647f | 1029 | p->code_bitmap = bitmap_new(TARGET_PAGE_SIZE); |
5b6dd868 BS |
1030 | |
1031 | tb = p->first_tb; | |
1032 | while (tb != NULL) { | |
1033 | n = (uintptr_t)tb & 3; | |
1034 | tb = (TranslationBlock *)((uintptr_t)tb & ~3); | |
1035 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
1036 | if (n == 0) { | |
1037 | /* NOTE: tb_end may be after the end of the page, but | |
1038 | it is not a problem */ | |
1039 | tb_start = tb->pc & ~TARGET_PAGE_MASK; | |
1040 | tb_end = tb_start + tb->size; | |
1041 | if (tb_end > TARGET_PAGE_SIZE) { | |
1042 | tb_end = TARGET_PAGE_SIZE; | |
1043 | } | |
1044 | } else { | |
1045 | tb_start = 0; | |
1046 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
1047 | } | |
510a647f | 1048 | bitmap_set(p->code_bitmap, tb_start, tb_end - tb_start); |
5b6dd868 BS |
1049 | tb = tb->page_next[n]; |
1050 | } | |
1051 | } | |
1052 | ||
75692087 | 1053 | /* Called with mmap_lock held for user mode emulation. */ |
648f034c | 1054 | TranslationBlock *tb_gen_code(CPUState *cpu, |
5b6dd868 | 1055 | target_ulong pc, target_ulong cs_base, |
89fee74a | 1056 | uint32_t flags, int cflags) |
5b6dd868 | 1057 | { |
648f034c | 1058 | CPUArchState *env = cpu->env_ptr; |
5b6dd868 | 1059 | TranslationBlock *tb; |
5b6dd868 BS |
1060 | tb_page_addr_t phys_pc, phys_page2; |
1061 | target_ulong virt_page2; | |
fec88f64 | 1062 | tcg_insn_unit *gen_code_buf; |
fca8a500 | 1063 | int gen_code_size, search_size; |
fec88f64 RH |
1064 | #ifdef CONFIG_PROFILER |
1065 | int64_t ti; | |
1066 | #endif | |
5b6dd868 BS |
1067 | |
1068 | phys_pc = get_page_addr_code(env, pc); | |
56c0269a | 1069 | if (use_icount && !(cflags & CF_IGNORE_ICOUNT)) { |
0266359e PB |
1070 | cflags |= CF_USE_ICOUNT; |
1071 | } | |
b125f9dc | 1072 | |
5b6dd868 | 1073 | tb = tb_alloc(pc); |
b125f9dc RH |
1074 | if (unlikely(!tb)) { |
1075 | buffer_overflow: | |
5b6dd868 | 1076 | /* flush must be done */ |
bbd77c18 | 1077 | tb_flush(cpu); |
5b6dd868 BS |
1078 | /* cannot fail at this point */ |
1079 | tb = tb_alloc(pc); | |
b125f9dc | 1080 | assert(tb != NULL); |
5b6dd868 | 1081 | /* Don't forget to invalidate previous TB info. */ |
5e5f07e0 | 1082 | tcg_ctx.tb_ctx.tb_invalidated_flag = 1; |
5b6dd868 | 1083 | } |
fec88f64 RH |
1084 | |
1085 | gen_code_buf = tcg_ctx.code_gen_ptr; | |
1086 | tb->tc_ptr = gen_code_buf; | |
5b6dd868 BS |
1087 | tb->cs_base = cs_base; |
1088 | tb->flags = flags; | |
1089 | tb->cflags = cflags; | |
fec88f64 RH |
1090 | |
1091 | #ifdef CONFIG_PROFILER | |
1092 | tcg_ctx.tb_count1++; /* includes aborted translations because of | |
1093 | exceptions */ | |
1094 | ti = profile_getclock(); | |
1095 | #endif | |
1096 | ||
1097 | tcg_func_start(&tcg_ctx); | |
1098 | ||
1099 | gen_intermediate_code(env, tb); | |
1100 | ||
1101 | trace_translate_block(tb, tb->pc, tb->tc_ptr); | |
1102 | ||
1103 | /* generate machine code */ | |
1104 | tb->tb_next_offset[0] = 0xffff; | |
1105 | tb->tb_next_offset[1] = 0xffff; | |
1106 | tcg_ctx.tb_next_offset = tb->tb_next_offset; | |
1107 | #ifdef USE_DIRECT_JUMP | |
1108 | tcg_ctx.tb_jmp_offset = tb->tb_jmp_offset; | |
1109 | tcg_ctx.tb_next = NULL; | |
1110 | #else | |
1111 | tcg_ctx.tb_jmp_offset = NULL; | |
1112 | tcg_ctx.tb_next = tb->tb_next; | |
1113 | #endif | |
1114 | ||
1115 | #ifdef CONFIG_PROFILER | |
1116 | tcg_ctx.tb_count++; | |
1117 | tcg_ctx.interm_time += profile_getclock() - ti; | |
1118 | tcg_ctx.code_time -= profile_getclock(); | |
1119 | #endif | |
1120 | ||
b125f9dc RH |
1121 | /* ??? Overflow could be handled better here. In particular, we |
1122 | don't need to re-do gen_intermediate_code, nor should we re-do | |
1123 | the tcg optimization currently hidden inside tcg_gen_code. All | |
1124 | that should be required is to flush the TBs, allocate a new TB, | |
1125 | re-initialize it per above, and re-do the actual code generation. */ | |
5bd2ec3d | 1126 | gen_code_size = tcg_gen_code(&tcg_ctx, tb); |
b125f9dc RH |
1127 | if (unlikely(gen_code_size < 0)) { |
1128 | goto buffer_overflow; | |
1129 | } | |
fca8a500 | 1130 | search_size = encode_search(tb, (void *)gen_code_buf + gen_code_size); |
b125f9dc RH |
1131 | if (unlikely(search_size < 0)) { |
1132 | goto buffer_overflow; | |
1133 | } | |
fec88f64 RH |
1134 | |
1135 | #ifdef CONFIG_PROFILER | |
1136 | tcg_ctx.code_time += profile_getclock(); | |
1137 | tcg_ctx.code_in_len += tb->size; | |
1138 | tcg_ctx.code_out_len += gen_code_size; | |
fca8a500 | 1139 | tcg_ctx.search_out_len += search_size; |
fec88f64 RH |
1140 | #endif |
1141 | ||
1142 | #ifdef DEBUG_DISAS | |
d977e1c2 AB |
1143 | if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) && |
1144 | qemu_log_in_addr_range(tb->pc)) { | |
fec88f64 RH |
1145 | qemu_log("OUT: [size=%d]\n", gen_code_size); |
1146 | log_disas(tb->tc_ptr, gen_code_size); | |
1147 | qemu_log("\n"); | |
1148 | qemu_log_flush(); | |
1149 | } | |
1150 | #endif | |
1151 | ||
fca8a500 RH |
1152 | tcg_ctx.code_gen_ptr = (void *) |
1153 | ROUND_UP((uintptr_t)gen_code_buf + gen_code_size + search_size, | |
1154 | CODE_GEN_ALIGN); | |
5b6dd868 BS |
1155 | |
1156 | /* check next page if needed */ | |
1157 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; | |
1158 | phys_page2 = -1; | |
1159 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { | |
1160 | phys_page2 = get_page_addr_code(env, virt_page2); | |
1161 | } | |
1162 | tb_link_page(tb, phys_pc, phys_page2); | |
1163 | return tb; | |
1164 | } | |
1165 | ||
1166 | /* | |
1167 | * Invalidate all TBs which intersect with the target physical address range | |
1168 | * [start;end[. NOTE: start and end may refer to *different* physical pages. | |
1169 | * 'is_cpu_write_access' should be true if called from a real cpu write | |
1170 | * access: the virtual CPU will exit the current TB if code is modified inside | |
1171 | * this TB. | |
75692087 PB |
1172 | * |
1173 | * Called with mmap_lock held for user-mode emulation | |
5b6dd868 | 1174 | */ |
35865339 | 1175 | void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end) |
5b6dd868 BS |
1176 | { |
1177 | while (start < end) { | |
35865339 | 1178 | tb_invalidate_phys_page_range(start, end, 0); |
5b6dd868 BS |
1179 | start &= TARGET_PAGE_MASK; |
1180 | start += TARGET_PAGE_SIZE; | |
1181 | } | |
1182 | } | |
1183 | ||
1184 | /* | |
1185 | * Invalidate all TBs which intersect with the target physical address range | |
1186 | * [start;end[. NOTE: start and end must refer to the *same* physical page. | |
1187 | * 'is_cpu_write_access' should be true if called from a real cpu write | |
1188 | * access: the virtual CPU will exit the current TB if code is modified inside | |
1189 | * this TB. | |
75692087 PB |
1190 | * |
1191 | * Called with mmap_lock held for user-mode emulation | |
5b6dd868 BS |
1192 | */ |
1193 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, | |
1194 | int is_cpu_write_access) | |
1195 | { | |
1196 | TranslationBlock *tb, *tb_next, *saved_tb; | |
4917cf44 | 1197 | CPUState *cpu = current_cpu; |
baea4fae | 1198 | #if defined(TARGET_HAS_PRECISE_SMC) |
4917cf44 AF |
1199 | CPUArchState *env = NULL; |
1200 | #endif | |
5b6dd868 BS |
1201 | tb_page_addr_t tb_start, tb_end; |
1202 | PageDesc *p; | |
1203 | int n; | |
1204 | #ifdef TARGET_HAS_PRECISE_SMC | |
1205 | int current_tb_not_found = is_cpu_write_access; | |
1206 | TranslationBlock *current_tb = NULL; | |
1207 | int current_tb_modified = 0; | |
1208 | target_ulong current_pc = 0; | |
1209 | target_ulong current_cs_base = 0; | |
89fee74a | 1210 | uint32_t current_flags = 0; |
5b6dd868 BS |
1211 | #endif /* TARGET_HAS_PRECISE_SMC */ |
1212 | ||
1213 | p = page_find(start >> TARGET_PAGE_BITS); | |
1214 | if (!p) { | |
1215 | return; | |
1216 | } | |
baea4fae | 1217 | #if defined(TARGET_HAS_PRECISE_SMC) |
4917cf44 AF |
1218 | if (cpu != NULL) { |
1219 | env = cpu->env_ptr; | |
d77953b9 | 1220 | } |
4917cf44 | 1221 | #endif |
5b6dd868 BS |
1222 | |
1223 | /* we remove all the TBs in the range [start, end[ */ | |
1224 | /* XXX: see if in some cases it could be faster to invalidate all | |
1225 | the code */ | |
1226 | tb = p->first_tb; | |
1227 | while (tb != NULL) { | |
1228 | n = (uintptr_t)tb & 3; | |
1229 | tb = (TranslationBlock *)((uintptr_t)tb & ~3); | |
1230 | tb_next = tb->page_next[n]; | |
1231 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
1232 | if (n == 0) { | |
1233 | /* NOTE: tb_end may be after the end of the page, but | |
1234 | it is not a problem */ | |
1235 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
1236 | tb_end = tb_start + tb->size; | |
1237 | } else { | |
1238 | tb_start = tb->page_addr[1]; | |
1239 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
1240 | } | |
1241 | if (!(tb_end <= start || tb_start >= end)) { | |
1242 | #ifdef TARGET_HAS_PRECISE_SMC | |
1243 | if (current_tb_not_found) { | |
1244 | current_tb_not_found = 0; | |
1245 | current_tb = NULL; | |
93afeade | 1246 | if (cpu->mem_io_pc) { |
5b6dd868 | 1247 | /* now we have a real cpu fault */ |
93afeade | 1248 | current_tb = tb_find_pc(cpu->mem_io_pc); |
5b6dd868 BS |
1249 | } |
1250 | } | |
1251 | if (current_tb == tb && | |
1252 | (current_tb->cflags & CF_COUNT_MASK) != 1) { | |
1253 | /* If we are modifying the current TB, we must stop | |
1254 | its execution. We could be more precise by checking | |
1255 | that the modification is after the current PC, but it | |
1256 | would require a specialized function to partially | |
1257 | restore the CPU state */ | |
1258 | ||
1259 | current_tb_modified = 1; | |
74f10515 | 1260 | cpu_restore_state_from_tb(cpu, current_tb, cpu->mem_io_pc); |
5b6dd868 BS |
1261 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1262 | ¤t_flags); | |
1263 | } | |
1264 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
1265 | /* we need to do that to handle the case where a signal | |
1266 | occurs while doing tb_phys_invalidate() */ | |
1267 | saved_tb = NULL; | |
d77953b9 AF |
1268 | if (cpu != NULL) { |
1269 | saved_tb = cpu->current_tb; | |
1270 | cpu->current_tb = NULL; | |
5b6dd868 BS |
1271 | } |
1272 | tb_phys_invalidate(tb, -1); | |
d77953b9 AF |
1273 | if (cpu != NULL) { |
1274 | cpu->current_tb = saved_tb; | |
c3affe56 AF |
1275 | if (cpu->interrupt_request && cpu->current_tb) { |
1276 | cpu_interrupt(cpu, cpu->interrupt_request); | |
5b6dd868 BS |
1277 | } |
1278 | } | |
1279 | } | |
1280 | tb = tb_next; | |
1281 | } | |
1282 | #if !defined(CONFIG_USER_ONLY) | |
1283 | /* if no code remaining, no need to continue to use slow writes */ | |
1284 | if (!p->first_tb) { | |
1285 | invalidate_page_bitmap(p); | |
fc377bcf | 1286 | tlb_unprotect_code(start); |
5b6dd868 BS |
1287 | } |
1288 | #endif | |
1289 | #ifdef TARGET_HAS_PRECISE_SMC | |
1290 | if (current_tb_modified) { | |
1291 | /* we generate a block containing just the instruction | |
1292 | modifying the memory. It will ensure that it cannot modify | |
1293 | itself */ | |
d77953b9 | 1294 | cpu->current_tb = NULL; |
648f034c | 1295 | tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); |
0ea8cb88 | 1296 | cpu_resume_from_signal(cpu, NULL); |
5b6dd868 BS |
1297 | } |
1298 | #endif | |
1299 | } | |
1300 | ||
1301 | /* len must be <= 8 and start must be a multiple of len */ | |
1302 | void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len) | |
1303 | { | |
1304 | PageDesc *p; | |
5b6dd868 BS |
1305 | |
1306 | #if 0 | |
1307 | if (1) { | |
1308 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", | |
1309 | cpu_single_env->mem_io_vaddr, len, | |
1310 | cpu_single_env->eip, | |
1311 | cpu_single_env->eip + | |
1312 | (intptr_t)cpu_single_env->segs[R_CS].base); | |
1313 | } | |
1314 | #endif | |
1315 | p = page_find(start >> TARGET_PAGE_BITS); | |
1316 | if (!p) { | |
1317 | return; | |
1318 | } | |
fc377bcf PB |
1319 | if (!p->code_bitmap && |
1320 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD) { | |
1321 | /* build code bitmap */ | |
1322 | build_page_bitmap(p); | |
1323 | } | |
5b6dd868 | 1324 | if (p->code_bitmap) { |
510a647f EC |
1325 | unsigned int nr; |
1326 | unsigned long b; | |
1327 | ||
1328 | nr = start & ~TARGET_PAGE_MASK; | |
1329 | b = p->code_bitmap[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG - 1)); | |
5b6dd868 BS |
1330 | if (b & ((1 << len) - 1)) { |
1331 | goto do_invalidate; | |
1332 | } | |
1333 | } else { | |
1334 | do_invalidate: | |
1335 | tb_invalidate_phys_page_range(start, start + len, 1); | |
1336 | } | |
1337 | } | |
1338 | ||
1339 | #if !defined(CONFIG_SOFTMMU) | |
75692087 | 1340 | /* Called with mmap_lock held. */ |
5b6dd868 | 1341 | static void tb_invalidate_phys_page(tb_page_addr_t addr, |
d02532f0 AG |
1342 | uintptr_t pc, void *puc, |
1343 | bool locked) | |
5b6dd868 BS |
1344 | { |
1345 | TranslationBlock *tb; | |
1346 | PageDesc *p; | |
1347 | int n; | |
1348 | #ifdef TARGET_HAS_PRECISE_SMC | |
1349 | TranslationBlock *current_tb = NULL; | |
4917cf44 AF |
1350 | CPUState *cpu = current_cpu; |
1351 | CPUArchState *env = NULL; | |
5b6dd868 BS |
1352 | int current_tb_modified = 0; |
1353 | target_ulong current_pc = 0; | |
1354 | target_ulong current_cs_base = 0; | |
89fee74a | 1355 | uint32_t current_flags = 0; |
5b6dd868 BS |
1356 | #endif |
1357 | ||
1358 | addr &= TARGET_PAGE_MASK; | |
1359 | p = page_find(addr >> TARGET_PAGE_BITS); | |
1360 | if (!p) { | |
1361 | return; | |
1362 | } | |
1363 | tb = p->first_tb; | |
1364 | #ifdef TARGET_HAS_PRECISE_SMC | |
1365 | if (tb && pc != 0) { | |
1366 | current_tb = tb_find_pc(pc); | |
1367 | } | |
4917cf44 AF |
1368 | if (cpu != NULL) { |
1369 | env = cpu->env_ptr; | |
d77953b9 | 1370 | } |
5b6dd868 BS |
1371 | #endif |
1372 | while (tb != NULL) { | |
1373 | n = (uintptr_t)tb & 3; | |
1374 | tb = (TranslationBlock *)((uintptr_t)tb & ~3); | |
1375 | #ifdef TARGET_HAS_PRECISE_SMC | |
1376 | if (current_tb == tb && | |
1377 | (current_tb->cflags & CF_COUNT_MASK) != 1) { | |
1378 | /* If we are modifying the current TB, we must stop | |
1379 | its execution. We could be more precise by checking | |
1380 | that the modification is after the current PC, but it | |
1381 | would require a specialized function to partially | |
1382 | restore the CPU state */ | |
1383 | ||
1384 | current_tb_modified = 1; | |
74f10515 | 1385 | cpu_restore_state_from_tb(cpu, current_tb, pc); |
5b6dd868 BS |
1386 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1387 | ¤t_flags); | |
1388 | } | |
1389 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
1390 | tb_phys_invalidate(tb, addr); | |
1391 | tb = tb->page_next[n]; | |
1392 | } | |
1393 | p->first_tb = NULL; | |
1394 | #ifdef TARGET_HAS_PRECISE_SMC | |
1395 | if (current_tb_modified) { | |
1396 | /* we generate a block containing just the instruction | |
1397 | modifying the memory. It will ensure that it cannot modify | |
1398 | itself */ | |
d77953b9 | 1399 | cpu->current_tb = NULL; |
648f034c | 1400 | tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); |
d02532f0 AG |
1401 | if (locked) { |
1402 | mmap_unlock(); | |
1403 | } | |
0ea8cb88 | 1404 | cpu_resume_from_signal(cpu, puc); |
5b6dd868 BS |
1405 | } |
1406 | #endif | |
1407 | } | |
1408 | #endif | |
1409 | ||
75692087 PB |
1410 | /* add the tb in the target page and protect it if necessary |
1411 | * | |
1412 | * Called with mmap_lock held for user-mode emulation. | |
1413 | */ | |
5b6dd868 BS |
1414 | static inline void tb_alloc_page(TranslationBlock *tb, |
1415 | unsigned int n, tb_page_addr_t page_addr) | |
1416 | { | |
1417 | PageDesc *p; | |
1418 | #ifndef CONFIG_USER_ONLY | |
1419 | bool page_already_protected; | |
1420 | #endif | |
1421 | ||
1422 | tb->page_addr[n] = page_addr; | |
1423 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1); | |
1424 | tb->page_next[n] = p->first_tb; | |
1425 | #ifndef CONFIG_USER_ONLY | |
1426 | page_already_protected = p->first_tb != NULL; | |
1427 | #endif | |
1428 | p->first_tb = (TranslationBlock *)((uintptr_t)tb | n); | |
1429 | invalidate_page_bitmap(p); | |
1430 | ||
5b6dd868 BS |
1431 | #if defined(CONFIG_USER_ONLY) |
1432 | if (p->flags & PAGE_WRITE) { | |
1433 | target_ulong addr; | |
1434 | PageDesc *p2; | |
1435 | int prot; | |
1436 | ||
1437 | /* force the host page as non writable (writes will have a | |
1438 | page fault + mprotect overhead) */ | |
1439 | page_addr &= qemu_host_page_mask; | |
1440 | prot = 0; | |
1441 | for (addr = page_addr; addr < page_addr + qemu_host_page_size; | |
1442 | addr += TARGET_PAGE_SIZE) { | |
1443 | ||
1444 | p2 = page_find(addr >> TARGET_PAGE_BITS); | |
1445 | if (!p2) { | |
1446 | continue; | |
1447 | } | |
1448 | prot |= p2->flags; | |
1449 | p2->flags &= ~PAGE_WRITE; | |
1450 | } | |
1451 | mprotect(g2h(page_addr), qemu_host_page_size, | |
1452 | (prot & PAGE_BITS) & ~PAGE_WRITE); | |
1453 | #ifdef DEBUG_TB_INVALIDATE | |
1454 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", | |
1455 | page_addr); | |
1456 | #endif | |
1457 | } | |
1458 | #else | |
1459 | /* if some code is already present, then the pages are already | |
1460 | protected. So we handle the case where only the first TB is | |
1461 | allocated in a physical page */ | |
1462 | if (!page_already_protected) { | |
1463 | tlb_protect_code(page_addr); | |
1464 | } | |
1465 | #endif | |
5b6dd868 BS |
1466 | } |
1467 | ||
1468 | /* add a new TB and link it to the physical page tables. phys_page2 is | |
75692087 | 1469 | * (-1) to indicate that only one page contains the TB. |
9fd1a948 PB |
1470 | * |
1471 | * Called with mmap_lock held for user-mode emulation. | |
75692087 | 1472 | */ |
5b6dd868 BS |
1473 | static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, |
1474 | tb_page_addr_t phys_page2) | |
1475 | { | |
1476 | unsigned int h; | |
1477 | TranslationBlock **ptb; | |
1478 | ||
5b6dd868 BS |
1479 | /* add in the physical hash table */ |
1480 | h = tb_phys_hash_func(phys_pc); | |
5e5f07e0 | 1481 | ptb = &tcg_ctx.tb_ctx.tb_phys_hash[h]; |
5b6dd868 BS |
1482 | tb->phys_hash_next = *ptb; |
1483 | *ptb = tb; | |
1484 | ||
1485 | /* add in the page list */ | |
1486 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); | |
1487 | if (phys_page2 != -1) { | |
1488 | tb_alloc_page(tb, 1, phys_page2); | |
1489 | } else { | |
1490 | tb->page_addr[1] = -1; | |
1491 | } | |
1492 | ||
1493 | tb->jmp_first = (TranslationBlock *)((uintptr_t)tb | 2); | |
1494 | tb->jmp_next[0] = NULL; | |
1495 | tb->jmp_next[1] = NULL; | |
1496 | ||
1497 | /* init original jump addresses */ | |
1498 | if (tb->tb_next_offset[0] != 0xffff) { | |
1499 | tb_reset_jump(tb, 0); | |
1500 | } | |
1501 | if (tb->tb_next_offset[1] != 0xffff) { | |
1502 | tb_reset_jump(tb, 1); | |
1503 | } | |
1504 | ||
1505 | #ifdef DEBUG_TB_CHECK | |
1506 | tb_page_check(); | |
1507 | #endif | |
5b6dd868 BS |
1508 | } |
1509 | ||
5b6dd868 BS |
1510 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
1511 | tb[1].tc_ptr. Return NULL if not found */ | |
a8a826a3 | 1512 | static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) |
5b6dd868 BS |
1513 | { |
1514 | int m_min, m_max, m; | |
1515 | uintptr_t v; | |
1516 | TranslationBlock *tb; | |
1517 | ||
5e5f07e0 | 1518 | if (tcg_ctx.tb_ctx.nb_tbs <= 0) { |
5b6dd868 BS |
1519 | return NULL; |
1520 | } | |
0b0d3320 EV |
1521 | if (tc_ptr < (uintptr_t)tcg_ctx.code_gen_buffer || |
1522 | tc_ptr >= (uintptr_t)tcg_ctx.code_gen_ptr) { | |
5b6dd868 BS |
1523 | return NULL; |
1524 | } | |
1525 | /* binary search (cf Knuth) */ | |
1526 | m_min = 0; | |
5e5f07e0 | 1527 | m_max = tcg_ctx.tb_ctx.nb_tbs - 1; |
5b6dd868 BS |
1528 | while (m_min <= m_max) { |
1529 | m = (m_min + m_max) >> 1; | |
5e5f07e0 | 1530 | tb = &tcg_ctx.tb_ctx.tbs[m]; |
5b6dd868 BS |
1531 | v = (uintptr_t)tb->tc_ptr; |
1532 | if (v == tc_ptr) { | |
1533 | return tb; | |
1534 | } else if (tc_ptr < v) { | |
1535 | m_max = m - 1; | |
1536 | } else { | |
1537 | m_min = m + 1; | |
1538 | } | |
1539 | } | |
5e5f07e0 | 1540 | return &tcg_ctx.tb_ctx.tbs[m_max]; |
5b6dd868 BS |
1541 | } |
1542 | ||
ec53b45b | 1543 | #if !defined(CONFIG_USER_ONLY) |
29d8ec7b | 1544 | void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) |
5b6dd868 BS |
1545 | { |
1546 | ram_addr_t ram_addr; | |
5c8a00ce | 1547 | MemoryRegion *mr; |
149f54b5 | 1548 | hwaddr l = 1; |
5b6dd868 | 1549 | |
41063e1e | 1550 | rcu_read_lock(); |
29d8ec7b | 1551 | mr = address_space_translate(as, addr, &addr, &l, false); |
5c8a00ce PB |
1552 | if (!(memory_region_is_ram(mr) |
1553 | || memory_region_is_romd(mr))) { | |
41063e1e | 1554 | rcu_read_unlock(); |
5b6dd868 BS |
1555 | return; |
1556 | } | |
5c8a00ce | 1557 | ram_addr = (memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK) |
149f54b5 | 1558 | + addr; |
5b6dd868 | 1559 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
41063e1e | 1560 | rcu_read_unlock(); |
5b6dd868 | 1561 | } |
ec53b45b | 1562 | #endif /* !defined(CONFIG_USER_ONLY) */ |
5b6dd868 | 1563 | |
239c51a5 | 1564 | void tb_check_watchpoint(CPUState *cpu) |
5b6dd868 BS |
1565 | { |
1566 | TranslationBlock *tb; | |
1567 | ||
93afeade | 1568 | tb = tb_find_pc(cpu->mem_io_pc); |
8d302e76 AJ |
1569 | if (tb) { |
1570 | /* We can use retranslation to find the PC. */ | |
1571 | cpu_restore_state_from_tb(cpu, tb, cpu->mem_io_pc); | |
1572 | tb_phys_invalidate(tb, -1); | |
1573 | } else { | |
1574 | /* The exception probably happened in a helper. The CPU state should | |
1575 | have been saved before calling it. Fetch the PC from there. */ | |
1576 | CPUArchState *env = cpu->env_ptr; | |
1577 | target_ulong pc, cs_base; | |
1578 | tb_page_addr_t addr; | |
89fee74a | 1579 | uint32_t flags; |
8d302e76 AJ |
1580 | |
1581 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); | |
1582 | addr = get_page_addr_code(env, pc); | |
1583 | tb_invalidate_phys_range(addr, addr + 1); | |
5b6dd868 | 1584 | } |
5b6dd868 BS |
1585 | } |
1586 | ||
1587 | #ifndef CONFIG_USER_ONLY | |
5b6dd868 BS |
1588 | /* in deterministic execution mode, instructions doing device I/Os |
1589 | must be at the end of the TB */ | |
90b40a69 | 1590 | void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) |
5b6dd868 | 1591 | { |
a47dddd7 | 1592 | #if defined(TARGET_MIPS) || defined(TARGET_SH4) |
90b40a69 | 1593 | CPUArchState *env = cpu->env_ptr; |
a47dddd7 | 1594 | #endif |
5b6dd868 BS |
1595 | TranslationBlock *tb; |
1596 | uint32_t n, cflags; | |
1597 | target_ulong pc, cs_base; | |
89fee74a | 1598 | uint32_t flags; |
5b6dd868 BS |
1599 | |
1600 | tb = tb_find_pc(retaddr); | |
1601 | if (!tb) { | |
a47dddd7 | 1602 | cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p", |
5b6dd868 BS |
1603 | (void *)retaddr); |
1604 | } | |
28ecfd7a | 1605 | n = cpu->icount_decr.u16.low + tb->icount; |
74f10515 | 1606 | cpu_restore_state_from_tb(cpu, tb, retaddr); |
5b6dd868 BS |
1607 | /* Calculate how many instructions had been executed before the fault |
1608 | occurred. */ | |
28ecfd7a | 1609 | n = n - cpu->icount_decr.u16.low; |
5b6dd868 BS |
1610 | /* Generate a new TB ending on the I/O insn. */ |
1611 | n++; | |
1612 | /* On MIPS and SH, delay slot instructions can only be restarted if | |
1613 | they were already the first instruction in the TB. If this is not | |
1614 | the first instruction in a TB then re-execute the preceding | |
1615 | branch. */ | |
1616 | #if defined(TARGET_MIPS) | |
1617 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { | |
c3577479 | 1618 | env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); |
28ecfd7a | 1619 | cpu->icount_decr.u16.low++; |
5b6dd868 BS |
1620 | env->hflags &= ~MIPS_HFLAG_BMASK; |
1621 | } | |
1622 | #elif defined(TARGET_SH4) | |
1623 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 | |
1624 | && n > 1) { | |
1625 | env->pc -= 2; | |
28ecfd7a | 1626 | cpu->icount_decr.u16.low++; |
5b6dd868 BS |
1627 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
1628 | } | |
1629 | #endif | |
1630 | /* This should never happen. */ | |
1631 | if (n > CF_COUNT_MASK) { | |
a47dddd7 | 1632 | cpu_abort(cpu, "TB too big during recompile"); |
5b6dd868 BS |
1633 | } |
1634 | ||
1635 | cflags = n | CF_LAST_IO; | |
1636 | pc = tb->pc; | |
1637 | cs_base = tb->cs_base; | |
1638 | flags = tb->flags; | |
1639 | tb_phys_invalidate(tb, -1); | |
02d57ea1 SF |
1640 | if (tb->cflags & CF_NOCACHE) { |
1641 | if (tb->orig_tb) { | |
1642 | /* Invalidate original TB if this TB was generated in | |
1643 | * cpu_exec_nocache() */ | |
1644 | tb_phys_invalidate(tb->orig_tb, -1); | |
1645 | } | |
1646 | tb_free(tb); | |
1647 | } | |
5b6dd868 BS |
1648 | /* FIXME: In theory this could raise an exception. In practice |
1649 | we have already translated the block once so it's probably ok. */ | |
648f034c | 1650 | tb_gen_code(cpu, pc, cs_base, flags, cflags); |
5b6dd868 BS |
1651 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
1652 | the first in the TB) then we end up generating a whole new TB and | |
1653 | repeating the fault, which is horribly inefficient. | |
1654 | Better would be to execute just this insn uncached, or generate a | |
1655 | second new TB. */ | |
0ea8cb88 | 1656 | cpu_resume_from_signal(cpu, NULL); |
5b6dd868 BS |
1657 | } |
1658 | ||
611d4f99 | 1659 | void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr) |
5b6dd868 BS |
1660 | { |
1661 | unsigned int i; | |
1662 | ||
1663 | /* Discard jump cache entries for any tb which might potentially | |
1664 | overlap the flushed page. */ | |
1665 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); | |
8cd70437 | 1666 | memset(&cpu->tb_jmp_cache[i], 0, |
5b6dd868 BS |
1667 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
1668 | ||
1669 | i = tb_jmp_cache_hash_page(addr); | |
8cd70437 | 1670 | memset(&cpu->tb_jmp_cache[i], 0, |
5b6dd868 BS |
1671 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
1672 | } | |
1673 | ||
1674 | void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) | |
1675 | { | |
1676 | int i, target_code_size, max_target_code_size; | |
1677 | int direct_jmp_count, direct_jmp2_count, cross_page; | |
1678 | TranslationBlock *tb; | |
1679 | ||
1680 | target_code_size = 0; | |
1681 | max_target_code_size = 0; | |
1682 | cross_page = 0; | |
1683 | direct_jmp_count = 0; | |
1684 | direct_jmp2_count = 0; | |
5e5f07e0 EV |
1685 | for (i = 0; i < tcg_ctx.tb_ctx.nb_tbs; i++) { |
1686 | tb = &tcg_ctx.tb_ctx.tbs[i]; | |
5b6dd868 BS |
1687 | target_code_size += tb->size; |
1688 | if (tb->size > max_target_code_size) { | |
1689 | max_target_code_size = tb->size; | |
1690 | } | |
1691 | if (tb->page_addr[1] != -1) { | |
1692 | cross_page++; | |
1693 | } | |
1694 | if (tb->tb_next_offset[0] != 0xffff) { | |
1695 | direct_jmp_count++; | |
1696 | if (tb->tb_next_offset[1] != 0xffff) { | |
1697 | direct_jmp2_count++; | |
1698 | } | |
1699 | } | |
1700 | } | |
1701 | /* XXX: avoid using doubles ? */ | |
1702 | cpu_fprintf(f, "Translation buffer state:\n"); | |
1703 | cpu_fprintf(f, "gen code size %td/%zd\n", | |
0b0d3320 | 1704 | tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, |
b125f9dc | 1705 | tcg_ctx.code_gen_highwater - tcg_ctx.code_gen_buffer); |
5b6dd868 | 1706 | cpu_fprintf(f, "TB count %d/%d\n", |
5e5f07e0 | 1707 | tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.code_gen_max_blocks); |
5b6dd868 | 1708 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
5e5f07e0 EV |
1709 | tcg_ctx.tb_ctx.nb_tbs ? target_code_size / |
1710 | tcg_ctx.tb_ctx.nb_tbs : 0, | |
1711 | max_target_code_size); | |
5b6dd868 | 1712 | cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)\n", |
5e5f07e0 EV |
1713 | tcg_ctx.tb_ctx.nb_tbs ? (tcg_ctx.code_gen_ptr - |
1714 | tcg_ctx.code_gen_buffer) / | |
1715 | tcg_ctx.tb_ctx.nb_tbs : 0, | |
1716 | target_code_size ? (double) (tcg_ctx.code_gen_ptr - | |
1717 | tcg_ctx.code_gen_buffer) / | |
1718 | target_code_size : 0); | |
1719 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", cross_page, | |
1720 | tcg_ctx.tb_ctx.nb_tbs ? (cross_page * 100) / | |
1721 | tcg_ctx.tb_ctx.nb_tbs : 0); | |
5b6dd868 BS |
1722 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", |
1723 | direct_jmp_count, | |
5e5f07e0 EV |
1724 | tcg_ctx.tb_ctx.nb_tbs ? (direct_jmp_count * 100) / |
1725 | tcg_ctx.tb_ctx.nb_tbs : 0, | |
5b6dd868 | 1726 | direct_jmp2_count, |
5e5f07e0 EV |
1727 | tcg_ctx.tb_ctx.nb_tbs ? (direct_jmp2_count * 100) / |
1728 | tcg_ctx.tb_ctx.nb_tbs : 0); | |
5b6dd868 | 1729 | cpu_fprintf(f, "\nStatistics:\n"); |
5e5f07e0 EV |
1730 | cpu_fprintf(f, "TB flush count %d\n", tcg_ctx.tb_ctx.tb_flush_count); |
1731 | cpu_fprintf(f, "TB invalidate count %d\n", | |
1732 | tcg_ctx.tb_ctx.tb_phys_invalidate_count); | |
5b6dd868 BS |
1733 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); |
1734 | tcg_dump_info(f, cpu_fprintf); | |
1735 | } | |
1736 | ||
246ae24d MF |
1737 | void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf) |
1738 | { | |
1739 | tcg_dump_op_count(f, cpu_fprintf); | |
1740 | } | |
1741 | ||
5b6dd868 BS |
1742 | #else /* CONFIG_USER_ONLY */ |
1743 | ||
c3affe56 | 1744 | void cpu_interrupt(CPUState *cpu, int mask) |
5b6dd868 | 1745 | { |
259186a7 | 1746 | cpu->interrupt_request |= mask; |
378df4b2 | 1747 | cpu->tcg_exit_req = 1; |
5b6dd868 BS |
1748 | } |
1749 | ||
1750 | /* | |
1751 | * Walks guest process memory "regions" one by one | |
1752 | * and calls callback function 'fn' for each region. | |
1753 | */ | |
1754 | struct walk_memory_regions_data { | |
1755 | walk_memory_regions_fn fn; | |
1756 | void *priv; | |
1a1c4db9 | 1757 | target_ulong start; |
5b6dd868 BS |
1758 | int prot; |
1759 | }; | |
1760 | ||
1761 | static int walk_memory_regions_end(struct walk_memory_regions_data *data, | |
1a1c4db9 | 1762 | target_ulong end, int new_prot) |
5b6dd868 | 1763 | { |
1a1c4db9 | 1764 | if (data->start != -1u) { |
5b6dd868 BS |
1765 | int rc = data->fn(data->priv, data->start, end, data->prot); |
1766 | if (rc != 0) { | |
1767 | return rc; | |
1768 | } | |
1769 | } | |
1770 | ||
1a1c4db9 | 1771 | data->start = (new_prot ? end : -1u); |
5b6dd868 BS |
1772 | data->prot = new_prot; |
1773 | ||
1774 | return 0; | |
1775 | } | |
1776 | ||
1777 | static int walk_memory_regions_1(struct walk_memory_regions_data *data, | |
1a1c4db9 | 1778 | target_ulong base, int level, void **lp) |
5b6dd868 | 1779 | { |
1a1c4db9 | 1780 | target_ulong pa; |
5b6dd868 BS |
1781 | int i, rc; |
1782 | ||
1783 | if (*lp == NULL) { | |
1784 | return walk_memory_regions_end(data, base, 0); | |
1785 | } | |
1786 | ||
1787 | if (level == 0) { | |
1788 | PageDesc *pd = *lp; | |
1789 | ||
03f49957 | 1790 | for (i = 0; i < V_L2_SIZE; ++i) { |
5b6dd868 BS |
1791 | int prot = pd[i].flags; |
1792 | ||
1793 | pa = base | (i << TARGET_PAGE_BITS); | |
1794 | if (prot != data->prot) { | |
1795 | rc = walk_memory_regions_end(data, pa, prot); | |
1796 | if (rc != 0) { | |
1797 | return rc; | |
1798 | } | |
1799 | } | |
1800 | } | |
1801 | } else { | |
1802 | void **pp = *lp; | |
1803 | ||
03f49957 | 1804 | for (i = 0; i < V_L2_SIZE; ++i) { |
1a1c4db9 | 1805 | pa = base | ((target_ulong)i << |
03f49957 | 1806 | (TARGET_PAGE_BITS + V_L2_BITS * level)); |
5b6dd868 BS |
1807 | rc = walk_memory_regions_1(data, pa, level - 1, pp + i); |
1808 | if (rc != 0) { | |
1809 | return rc; | |
1810 | } | |
1811 | } | |
1812 | } | |
1813 | ||
1814 | return 0; | |
1815 | } | |
1816 | ||
1817 | int walk_memory_regions(void *priv, walk_memory_regions_fn fn) | |
1818 | { | |
1819 | struct walk_memory_regions_data data; | |
1820 | uintptr_t i; | |
1821 | ||
1822 | data.fn = fn; | |
1823 | data.priv = priv; | |
1a1c4db9 | 1824 | data.start = -1u; |
5b6dd868 BS |
1825 | data.prot = 0; |
1826 | ||
1827 | for (i = 0; i < V_L1_SIZE; i++) { | |
1a1c4db9 | 1828 | int rc = walk_memory_regions_1(&data, (target_ulong)i << (V_L1_SHIFT + TARGET_PAGE_BITS), |
03f49957 | 1829 | V_L1_SHIFT / V_L2_BITS - 1, l1_map + i); |
5b6dd868 BS |
1830 | if (rc != 0) { |
1831 | return rc; | |
1832 | } | |
1833 | } | |
1834 | ||
1835 | return walk_memory_regions_end(&data, 0, 0); | |
1836 | } | |
1837 | ||
1a1c4db9 MI |
1838 | static int dump_region(void *priv, target_ulong start, |
1839 | target_ulong end, unsigned long prot) | |
5b6dd868 BS |
1840 | { |
1841 | FILE *f = (FILE *)priv; | |
1842 | ||
1a1c4db9 MI |
1843 | (void) fprintf(f, TARGET_FMT_lx"-"TARGET_FMT_lx |
1844 | " "TARGET_FMT_lx" %c%c%c\n", | |
5b6dd868 BS |
1845 | start, end, end - start, |
1846 | ((prot & PAGE_READ) ? 'r' : '-'), | |
1847 | ((prot & PAGE_WRITE) ? 'w' : '-'), | |
1848 | ((prot & PAGE_EXEC) ? 'x' : '-')); | |
1849 | ||
1850 | return 0; | |
1851 | } | |
1852 | ||
1853 | /* dump memory mappings */ | |
1854 | void page_dump(FILE *f) | |
1855 | { | |
1a1c4db9 | 1856 | const int length = sizeof(target_ulong) * 2; |
227b8175 SW |
1857 | (void) fprintf(f, "%-*s %-*s %-*s %s\n", |
1858 | length, "start", length, "end", length, "size", "prot"); | |
5b6dd868 BS |
1859 | walk_memory_regions(f, dump_region); |
1860 | } | |
1861 | ||
1862 | int page_get_flags(target_ulong address) | |
1863 | { | |
1864 | PageDesc *p; | |
1865 | ||
1866 | p = page_find(address >> TARGET_PAGE_BITS); | |
1867 | if (!p) { | |
1868 | return 0; | |
1869 | } | |
1870 | return p->flags; | |
1871 | } | |
1872 | ||
1873 | /* Modify the flags of a page and invalidate the code if necessary. | |
1874 | The flag PAGE_WRITE_ORG is positioned automatically depending | |
1875 | on PAGE_WRITE. The mmap_lock should already be held. */ | |
1876 | void page_set_flags(target_ulong start, target_ulong end, int flags) | |
1877 | { | |
1878 | target_ulong addr, len; | |
1879 | ||
1880 | /* This function should never be called with addresses outside the | |
1881 | guest address space. If this assert fires, it probably indicates | |
1882 | a missing call to h2g_valid. */ | |
1883 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS | |
1a1c4db9 | 1884 | assert(end < ((target_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); |
5b6dd868 BS |
1885 | #endif |
1886 | assert(start < end); | |
1887 | ||
1888 | start = start & TARGET_PAGE_MASK; | |
1889 | end = TARGET_PAGE_ALIGN(end); | |
1890 | ||
1891 | if (flags & PAGE_WRITE) { | |
1892 | flags |= PAGE_WRITE_ORG; | |
1893 | } | |
1894 | ||
1895 | for (addr = start, len = end - start; | |
1896 | len != 0; | |
1897 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
1898 | PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
1899 | ||
1900 | /* If the write protection bit is set, then we invalidate | |
1901 | the code inside. */ | |
1902 | if (!(p->flags & PAGE_WRITE) && | |
1903 | (flags & PAGE_WRITE) && | |
1904 | p->first_tb) { | |
d02532f0 | 1905 | tb_invalidate_phys_page(addr, 0, NULL, false); |
5b6dd868 BS |
1906 | } |
1907 | p->flags = flags; | |
1908 | } | |
1909 | } | |
1910 | ||
1911 | int page_check_range(target_ulong start, target_ulong len, int flags) | |
1912 | { | |
1913 | PageDesc *p; | |
1914 | target_ulong end; | |
1915 | target_ulong addr; | |
1916 | ||
1917 | /* This function should never be called with addresses outside the | |
1918 | guest address space. If this assert fires, it probably indicates | |
1919 | a missing call to h2g_valid. */ | |
1920 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS | |
1a1c4db9 | 1921 | assert(start < ((target_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); |
5b6dd868 BS |
1922 | #endif |
1923 | ||
1924 | if (len == 0) { | |
1925 | return 0; | |
1926 | } | |
1927 | if (start + len - 1 < start) { | |
1928 | /* We've wrapped around. */ | |
1929 | return -1; | |
1930 | } | |
1931 | ||
1932 | /* must do before we loose bits in the next step */ | |
1933 | end = TARGET_PAGE_ALIGN(start + len); | |
1934 | start = start & TARGET_PAGE_MASK; | |
1935 | ||
1936 | for (addr = start, len = end - start; | |
1937 | len != 0; | |
1938 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
1939 | p = page_find(addr >> TARGET_PAGE_BITS); | |
1940 | if (!p) { | |
1941 | return -1; | |
1942 | } | |
1943 | if (!(p->flags & PAGE_VALID)) { | |
1944 | return -1; | |
1945 | } | |
1946 | ||
1947 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) { | |
1948 | return -1; | |
1949 | } | |
1950 | if (flags & PAGE_WRITE) { | |
1951 | if (!(p->flags & PAGE_WRITE_ORG)) { | |
1952 | return -1; | |
1953 | } | |
1954 | /* unprotect the page if it was put read-only because it | |
1955 | contains translated code */ | |
1956 | if (!(p->flags & PAGE_WRITE)) { | |
1957 | if (!page_unprotect(addr, 0, NULL)) { | |
1958 | return -1; | |
1959 | } | |
1960 | } | |
5b6dd868 BS |
1961 | } |
1962 | } | |
1963 | return 0; | |
1964 | } | |
1965 | ||
1966 | /* called from signal handler: invalidate the code and unprotect the | |
1967 | page. Return TRUE if the fault was successfully handled. */ | |
1968 | int page_unprotect(target_ulong address, uintptr_t pc, void *puc) | |
1969 | { | |
1970 | unsigned int prot; | |
1971 | PageDesc *p; | |
1972 | target_ulong host_start, host_end, addr; | |
1973 | ||
1974 | /* Technically this isn't safe inside a signal handler. However we | |
1975 | know this only ever happens in a synchronous SEGV handler, so in | |
1976 | practice it seems to be ok. */ | |
1977 | mmap_lock(); | |
1978 | ||
1979 | p = page_find(address >> TARGET_PAGE_BITS); | |
1980 | if (!p) { | |
1981 | mmap_unlock(); | |
1982 | return 0; | |
1983 | } | |
1984 | ||
1985 | /* if the page was really writable, then we change its | |
1986 | protection back to writable */ | |
1987 | if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) { | |
1988 | host_start = address & qemu_host_page_mask; | |
1989 | host_end = host_start + qemu_host_page_size; | |
1990 | ||
1991 | prot = 0; | |
1992 | for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) { | |
1993 | p = page_find(addr >> TARGET_PAGE_BITS); | |
1994 | p->flags |= PAGE_WRITE; | |
1995 | prot |= p->flags; | |
1996 | ||
1997 | /* and since the content will be modified, we must invalidate | |
1998 | the corresponding translated code. */ | |
d02532f0 | 1999 | tb_invalidate_phys_page(addr, pc, puc, true); |
5b6dd868 BS |
2000 | #ifdef DEBUG_TB_CHECK |
2001 | tb_invalidate_check(addr); | |
2002 | #endif | |
2003 | } | |
2004 | mprotect((void *)g2h(host_start), qemu_host_page_size, | |
2005 | prot & PAGE_BITS); | |
2006 | ||
2007 | mmap_unlock(); | |
2008 | return 1; | |
2009 | } | |
2010 | mmap_unlock(); | |
2011 | return 0; | |
2012 | } | |
2013 | #endif /* CONFIG_USER_ONLY */ |