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Commit | Line | Data |
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d19893da FB |
1 | /* |
2 | * Host code generation | |
5fafdf24 | 3 | * |
d19893da FB |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
9 | * version 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
d19893da | 18 | */ |
5b6dd868 BS |
19 | #ifdef _WIN32 |
20 | #include <windows.h> | |
21 | #else | |
22 | #include <sys/types.h> | |
23 | #include <sys/mman.h> | |
24 | #endif | |
d19893da FB |
25 | #include <stdarg.h> |
26 | #include <stdlib.h> | |
27 | #include <stdio.h> | |
28 | #include <string.h> | |
29 | #include <inttypes.h> | |
30 | ||
31 | #include "config.h" | |
2054396a | 32 | |
5b6dd868 | 33 | #include "qemu-common.h" |
af5ad107 | 34 | #define NO_CPU_IO_DEFS |
d3eead2e | 35 | #include "cpu.h" |
6db8b538 | 36 | #include "trace.h" |
76cad711 | 37 | #include "disas/disas.h" |
57fec1fe | 38 | #include "tcg.h" |
5b6dd868 BS |
39 | #if defined(CONFIG_USER_ONLY) |
40 | #include "qemu.h" | |
41 | #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) | |
42 | #include <sys/param.h> | |
43 | #if __FreeBSD_version >= 700104 | |
44 | #define HAVE_KINFO_GETVMMAP | |
45 | #define sigqueue sigqueue_freebsd /* avoid redefinition */ | |
46 | #include <sys/time.h> | |
47 | #include <sys/proc.h> | |
48 | #include <machine/profile.h> | |
49 | #define _KERNEL | |
50 | #include <sys/user.h> | |
51 | #undef _KERNEL | |
52 | #undef sigqueue | |
53 | #include <libutil.h> | |
54 | #endif | |
55 | #endif | |
0bc3cd62 PB |
56 | #else |
57 | #include "exec/address-spaces.h" | |
5b6dd868 BS |
58 | #endif |
59 | ||
022c62cb | 60 | #include "exec/cputlb.h" |
e1b89321 | 61 | #include "exec/tb-hash.h" |
5b6dd868 | 62 | #include "translate-all.h" |
510a647f | 63 | #include "qemu/bitmap.h" |
0aa09897 | 64 | #include "qemu/timer.h" |
5b6dd868 BS |
65 | |
66 | //#define DEBUG_TB_INVALIDATE | |
67 | //#define DEBUG_FLUSH | |
68 | /* make various TB consistency checks */ | |
69 | //#define DEBUG_TB_CHECK | |
70 | ||
71 | #if !defined(CONFIG_USER_ONLY) | |
72 | /* TB consistency checks only implemented for usermode emulation. */ | |
73 | #undef DEBUG_TB_CHECK | |
74 | #endif | |
75 | ||
76 | #define SMC_BITMAP_USE_THRESHOLD 10 | |
77 | ||
5b6dd868 BS |
78 | typedef struct PageDesc { |
79 | /* list of TBs intersecting this ram page */ | |
80 | TranslationBlock *first_tb; | |
81 | /* in order to optimize self modifying code, we count the number | |
82 | of lookups we do to a given page to use a bitmap */ | |
83 | unsigned int code_write_count; | |
510a647f | 84 | unsigned long *code_bitmap; |
5b6dd868 BS |
85 | #if defined(CONFIG_USER_ONLY) |
86 | unsigned long flags; | |
87 | #endif | |
88 | } PageDesc; | |
89 | ||
90 | /* In system mode we want L1_MAP to be based on ram offsets, | |
91 | while in user mode we want it to be based on virtual addresses. */ | |
92 | #if !defined(CONFIG_USER_ONLY) | |
93 | #if HOST_LONG_BITS < TARGET_PHYS_ADDR_SPACE_BITS | |
94 | # define L1_MAP_ADDR_SPACE_BITS HOST_LONG_BITS | |
95 | #else | |
96 | # define L1_MAP_ADDR_SPACE_BITS TARGET_PHYS_ADDR_SPACE_BITS | |
97 | #endif | |
98 | #else | |
99 | # define L1_MAP_ADDR_SPACE_BITS TARGET_VIRT_ADDR_SPACE_BITS | |
100 | #endif | |
101 | ||
03f49957 PB |
102 | /* Size of the L2 (and L3, etc) page tables. */ |
103 | #define V_L2_BITS 10 | |
104 | #define V_L2_SIZE (1 << V_L2_BITS) | |
105 | ||
5b6dd868 BS |
106 | /* The bits remaining after N lower levels of page tables. */ |
107 | #define V_L1_BITS_REM \ | |
03f49957 | 108 | ((L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS) % V_L2_BITS) |
5b6dd868 BS |
109 | |
110 | #if V_L1_BITS_REM < 4 | |
03f49957 | 111 | #define V_L1_BITS (V_L1_BITS_REM + V_L2_BITS) |
5b6dd868 BS |
112 | #else |
113 | #define V_L1_BITS V_L1_BITS_REM | |
114 | #endif | |
115 | ||
116 | #define V_L1_SIZE ((target_ulong)1 << V_L1_BITS) | |
117 | ||
118 | #define V_L1_SHIFT (L1_MAP_ADDR_SPACE_BITS - TARGET_PAGE_BITS - V_L1_BITS) | |
119 | ||
120 | uintptr_t qemu_real_host_page_size; | |
4e51361d | 121 | uintptr_t qemu_real_host_page_mask; |
5b6dd868 BS |
122 | uintptr_t qemu_host_page_size; |
123 | uintptr_t qemu_host_page_mask; | |
124 | ||
d1142fb8 | 125 | /* The bottom level has pointers to PageDesc */ |
5b6dd868 BS |
126 | static void *l1_map[V_L1_SIZE]; |
127 | ||
57fec1fe FB |
128 | /* code generation context */ |
129 | TCGContext tcg_ctx; | |
d19893da | 130 | |
677ef623 FK |
131 | /* translation block context */ |
132 | #ifdef CONFIG_USER_ONLY | |
133 | __thread int have_tb_lock; | |
134 | #endif | |
135 | ||
136 | void tb_lock(void) | |
137 | { | |
138 | #ifdef CONFIG_USER_ONLY | |
139 | assert(!have_tb_lock); | |
140 | qemu_mutex_lock(&tcg_ctx.tb_ctx.tb_lock); | |
141 | have_tb_lock++; | |
142 | #endif | |
143 | } | |
144 | ||
145 | void tb_unlock(void) | |
146 | { | |
147 | #ifdef CONFIG_USER_ONLY | |
148 | assert(have_tb_lock); | |
149 | have_tb_lock--; | |
150 | qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); | |
151 | #endif | |
152 | } | |
153 | ||
154 | void tb_lock_reset(void) | |
155 | { | |
156 | #ifdef CONFIG_USER_ONLY | |
157 | if (have_tb_lock) { | |
158 | qemu_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock); | |
159 | have_tb_lock = 0; | |
160 | } | |
161 | #endif | |
162 | } | |
163 | ||
5b6dd868 BS |
164 | static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, |
165 | tb_page_addr_t phys_page2); | |
a8a826a3 | 166 | static TranslationBlock *tb_find_pc(uintptr_t tc_ptr); |
5b6dd868 | 167 | |
57fec1fe FB |
168 | void cpu_gen_init(void) |
169 | { | |
170 | tcg_context_init(&tcg_ctx); | |
57fec1fe FB |
171 | } |
172 | ||
d19893da | 173 | /* return non zero if the very first instruction is invalid so that |
75692087 PB |
174 | * the virtual CPU can trigger an exception. |
175 | * | |
176 | * '*gen_code_size_ptr' contains the size of the generated code (host | |
177 | * code). | |
178 | * | |
179 | * Called with mmap_lock held for user-mode emulation. | |
180 | */ | |
9349b4f9 | 181 | int cpu_gen_code(CPUArchState *env, TranslationBlock *tb, int *gen_code_size_ptr) |
d19893da | 182 | { |
57fec1fe | 183 | TCGContext *s = &tcg_ctx; |
1813e175 | 184 | tcg_insn_unit *gen_code_buf; |
d19893da | 185 | int gen_code_size; |
57fec1fe FB |
186 | #ifdef CONFIG_PROFILER |
187 | int64_t ti; | |
188 | #endif | |
189 | ||
190 | #ifdef CONFIG_PROFILER | |
b67d9a52 FB |
191 | s->tb_count1++; /* includes aborted translations because of |
192 | exceptions */ | |
57fec1fe FB |
193 | ti = profile_getclock(); |
194 | #endif | |
195 | tcg_func_start(s); | |
d19893da | 196 | |
2cfc5f17 TS |
197 | gen_intermediate_code(env, tb); |
198 | ||
6db8b538 AB |
199 | trace_translate_block(tb, tb->pc, tb->tc_ptr); |
200 | ||
ec6338ba | 201 | /* generate machine code */ |
57fec1fe | 202 | gen_code_buf = tb->tc_ptr; |
ec6338ba FB |
203 | tb->tb_next_offset[0] = 0xffff; |
204 | tb->tb_next_offset[1] = 0xffff; | |
57fec1fe | 205 | s->tb_next_offset = tb->tb_next_offset; |
4cbb86e1 | 206 | #ifdef USE_DIRECT_JUMP |
57fec1fe FB |
207 | s->tb_jmp_offset = tb->tb_jmp_offset; |
208 | s->tb_next = NULL; | |
d19893da | 209 | #else |
57fec1fe FB |
210 | s->tb_jmp_offset = NULL; |
211 | s->tb_next = tb->tb_next; | |
d19893da | 212 | #endif |
57fec1fe FB |
213 | |
214 | #ifdef CONFIG_PROFILER | |
b67d9a52 FB |
215 | s->tb_count++; |
216 | s->interm_time += profile_getclock() - ti; | |
217 | s->code_time -= profile_getclock(); | |
57fec1fe | 218 | #endif |
54604f74 | 219 | gen_code_size = tcg_gen_code(s, gen_code_buf); |
d19893da | 220 | *gen_code_size_ptr = gen_code_size; |
57fec1fe | 221 | #ifdef CONFIG_PROFILER |
b67d9a52 FB |
222 | s->code_time += profile_getclock(); |
223 | s->code_in_len += tb->size; | |
224 | s->code_out_len += gen_code_size; | |
57fec1fe FB |
225 | #endif |
226 | ||
d19893da | 227 | #ifdef DEBUG_DISAS |
8fec2b8c | 228 | if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM)) { |
1813e175 RH |
229 | qemu_log("OUT: [size=%d]\n", gen_code_size); |
230 | log_disas(tb->tc_ptr, gen_code_size); | |
93fcfe39 | 231 | qemu_log("\n"); |
31b1a7b4 | 232 | qemu_log_flush(); |
d19893da FB |
233 | } |
234 | #endif | |
235 | return 0; | |
236 | } | |
237 | ||
5fafdf24 | 238 | /* The cpu state corresponding to 'searched_pc' is restored. |
d19893da | 239 | */ |
74f10515 | 240 | static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, |
a8a826a3 | 241 | uintptr_t searched_pc) |
d19893da | 242 | { |
74f10515 | 243 | CPUArchState *env = cpu->env_ptr; |
57fec1fe FB |
244 | TCGContext *s = &tcg_ctx; |
245 | int j; | |
6375e09e | 246 | uintptr_t tc_ptr; |
57fec1fe FB |
247 | #ifdef CONFIG_PROFILER |
248 | int64_t ti; | |
249 | #endif | |
250 | ||
251 | #ifdef CONFIG_PROFILER | |
252 | ti = profile_getclock(); | |
253 | #endif | |
254 | tcg_func_start(s); | |
d19893da | 255 | |
2cfc5f17 | 256 | gen_intermediate_code_pc(env, tb); |
3b46e624 | 257 | |
bd79255d | 258 | if (tb->cflags & CF_USE_ICOUNT) { |
414b15c9 | 259 | assert(use_icount); |
2e70f6ef | 260 | /* Reset the cycle counter to the start of the block. */ |
28ecfd7a | 261 | cpu->icount_decr.u16.low += tb->icount; |
2e70f6ef | 262 | /* Clear the IO flag. */ |
99df7dce | 263 | cpu->can_do_io = 0; |
2e70f6ef PB |
264 | } |
265 | ||
d19893da | 266 | /* find opc index corresponding to search_pc */ |
6375e09e | 267 | tc_ptr = (uintptr_t)tb->tc_ptr; |
d19893da FB |
268 | if (searched_pc < tc_ptr) |
269 | return -1; | |
57fec1fe FB |
270 | |
271 | s->tb_next_offset = tb->tb_next_offset; | |
272 | #ifdef USE_DIRECT_JUMP | |
273 | s->tb_jmp_offset = tb->tb_jmp_offset; | |
274 | s->tb_next = NULL; | |
275 | #else | |
276 | s->tb_jmp_offset = NULL; | |
277 | s->tb_next = tb->tb_next; | |
278 | #endif | |
1813e175 RH |
279 | j = tcg_gen_code_search_pc(s, (tcg_insn_unit *)tc_ptr, |
280 | searched_pc - tc_ptr); | |
57fec1fe FB |
281 | if (j < 0) |
282 | return -1; | |
d19893da | 283 | /* now find start of instruction before */ |
ab1103de | 284 | while (s->gen_opc_instr_start[j] == 0) { |
d19893da | 285 | j--; |
ab1103de | 286 | } |
28ecfd7a | 287 | cpu->icount_decr.u16.low -= s->gen_opc_icount[j]; |
3b46e624 | 288 | |
e87b7cb0 | 289 | restore_state_to_opc(env, tb, j); |
57fec1fe FB |
290 | |
291 | #ifdef CONFIG_PROFILER | |
b67d9a52 FB |
292 | s->restore_time += profile_getclock() - ti; |
293 | s->restore_count++; | |
57fec1fe | 294 | #endif |
d19893da FB |
295 | return 0; |
296 | } | |
5b6dd868 | 297 | |
3f38f309 | 298 | bool cpu_restore_state(CPUState *cpu, uintptr_t retaddr) |
a8a826a3 BS |
299 | { |
300 | TranslationBlock *tb; | |
301 | ||
302 | tb = tb_find_pc(retaddr); | |
303 | if (tb) { | |
74f10515 | 304 | cpu_restore_state_from_tb(cpu, tb, retaddr); |
d8a499f1 PD |
305 | if (tb->cflags & CF_NOCACHE) { |
306 | /* one-shot translation, invalidate it immediately */ | |
307 | cpu->current_tb = NULL; | |
308 | tb_phys_invalidate(tb, -1); | |
309 | tb_free(tb); | |
310 | } | |
a8a826a3 BS |
311 | return true; |
312 | } | |
313 | return false; | |
314 | } | |
315 | ||
5b6dd868 | 316 | #ifdef _WIN32 |
2d8ac5eb | 317 | static __attribute__((unused)) void map_exec(void *addr, long size) |
5b6dd868 BS |
318 | { |
319 | DWORD old_protect; | |
320 | VirtualProtect(addr, size, | |
321 | PAGE_EXECUTE_READWRITE, &old_protect); | |
322 | } | |
323 | #else | |
2d8ac5eb | 324 | static __attribute__((unused)) void map_exec(void *addr, long size) |
5b6dd868 BS |
325 | { |
326 | unsigned long start, end, page_size; | |
327 | ||
328 | page_size = getpagesize(); | |
329 | start = (unsigned long)addr; | |
330 | start &= ~(page_size - 1); | |
331 | ||
332 | end = (unsigned long)addr + size; | |
333 | end += page_size - 1; | |
334 | end &= ~(page_size - 1); | |
335 | ||
336 | mprotect((void *)start, end - start, | |
337 | PROT_READ | PROT_WRITE | PROT_EXEC); | |
338 | } | |
339 | #endif | |
340 | ||
47c16ed5 | 341 | void page_size_init(void) |
5b6dd868 BS |
342 | { |
343 | /* NOTE: we can always suppose that qemu_host_page_size >= | |
344 | TARGET_PAGE_SIZE */ | |
5b6dd868 | 345 | qemu_real_host_page_size = getpagesize(); |
4e51361d | 346 | qemu_real_host_page_mask = ~(qemu_real_host_page_size - 1); |
5b6dd868 BS |
347 | if (qemu_host_page_size == 0) { |
348 | qemu_host_page_size = qemu_real_host_page_size; | |
349 | } | |
350 | if (qemu_host_page_size < TARGET_PAGE_SIZE) { | |
351 | qemu_host_page_size = TARGET_PAGE_SIZE; | |
352 | } | |
353 | qemu_host_page_mask = ~(qemu_host_page_size - 1); | |
47c16ed5 | 354 | } |
5b6dd868 | 355 | |
47c16ed5 AK |
356 | static void page_init(void) |
357 | { | |
358 | page_size_init(); | |
5b6dd868 BS |
359 | #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) |
360 | { | |
361 | #ifdef HAVE_KINFO_GETVMMAP | |
362 | struct kinfo_vmentry *freep; | |
363 | int i, cnt; | |
364 | ||
365 | freep = kinfo_getvmmap(getpid(), &cnt); | |
366 | if (freep) { | |
367 | mmap_lock(); | |
368 | for (i = 0; i < cnt; i++) { | |
369 | unsigned long startaddr, endaddr; | |
370 | ||
371 | startaddr = freep[i].kve_start; | |
372 | endaddr = freep[i].kve_end; | |
373 | if (h2g_valid(startaddr)) { | |
374 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
375 | ||
376 | if (h2g_valid(endaddr)) { | |
377 | endaddr = h2g(endaddr); | |
378 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
379 | } else { | |
380 | #if TARGET_ABI_BITS <= L1_MAP_ADDR_SPACE_BITS | |
381 | endaddr = ~0ul; | |
382 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
383 | #endif | |
384 | } | |
385 | } | |
386 | } | |
387 | free(freep); | |
388 | mmap_unlock(); | |
389 | } | |
390 | #else | |
391 | FILE *f; | |
392 | ||
393 | last_brk = (unsigned long)sbrk(0); | |
394 | ||
395 | f = fopen("/compat/linux/proc/self/maps", "r"); | |
396 | if (f) { | |
397 | mmap_lock(); | |
398 | ||
399 | do { | |
400 | unsigned long startaddr, endaddr; | |
401 | int n; | |
402 | ||
403 | n = fscanf(f, "%lx-%lx %*[^\n]\n", &startaddr, &endaddr); | |
404 | ||
405 | if (n == 2 && h2g_valid(startaddr)) { | |
406 | startaddr = h2g(startaddr) & TARGET_PAGE_MASK; | |
407 | ||
408 | if (h2g_valid(endaddr)) { | |
409 | endaddr = h2g(endaddr); | |
410 | } else { | |
411 | endaddr = ~0ul; | |
412 | } | |
413 | page_set_flags(startaddr, endaddr, PAGE_RESERVED); | |
414 | } | |
415 | } while (!feof(f)); | |
416 | ||
417 | fclose(f); | |
418 | mmap_unlock(); | |
419 | } | |
420 | #endif | |
421 | } | |
422 | #endif | |
423 | } | |
424 | ||
75692087 PB |
425 | /* If alloc=1: |
426 | * Called with mmap_lock held for user-mode emulation. | |
427 | */ | |
5b6dd868 BS |
428 | static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) |
429 | { | |
430 | PageDesc *pd; | |
431 | void **lp; | |
432 | int i; | |
433 | ||
5b6dd868 BS |
434 | /* Level 1. Always allocated. */ |
435 | lp = l1_map + ((index >> V_L1_SHIFT) & (V_L1_SIZE - 1)); | |
436 | ||
437 | /* Level 2..N-1. */ | |
03f49957 | 438 | for (i = V_L1_SHIFT / V_L2_BITS - 1; i > 0; i--) { |
6940fab8 | 439 | void **p = atomic_rcu_read(lp); |
5b6dd868 BS |
440 | |
441 | if (p == NULL) { | |
442 | if (!alloc) { | |
443 | return NULL; | |
444 | } | |
e3a0abfd | 445 | p = g_new0(void *, V_L2_SIZE); |
6940fab8 | 446 | atomic_rcu_set(lp, p); |
5b6dd868 BS |
447 | } |
448 | ||
03f49957 | 449 | lp = p + ((index >> (i * V_L2_BITS)) & (V_L2_SIZE - 1)); |
5b6dd868 BS |
450 | } |
451 | ||
6940fab8 | 452 | pd = atomic_rcu_read(lp); |
5b6dd868 BS |
453 | if (pd == NULL) { |
454 | if (!alloc) { | |
455 | return NULL; | |
456 | } | |
e3a0abfd | 457 | pd = g_new0(PageDesc, V_L2_SIZE); |
6940fab8 | 458 | atomic_rcu_set(lp, pd); |
5b6dd868 BS |
459 | } |
460 | ||
03f49957 | 461 | return pd + (index & (V_L2_SIZE - 1)); |
5b6dd868 BS |
462 | } |
463 | ||
464 | static inline PageDesc *page_find(tb_page_addr_t index) | |
465 | { | |
466 | return page_find_alloc(index, 0); | |
467 | } | |
468 | ||
5b6dd868 BS |
469 | #if defined(CONFIG_USER_ONLY) |
470 | /* Currently it is not recommended to allocate big chunks of data in | |
471 | user mode. It will change when a dedicated libc will be used. */ | |
472 | /* ??? 64-bit hosts ought to have no problem mmaping data outside the | |
473 | region in which the guest needs to run. Revisit this. */ | |
474 | #define USE_STATIC_CODE_GEN_BUFFER | |
475 | #endif | |
476 | ||
477 | /* ??? Should configure for this, not list operating systems here. */ | |
478 | #if (defined(__linux__) \ | |
479 | || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \ | |
480 | || defined(__DragonFly__) || defined(__OpenBSD__) \ | |
481 | || defined(__NetBSD__)) | |
482 | # define USE_MMAP | |
483 | #endif | |
484 | ||
485 | /* Minimum size of the code gen buffer. This number is randomly chosen, | |
486 | but not so small that we can't have a fair number of TB's live. */ | |
487 | #define MIN_CODE_GEN_BUFFER_SIZE (1024u * 1024) | |
488 | ||
489 | /* Maximum size of the code gen buffer we'd like to use. Unless otherwise | |
490 | indicated, this is constrained by the range of direct branches on the | |
491 | host cpu, as used by the TCG implementation of goto_tb. */ | |
492 | #if defined(__x86_64__) | |
493 | # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024) | |
494 | #elif defined(__sparc__) | |
495 | # define MAX_CODE_GEN_BUFFER_SIZE (2ul * 1024 * 1024 * 1024) | |
4a136e0a CF |
496 | #elif defined(__aarch64__) |
497 | # define MAX_CODE_GEN_BUFFER_SIZE (128ul * 1024 * 1024) | |
5b6dd868 BS |
498 | #elif defined(__arm__) |
499 | # define MAX_CODE_GEN_BUFFER_SIZE (16u * 1024 * 1024) | |
500 | #elif defined(__s390x__) | |
501 | /* We have a +- 4GB range on the branches; leave some slop. */ | |
502 | # define MAX_CODE_GEN_BUFFER_SIZE (3ul * 1024 * 1024 * 1024) | |
479eb121 RH |
503 | #elif defined(__mips__) |
504 | /* We have a 256MB branch region, but leave room to make sure the | |
505 | main executable is also within that region. */ | |
506 | # define MAX_CODE_GEN_BUFFER_SIZE (128ul * 1024 * 1024) | |
5b6dd868 BS |
507 | #else |
508 | # define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) | |
509 | #endif | |
510 | ||
511 | #define DEFAULT_CODE_GEN_BUFFER_SIZE_1 (32u * 1024 * 1024) | |
512 | ||
513 | #define DEFAULT_CODE_GEN_BUFFER_SIZE \ | |
514 | (DEFAULT_CODE_GEN_BUFFER_SIZE_1 < MAX_CODE_GEN_BUFFER_SIZE \ | |
515 | ? DEFAULT_CODE_GEN_BUFFER_SIZE_1 : MAX_CODE_GEN_BUFFER_SIZE) | |
516 | ||
517 | static inline size_t size_code_gen_buffer(size_t tb_size) | |
518 | { | |
519 | /* Size the buffer. */ | |
520 | if (tb_size == 0) { | |
521 | #ifdef USE_STATIC_CODE_GEN_BUFFER | |
522 | tb_size = DEFAULT_CODE_GEN_BUFFER_SIZE; | |
523 | #else | |
524 | /* ??? Needs adjustments. */ | |
525 | /* ??? If we relax the requirement that CONFIG_USER_ONLY use the | |
526 | static buffer, we could size this on RESERVED_VA, on the text | |
527 | segment size of the executable, or continue to use the default. */ | |
528 | tb_size = (unsigned long)(ram_size / 4); | |
529 | #endif | |
530 | } | |
531 | if (tb_size < MIN_CODE_GEN_BUFFER_SIZE) { | |
532 | tb_size = MIN_CODE_GEN_BUFFER_SIZE; | |
533 | } | |
534 | if (tb_size > MAX_CODE_GEN_BUFFER_SIZE) { | |
535 | tb_size = MAX_CODE_GEN_BUFFER_SIZE; | |
536 | } | |
0b0d3320 | 537 | tcg_ctx.code_gen_buffer_size = tb_size; |
5b6dd868 BS |
538 | return tb_size; |
539 | } | |
540 | ||
483c76e1 RH |
541 | #ifdef __mips__ |
542 | /* In order to use J and JAL within the code_gen_buffer, we require | |
543 | that the buffer not cross a 256MB boundary. */ | |
544 | static inline bool cross_256mb(void *addr, size_t size) | |
545 | { | |
546 | return ((uintptr_t)addr ^ ((uintptr_t)addr + size)) & 0xf0000000; | |
547 | } | |
548 | ||
549 | /* We weren't able to allocate a buffer without crossing that boundary, | |
550 | so make do with the larger portion of the buffer that doesn't cross. | |
551 | Returns the new base of the buffer, and adjusts code_gen_buffer_size. */ | |
552 | static inline void *split_cross_256mb(void *buf1, size_t size1) | |
553 | { | |
554 | void *buf2 = (void *)(((uintptr_t)buf1 + size1) & 0xf0000000); | |
555 | size_t size2 = buf1 + size1 - buf2; | |
556 | ||
557 | size1 = buf2 - buf1; | |
558 | if (size1 < size2) { | |
559 | size1 = size2; | |
560 | buf1 = buf2; | |
561 | } | |
562 | ||
563 | tcg_ctx.code_gen_buffer_size = size1; | |
564 | return buf1; | |
565 | } | |
566 | #endif | |
567 | ||
5b6dd868 BS |
568 | #ifdef USE_STATIC_CODE_GEN_BUFFER |
569 | static uint8_t static_code_gen_buffer[DEFAULT_CODE_GEN_BUFFER_SIZE] | |
570 | __attribute__((aligned(CODE_GEN_ALIGN))); | |
571 | ||
572 | static inline void *alloc_code_gen_buffer(void) | |
573 | { | |
483c76e1 RH |
574 | void *buf = static_code_gen_buffer; |
575 | #ifdef __mips__ | |
576 | if (cross_256mb(buf, tcg_ctx.code_gen_buffer_size)) { | |
577 | buf = split_cross_256mb(buf, tcg_ctx.code_gen_buffer_size); | |
578 | } | |
579 | #endif | |
580 | map_exec(buf, tcg_ctx.code_gen_buffer_size); | |
581 | return buf; | |
5b6dd868 BS |
582 | } |
583 | #elif defined(USE_MMAP) | |
584 | static inline void *alloc_code_gen_buffer(void) | |
585 | { | |
586 | int flags = MAP_PRIVATE | MAP_ANONYMOUS; | |
587 | uintptr_t start = 0; | |
588 | void *buf; | |
589 | ||
590 | /* Constrain the position of the buffer based on the host cpu. | |
591 | Note that these addresses are chosen in concert with the | |
592 | addresses assigned in the relevant linker script file. */ | |
593 | # if defined(__PIE__) || defined(__PIC__) | |
594 | /* Don't bother setting a preferred location if we're building | |
595 | a position-independent executable. We're more likely to get | |
596 | an address near the main executable if we let the kernel | |
597 | choose the address. */ | |
598 | # elif defined(__x86_64__) && defined(MAP_32BIT) | |
599 | /* Force the memory down into low memory with the executable. | |
600 | Leave the choice of exact location with the kernel. */ | |
601 | flags |= MAP_32BIT; | |
602 | /* Cannot expect to map more than 800MB in low memory. */ | |
0b0d3320 EV |
603 | if (tcg_ctx.code_gen_buffer_size > 800u * 1024 * 1024) { |
604 | tcg_ctx.code_gen_buffer_size = 800u * 1024 * 1024; | |
5b6dd868 BS |
605 | } |
606 | # elif defined(__sparc__) | |
607 | start = 0x40000000ul; | |
608 | # elif defined(__s390x__) | |
609 | start = 0x90000000ul; | |
479eb121 RH |
610 | # elif defined(__mips__) |
611 | /* ??? We ought to more explicitly manage layout for softmmu too. */ | |
612 | # ifdef CONFIG_USER_ONLY | |
613 | start = 0x68000000ul; | |
614 | # elif _MIPS_SIM == _ABI64 | |
615 | start = 0x128000000ul; | |
616 | # else | |
617 | start = 0x08000000ul; | |
618 | # endif | |
5b6dd868 BS |
619 | # endif |
620 | ||
0b0d3320 | 621 | buf = mmap((void *)start, tcg_ctx.code_gen_buffer_size, |
5b6dd868 | 622 | PROT_WRITE | PROT_READ | PROT_EXEC, flags, -1, 0); |
483c76e1 RH |
623 | if (buf == MAP_FAILED) { |
624 | return NULL; | |
625 | } | |
626 | ||
627 | #ifdef __mips__ | |
628 | if (cross_256mb(buf, tcg_ctx.code_gen_buffer_size)) { | |
5d831be2 | 629 | /* Try again, with the original still mapped, to avoid re-acquiring |
483c76e1 RH |
630 | that 256mb crossing. This time don't specify an address. */ |
631 | size_t size2, size1 = tcg_ctx.code_gen_buffer_size; | |
632 | void *buf2 = mmap(NULL, size1, PROT_WRITE | PROT_READ | PROT_EXEC, | |
633 | flags, -1, 0); | |
634 | if (buf2 != MAP_FAILED) { | |
635 | if (!cross_256mb(buf2, size1)) { | |
636 | /* Success! Use the new buffer. */ | |
637 | munmap(buf, size1); | |
638 | return buf2; | |
639 | } | |
640 | /* Failure. Work with what we had. */ | |
641 | munmap(buf2, size1); | |
642 | } | |
643 | ||
644 | /* Split the original buffer. Free the smaller half. */ | |
645 | buf2 = split_cross_256mb(buf, size1); | |
646 | size2 = tcg_ctx.code_gen_buffer_size; | |
647 | munmap(buf + (buf == buf2 ? size2 : 0), size1 - size2); | |
648 | return buf2; | |
649 | } | |
650 | #endif | |
651 | ||
652 | return buf; | |
5b6dd868 BS |
653 | } |
654 | #else | |
655 | static inline void *alloc_code_gen_buffer(void) | |
656 | { | |
8b98ade3 | 657 | void *buf = g_try_malloc(tcg_ctx.code_gen_buffer_size); |
5b6dd868 | 658 | |
483c76e1 RH |
659 | if (buf == NULL) { |
660 | return NULL; | |
661 | } | |
662 | ||
663 | #ifdef __mips__ | |
664 | if (cross_256mb(buf, tcg_ctx.code_gen_buffer_size)) { | |
665 | void *buf2 = g_malloc(tcg_ctx.code_gen_buffer_size); | |
666 | if (buf2 != NULL && !cross_256mb(buf2, size1)) { | |
667 | /* Success! Use the new buffer. */ | |
668 | free(buf); | |
669 | buf = buf2; | |
670 | } else { | |
671 | /* Failure. Work with what we had. Since this is malloc | |
672 | and not mmap, we can't free the other half. */ | |
673 | free(buf2); | |
674 | buf = split_cross_256mb(buf, tcg_ctx.code_gen_buffer_size); | |
675 | } | |
5b6dd868 | 676 | } |
483c76e1 RH |
677 | #endif |
678 | ||
679 | map_exec(buf, tcg_ctx.code_gen_buffer_size); | |
5b6dd868 BS |
680 | return buf; |
681 | } | |
682 | #endif /* USE_STATIC_CODE_GEN_BUFFER, USE_MMAP */ | |
683 | ||
684 | static inline void code_gen_alloc(size_t tb_size) | |
685 | { | |
0b0d3320 EV |
686 | tcg_ctx.code_gen_buffer_size = size_code_gen_buffer(tb_size); |
687 | tcg_ctx.code_gen_buffer = alloc_code_gen_buffer(); | |
688 | if (tcg_ctx.code_gen_buffer == NULL) { | |
5b6dd868 BS |
689 | fprintf(stderr, "Could not allocate dynamic translator buffer\n"); |
690 | exit(1); | |
691 | } | |
692 | ||
0b0d3320 EV |
693 | qemu_madvise(tcg_ctx.code_gen_buffer, tcg_ctx.code_gen_buffer_size, |
694 | QEMU_MADV_HUGEPAGE); | |
5b6dd868 BS |
695 | |
696 | /* Steal room for the prologue at the end of the buffer. This ensures | |
697 | (via the MAX_CODE_GEN_BUFFER_SIZE limits above) that direct branches | |
698 | from TB's to the prologue are going to be in range. It also means | |
699 | that we don't need to mark (additional) portions of the data segment | |
700 | as executable. */ | |
0b0d3320 EV |
701 | tcg_ctx.code_gen_prologue = tcg_ctx.code_gen_buffer + |
702 | tcg_ctx.code_gen_buffer_size - 1024; | |
703 | tcg_ctx.code_gen_buffer_size -= 1024; | |
5b6dd868 | 704 | |
0b0d3320 | 705 | tcg_ctx.code_gen_buffer_max_size = tcg_ctx.code_gen_buffer_size - |
5b6dd868 | 706 | (TCG_MAX_OP_SIZE * OPC_BUF_SIZE); |
0b0d3320 EV |
707 | tcg_ctx.code_gen_max_blocks = tcg_ctx.code_gen_buffer_size / |
708 | CODE_GEN_AVG_BLOCK_SIZE; | |
5e5f07e0 EV |
709 | tcg_ctx.tb_ctx.tbs = |
710 | g_malloc(tcg_ctx.code_gen_max_blocks * sizeof(TranslationBlock)); | |
677ef623 | 711 | qemu_mutex_init(&tcg_ctx.tb_ctx.tb_lock); |
5b6dd868 BS |
712 | } |
713 | ||
714 | /* Must be called before using the QEMU cpus. 'tb_size' is the size | |
715 | (in bytes) allocated to the translation buffer. Zero means default | |
716 | size. */ | |
717 | void tcg_exec_init(unsigned long tb_size) | |
718 | { | |
719 | cpu_gen_init(); | |
720 | code_gen_alloc(tb_size); | |
0b0d3320 EV |
721 | tcg_ctx.code_gen_ptr = tcg_ctx.code_gen_buffer; |
722 | tcg_register_jit(tcg_ctx.code_gen_buffer, tcg_ctx.code_gen_buffer_size); | |
5b6dd868 | 723 | page_init(); |
4cbea598 | 724 | #if defined(CONFIG_SOFTMMU) |
5b6dd868 BS |
725 | /* There's no guest base to take into account, so go ahead and |
726 | initialize the prologue now. */ | |
727 | tcg_prologue_init(&tcg_ctx); | |
728 | #endif | |
729 | } | |
730 | ||
731 | bool tcg_enabled(void) | |
732 | { | |
0b0d3320 | 733 | return tcg_ctx.code_gen_buffer != NULL; |
5b6dd868 BS |
734 | } |
735 | ||
736 | /* Allocate a new translation block. Flush the translation buffer if | |
737 | too many translation blocks or too much generated code. */ | |
738 | static TranslationBlock *tb_alloc(target_ulong pc) | |
739 | { | |
740 | TranslationBlock *tb; | |
741 | ||
5e5f07e0 | 742 | if (tcg_ctx.tb_ctx.nb_tbs >= tcg_ctx.code_gen_max_blocks || |
0b0d3320 EV |
743 | (tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) >= |
744 | tcg_ctx.code_gen_buffer_max_size) { | |
5b6dd868 BS |
745 | return NULL; |
746 | } | |
5e5f07e0 | 747 | tb = &tcg_ctx.tb_ctx.tbs[tcg_ctx.tb_ctx.nb_tbs++]; |
5b6dd868 BS |
748 | tb->pc = pc; |
749 | tb->cflags = 0; | |
750 | return tb; | |
751 | } | |
752 | ||
753 | void tb_free(TranslationBlock *tb) | |
754 | { | |
755 | /* In practice this is mostly used for single use temporary TB | |
756 | Ignore the hard cases and just back up if this TB happens to | |
757 | be the last one generated. */ | |
5e5f07e0 EV |
758 | if (tcg_ctx.tb_ctx.nb_tbs > 0 && |
759 | tb == &tcg_ctx.tb_ctx.tbs[tcg_ctx.tb_ctx.nb_tbs - 1]) { | |
0b0d3320 | 760 | tcg_ctx.code_gen_ptr = tb->tc_ptr; |
5e5f07e0 | 761 | tcg_ctx.tb_ctx.nb_tbs--; |
5b6dd868 BS |
762 | } |
763 | } | |
764 | ||
765 | static inline void invalidate_page_bitmap(PageDesc *p) | |
766 | { | |
767 | if (p->code_bitmap) { | |
768 | g_free(p->code_bitmap); | |
769 | p->code_bitmap = NULL; | |
770 | } | |
771 | p->code_write_count = 0; | |
772 | } | |
773 | ||
774 | /* Set to NULL all the 'first_tb' fields in all PageDescs. */ | |
775 | static void page_flush_tb_1(int level, void **lp) | |
776 | { | |
777 | int i; | |
778 | ||
779 | if (*lp == NULL) { | |
780 | return; | |
781 | } | |
782 | if (level == 0) { | |
783 | PageDesc *pd = *lp; | |
784 | ||
03f49957 | 785 | for (i = 0; i < V_L2_SIZE; ++i) { |
5b6dd868 BS |
786 | pd[i].first_tb = NULL; |
787 | invalidate_page_bitmap(pd + i); | |
788 | } | |
789 | } else { | |
790 | void **pp = *lp; | |
791 | ||
03f49957 | 792 | for (i = 0; i < V_L2_SIZE; ++i) { |
5b6dd868 BS |
793 | page_flush_tb_1(level - 1, pp + i); |
794 | } | |
795 | } | |
796 | } | |
797 | ||
798 | static void page_flush_tb(void) | |
799 | { | |
800 | int i; | |
801 | ||
802 | for (i = 0; i < V_L1_SIZE; i++) { | |
03f49957 | 803 | page_flush_tb_1(V_L1_SHIFT / V_L2_BITS - 1, l1_map + i); |
5b6dd868 BS |
804 | } |
805 | } | |
806 | ||
807 | /* flush all the translation blocks */ | |
808 | /* XXX: tb_flush is currently not thread safe */ | |
bbd77c18 | 809 | void tb_flush(CPUState *cpu) |
5b6dd868 | 810 | { |
5b6dd868 BS |
811 | #if defined(DEBUG_FLUSH) |
812 | printf("qemu: flush code_size=%ld nb_tbs=%d avg_tb_size=%ld\n", | |
0b0d3320 | 813 | (unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer), |
5e5f07e0 | 814 | tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.tb_ctx.nb_tbs > 0 ? |
0b0d3320 | 815 | ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer)) / |
5e5f07e0 | 816 | tcg_ctx.tb_ctx.nb_tbs : 0); |
5b6dd868 | 817 | #endif |
0b0d3320 EV |
818 | if ((unsigned long)(tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer) |
819 | > tcg_ctx.code_gen_buffer_size) { | |
a47dddd7 | 820 | cpu_abort(cpu, "Internal error: code buffer overflow\n"); |
5b6dd868 | 821 | } |
5e5f07e0 | 822 | tcg_ctx.tb_ctx.nb_tbs = 0; |
5b6dd868 | 823 | |
bdc44640 | 824 | CPU_FOREACH(cpu) { |
8cd70437 | 825 | memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache)); |
5b6dd868 BS |
826 | } |
827 | ||
eb2535f4 | 828 | memset(tcg_ctx.tb_ctx.tb_phys_hash, 0, sizeof(tcg_ctx.tb_ctx.tb_phys_hash)); |
5b6dd868 BS |
829 | page_flush_tb(); |
830 | ||
0b0d3320 | 831 | tcg_ctx.code_gen_ptr = tcg_ctx.code_gen_buffer; |
5b6dd868 BS |
832 | /* XXX: flush processor icache at this point if cache flush is |
833 | expensive */ | |
5e5f07e0 | 834 | tcg_ctx.tb_ctx.tb_flush_count++; |
5b6dd868 BS |
835 | } |
836 | ||
837 | #ifdef DEBUG_TB_CHECK | |
838 | ||
839 | static void tb_invalidate_check(target_ulong address) | |
840 | { | |
841 | TranslationBlock *tb; | |
842 | int i; | |
843 | ||
844 | address &= TARGET_PAGE_MASK; | |
845 | for (i = 0; i < CODE_GEN_PHYS_HASH_SIZE; i++) { | |
5e5f07e0 | 846 | for (tb = tb_ctx.tb_phys_hash[i]; tb != NULL; tb = tb->phys_hash_next) { |
5b6dd868 BS |
847 | if (!(address + TARGET_PAGE_SIZE <= tb->pc || |
848 | address >= tb->pc + tb->size)) { | |
849 | printf("ERROR invalidate: address=" TARGET_FMT_lx | |
850 | " PC=%08lx size=%04x\n", | |
851 | address, (long)tb->pc, tb->size); | |
852 | } | |
853 | } | |
854 | } | |
855 | } | |
856 | ||
857 | /* verify that all the pages have correct rights for code */ | |
858 | static void tb_page_check(void) | |
859 | { | |
860 | TranslationBlock *tb; | |
861 | int i, flags1, flags2; | |
862 | ||
863 | for (i = 0; i < CODE_GEN_PHYS_HASH_SIZE; i++) { | |
5e5f07e0 EV |
864 | for (tb = tcg_ctx.tb_ctx.tb_phys_hash[i]; tb != NULL; |
865 | tb = tb->phys_hash_next) { | |
5b6dd868 BS |
866 | flags1 = page_get_flags(tb->pc); |
867 | flags2 = page_get_flags(tb->pc + tb->size - 1); | |
868 | if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { | |
869 | printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", | |
870 | (long)tb->pc, tb->size, flags1, flags2); | |
871 | } | |
872 | } | |
873 | } | |
874 | } | |
875 | ||
876 | #endif | |
877 | ||
0c884d16 | 878 | static inline void tb_hash_remove(TranslationBlock **ptb, TranslationBlock *tb) |
5b6dd868 BS |
879 | { |
880 | TranslationBlock *tb1; | |
881 | ||
882 | for (;;) { | |
883 | tb1 = *ptb; | |
884 | if (tb1 == tb) { | |
0c884d16 | 885 | *ptb = tb1->phys_hash_next; |
5b6dd868 BS |
886 | break; |
887 | } | |
0c884d16 | 888 | ptb = &tb1->phys_hash_next; |
5b6dd868 BS |
889 | } |
890 | } | |
891 | ||
892 | static inline void tb_page_remove(TranslationBlock **ptb, TranslationBlock *tb) | |
893 | { | |
894 | TranslationBlock *tb1; | |
895 | unsigned int n1; | |
896 | ||
897 | for (;;) { | |
898 | tb1 = *ptb; | |
899 | n1 = (uintptr_t)tb1 & 3; | |
900 | tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3); | |
901 | if (tb1 == tb) { | |
902 | *ptb = tb1->page_next[n1]; | |
903 | break; | |
904 | } | |
905 | ptb = &tb1->page_next[n1]; | |
906 | } | |
907 | } | |
908 | ||
909 | static inline void tb_jmp_remove(TranslationBlock *tb, int n) | |
910 | { | |
911 | TranslationBlock *tb1, **ptb; | |
912 | unsigned int n1; | |
913 | ||
914 | ptb = &tb->jmp_next[n]; | |
915 | tb1 = *ptb; | |
916 | if (tb1) { | |
917 | /* find tb(n) in circular list */ | |
918 | for (;;) { | |
919 | tb1 = *ptb; | |
920 | n1 = (uintptr_t)tb1 & 3; | |
921 | tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3); | |
922 | if (n1 == n && tb1 == tb) { | |
923 | break; | |
924 | } | |
925 | if (n1 == 2) { | |
926 | ptb = &tb1->jmp_first; | |
927 | } else { | |
928 | ptb = &tb1->jmp_next[n1]; | |
929 | } | |
930 | } | |
931 | /* now we can suppress tb(n) from the list */ | |
932 | *ptb = tb->jmp_next[n]; | |
933 | ||
934 | tb->jmp_next[n] = NULL; | |
935 | } | |
936 | } | |
937 | ||
938 | /* reset the jump entry 'n' of a TB so that it is not chained to | |
939 | another TB */ | |
940 | static inline void tb_reset_jump(TranslationBlock *tb, int n) | |
941 | { | |
942 | tb_set_jmp_target(tb, n, (uintptr_t)(tb->tc_ptr + tb->tb_next_offset[n])); | |
943 | } | |
944 | ||
0c884d16 | 945 | /* invalidate one TB */ |
5b6dd868 BS |
946 | void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr) |
947 | { | |
182735ef | 948 | CPUState *cpu; |
5b6dd868 BS |
949 | PageDesc *p; |
950 | unsigned int h, n1; | |
951 | tb_page_addr_t phys_pc; | |
952 | TranslationBlock *tb1, *tb2; | |
953 | ||
954 | /* remove the TB from the hash list */ | |
955 | phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
956 | h = tb_phys_hash_func(phys_pc); | |
5e5f07e0 | 957 | tb_hash_remove(&tcg_ctx.tb_ctx.tb_phys_hash[h], tb); |
5b6dd868 BS |
958 | |
959 | /* remove the TB from the page list */ | |
960 | if (tb->page_addr[0] != page_addr) { | |
961 | p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS); | |
962 | tb_page_remove(&p->first_tb, tb); | |
963 | invalidate_page_bitmap(p); | |
964 | } | |
965 | if (tb->page_addr[1] != -1 && tb->page_addr[1] != page_addr) { | |
966 | p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS); | |
967 | tb_page_remove(&p->first_tb, tb); | |
968 | invalidate_page_bitmap(p); | |
969 | } | |
970 | ||
5e5f07e0 | 971 | tcg_ctx.tb_ctx.tb_invalidated_flag = 1; |
5b6dd868 BS |
972 | |
973 | /* remove the TB from the hash list */ | |
974 | h = tb_jmp_cache_hash_func(tb->pc); | |
bdc44640 | 975 | CPU_FOREACH(cpu) { |
8cd70437 AF |
976 | if (cpu->tb_jmp_cache[h] == tb) { |
977 | cpu->tb_jmp_cache[h] = NULL; | |
5b6dd868 BS |
978 | } |
979 | } | |
980 | ||
981 | /* suppress this TB from the two jump lists */ | |
982 | tb_jmp_remove(tb, 0); | |
983 | tb_jmp_remove(tb, 1); | |
984 | ||
985 | /* suppress any remaining jumps to this TB */ | |
986 | tb1 = tb->jmp_first; | |
987 | for (;;) { | |
988 | n1 = (uintptr_t)tb1 & 3; | |
989 | if (n1 == 2) { | |
990 | break; | |
991 | } | |
992 | tb1 = (TranslationBlock *)((uintptr_t)tb1 & ~3); | |
993 | tb2 = tb1->jmp_next[n1]; | |
994 | tb_reset_jump(tb1, n1); | |
995 | tb1->jmp_next[n1] = NULL; | |
996 | tb1 = tb2; | |
997 | } | |
998 | tb->jmp_first = (TranslationBlock *)((uintptr_t)tb | 2); /* fail safe */ | |
999 | ||
5e5f07e0 | 1000 | tcg_ctx.tb_ctx.tb_phys_invalidate_count++; |
5b6dd868 BS |
1001 | } |
1002 | ||
5b6dd868 BS |
1003 | static void build_page_bitmap(PageDesc *p) |
1004 | { | |
1005 | int n, tb_start, tb_end; | |
1006 | TranslationBlock *tb; | |
1007 | ||
510a647f | 1008 | p->code_bitmap = bitmap_new(TARGET_PAGE_SIZE); |
5b6dd868 BS |
1009 | |
1010 | tb = p->first_tb; | |
1011 | while (tb != NULL) { | |
1012 | n = (uintptr_t)tb & 3; | |
1013 | tb = (TranslationBlock *)((uintptr_t)tb & ~3); | |
1014 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
1015 | if (n == 0) { | |
1016 | /* NOTE: tb_end may be after the end of the page, but | |
1017 | it is not a problem */ | |
1018 | tb_start = tb->pc & ~TARGET_PAGE_MASK; | |
1019 | tb_end = tb_start + tb->size; | |
1020 | if (tb_end > TARGET_PAGE_SIZE) { | |
1021 | tb_end = TARGET_PAGE_SIZE; | |
1022 | } | |
1023 | } else { | |
1024 | tb_start = 0; | |
1025 | tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
1026 | } | |
510a647f | 1027 | bitmap_set(p->code_bitmap, tb_start, tb_end - tb_start); |
5b6dd868 BS |
1028 | tb = tb->page_next[n]; |
1029 | } | |
1030 | } | |
1031 | ||
75692087 | 1032 | /* Called with mmap_lock held for user mode emulation. */ |
648f034c | 1033 | TranslationBlock *tb_gen_code(CPUState *cpu, |
5b6dd868 BS |
1034 | target_ulong pc, target_ulong cs_base, |
1035 | int flags, int cflags) | |
1036 | { | |
648f034c | 1037 | CPUArchState *env = cpu->env_ptr; |
5b6dd868 | 1038 | TranslationBlock *tb; |
5b6dd868 BS |
1039 | tb_page_addr_t phys_pc, phys_page2; |
1040 | target_ulong virt_page2; | |
1041 | int code_gen_size; | |
1042 | ||
1043 | phys_pc = get_page_addr_code(env, pc); | |
0266359e PB |
1044 | if (use_icount) { |
1045 | cflags |= CF_USE_ICOUNT; | |
1046 | } | |
5b6dd868 BS |
1047 | tb = tb_alloc(pc); |
1048 | if (!tb) { | |
1049 | /* flush must be done */ | |
bbd77c18 | 1050 | tb_flush(cpu); |
5b6dd868 BS |
1051 | /* cannot fail at this point */ |
1052 | tb = tb_alloc(pc); | |
1053 | /* Don't forget to invalidate previous TB info. */ | |
5e5f07e0 | 1054 | tcg_ctx.tb_ctx.tb_invalidated_flag = 1; |
5b6dd868 | 1055 | } |
1813e175 | 1056 | tb->tc_ptr = tcg_ctx.code_gen_ptr; |
5b6dd868 BS |
1057 | tb->cs_base = cs_base; |
1058 | tb->flags = flags; | |
1059 | tb->cflags = cflags; | |
1060 | cpu_gen_code(env, tb, &code_gen_size); | |
0b0d3320 EV |
1061 | tcg_ctx.code_gen_ptr = (void *)(((uintptr_t)tcg_ctx.code_gen_ptr + |
1062 | code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); | |
5b6dd868 BS |
1063 | |
1064 | /* check next page if needed */ | |
1065 | virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; | |
1066 | phys_page2 = -1; | |
1067 | if ((pc & TARGET_PAGE_MASK) != virt_page2) { | |
1068 | phys_page2 = get_page_addr_code(env, virt_page2); | |
1069 | } | |
1070 | tb_link_page(tb, phys_pc, phys_page2); | |
1071 | return tb; | |
1072 | } | |
1073 | ||
1074 | /* | |
1075 | * Invalidate all TBs which intersect with the target physical address range | |
1076 | * [start;end[. NOTE: start and end may refer to *different* physical pages. | |
1077 | * 'is_cpu_write_access' should be true if called from a real cpu write | |
1078 | * access: the virtual CPU will exit the current TB if code is modified inside | |
1079 | * this TB. | |
75692087 PB |
1080 | * |
1081 | * Called with mmap_lock held for user-mode emulation | |
5b6dd868 | 1082 | */ |
35865339 | 1083 | void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end) |
5b6dd868 BS |
1084 | { |
1085 | while (start < end) { | |
35865339 | 1086 | tb_invalidate_phys_page_range(start, end, 0); |
5b6dd868 BS |
1087 | start &= TARGET_PAGE_MASK; |
1088 | start += TARGET_PAGE_SIZE; | |
1089 | } | |
1090 | } | |
1091 | ||
1092 | /* | |
1093 | * Invalidate all TBs which intersect with the target physical address range | |
1094 | * [start;end[. NOTE: start and end must refer to the *same* physical page. | |
1095 | * 'is_cpu_write_access' should be true if called from a real cpu write | |
1096 | * access: the virtual CPU will exit the current TB if code is modified inside | |
1097 | * this TB. | |
75692087 PB |
1098 | * |
1099 | * Called with mmap_lock held for user-mode emulation | |
5b6dd868 BS |
1100 | */ |
1101 | void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end, | |
1102 | int is_cpu_write_access) | |
1103 | { | |
1104 | TranslationBlock *tb, *tb_next, *saved_tb; | |
4917cf44 | 1105 | CPUState *cpu = current_cpu; |
baea4fae | 1106 | #if defined(TARGET_HAS_PRECISE_SMC) |
4917cf44 AF |
1107 | CPUArchState *env = NULL; |
1108 | #endif | |
5b6dd868 BS |
1109 | tb_page_addr_t tb_start, tb_end; |
1110 | PageDesc *p; | |
1111 | int n; | |
1112 | #ifdef TARGET_HAS_PRECISE_SMC | |
1113 | int current_tb_not_found = is_cpu_write_access; | |
1114 | TranslationBlock *current_tb = NULL; | |
1115 | int current_tb_modified = 0; | |
1116 | target_ulong current_pc = 0; | |
1117 | target_ulong current_cs_base = 0; | |
1118 | int current_flags = 0; | |
1119 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
1120 | ||
1121 | p = page_find(start >> TARGET_PAGE_BITS); | |
1122 | if (!p) { | |
1123 | return; | |
1124 | } | |
baea4fae | 1125 | #if defined(TARGET_HAS_PRECISE_SMC) |
4917cf44 AF |
1126 | if (cpu != NULL) { |
1127 | env = cpu->env_ptr; | |
d77953b9 | 1128 | } |
4917cf44 | 1129 | #endif |
5b6dd868 BS |
1130 | |
1131 | /* we remove all the TBs in the range [start, end[ */ | |
1132 | /* XXX: see if in some cases it could be faster to invalidate all | |
1133 | the code */ | |
1134 | tb = p->first_tb; | |
1135 | while (tb != NULL) { | |
1136 | n = (uintptr_t)tb & 3; | |
1137 | tb = (TranslationBlock *)((uintptr_t)tb & ~3); | |
1138 | tb_next = tb->page_next[n]; | |
1139 | /* NOTE: this is subtle as a TB may span two physical pages */ | |
1140 | if (n == 0) { | |
1141 | /* NOTE: tb_end may be after the end of the page, but | |
1142 | it is not a problem */ | |
1143 | tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); | |
1144 | tb_end = tb_start + tb->size; | |
1145 | } else { | |
1146 | tb_start = tb->page_addr[1]; | |
1147 | tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); | |
1148 | } | |
1149 | if (!(tb_end <= start || tb_start >= end)) { | |
1150 | #ifdef TARGET_HAS_PRECISE_SMC | |
1151 | if (current_tb_not_found) { | |
1152 | current_tb_not_found = 0; | |
1153 | current_tb = NULL; | |
93afeade | 1154 | if (cpu->mem_io_pc) { |
5b6dd868 | 1155 | /* now we have a real cpu fault */ |
93afeade | 1156 | current_tb = tb_find_pc(cpu->mem_io_pc); |
5b6dd868 BS |
1157 | } |
1158 | } | |
1159 | if (current_tb == tb && | |
1160 | (current_tb->cflags & CF_COUNT_MASK) != 1) { | |
1161 | /* If we are modifying the current TB, we must stop | |
1162 | its execution. We could be more precise by checking | |
1163 | that the modification is after the current PC, but it | |
1164 | would require a specialized function to partially | |
1165 | restore the CPU state */ | |
1166 | ||
1167 | current_tb_modified = 1; | |
74f10515 | 1168 | cpu_restore_state_from_tb(cpu, current_tb, cpu->mem_io_pc); |
5b6dd868 BS |
1169 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1170 | ¤t_flags); | |
1171 | } | |
1172 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
1173 | /* we need to do that to handle the case where a signal | |
1174 | occurs while doing tb_phys_invalidate() */ | |
1175 | saved_tb = NULL; | |
d77953b9 AF |
1176 | if (cpu != NULL) { |
1177 | saved_tb = cpu->current_tb; | |
1178 | cpu->current_tb = NULL; | |
5b6dd868 BS |
1179 | } |
1180 | tb_phys_invalidate(tb, -1); | |
d77953b9 AF |
1181 | if (cpu != NULL) { |
1182 | cpu->current_tb = saved_tb; | |
c3affe56 AF |
1183 | if (cpu->interrupt_request && cpu->current_tb) { |
1184 | cpu_interrupt(cpu, cpu->interrupt_request); | |
5b6dd868 BS |
1185 | } |
1186 | } | |
1187 | } | |
1188 | tb = tb_next; | |
1189 | } | |
1190 | #if !defined(CONFIG_USER_ONLY) | |
1191 | /* if no code remaining, no need to continue to use slow writes */ | |
1192 | if (!p->first_tb) { | |
1193 | invalidate_page_bitmap(p); | |
fc377bcf | 1194 | tlb_unprotect_code(start); |
5b6dd868 BS |
1195 | } |
1196 | #endif | |
1197 | #ifdef TARGET_HAS_PRECISE_SMC | |
1198 | if (current_tb_modified) { | |
1199 | /* we generate a block containing just the instruction | |
1200 | modifying the memory. It will ensure that it cannot modify | |
1201 | itself */ | |
d77953b9 | 1202 | cpu->current_tb = NULL; |
648f034c | 1203 | tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); |
0ea8cb88 | 1204 | cpu_resume_from_signal(cpu, NULL); |
5b6dd868 BS |
1205 | } |
1206 | #endif | |
1207 | } | |
1208 | ||
1209 | /* len must be <= 8 and start must be a multiple of len */ | |
1210 | void tb_invalidate_phys_page_fast(tb_page_addr_t start, int len) | |
1211 | { | |
1212 | PageDesc *p; | |
5b6dd868 BS |
1213 | |
1214 | #if 0 | |
1215 | if (1) { | |
1216 | qemu_log("modifying code at 0x%x size=%d EIP=%x PC=%08x\n", | |
1217 | cpu_single_env->mem_io_vaddr, len, | |
1218 | cpu_single_env->eip, | |
1219 | cpu_single_env->eip + | |
1220 | (intptr_t)cpu_single_env->segs[R_CS].base); | |
1221 | } | |
1222 | #endif | |
1223 | p = page_find(start >> TARGET_PAGE_BITS); | |
1224 | if (!p) { | |
1225 | return; | |
1226 | } | |
fc377bcf PB |
1227 | if (!p->code_bitmap && |
1228 | ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD) { | |
1229 | /* build code bitmap */ | |
1230 | build_page_bitmap(p); | |
1231 | } | |
5b6dd868 | 1232 | if (p->code_bitmap) { |
510a647f EC |
1233 | unsigned int nr; |
1234 | unsigned long b; | |
1235 | ||
1236 | nr = start & ~TARGET_PAGE_MASK; | |
1237 | b = p->code_bitmap[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG - 1)); | |
5b6dd868 BS |
1238 | if (b & ((1 << len) - 1)) { |
1239 | goto do_invalidate; | |
1240 | } | |
1241 | } else { | |
1242 | do_invalidate: | |
1243 | tb_invalidate_phys_page_range(start, start + len, 1); | |
1244 | } | |
1245 | } | |
1246 | ||
1247 | #if !defined(CONFIG_SOFTMMU) | |
75692087 | 1248 | /* Called with mmap_lock held. */ |
5b6dd868 | 1249 | static void tb_invalidate_phys_page(tb_page_addr_t addr, |
d02532f0 AG |
1250 | uintptr_t pc, void *puc, |
1251 | bool locked) | |
5b6dd868 BS |
1252 | { |
1253 | TranslationBlock *tb; | |
1254 | PageDesc *p; | |
1255 | int n; | |
1256 | #ifdef TARGET_HAS_PRECISE_SMC | |
1257 | TranslationBlock *current_tb = NULL; | |
4917cf44 AF |
1258 | CPUState *cpu = current_cpu; |
1259 | CPUArchState *env = NULL; | |
5b6dd868 BS |
1260 | int current_tb_modified = 0; |
1261 | target_ulong current_pc = 0; | |
1262 | target_ulong current_cs_base = 0; | |
1263 | int current_flags = 0; | |
1264 | #endif | |
1265 | ||
1266 | addr &= TARGET_PAGE_MASK; | |
1267 | p = page_find(addr >> TARGET_PAGE_BITS); | |
1268 | if (!p) { | |
1269 | return; | |
1270 | } | |
1271 | tb = p->first_tb; | |
1272 | #ifdef TARGET_HAS_PRECISE_SMC | |
1273 | if (tb && pc != 0) { | |
1274 | current_tb = tb_find_pc(pc); | |
1275 | } | |
4917cf44 AF |
1276 | if (cpu != NULL) { |
1277 | env = cpu->env_ptr; | |
d77953b9 | 1278 | } |
5b6dd868 BS |
1279 | #endif |
1280 | while (tb != NULL) { | |
1281 | n = (uintptr_t)tb & 3; | |
1282 | tb = (TranslationBlock *)((uintptr_t)tb & ~3); | |
1283 | #ifdef TARGET_HAS_PRECISE_SMC | |
1284 | if (current_tb == tb && | |
1285 | (current_tb->cflags & CF_COUNT_MASK) != 1) { | |
1286 | /* If we are modifying the current TB, we must stop | |
1287 | its execution. We could be more precise by checking | |
1288 | that the modification is after the current PC, but it | |
1289 | would require a specialized function to partially | |
1290 | restore the CPU state */ | |
1291 | ||
1292 | current_tb_modified = 1; | |
74f10515 | 1293 | cpu_restore_state_from_tb(cpu, current_tb, pc); |
5b6dd868 BS |
1294 | cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base, |
1295 | ¤t_flags); | |
1296 | } | |
1297 | #endif /* TARGET_HAS_PRECISE_SMC */ | |
1298 | tb_phys_invalidate(tb, addr); | |
1299 | tb = tb->page_next[n]; | |
1300 | } | |
1301 | p->first_tb = NULL; | |
1302 | #ifdef TARGET_HAS_PRECISE_SMC | |
1303 | if (current_tb_modified) { | |
1304 | /* we generate a block containing just the instruction | |
1305 | modifying the memory. It will ensure that it cannot modify | |
1306 | itself */ | |
d77953b9 | 1307 | cpu->current_tb = NULL; |
648f034c | 1308 | tb_gen_code(cpu, current_pc, current_cs_base, current_flags, 1); |
d02532f0 AG |
1309 | if (locked) { |
1310 | mmap_unlock(); | |
1311 | } | |
0ea8cb88 | 1312 | cpu_resume_from_signal(cpu, puc); |
5b6dd868 BS |
1313 | } |
1314 | #endif | |
1315 | } | |
1316 | #endif | |
1317 | ||
75692087 PB |
1318 | /* add the tb in the target page and protect it if necessary |
1319 | * | |
1320 | * Called with mmap_lock held for user-mode emulation. | |
1321 | */ | |
5b6dd868 BS |
1322 | static inline void tb_alloc_page(TranslationBlock *tb, |
1323 | unsigned int n, tb_page_addr_t page_addr) | |
1324 | { | |
1325 | PageDesc *p; | |
1326 | #ifndef CONFIG_USER_ONLY | |
1327 | bool page_already_protected; | |
1328 | #endif | |
1329 | ||
1330 | tb->page_addr[n] = page_addr; | |
1331 | p = page_find_alloc(page_addr >> TARGET_PAGE_BITS, 1); | |
1332 | tb->page_next[n] = p->first_tb; | |
1333 | #ifndef CONFIG_USER_ONLY | |
1334 | page_already_protected = p->first_tb != NULL; | |
1335 | #endif | |
1336 | p->first_tb = (TranslationBlock *)((uintptr_t)tb | n); | |
1337 | invalidate_page_bitmap(p); | |
1338 | ||
5b6dd868 BS |
1339 | #if defined(CONFIG_USER_ONLY) |
1340 | if (p->flags & PAGE_WRITE) { | |
1341 | target_ulong addr; | |
1342 | PageDesc *p2; | |
1343 | int prot; | |
1344 | ||
1345 | /* force the host page as non writable (writes will have a | |
1346 | page fault + mprotect overhead) */ | |
1347 | page_addr &= qemu_host_page_mask; | |
1348 | prot = 0; | |
1349 | for (addr = page_addr; addr < page_addr + qemu_host_page_size; | |
1350 | addr += TARGET_PAGE_SIZE) { | |
1351 | ||
1352 | p2 = page_find(addr >> TARGET_PAGE_BITS); | |
1353 | if (!p2) { | |
1354 | continue; | |
1355 | } | |
1356 | prot |= p2->flags; | |
1357 | p2->flags &= ~PAGE_WRITE; | |
1358 | } | |
1359 | mprotect(g2h(page_addr), qemu_host_page_size, | |
1360 | (prot & PAGE_BITS) & ~PAGE_WRITE); | |
1361 | #ifdef DEBUG_TB_INVALIDATE | |
1362 | printf("protecting code page: 0x" TARGET_FMT_lx "\n", | |
1363 | page_addr); | |
1364 | #endif | |
1365 | } | |
1366 | #else | |
1367 | /* if some code is already present, then the pages are already | |
1368 | protected. So we handle the case where only the first TB is | |
1369 | allocated in a physical page */ | |
1370 | if (!page_already_protected) { | |
1371 | tlb_protect_code(page_addr); | |
1372 | } | |
1373 | #endif | |
5b6dd868 BS |
1374 | } |
1375 | ||
1376 | /* add a new TB and link it to the physical page tables. phys_page2 is | |
75692087 PB |
1377 | * (-1) to indicate that only one page contains the TB. |
1378 | */ | |
5b6dd868 BS |
1379 | static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, |
1380 | tb_page_addr_t phys_page2) | |
1381 | { | |
1382 | unsigned int h; | |
1383 | TranslationBlock **ptb; | |
1384 | ||
1385 | /* Grab the mmap lock to stop another thread invalidating this TB | |
1386 | before we are done. */ | |
1387 | mmap_lock(); | |
1388 | /* add in the physical hash table */ | |
1389 | h = tb_phys_hash_func(phys_pc); | |
5e5f07e0 | 1390 | ptb = &tcg_ctx.tb_ctx.tb_phys_hash[h]; |
5b6dd868 BS |
1391 | tb->phys_hash_next = *ptb; |
1392 | *ptb = tb; | |
1393 | ||
1394 | /* add in the page list */ | |
1395 | tb_alloc_page(tb, 0, phys_pc & TARGET_PAGE_MASK); | |
1396 | if (phys_page2 != -1) { | |
1397 | tb_alloc_page(tb, 1, phys_page2); | |
1398 | } else { | |
1399 | tb->page_addr[1] = -1; | |
1400 | } | |
1401 | ||
1402 | tb->jmp_first = (TranslationBlock *)((uintptr_t)tb | 2); | |
1403 | tb->jmp_next[0] = NULL; | |
1404 | tb->jmp_next[1] = NULL; | |
1405 | ||
1406 | /* init original jump addresses */ | |
1407 | if (tb->tb_next_offset[0] != 0xffff) { | |
1408 | tb_reset_jump(tb, 0); | |
1409 | } | |
1410 | if (tb->tb_next_offset[1] != 0xffff) { | |
1411 | tb_reset_jump(tb, 1); | |
1412 | } | |
1413 | ||
1414 | #ifdef DEBUG_TB_CHECK | |
1415 | tb_page_check(); | |
1416 | #endif | |
1417 | mmap_unlock(); | |
1418 | } | |
1419 | ||
5b6dd868 BS |
1420 | /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < |
1421 | tb[1].tc_ptr. Return NULL if not found */ | |
a8a826a3 | 1422 | static TranslationBlock *tb_find_pc(uintptr_t tc_ptr) |
5b6dd868 BS |
1423 | { |
1424 | int m_min, m_max, m; | |
1425 | uintptr_t v; | |
1426 | TranslationBlock *tb; | |
1427 | ||
5e5f07e0 | 1428 | if (tcg_ctx.tb_ctx.nb_tbs <= 0) { |
5b6dd868 BS |
1429 | return NULL; |
1430 | } | |
0b0d3320 EV |
1431 | if (tc_ptr < (uintptr_t)tcg_ctx.code_gen_buffer || |
1432 | tc_ptr >= (uintptr_t)tcg_ctx.code_gen_ptr) { | |
5b6dd868 BS |
1433 | return NULL; |
1434 | } | |
1435 | /* binary search (cf Knuth) */ | |
1436 | m_min = 0; | |
5e5f07e0 | 1437 | m_max = tcg_ctx.tb_ctx.nb_tbs - 1; |
5b6dd868 BS |
1438 | while (m_min <= m_max) { |
1439 | m = (m_min + m_max) >> 1; | |
5e5f07e0 | 1440 | tb = &tcg_ctx.tb_ctx.tbs[m]; |
5b6dd868 BS |
1441 | v = (uintptr_t)tb->tc_ptr; |
1442 | if (v == tc_ptr) { | |
1443 | return tb; | |
1444 | } else if (tc_ptr < v) { | |
1445 | m_max = m - 1; | |
1446 | } else { | |
1447 | m_min = m + 1; | |
1448 | } | |
1449 | } | |
5e5f07e0 | 1450 | return &tcg_ctx.tb_ctx.tbs[m_max]; |
5b6dd868 BS |
1451 | } |
1452 | ||
ec53b45b | 1453 | #if !defined(CONFIG_USER_ONLY) |
29d8ec7b | 1454 | void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr) |
5b6dd868 BS |
1455 | { |
1456 | ram_addr_t ram_addr; | |
5c8a00ce | 1457 | MemoryRegion *mr; |
149f54b5 | 1458 | hwaddr l = 1; |
5b6dd868 | 1459 | |
41063e1e | 1460 | rcu_read_lock(); |
29d8ec7b | 1461 | mr = address_space_translate(as, addr, &addr, &l, false); |
5c8a00ce PB |
1462 | if (!(memory_region_is_ram(mr) |
1463 | || memory_region_is_romd(mr))) { | |
41063e1e | 1464 | rcu_read_unlock(); |
5b6dd868 BS |
1465 | return; |
1466 | } | |
5c8a00ce | 1467 | ram_addr = (memory_region_get_ram_addr(mr) & TARGET_PAGE_MASK) |
149f54b5 | 1468 | + addr; |
5b6dd868 | 1469 | tb_invalidate_phys_page_range(ram_addr, ram_addr + 1, 0); |
41063e1e | 1470 | rcu_read_unlock(); |
5b6dd868 | 1471 | } |
ec53b45b | 1472 | #endif /* !defined(CONFIG_USER_ONLY) */ |
5b6dd868 | 1473 | |
239c51a5 | 1474 | void tb_check_watchpoint(CPUState *cpu) |
5b6dd868 BS |
1475 | { |
1476 | TranslationBlock *tb; | |
1477 | ||
93afeade | 1478 | tb = tb_find_pc(cpu->mem_io_pc); |
8d302e76 AJ |
1479 | if (tb) { |
1480 | /* We can use retranslation to find the PC. */ | |
1481 | cpu_restore_state_from_tb(cpu, tb, cpu->mem_io_pc); | |
1482 | tb_phys_invalidate(tb, -1); | |
1483 | } else { | |
1484 | /* The exception probably happened in a helper. The CPU state should | |
1485 | have been saved before calling it. Fetch the PC from there. */ | |
1486 | CPUArchState *env = cpu->env_ptr; | |
1487 | target_ulong pc, cs_base; | |
1488 | tb_page_addr_t addr; | |
1489 | int flags; | |
1490 | ||
1491 | cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags); | |
1492 | addr = get_page_addr_code(env, pc); | |
1493 | tb_invalidate_phys_range(addr, addr + 1); | |
5b6dd868 | 1494 | } |
5b6dd868 BS |
1495 | } |
1496 | ||
1497 | #ifndef CONFIG_USER_ONLY | |
1498 | /* mask must never be zero, except for A20 change call */ | |
c3affe56 | 1499 | static void tcg_handle_interrupt(CPUState *cpu, int mask) |
5b6dd868 | 1500 | { |
5b6dd868 BS |
1501 | int old_mask; |
1502 | ||
259186a7 AF |
1503 | old_mask = cpu->interrupt_request; |
1504 | cpu->interrupt_request |= mask; | |
5b6dd868 BS |
1505 | |
1506 | /* | |
1507 | * If called from iothread context, wake the target cpu in | |
1508 | * case its halted. | |
1509 | */ | |
1510 | if (!qemu_cpu_is_self(cpu)) { | |
1511 | qemu_cpu_kick(cpu); | |
1512 | return; | |
1513 | } | |
1514 | ||
1515 | if (use_icount) { | |
28ecfd7a | 1516 | cpu->icount_decr.u16.high = 0xffff; |
414b15c9 | 1517 | if (!cpu->can_do_io |
5b6dd868 | 1518 | && (mask & ~old_mask) != 0) { |
a47dddd7 | 1519 | cpu_abort(cpu, "Raised interrupt while not in I/O function"); |
5b6dd868 BS |
1520 | } |
1521 | } else { | |
378df4b2 | 1522 | cpu->tcg_exit_req = 1; |
5b6dd868 BS |
1523 | } |
1524 | } | |
1525 | ||
1526 | CPUInterruptHandler cpu_interrupt_handler = tcg_handle_interrupt; | |
1527 | ||
1528 | /* in deterministic execution mode, instructions doing device I/Os | |
1529 | must be at the end of the TB */ | |
90b40a69 | 1530 | void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) |
5b6dd868 | 1531 | { |
a47dddd7 | 1532 | #if defined(TARGET_MIPS) || defined(TARGET_SH4) |
90b40a69 | 1533 | CPUArchState *env = cpu->env_ptr; |
a47dddd7 | 1534 | #endif |
5b6dd868 BS |
1535 | TranslationBlock *tb; |
1536 | uint32_t n, cflags; | |
1537 | target_ulong pc, cs_base; | |
1538 | uint64_t flags; | |
1539 | ||
1540 | tb = tb_find_pc(retaddr); | |
1541 | if (!tb) { | |
a47dddd7 | 1542 | cpu_abort(cpu, "cpu_io_recompile: could not find TB for pc=%p", |
5b6dd868 BS |
1543 | (void *)retaddr); |
1544 | } | |
28ecfd7a | 1545 | n = cpu->icount_decr.u16.low + tb->icount; |
74f10515 | 1546 | cpu_restore_state_from_tb(cpu, tb, retaddr); |
5b6dd868 BS |
1547 | /* Calculate how many instructions had been executed before the fault |
1548 | occurred. */ | |
28ecfd7a | 1549 | n = n - cpu->icount_decr.u16.low; |
5b6dd868 BS |
1550 | /* Generate a new TB ending on the I/O insn. */ |
1551 | n++; | |
1552 | /* On MIPS and SH, delay slot instructions can only be restarted if | |
1553 | they were already the first instruction in the TB. If this is not | |
1554 | the first instruction in a TB then re-execute the preceding | |
1555 | branch. */ | |
1556 | #if defined(TARGET_MIPS) | |
1557 | if ((env->hflags & MIPS_HFLAG_BMASK) != 0 && n > 1) { | |
c3577479 | 1558 | env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); |
28ecfd7a | 1559 | cpu->icount_decr.u16.low++; |
5b6dd868 BS |
1560 | env->hflags &= ~MIPS_HFLAG_BMASK; |
1561 | } | |
1562 | #elif defined(TARGET_SH4) | |
1563 | if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 | |
1564 | && n > 1) { | |
1565 | env->pc -= 2; | |
28ecfd7a | 1566 | cpu->icount_decr.u16.low++; |
5b6dd868 BS |
1567 | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
1568 | } | |
1569 | #endif | |
1570 | /* This should never happen. */ | |
1571 | if (n > CF_COUNT_MASK) { | |
a47dddd7 | 1572 | cpu_abort(cpu, "TB too big during recompile"); |
5b6dd868 BS |
1573 | } |
1574 | ||
1575 | cflags = n | CF_LAST_IO; | |
1576 | pc = tb->pc; | |
1577 | cs_base = tb->cs_base; | |
1578 | flags = tb->flags; | |
1579 | tb_phys_invalidate(tb, -1); | |
02d57ea1 SF |
1580 | if (tb->cflags & CF_NOCACHE) { |
1581 | if (tb->orig_tb) { | |
1582 | /* Invalidate original TB if this TB was generated in | |
1583 | * cpu_exec_nocache() */ | |
1584 | tb_phys_invalidate(tb->orig_tb, -1); | |
1585 | } | |
1586 | tb_free(tb); | |
1587 | } | |
5b6dd868 BS |
1588 | /* FIXME: In theory this could raise an exception. In practice |
1589 | we have already translated the block once so it's probably ok. */ | |
648f034c | 1590 | tb_gen_code(cpu, pc, cs_base, flags, cflags); |
5b6dd868 BS |
1591 | /* TODO: If env->pc != tb->pc (i.e. the faulting instruction was not |
1592 | the first in the TB) then we end up generating a whole new TB and | |
1593 | repeating the fault, which is horribly inefficient. | |
1594 | Better would be to execute just this insn uncached, or generate a | |
1595 | second new TB. */ | |
0ea8cb88 | 1596 | cpu_resume_from_signal(cpu, NULL); |
5b6dd868 BS |
1597 | } |
1598 | ||
611d4f99 | 1599 | void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr) |
5b6dd868 BS |
1600 | { |
1601 | unsigned int i; | |
1602 | ||
1603 | /* Discard jump cache entries for any tb which might potentially | |
1604 | overlap the flushed page. */ | |
1605 | i = tb_jmp_cache_hash_page(addr - TARGET_PAGE_SIZE); | |
8cd70437 | 1606 | memset(&cpu->tb_jmp_cache[i], 0, |
5b6dd868 BS |
1607 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
1608 | ||
1609 | i = tb_jmp_cache_hash_page(addr); | |
8cd70437 | 1610 | memset(&cpu->tb_jmp_cache[i], 0, |
5b6dd868 BS |
1611 | TB_JMP_PAGE_SIZE * sizeof(TranslationBlock *)); |
1612 | } | |
1613 | ||
1614 | void dump_exec_info(FILE *f, fprintf_function cpu_fprintf) | |
1615 | { | |
1616 | int i, target_code_size, max_target_code_size; | |
1617 | int direct_jmp_count, direct_jmp2_count, cross_page; | |
1618 | TranslationBlock *tb; | |
1619 | ||
1620 | target_code_size = 0; | |
1621 | max_target_code_size = 0; | |
1622 | cross_page = 0; | |
1623 | direct_jmp_count = 0; | |
1624 | direct_jmp2_count = 0; | |
5e5f07e0 EV |
1625 | for (i = 0; i < tcg_ctx.tb_ctx.nb_tbs; i++) { |
1626 | tb = &tcg_ctx.tb_ctx.tbs[i]; | |
5b6dd868 BS |
1627 | target_code_size += tb->size; |
1628 | if (tb->size > max_target_code_size) { | |
1629 | max_target_code_size = tb->size; | |
1630 | } | |
1631 | if (tb->page_addr[1] != -1) { | |
1632 | cross_page++; | |
1633 | } | |
1634 | if (tb->tb_next_offset[0] != 0xffff) { | |
1635 | direct_jmp_count++; | |
1636 | if (tb->tb_next_offset[1] != 0xffff) { | |
1637 | direct_jmp2_count++; | |
1638 | } | |
1639 | } | |
1640 | } | |
1641 | /* XXX: avoid using doubles ? */ | |
1642 | cpu_fprintf(f, "Translation buffer state:\n"); | |
1643 | cpu_fprintf(f, "gen code size %td/%zd\n", | |
0b0d3320 EV |
1644 | tcg_ctx.code_gen_ptr - tcg_ctx.code_gen_buffer, |
1645 | tcg_ctx.code_gen_buffer_max_size); | |
5b6dd868 | 1646 | cpu_fprintf(f, "TB count %d/%d\n", |
5e5f07e0 | 1647 | tcg_ctx.tb_ctx.nb_tbs, tcg_ctx.code_gen_max_blocks); |
5b6dd868 | 1648 | cpu_fprintf(f, "TB avg target size %d max=%d bytes\n", |
5e5f07e0 EV |
1649 | tcg_ctx.tb_ctx.nb_tbs ? target_code_size / |
1650 | tcg_ctx.tb_ctx.nb_tbs : 0, | |
1651 | max_target_code_size); | |
5b6dd868 | 1652 | cpu_fprintf(f, "TB avg host size %td bytes (expansion ratio: %0.1f)\n", |
5e5f07e0 EV |
1653 | tcg_ctx.tb_ctx.nb_tbs ? (tcg_ctx.code_gen_ptr - |
1654 | tcg_ctx.code_gen_buffer) / | |
1655 | tcg_ctx.tb_ctx.nb_tbs : 0, | |
1656 | target_code_size ? (double) (tcg_ctx.code_gen_ptr - | |
1657 | tcg_ctx.code_gen_buffer) / | |
1658 | target_code_size : 0); | |
1659 | cpu_fprintf(f, "cross page TB count %d (%d%%)\n", cross_page, | |
1660 | tcg_ctx.tb_ctx.nb_tbs ? (cross_page * 100) / | |
1661 | tcg_ctx.tb_ctx.nb_tbs : 0); | |
5b6dd868 BS |
1662 | cpu_fprintf(f, "direct jump count %d (%d%%) (2 jumps=%d %d%%)\n", |
1663 | direct_jmp_count, | |
5e5f07e0 EV |
1664 | tcg_ctx.tb_ctx.nb_tbs ? (direct_jmp_count * 100) / |
1665 | tcg_ctx.tb_ctx.nb_tbs : 0, | |
5b6dd868 | 1666 | direct_jmp2_count, |
5e5f07e0 EV |
1667 | tcg_ctx.tb_ctx.nb_tbs ? (direct_jmp2_count * 100) / |
1668 | tcg_ctx.tb_ctx.nb_tbs : 0); | |
5b6dd868 | 1669 | cpu_fprintf(f, "\nStatistics:\n"); |
5e5f07e0 EV |
1670 | cpu_fprintf(f, "TB flush count %d\n", tcg_ctx.tb_ctx.tb_flush_count); |
1671 | cpu_fprintf(f, "TB invalidate count %d\n", | |
1672 | tcg_ctx.tb_ctx.tb_phys_invalidate_count); | |
5b6dd868 BS |
1673 | cpu_fprintf(f, "TLB flush count %d\n", tlb_flush_count); |
1674 | tcg_dump_info(f, cpu_fprintf); | |
1675 | } | |
1676 | ||
246ae24d MF |
1677 | void dump_opcount_info(FILE *f, fprintf_function cpu_fprintf) |
1678 | { | |
1679 | tcg_dump_op_count(f, cpu_fprintf); | |
1680 | } | |
1681 | ||
5b6dd868 BS |
1682 | #else /* CONFIG_USER_ONLY */ |
1683 | ||
c3affe56 | 1684 | void cpu_interrupt(CPUState *cpu, int mask) |
5b6dd868 | 1685 | { |
259186a7 | 1686 | cpu->interrupt_request |= mask; |
378df4b2 | 1687 | cpu->tcg_exit_req = 1; |
5b6dd868 BS |
1688 | } |
1689 | ||
1690 | /* | |
1691 | * Walks guest process memory "regions" one by one | |
1692 | * and calls callback function 'fn' for each region. | |
1693 | */ | |
1694 | struct walk_memory_regions_data { | |
1695 | walk_memory_regions_fn fn; | |
1696 | void *priv; | |
1a1c4db9 | 1697 | target_ulong start; |
5b6dd868 BS |
1698 | int prot; |
1699 | }; | |
1700 | ||
1701 | static int walk_memory_regions_end(struct walk_memory_regions_data *data, | |
1a1c4db9 | 1702 | target_ulong end, int new_prot) |
5b6dd868 | 1703 | { |
1a1c4db9 | 1704 | if (data->start != -1u) { |
5b6dd868 BS |
1705 | int rc = data->fn(data->priv, data->start, end, data->prot); |
1706 | if (rc != 0) { | |
1707 | return rc; | |
1708 | } | |
1709 | } | |
1710 | ||
1a1c4db9 | 1711 | data->start = (new_prot ? end : -1u); |
5b6dd868 BS |
1712 | data->prot = new_prot; |
1713 | ||
1714 | return 0; | |
1715 | } | |
1716 | ||
1717 | static int walk_memory_regions_1(struct walk_memory_regions_data *data, | |
1a1c4db9 | 1718 | target_ulong base, int level, void **lp) |
5b6dd868 | 1719 | { |
1a1c4db9 | 1720 | target_ulong pa; |
5b6dd868 BS |
1721 | int i, rc; |
1722 | ||
1723 | if (*lp == NULL) { | |
1724 | return walk_memory_regions_end(data, base, 0); | |
1725 | } | |
1726 | ||
1727 | if (level == 0) { | |
1728 | PageDesc *pd = *lp; | |
1729 | ||
03f49957 | 1730 | for (i = 0; i < V_L2_SIZE; ++i) { |
5b6dd868 BS |
1731 | int prot = pd[i].flags; |
1732 | ||
1733 | pa = base | (i << TARGET_PAGE_BITS); | |
1734 | if (prot != data->prot) { | |
1735 | rc = walk_memory_regions_end(data, pa, prot); | |
1736 | if (rc != 0) { | |
1737 | return rc; | |
1738 | } | |
1739 | } | |
1740 | } | |
1741 | } else { | |
1742 | void **pp = *lp; | |
1743 | ||
03f49957 | 1744 | for (i = 0; i < V_L2_SIZE; ++i) { |
1a1c4db9 | 1745 | pa = base | ((target_ulong)i << |
03f49957 | 1746 | (TARGET_PAGE_BITS + V_L2_BITS * level)); |
5b6dd868 BS |
1747 | rc = walk_memory_regions_1(data, pa, level - 1, pp + i); |
1748 | if (rc != 0) { | |
1749 | return rc; | |
1750 | } | |
1751 | } | |
1752 | } | |
1753 | ||
1754 | return 0; | |
1755 | } | |
1756 | ||
1757 | int walk_memory_regions(void *priv, walk_memory_regions_fn fn) | |
1758 | { | |
1759 | struct walk_memory_regions_data data; | |
1760 | uintptr_t i; | |
1761 | ||
1762 | data.fn = fn; | |
1763 | data.priv = priv; | |
1a1c4db9 | 1764 | data.start = -1u; |
5b6dd868 BS |
1765 | data.prot = 0; |
1766 | ||
1767 | for (i = 0; i < V_L1_SIZE; i++) { | |
1a1c4db9 | 1768 | int rc = walk_memory_regions_1(&data, (target_ulong)i << (V_L1_SHIFT + TARGET_PAGE_BITS), |
03f49957 | 1769 | V_L1_SHIFT / V_L2_BITS - 1, l1_map + i); |
5b6dd868 BS |
1770 | if (rc != 0) { |
1771 | return rc; | |
1772 | } | |
1773 | } | |
1774 | ||
1775 | return walk_memory_regions_end(&data, 0, 0); | |
1776 | } | |
1777 | ||
1a1c4db9 MI |
1778 | static int dump_region(void *priv, target_ulong start, |
1779 | target_ulong end, unsigned long prot) | |
5b6dd868 BS |
1780 | { |
1781 | FILE *f = (FILE *)priv; | |
1782 | ||
1a1c4db9 MI |
1783 | (void) fprintf(f, TARGET_FMT_lx"-"TARGET_FMT_lx |
1784 | " "TARGET_FMT_lx" %c%c%c\n", | |
5b6dd868 BS |
1785 | start, end, end - start, |
1786 | ((prot & PAGE_READ) ? 'r' : '-'), | |
1787 | ((prot & PAGE_WRITE) ? 'w' : '-'), | |
1788 | ((prot & PAGE_EXEC) ? 'x' : '-')); | |
1789 | ||
1790 | return 0; | |
1791 | } | |
1792 | ||
1793 | /* dump memory mappings */ | |
1794 | void page_dump(FILE *f) | |
1795 | { | |
1a1c4db9 | 1796 | const int length = sizeof(target_ulong) * 2; |
227b8175 SW |
1797 | (void) fprintf(f, "%-*s %-*s %-*s %s\n", |
1798 | length, "start", length, "end", length, "size", "prot"); | |
5b6dd868 BS |
1799 | walk_memory_regions(f, dump_region); |
1800 | } | |
1801 | ||
1802 | int page_get_flags(target_ulong address) | |
1803 | { | |
1804 | PageDesc *p; | |
1805 | ||
1806 | p = page_find(address >> TARGET_PAGE_BITS); | |
1807 | if (!p) { | |
1808 | return 0; | |
1809 | } | |
1810 | return p->flags; | |
1811 | } | |
1812 | ||
1813 | /* Modify the flags of a page and invalidate the code if necessary. | |
1814 | The flag PAGE_WRITE_ORG is positioned automatically depending | |
1815 | on PAGE_WRITE. The mmap_lock should already be held. */ | |
1816 | void page_set_flags(target_ulong start, target_ulong end, int flags) | |
1817 | { | |
1818 | target_ulong addr, len; | |
1819 | ||
1820 | /* This function should never be called with addresses outside the | |
1821 | guest address space. If this assert fires, it probably indicates | |
1822 | a missing call to h2g_valid. */ | |
1823 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS | |
1a1c4db9 | 1824 | assert(end < ((target_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); |
5b6dd868 BS |
1825 | #endif |
1826 | assert(start < end); | |
1827 | ||
1828 | start = start & TARGET_PAGE_MASK; | |
1829 | end = TARGET_PAGE_ALIGN(end); | |
1830 | ||
1831 | if (flags & PAGE_WRITE) { | |
1832 | flags |= PAGE_WRITE_ORG; | |
1833 | } | |
1834 | ||
1835 | for (addr = start, len = end - start; | |
1836 | len != 0; | |
1837 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
1838 | PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); | |
1839 | ||
1840 | /* If the write protection bit is set, then we invalidate | |
1841 | the code inside. */ | |
1842 | if (!(p->flags & PAGE_WRITE) && | |
1843 | (flags & PAGE_WRITE) && | |
1844 | p->first_tb) { | |
d02532f0 | 1845 | tb_invalidate_phys_page(addr, 0, NULL, false); |
5b6dd868 BS |
1846 | } |
1847 | p->flags = flags; | |
1848 | } | |
1849 | } | |
1850 | ||
1851 | int page_check_range(target_ulong start, target_ulong len, int flags) | |
1852 | { | |
1853 | PageDesc *p; | |
1854 | target_ulong end; | |
1855 | target_ulong addr; | |
1856 | ||
1857 | /* This function should never be called with addresses outside the | |
1858 | guest address space. If this assert fires, it probably indicates | |
1859 | a missing call to h2g_valid. */ | |
1860 | #if TARGET_ABI_BITS > L1_MAP_ADDR_SPACE_BITS | |
1a1c4db9 | 1861 | assert(start < ((target_ulong)1 << L1_MAP_ADDR_SPACE_BITS)); |
5b6dd868 BS |
1862 | #endif |
1863 | ||
1864 | if (len == 0) { | |
1865 | return 0; | |
1866 | } | |
1867 | if (start + len - 1 < start) { | |
1868 | /* We've wrapped around. */ | |
1869 | return -1; | |
1870 | } | |
1871 | ||
1872 | /* must do before we loose bits in the next step */ | |
1873 | end = TARGET_PAGE_ALIGN(start + len); | |
1874 | start = start & TARGET_PAGE_MASK; | |
1875 | ||
1876 | for (addr = start, len = end - start; | |
1877 | len != 0; | |
1878 | len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { | |
1879 | p = page_find(addr >> TARGET_PAGE_BITS); | |
1880 | if (!p) { | |
1881 | return -1; | |
1882 | } | |
1883 | if (!(p->flags & PAGE_VALID)) { | |
1884 | return -1; | |
1885 | } | |
1886 | ||
1887 | if ((flags & PAGE_READ) && !(p->flags & PAGE_READ)) { | |
1888 | return -1; | |
1889 | } | |
1890 | if (flags & PAGE_WRITE) { | |
1891 | if (!(p->flags & PAGE_WRITE_ORG)) { | |
1892 | return -1; | |
1893 | } | |
1894 | /* unprotect the page if it was put read-only because it | |
1895 | contains translated code */ | |
1896 | if (!(p->flags & PAGE_WRITE)) { | |
1897 | if (!page_unprotect(addr, 0, NULL)) { | |
1898 | return -1; | |
1899 | } | |
1900 | } | |
5b6dd868 BS |
1901 | } |
1902 | } | |
1903 | return 0; | |
1904 | } | |
1905 | ||
1906 | /* called from signal handler: invalidate the code and unprotect the | |
1907 | page. Return TRUE if the fault was successfully handled. */ | |
1908 | int page_unprotect(target_ulong address, uintptr_t pc, void *puc) | |
1909 | { | |
1910 | unsigned int prot; | |
1911 | PageDesc *p; | |
1912 | target_ulong host_start, host_end, addr; | |
1913 | ||
1914 | /* Technically this isn't safe inside a signal handler. However we | |
1915 | know this only ever happens in a synchronous SEGV handler, so in | |
1916 | practice it seems to be ok. */ | |
1917 | mmap_lock(); | |
1918 | ||
1919 | p = page_find(address >> TARGET_PAGE_BITS); | |
1920 | if (!p) { | |
1921 | mmap_unlock(); | |
1922 | return 0; | |
1923 | } | |
1924 | ||
1925 | /* if the page was really writable, then we change its | |
1926 | protection back to writable */ | |
1927 | if ((p->flags & PAGE_WRITE_ORG) && !(p->flags & PAGE_WRITE)) { | |
1928 | host_start = address & qemu_host_page_mask; | |
1929 | host_end = host_start + qemu_host_page_size; | |
1930 | ||
1931 | prot = 0; | |
1932 | for (addr = host_start ; addr < host_end ; addr += TARGET_PAGE_SIZE) { | |
1933 | p = page_find(addr >> TARGET_PAGE_BITS); | |
1934 | p->flags |= PAGE_WRITE; | |
1935 | prot |= p->flags; | |
1936 | ||
1937 | /* and since the content will be modified, we must invalidate | |
1938 | the corresponding translated code. */ | |
d02532f0 | 1939 | tb_invalidate_phys_page(addr, pc, puc, true); |
5b6dd868 BS |
1940 | #ifdef DEBUG_TB_CHECK |
1941 | tb_invalidate_check(addr); | |
1942 | #endif | |
1943 | } | |
1944 | mprotect((void *)g2h(host_start), qemu_host_page_size, | |
1945 | prot & PAGE_BITS); | |
1946 | ||
1947 | mmap_unlock(); | |
1948 | return 1; | |
1949 | } | |
1950 | mmap_unlock(); | |
1951 | return 0; | |
1952 | } | |
1953 | #endif /* CONFIG_USER_ONLY */ |