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1/*
2 * Host code generation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#include <stdarg.h>
21#include <stdlib.h>
22#include <stdio.h>
23#include <string.h>
24#include <inttypes.h>
25
26#include "config.h"
2054396a 27
d19893da 28#define IN_OP_I386
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29#if defined(TARGET_I386)
30#include "cpu-i386.h"
31#define OPC_CPU_H "opc-i386.h"
32#elif defined(TARGET_ARM)
33#include "cpu-arm.h"
34#define OPC_CPU_H "opc-arm.h"
35#else
36#error unsupported target CPU
37#endif
38
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39#include "exec.h"
40#include "disas.h"
41
42enum {
43#define DEF(s, n, copy_size) INDEX_op_ ## s,
2054396a 44#include OPC_CPU_H
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45#undef DEF
46 NB_OPS,
47};
48
49#include "dyngen.h"
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50#if defined(TARGET_I386)
51#include "op-i386.h"
52#elif defined(TARGET_ARM)
53#include "op-arm.h"
54#else
55#error unsupported target CPU
56#endif
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57
58uint16_t gen_opc_buf[OPC_BUF_SIZE];
59uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
60uint32_t gen_opc_pc[OPC_BUF_SIZE];
61uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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62#if defined(TARGET_I386)
63uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
64#endif
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65
66#ifdef DEBUG_DISAS
67static const char *op_str[] = {
68#define DEF(s, n, copy_size) #s,
2054396a 69#include OPC_CPU_H
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70#undef DEF
71};
72
73static uint8_t op_nb_args[] = {
74#define DEF(s, n, copy_size) n,
2054396a 75#include OPC_CPU_H
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76#undef DEF
77};
78
79void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf)
80{
81 const uint16_t *opc_ptr;
82 const uint32_t *opparam_ptr;
83 int c, n, i;
84
85 opc_ptr = opc_buf;
86 opparam_ptr = opparam_buf;
87 for(;;) {
88 c = *opc_ptr++;
89 n = op_nb_args[c];
90 fprintf(logfile, "0x%04x: %s",
91 (int)(opc_ptr - opc_buf - 1), op_str[c]);
92 for(i = 0; i < n; i++) {
93 fprintf(logfile, " 0x%x", opparam_ptr[i]);
94 }
95 fprintf(logfile, "\n");
96 if (c == INDEX_op_end)
97 break;
98 opparam_ptr += n;
99 }
100}
101
102#endif
103
104/* return non zero if the very first instruction is invalid so that
105 the virtual CPU can trigger an exception.
106
107 '*gen_code_size_ptr' contains the size of the generated code (host
108 code).
109*/
4c3a88a2 110int cpu_gen_code(CPUState *env, TranslationBlock *tb,
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111 int max_code_size, int *gen_code_size_ptr)
112{
113 uint8_t *gen_code_buf;
114 int gen_code_size;
115
4c3a88a2 116 if (gen_intermediate_code(env, tb) < 0)
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117 return -1;
118
119 /* generate machine code */
120 tb->tb_next_offset[0] = 0xffff;
121 tb->tb_next_offset[1] = 0xffff;
122 gen_code_buf = tb->tc_ptr;
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123#ifdef USE_DIRECT_JUMP
124 /* the following two entries are optional (only used for string ops) */
125 tb->tb_jmp_offset[2] = 0xffff;
126 tb->tb_jmp_offset[3] = 0xffff;
127#endif
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128 gen_code_size = dyngen_code(gen_code_buf, tb->tb_next_offset,
129#ifdef USE_DIRECT_JUMP
130 tb->tb_jmp_offset,
131#else
132 NULL,
133#endif
134 gen_opc_buf, gen_opparam_buf);
135 *gen_code_size_ptr = gen_code_size;
136#ifdef DEBUG_DISAS
137 if (loglevel) {
138 fprintf(logfile, "OUT: [size=%d]\n", *gen_code_size_ptr);
139 disas(logfile, gen_code_buf, *gen_code_size_ptr, 1, 0);
140 fprintf(logfile, "\n");
141 fflush(logfile);
142 }
143#endif
144 return 0;
145}
146
147static const unsigned short opc_copy_size[] = {
148#define DEF(s, n, copy_size) copy_size,
2054396a 149#include OPC_CPU_H
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150#undef DEF
151};
152
f76af4b3 153/* The cpu state corresponding to 'searched_pc' is restored.
d19893da 154 */
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155int cpu_restore_state(TranslationBlock *tb,
156 CPUState *env, unsigned long searched_pc)
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157{
158 int j, c;
159 unsigned long tc_ptr;
160 uint16_t *opc_ptr;
161
4c3a88a2 162 if (gen_intermediate_code_pc(env, tb) < 0)
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163 return -1;
164
165 /* find opc index corresponding to search_pc */
166 tc_ptr = (unsigned long)tb->tc_ptr;
167 if (searched_pc < tc_ptr)
168 return -1;
169 j = 0;
170 opc_ptr = gen_opc_buf;
171 for(;;) {
172 c = *opc_ptr;
173 if (c == INDEX_op_end)
174 return -1;
175 tc_ptr += opc_copy_size[c];
176 if (searched_pc < tc_ptr)
177 break;
178 opc_ptr++;
179 }
180 j = opc_ptr - gen_opc_buf;
181 /* now find start of instruction before */
182 while (gen_opc_instr_start[j] == 0)
183 j--;
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184#if defined(TARGET_I386)
185 {
186 int cc_op;
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187#ifdef DEBUG_DISAS
188 if (loglevel) {
189 int i;
6e0374f6 190 fprintf(logfile, "RESTORE:\n");
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191 for(i=0;i<=j; i++) {
192 if (gen_opc_instr_start[i]) {
6e0374f6 193 fprintf(logfile, "0x%04x: 0x%08x\n", i, gen_opc_pc[i]);
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194 }
195 }
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196 fprintf(logfile, "spc=0x%08lx j=0x%x eip=0x%lx cs_base=%lx\n",
197 searched_pc, j, gen_opc_pc[j] - tb->cs_base, tb->cs_base);
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198 }
199#endif
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200 env->eip = gen_opc_pc[j] - tb->cs_base;
201 cc_op = gen_opc_cc_op[j];
202 if (cc_op != CC_OP_DYNAMIC)
203 env->cc_op = cc_op;
204 }
205#elif defined(TARGET_ARM)
206 env->regs[15] = gen_opc_pc[j];
207#endif
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208 return 0;
209}
210
211