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a6a796ca
HSDT
1/*
2* Huawei SSD device driver
3* Copyright (c) 2016, Huawei Technologies Co., Ltd.
4*
5* This program is free software; you can redistribute it and/or modify it
6* under the terms and conditions of the GNU General Public License,
7* version 2, as published by the Free Software Foundation.
8*
9* This program is distributed in the hope it will be useful, but WITHOUT
10* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12* more details.
13*/
14
15#ifndef LINUX_VERSION_CODE
16#include <linux/version.h>
17#endif
18#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16))
19#include <linux/config.h>
20#endif
21#include <linux/types.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/bio.h>
25#include <linux/timer.h>
26#include <linux/init.h>
27#include <linux/pci.h>
28#include <linux/slab.h>
29#include <linux/spinlock.h>
30#include <linux/blkdev.h>
31#include <linux/sched.h>
32#include <linux/fcntl.h>
33#include <linux/interrupt.h>
34#include <linux/compiler.h>
35#include <linux/bitops.h>
36#include <linux/delay.h>
37#include <linux/time.h>
38#include <linux/stat.h>
39#include <linux/fs.h>
40#include <linux/dma-mapping.h>
41#include <linux/completion.h>
42#include <linux/workqueue.h>
43#include <linux/mm.h>
44#include <linux/ioctl.h>
45#include <linux/hdreg.h> /* HDIO_GETGEO */
46#include <linux/list.h>
47#include <linux/reboot.h>
48#include <linux/kthread.h>
49#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))
50#include <linux/seq_file.h>
51#endif
52#include <asm/uaccess.h>
53#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,2,0))
54#include <linux/scatterlist.h>
55#include <linux/vmalloc.h>
56#else
57#include <asm/scatterlist.h>
58#endif
59#include <asm/io.h>
60#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17))
61#include <linux/devfs_fs_kernel.h>
62#endif
63
64/* driver */
65#define MODULE_NAME "hio"
a9d1e0c7 66#define DRIVER_VERSION "2.1.0.28"
a6a796ca
HSDT
67#define DRIVER_VERSION_LEN 16
68
69#define SSD_FW_MIN 0x1
70
71#define SSD_DEV_NAME MODULE_NAME
72#define SSD_DEV_NAME_LEN 16
73#define SSD_CDEV_NAME "c"SSD_DEV_NAME
74#define SSD_SDEV_NAME "s"SSD_DEV_NAME
75
76
77#define SSD_CMAJOR 0
78#define SSD_MAJOR 0
79#define SSD_MAJOR_SL 0
80#define SSD_MINORS 16
81
82#define SSD_MAX_DEV 702
83#define SSD_ALPHABET_NUM 26
84
85#define hio_info(f, arg...) printk(KERN_INFO MODULE_NAME"info: " f , ## arg)
86#define hio_note(f, arg...) printk(KERN_NOTICE MODULE_NAME"note: " f , ## arg)
87#define hio_warn(f, arg...) printk(KERN_WARNING MODULE_NAME"warn: " f , ## arg)
88#define hio_err(f, arg...) printk(KERN_ERR MODULE_NAME"err: " f , ## arg)
89
90/* slave port */
91#define SSD_SLAVE_PORT_DEVID 0x000a
92
93/* int mode */
94
95/* 2.6.9 msi affinity bug, should turn msi & msi-x off */
96//#define SSD_MSI
97#define SSD_ESCAPE_IRQ
98
99//#define SSD_MSIX
100#ifndef MODULE
101#define SSD_MSIX
102#endif
103#define SSD_MSIX_VEC 8
104#ifdef SSD_MSIX
105#undef SSD_MSI
106//#undef SSD_ESCAPE_IRQ
107#define SSD_MSIX_AFFINITY_FORCE
108#endif
109
110#define SSD_TRIM
111
112/* Over temperature protect */
113#define SSD_OT_PROTECT
114
115#ifdef SSD_QUEUE_PBIO
116#define BIO_SSD_PBIO 20
117#endif
118
119/* debug */
120//#define SSD_DEBUG_ERR
121
122/* cmd timer */
123#define SSD_CMD_TIMEOUT (60*HZ)
124
125/* i2c & smbus */
126#define SSD_SPI_TIMEOUT (5*HZ)
127#define SSD_I2C_TIMEOUT (5*HZ)
128
129#define SSD_I2C_MAX_DATA (127)
130#define SSD_SMBUS_BLOCK_MAX (32)
131#define SSD_SMBUS_DATA_MAX (SSD_SMBUS_BLOCK_MAX + 2)
132
133/* wait for init */
134#define SSD_INIT_WAIT (1000) //1s
135#define SSD_CONTROLLER_WAIT (20*1000/SSD_INIT_WAIT) //20s
136#define SSD_INIT_MAX_WAIT (500*1000/SSD_INIT_WAIT) //500s
137#define SSD_INIT_MAX_WAIT_V3_2 (1400*1000/SSD_INIT_WAIT) //1400s
138#define SSD_RAM_INIT_MAX_WAIT (10*1000/SSD_INIT_WAIT) //10s
139#define SSD_CH_INFO_MAX_WAIT (10*1000/SSD_INIT_WAIT) //10s
140
141/* blkdev busy wait */
142#define SSD_DEV_BUSY_WAIT 1000 //ms
143#define SSD_DEV_BUSY_MAX_WAIT (8*1000/SSD_DEV_BUSY_WAIT) //8s
144
145/* smbus retry */
146#define SSD_SMBUS_RETRY_INTERVAL (5) //ms
147#define SSD_SMBUS_RETRY_MAX (1000/SSD_SMBUS_RETRY_INTERVAL)
148
149#define SSD_BM_RETRY_MAX 7
150
151/* bm routine interval */
152#define SSD_BM_CAP_LEARNING_DELAY (10*60*1000)
153
154/* routine interval */
155#define SSD_ROUTINE_INTERVAL (10*1000) //10s
156#define SSD_HWMON_ROUTINE_TICK (60*1000/SSD_ROUTINE_INTERVAL)
157#define SSD_CAPMON_ROUTINE_TICK ((3600*1000/SSD_ROUTINE_INTERVAL)*24*30)
158#define SSD_CAPMON2_ROUTINE_TICK (10*60*1000/SSD_ROUTINE_INTERVAL) //fault recover
159
160/* dma align */
161#define SSD_DMA_ALIGN (16)
162
163/* some hw defalut */
164#define SSD_LOG_MAX_SZ 4096
165
166#define SSD_NAND_OOB_SZ 1024
167#define SSD_NAND_ID_SZ 8
168#define SSD_NAND_ID_BUFF_SZ 1024
169#define SSD_NAND_MAX_CE 2
170
171#define SSD_BBT_RESERVED 8
172
173#define SSD_ECC_MAX_FLIP (64+1)
174
175#define SSD_RAM_ALIGN 16
176
177
178#define SSD_RELOAD_FLAG 0x3333CCCC
179#define SSD_RELOAD_FW 0xAA5555AA
180#define SSD_RESET_NOINIT 0xAA5555AA
181#define SSD_RESET 0x55AAAA55
182#define SSD_RESET_FULL 0x5A
183//#define SSD_RESET_WAIT 1000 //1s
184//#define SSD_RESET_MAX_WAIT (200*1000/SSD_RESET_WAIT) //200s
185
186
187/* reverion 1 */
188#define SSD_PROTOCOL_V1 0x0
189
190#define SSD_ROM_SIZE (16*1024*1024)
191#define SSD_ROM_BLK_SIZE (256*1024)
192#define SSD_ROM_PAGE_SIZE (256)
193#define SSD_ROM_NR_BRIDGE_FW 2
194#define SSD_ROM_NR_CTRL_FW 2
195#define SSD_ROM_BRIDGE_FW_BASE 0
196#define SSD_ROM_BRIDGE_FW_SIZE (2*1024*1024)
197#define SSD_ROM_CTRL_FW_BASE (SSD_ROM_NR_BRIDGE_FW*SSD_ROM_BRIDGE_FW_SIZE)
198#define SSD_ROM_CTRL_FW_SIZE (5*1024*1024)
199#define SSD_ROM_LABEL_BASE (SSD_ROM_CTRL_FW_BASE+SSD_ROM_CTRL_FW_SIZE*SSD_ROM_NR_CTRL_FW)
200#define SSD_ROM_VP_BASE (SSD_ROM_LABEL_BASE+SSD_ROM_BLK_SIZE)
201
202/* reverion 3 */
203#define SSD_PROTOCOL_V3 0x3000000
204#define SSD_PROTOCOL_V3_1_1 0x3010001
205#define SSD_PROTOCOL_V3_1_3 0x3010003
206#define SSD_PROTOCOL_V3_2 0x3020000
207#define SSD_PROTOCOL_V3_2_1 0x3020001 /* <4KB improved */
208#define SSD_PROTOCOL_V3_2_2 0x3020002 /* ot protect */
209#define SSD_PROTOCOL_V3_2_4 0x3020004
210
211
212#define SSD_PV3_ROM_NR_BM_FW 1
213#define SSD_PV3_ROM_BM_FW_SZ (64*1024*8)
214
215#define SSD_ROM_LOG_SZ (64*1024*4)
216
217#define SSD_ROM_NR_SMART_MAX 2
218#define SSD_PV3_ROM_NR_SMART SSD_ROM_NR_SMART_MAX
219#define SSD_PV3_ROM_SMART_SZ (64*1024)
220
221/* reverion 3.2 */
222#define SSD_PV3_2_ROM_LOG_SZ (64*1024*80) /* 5MB */
223#define SSD_PV3_2_ROM_SEC_SZ (256*1024) /* 256KB */
224
225
226/* register */
227#define SSD_REQ_FIFO_REG 0x0000
228#define SSD_RESP_FIFO_REG 0x0008 //0x0010
229#define SSD_RESP_PTR_REG 0x0010 //0x0018
230#define SSD_INTR_INTERVAL_REG 0x0018
231#define SSD_READY_REG 0x001C
232#define SSD_BRIDGE_TEST_REG 0x0020
233#define SSD_STRIPE_SIZE_REG 0x0028
234#define SSD_CTRL_VER_REG 0x0030 //controller
235#define SSD_BRIDGE_VER_REG 0x0034 //bridge
236#define SSD_PCB_VER_REG 0x0038
237#define SSD_BURN_FLAG_REG 0x0040
238#define SSD_BRIDGE_INFO_REG 0x0044
239
240#define SSD_WL_VAL_REG 0x0048 //32-bit
241
242#define SSD_BB_INFO_REG 0x004C
243
244#define SSD_ECC_TEST_REG 0x0050 //test only
245#define SSD_ERASE_TEST_REG 0x0058 //test only
246#define SSD_WRITE_TEST_REG 0x0060 //test only
247
248#define SSD_RESET_REG 0x0068
249#define SSD_RELOAD_FW_REG 0x0070
250
251#define SSD_RESERVED_BLKS_REG 0x0074
252#define SSD_VALID_PAGES_REG 0x0078
253#define SSD_CH_INFO_REG 0x007C
254
255#define SSD_CTRL_TEST_REG_SZ 0x8
256#define SSD_CTRL_TEST_REG0 0x0080
257#define SSD_CTRL_TEST_REG1 0x0088
258#define SSD_CTRL_TEST_REG2 0x0090
259#define SSD_CTRL_TEST_REG3 0x0098
260#define SSD_CTRL_TEST_REG4 0x00A0
261#define SSD_CTRL_TEST_REG5 0x00A8
262#define SSD_CTRL_TEST_REG6 0x00B0
263#define SSD_CTRL_TEST_REG7 0x00B8
264
265#define SSD_FLASH_INFO_REG0 0x00C0
266#define SSD_FLASH_INFO_REG1 0x00C8
267#define SSD_FLASH_INFO_REG2 0x00D0
268#define SSD_FLASH_INFO_REG3 0x00D8
269#define SSD_FLASH_INFO_REG4 0x00E0
270#define SSD_FLASH_INFO_REG5 0x00E8
271#define SSD_FLASH_INFO_REG6 0x00F0
272#define SSD_FLASH_INFO_REG7 0x00F8
273
274#define SSD_RESP_INFO_REG 0x01B8
275#define SSD_NAND_BUFF_BASE 0x01BC //for nand write
276
277#define SSD_CHIP_INFO_REG_SZ 0x10
278#define SSD_CHIP_INFO_REG0 0x0100 //128 bit
279#define SSD_CHIP_INFO_REG1 0x0110
280#define SSD_CHIP_INFO_REG2 0x0120
281#define SSD_CHIP_INFO_REG3 0x0130
282#define SSD_CHIP_INFO_REG4 0x0140
283#define SSD_CHIP_INFO_REG5 0x0150
284#define SSD_CHIP_INFO_REG6 0x0160
285#define SSD_CHIP_INFO_REG7 0x0170
286
287#define SSD_RAM_INFO_REG 0x01C4
288
289#define SSD_BBT_BASE_REG 0x01C8
290#define SSD_ECT_BASE_REG 0x01CC
291
292#define SSD_CLEAR_INTR_REG 0x01F0
293
294#define SSD_INIT_STATE_REG_SZ 0x8
295#define SSD_INIT_STATE_REG0 0x0200
296#define SSD_INIT_STATE_REG1 0x0208
297#define SSD_INIT_STATE_REG2 0x0210
298#define SSD_INIT_STATE_REG3 0x0218
299#define SSD_INIT_STATE_REG4 0x0220
300#define SSD_INIT_STATE_REG5 0x0228
301#define SSD_INIT_STATE_REG6 0x0230
302#define SSD_INIT_STATE_REG7 0x0238
303
304#define SSD_ROM_INFO_REG 0x0600
305#define SSD_ROM_BRIDGE_FW_INFO_REG 0x0604
306#define SSD_ROM_CTRL_FW_INFO_REG 0x0608
307#define SSD_ROM_VP_INFO_REG 0x060C
308
309#define SSD_LOG_INFO_REG 0x0610
310#define SSD_LED_REG 0x0614
311#define SSD_MSG_BASE_REG 0x06F8
312
313/*spi reg */
314#define SSD_SPI_REG_CMD 0x0180
315#define SSD_SPI_REG_CMD_HI 0x0184
316#define SSD_SPI_REG_WDATA 0x0188
317#define SSD_SPI_REG_ID 0x0190
318#define SSD_SPI_REG_STATUS 0x0198
319#define SSD_SPI_REG_RDATA 0x01A0
320#define SSD_SPI_REG_READY 0x01A8
321
322/* i2c register */
323#define SSD_I2C_CTRL_REG 0x06F0
324#define SSD_I2C_RDATA_REG 0x06F4
325
326/* temperature reg */
327#define SSD_BRIGE_TEMP_REG 0x0618
328
329#define SSD_CTRL_TEMP_REG0 0x0700
330#define SSD_CTRL_TEMP_REG1 0x0708
331#define SSD_CTRL_TEMP_REG2 0x0710
332#define SSD_CTRL_TEMP_REG3 0x0718
333#define SSD_CTRL_TEMP_REG4 0x0720
334#define SSD_CTRL_TEMP_REG5 0x0728
335#define SSD_CTRL_TEMP_REG6 0x0730
336#define SSD_CTRL_TEMP_REG7 0x0738
337
338/* reversion 3 reg */
339#define SSD_PROTOCOL_VER_REG 0x01B4
340
341#define SSD_FLUSH_TIMEOUT_REG 0x02A4
342#define SSD_BM_FAULT_REG 0x0660
343
344#define SSD_PV3_RAM_STATUS_REG_SZ 0x4
345#define SSD_PV3_RAM_STATUS_REG0 0x0260
346#define SSD_PV3_RAM_STATUS_REG1 0x0264
347#define SSD_PV3_RAM_STATUS_REG2 0x0268
348#define SSD_PV3_RAM_STATUS_REG3 0x026C
349#define SSD_PV3_RAM_STATUS_REG4 0x0270
350#define SSD_PV3_RAM_STATUS_REG5 0x0274
351#define SSD_PV3_RAM_STATUS_REG6 0x0278
352#define SSD_PV3_RAM_STATUS_REG7 0x027C
353
354#define SSD_PV3_CHIP_INFO_REG_SZ 0x40
355#define SSD_PV3_CHIP_INFO_REG0 0x0300
356#define SSD_PV3_CHIP_INFO_REG1 0x0340
357#define SSD_PV3_CHIP_INFO_REG2 0x0380
358#define SSD_PV3_CHIP_INFO_REG3 0x03B0
359#define SSD_PV3_CHIP_INFO_REG4 0x0400
360#define SSD_PV3_CHIP_INFO_REG5 0x0440
361#define SSD_PV3_CHIP_INFO_REG6 0x0480
362#define SSD_PV3_CHIP_INFO_REG7 0x04B0
363
364#define SSD_PV3_INIT_STATE_REG_SZ 0x20
365#define SSD_PV3_INIT_STATE_REG0 0x0500
366#define SSD_PV3_INIT_STATE_REG1 0x0520
367#define SSD_PV3_INIT_STATE_REG2 0x0540
368#define SSD_PV3_INIT_STATE_REG3 0x0560
369#define SSD_PV3_INIT_STATE_REG4 0x0580
370#define SSD_PV3_INIT_STATE_REG5 0x05A0
371#define SSD_PV3_INIT_STATE_REG6 0x05C0
372#define SSD_PV3_INIT_STATE_REG7 0x05E0
373
374/* reversion 3.1.1 reg */
375#define SSD_FULL_RESET_REG 0x01B0
376
377#define SSD_CTRL_REG_ZONE_SZ 0x800
378
379#define SSD_BB_THRESHOLD_L1_REG 0x2C0
380#define SSD_BB_THRESHOLD_L2_REG 0x2C4
381
382#define SSD_BB_ACC_REG_SZ 0x4
383#define SSD_BB_ACC_REG0 0x21C0
384#define SSD_BB_ACC_REG1 0x29C0
385#define SSD_BB_ACC_REG2 0x31C0
386
387#define SSD_EC_THRESHOLD_L1_REG 0x2C8
388#define SSD_EC_THRESHOLD_L2_REG 0x2CC
389
390#define SSD_EC_ACC_REG_SZ 0x4
391#define SSD_EC_ACC_REG0 0x21E0
392#define SSD_EC_ACC_REG1 0x29E0
393#define SSD_EC_ACC_REG2 0x31E0
394
395/* reversion 3.1.2 & 3.1.3 reg */
396#define SSD_HW_STATUS_REG 0x02AC
397
398#define SSD_PLP_INFO_REG 0x0664
399
400/*reversion 3.2 reg*/
401#define SSD_POWER_ON_REG 0x01EC
402#define SSD_PCIE_LINKSTATUS_REG 0x01F8
403#define SSD_PL_CAP_LEARN_REG 0x01FC
404
405#define SSD_FPGA_1V0_REG0 0x2070
406#define SSD_FPGA_1V8_REG0 0x2078
407#define SSD_FPGA_1V0_REG1 0x2870
408#define SSD_FPGA_1V8_REG1 0x2878
409
410/*reversion 3.2 reg*/
411#define SSD_READ_OT_REG0 0x2260
412#define SSD_WRITE_OT_REG0 0x2264
413#define SSD_READ_OT_REG1 0x2A60
414#define SSD_WRITE_OT_REG1 0x2A64
415
416
417/* function */
418#define SSD_FUNC_READ 0x01
419#define SSD_FUNC_WRITE 0x02
420#define SSD_FUNC_NAND_READ_WOOB 0x03
421#define SSD_FUNC_NAND_READ 0x04
422#define SSD_FUNC_NAND_WRITE 0x05
423#define SSD_FUNC_NAND_ERASE 0x06
424#define SSD_FUNC_NAND_READ_ID 0x07
425#define SSD_FUNC_READ_LOG 0x08
426#define SSD_FUNC_TRIM 0x09
427#define SSD_FUNC_RAM_READ 0x10
428#define SSD_FUNC_RAM_WRITE 0x11
429#define SSD_FUNC_FLUSH 0x12 //cache / bbt
430
431/* spi function */
432#define SSD_SPI_CMD_PROGRAM 0x02
433#define SSD_SPI_CMD_READ 0x03
434#define SSD_SPI_CMD_W_DISABLE 0x04
435#define SSD_SPI_CMD_READ_STATUS 0x05
436#define SSD_SPI_CMD_W_ENABLE 0x06
437#define SSD_SPI_CMD_ERASE 0xd8
438#define SSD_SPI_CMD_CLSR 0x30
439#define SSD_SPI_CMD_READ_ID 0x9f
440
441/* i2c */
442#define SSD_I2C_CTRL_READ 0x00
443#define SSD_I2C_CTRL_WRITE 0x01
444
445/* i2c internal register */
446#define SSD_I2C_CFG_REG 0x00
447#define SSD_I2C_DATA_REG 0x01
448#define SSD_I2C_CMD_REG 0x02
449#define SSD_I2C_STATUS_REG 0x03
450#define SSD_I2C_SADDR_REG 0x04
451#define SSD_I2C_LEN_REG 0x05
452#define SSD_I2C_RLEN_REG 0x06
453#define SSD_I2C_WLEN_REG 0x07
454#define SSD_I2C_RESET_REG 0x08 //write for reset
455#define SSD_I2C_PRER_REG 0x09
456
457
458/* hw mon */
459/* FPGA volt = ADC_value / 4096 * 3v */
460#define SSD_FPGA_1V0_ADC_MIN 1228 // 0.9v
461#define SSD_FPGA_1V0_ADC_MAX 1502 // 1.1v
462#define SSD_FPGA_1V8_ADC_MIN 2211 // 1.62v
463#define SSD_FPGA_1V8_ADC_MAX 2703 // 1.98
464
465/* ADC value */
466#define SSD_FPGA_VOLT_MAX(val) (((val) & 0xffff) >> 4)
467#define SSD_FPGA_VOLT_MIN(val) (((val >> 16) & 0xffff) >> 4)
468#define SSD_FPGA_VOLT_CUR(val) (((val >> 32) & 0xffff) >> 4)
469#define SSD_FPGA_VOLT(val) ((val * 3000) >> 12)
470
471#define SSD_VOLT_LOG_DATA(idx, ctrl, volt) (((uint32_t)idx << 24) | ((uint32_t)ctrl << 16) | ((uint32_t)volt))
472
473enum ssd_fpga_volt
474{
475 SSD_FPGA_1V0 = 0,
476 SSD_FPGA_1V8,
477 SSD_FPGA_VOLT_NR
478};
479
480enum ssd_clock
481{
482 SSD_CLOCK_166M_LOST = 0,
483 SSD_CLOCK_166M_SKEW,
484 SSD_CLOCK_156M_LOST,
485 SSD_CLOCK_156M_SKEW,
486 SSD_CLOCK_NR
487};
488
489/* sensor */
490#define SSD_SENSOR_LM75_SADDRESS (0x49 << 1)
491#define SSD_SENSOR_LM80_SADDRESS (0x28 << 1)
492
493#define SSD_SENSOR_CONVERT_TEMP(val) ((int)(val >> 8))
494
495#define SSD_INLET_OT_TEMP (55) //55 DegC
496#define SSD_INLET_OT_HYST (50) //50 DegC
497#define SSD_FLASH_OT_TEMP (70) //70 DegC
498#define SSD_FLASH_OT_HYST (65) //65 DegC
499
500enum ssd_sensor
501{
502 SSD_SENSOR_LM80 = 0,
503 SSD_SENSOR_LM75,
504 SSD_SENSOR_NR
505};
506
507
508/* lm75 */
509enum ssd_lm75_reg
510{
511 SSD_LM75_REG_TEMP = 0,
512 SSD_LM75_REG_CONF,
513 SSD_LM75_REG_THYST,
514 SSD_LM75_REG_TOS
515};
516
517/* lm96080 */
518#define SSD_LM80_REG_IN_MAX(nr) (0x2a + (nr) * 2)
519#define SSD_LM80_REG_IN_MIN(nr) (0x2b + (nr) * 2)
520#define SSD_LM80_REG_IN(nr) (0x20 + (nr))
521
522#define SSD_LM80_REG_FAN1 0x28
523#define SSD_LM80_REG_FAN2 0x29
524#define SSD_LM80_REG_FAN_MIN(nr) (0x3b + (nr))
525
526#define SSD_LM80_REG_TEMP 0x27
527#define SSD_LM80_REG_TEMP_HOT_MAX 0x38
528#define SSD_LM80_REG_TEMP_HOT_HYST 0x39
529#define SSD_LM80_REG_TEMP_OS_MAX 0x3a
530#define SSD_LM80_REG_TEMP_OS_HYST 0x3b
531
532#define SSD_LM80_REG_CONFIG 0x00
533#define SSD_LM80_REG_ALARM1 0x01
534#define SSD_LM80_REG_ALARM2 0x02
535#define SSD_LM80_REG_MASK1 0x03
536#define SSD_LM80_REG_MASK2 0x04
537#define SSD_LM80_REG_FANDIV 0x05
538#define SSD_LM80_REG_RES 0x06
539
540#define SSD_LM80_CONVERT_VOLT(val) ((val * 10) >> 8)
541
542#define SSD_LM80_3V3_VOLT(val) ((val)*33/19)
543
544#define SSD_LM80_CONV_INTERVAL (1000)
545
546enum ssd_lm80_in
547{
548 SSD_LM80_IN_CAP = 0,
549 SSD_LM80_IN_1V2,
550 SSD_LM80_IN_1V2a,
551 SSD_LM80_IN_1V5,
552 SSD_LM80_IN_1V8,
553 SSD_LM80_IN_FPGA_3V3,
554 SSD_LM80_IN_3V3,
555 SSD_LM80_IN_NR
556};
557
558struct ssd_lm80_limit
559{
560 uint8_t low;
561 uint8_t high;
562};
563
564/* +/- 5% except cap in*/
565static struct ssd_lm80_limit ssd_lm80_limit[SSD_LM80_IN_NR] = {
566 {171, 217}, /* CAP in: 1710 ~ 2170 */
567 {114, 126},
568 {114, 126},
569 {142, 158},
570 {171, 189},
571 {180, 200},
572 {180, 200},
573};
574
575/* temperature sensors */
576enum ssd_temp_sensor
577{
578 SSD_TEMP_INLET = 0,
579 SSD_TEMP_FLASH,
580 SSD_TEMP_CTRL,
581 SSD_TEMP_NR
582};
583
584
585#ifdef SSD_OT_PROTECT
586#define SSD_OT_DELAY (60) //ms
587
588#define SSD_OT_TEMP (90) //90 DegC
589
590#define SSD_OT_TEMP_HYST (85) //85 DegC
591#endif
592
593/* fpga temperature */
594//#define CONVERT_TEMP(val) ((float)(val)*503.975f/4096.0f-273.15f)
595#define CONVERT_TEMP(val) ((val)*504/4096-273)
596
597#define MAX_TEMP(val) CONVERT_TEMP(((val & 0xffff) >> 4))
598#define MIN_TEMP(val) CONVERT_TEMP((((val>>16) & 0xffff) >> 4))
599#define CUR_TEMP(val) CONVERT_TEMP((((val>>32) & 0xffff) >> 4))
600
601
602/* CAP monitor */
603#define SSD_PL_CAP_U1 SSD_LM80_REG_IN(SSD_LM80_IN_CAP)
604#define SSD_PL_CAP_U2 SSD_LM80_REG_IN(SSD_LM80_IN_1V8)
605#define SSD_PL_CAP_LEARN(u1, u2, t) ((t*(u1+u2))/(2*162*(u1-u2)))
606#define SSD_PL_CAP_LEARN_WAIT (20) //20ms
607#define SSD_PL_CAP_LEARN_MAX_WAIT (1000/SSD_PL_CAP_LEARN_WAIT) //1s
608
609#define SSD_PL_CAP_CHARGE_WAIT (1000)
610#define SSD_PL_CAP_CHARGE_MAX_WAIT ((120*1000)/SSD_PL_CAP_CHARGE_WAIT) //120s
611
612#define SSD_PL_CAP_VOLT(val) (val*7)
613
614#define SSD_PL_CAP_VOLT_FULL (13700)
615#define SSD_PL_CAP_VOLT_READY (12880)
616
617#define SSD_PL_CAP_THRESHOLD (8900)
618#define SSD_PL_CAP_CP_THRESHOLD (5800)
619#define SSD_PL_CAP_THRESHOLD_HYST (100)
620
621enum ssd_pl_cap_status
622{
623 SSD_PL_CAP = 0,
624 SSD_PL_CAP_NR
625};
626
627enum ssd_pl_cap_type
628{
629 SSD_PL_CAP_DEFAULT = 0, /* 4 cap */
630 SSD_PL_CAP_CP /* 3 cap */
631};
632
633
634/* hwmon offset */
635#define SSD_HWMON_OFFS_TEMP (0)
636#define SSD_HWMON_OFFS_SENSOR (SSD_HWMON_OFFS_TEMP + SSD_TEMP_NR)
637#define SSD_HWMON_OFFS_PL_CAP (SSD_HWMON_OFFS_SENSOR + SSD_SENSOR_NR)
638#define SSD_HWMON_OFFS_LM80 (SSD_HWMON_OFFS_PL_CAP + SSD_PL_CAP_NR)
639#define SSD_HWMON_OFFS_CLOCK (SSD_HWMON_OFFS_LM80 + SSD_LM80_IN_NR)
640#define SSD_HWMON_OFFS_FPGA (SSD_HWMON_OFFS_CLOCK + SSD_CLOCK_NR)
641
642#define SSD_HWMON_TEMP(idx) (SSD_HWMON_OFFS_TEMP + idx)
643#define SSD_HWMON_SENSOR(idx) (SSD_HWMON_OFFS_SENSOR + idx)
644#define SSD_HWMON_PL_CAP(idx) (SSD_HWMON_OFFS_PL_CAP + idx)
645#define SSD_HWMON_LM80(idx) (SSD_HWMON_OFFS_LM80 + idx)
646#define SSD_HWMON_CLOCK(idx) (SSD_HWMON_OFFS_CLOCK + idx)
647#define SSD_HWMON_FPGA(ctrl, idx) (SSD_HWMON_OFFS_FPGA + (ctrl * SSD_FPGA_VOLT_NR) + idx)
648
649
650
651/* fifo */
652typedef struct sfifo
653{
654 uint32_t in;
655 uint32_t out;
656 uint32_t size;
657 uint32_t esize;
658 uint32_t mask;
659 spinlock_t lock;
660 void *data;
661} sfifo_t;
662
663static int sfifo_alloc(struct sfifo *fifo, uint32_t size, uint32_t esize)
664{
665 uint32_t __size = 1;
666
667 if (!fifo || size > INT_MAX || esize == 0) {
668 return -EINVAL;
669 }
670
671 while (__size < size) __size <<= 1;
672
673 if (__size < 2) {
674 return -EINVAL;
675 }
676
677 fifo->data = vmalloc(esize * __size);
678 if (!fifo->data) {
679 return -ENOMEM;
680 }
681
682 fifo->in = 0;
683 fifo->out = 0;
684 fifo->mask = __size - 1;
685 fifo->size = __size;
686 fifo->esize = esize;
687 spin_lock_init(&fifo->lock);
688
689 return 0;
690}
691
692static void sfifo_free(struct sfifo *fifo)
693{
694 if (!fifo) {
695 return;
696 }
697
698 vfree(fifo->data);
699 fifo->data = NULL;
700 fifo->in = 0;
701 fifo->out = 0;
702 fifo->mask = 0;
703 fifo->size = 0;
704 fifo->esize = 0;
705}
706
707static int __sfifo_put(struct sfifo *fifo, void *val)
708{
709 if (((fifo->in + 1) & fifo->mask) == fifo->out) {
710 return -1;
711 }
712
713 memcpy((fifo->data + (fifo->in * fifo->esize)), val, fifo->esize);
714 fifo->in = (fifo->in + 1) & fifo->mask;
715
716 return 0;
717}
718
719static int sfifo_put(struct sfifo *fifo, void *val)
720{
721 int ret = 0;
722
723 if (!fifo || !val) {
724 return -EINVAL;
725 }
726
727 if (!in_interrupt()) {
728 spin_lock_irq(&fifo->lock);
729 ret = __sfifo_put(fifo, val);
730 spin_unlock_irq(&fifo->lock);
731 } else {
732 spin_lock(&fifo->lock);
733 ret = __sfifo_put(fifo, val);
734 spin_unlock(&fifo->lock);
735 }
736
737 return ret;
738}
739
740static int __sfifo_get(struct sfifo *fifo, void *val)
741{
742 if (fifo->out == fifo->in) {
743 return -1;
744 }
745
746 memcpy(val, (fifo->data + (fifo->out * fifo->esize)), fifo->esize);
747 fifo->out = (fifo->out + 1) & fifo->mask;
748
749 return 0;
750}
751
752static int sfifo_get(struct sfifo *fifo, void *val)
753{
754 int ret = 0;
755
756 if (!fifo || !val) {
757 return -EINVAL;
758 }
759
760 if (!in_interrupt()) {
761 spin_lock_irq(&fifo->lock);
762 ret = __sfifo_get(fifo, val);
763 spin_unlock_irq(&fifo->lock);
764 } else {
765 spin_lock(&fifo->lock);
766 ret = __sfifo_get(fifo, val);
767 spin_unlock(&fifo->lock);
768 }
769
770 return ret;
771}
772
773/* bio list */
774#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
775struct ssd_blist {
776 struct bio *prev;
777 struct bio *next;
778};
779
780static inline void ssd_blist_init(struct ssd_blist *ssd_bl)
781{
782 ssd_bl->prev = NULL;
783 ssd_bl->next = NULL;
784}
785
786static inline struct bio *ssd_blist_get(struct ssd_blist *ssd_bl)
787{
788 struct bio *bio = ssd_bl->prev;
789
790 ssd_bl->prev = NULL;
791 ssd_bl->next = NULL;
792
793 return bio;
794}
795
796static inline void ssd_blist_add(struct ssd_blist *ssd_bl, struct bio *bio)
797{
798 bio->bi_next = NULL;
799
800 if (ssd_bl->next) {
801 ssd_bl->next->bi_next = bio;
802 } else {
803 ssd_bl->prev = bio;
804 }
805
806 ssd_bl->next = bio;
807}
808
809#else
810#define ssd_blist bio_list
811#define ssd_blist_init bio_list_init
812#define ssd_blist_get bio_list_get
813#define ssd_blist_add bio_list_add
814#endif
815
816#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0))
817#define bio_start(bio) (bio->bi_sector)
818#else
819#define bio_start(bio) (bio->bi_iter.bi_sector)
820#endif
821
822/* mutex */
823#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16))
824#define mutex_lock down
825#define mutex_unlock up
826#define mutex semaphore
827#define mutex_init init_MUTEX
828#endif
829
830/* i2c */
831typedef union ssd_i2c_ctrl {
832 uint32_t val;
833 struct {
834 uint8_t wdata;
835 uint8_t addr;
836 uint16_t rw:1;
837 uint16_t pad:15;
838 } bits;
839}__attribute__((packed)) ssd_i2c_ctrl_t;
840
841typedef union ssd_i2c_data {
842 uint32_t val;
843 struct {
844 uint32_t rdata:8;
845 uint32_t valid:1;
846 uint32_t pad:23;
847 } bits;
848}__attribute__((packed)) ssd_i2c_data_t;
849
850/* write mode */
851enum ssd_write_mode
852{
853 SSD_WMODE_BUFFER = 0,
854 SSD_WMODE_BUFFER_EX,
855 SSD_WMODE_FUA,
856 /* dummy */
857 SSD_WMODE_AUTO,
858 SSD_WMODE_DEFAULT
859};
860
861/* reset type */
862enum ssd_reset_type
863{
864 SSD_RST_NOINIT = 0,
865 SSD_RST_NORMAL,
866 SSD_RST_FULL
867};
868
869/* ssd msg */
870typedef struct ssd_sg_entry
871{
872 uint64_t block:48;
873 uint64_t length:16;
874 uint64_t buf;
875}__attribute__((packed))ssd_sg_entry_t;
876
877typedef struct ssd_rw_msg
878{
879 uint8_t tag;
880 uint8_t flag;
881 uint8_t nsegs;
882 uint8_t fun;
883 uint32_t reserved; //for 64-bit align
884 struct ssd_sg_entry sge[1]; //base
885}__attribute__((packed))ssd_rw_msg_t;
886
887typedef struct ssd_resp_msg
888{
889 uint8_t tag;
890 uint8_t status:2;
891 uint8_t bitflip:6;
892 uint8_t log;
893 uint8_t fun;
894 uint32_t reserved;
895}__attribute__((packed))ssd_resp_msg_t;
896
897typedef struct ssd_flush_msg
898{
899 uint8_t tag;
900 uint8_t flag:2; //flash cache 0 or bbt 1
901 uint8_t flash:6;
902 uint8_t ctrl_idx;
903 uint8_t fun;
904 uint32_t reserved; //align
905}__attribute__((packed))ssd_flush_msg_t;
906
907typedef struct ssd_nand_op_msg
908{
909 uint8_t tag;
910 uint8_t flag;
911 uint8_t ctrl_idx;
912 uint8_t fun;
913 uint32_t reserved; //align
914 uint16_t page_count;
915 uint8_t chip_ce;
916 uint8_t chip_no;
917 uint32_t page_no;
918 uint64_t buf;
919}__attribute__((packed))ssd_nand_op_msg_t;
920
921typedef struct ssd_ram_op_msg
922{
923 uint8_t tag;
924 uint8_t flag;
925 uint8_t ctrl_idx;
926 uint8_t fun;
927 uint32_t reserved; //align
928 uint32_t start;
929 uint32_t length;
930 uint64_t buf;
931}__attribute__((packed))ssd_ram_op_msg_t;
932
933
934/* log msg */
935typedef struct ssd_log_msg
936{
937 uint8_t tag;
938 uint8_t flag;
939 uint8_t ctrl_idx;
940 uint8_t fun;
941 uint32_t reserved; //align
942 uint64_t buf;
943}__attribute__((packed))ssd_log_msg_t;
944
945typedef struct ssd_log_op_msg
946{
947 uint8_t tag;
948 uint8_t flag;
949 uint8_t ctrl_idx;
950 uint8_t fun;
951 uint32_t reserved; //align
952 uint64_t reserved1; //align
953 uint64_t buf;
954}__attribute__((packed))ssd_log_op_msg_t;
955
956typedef struct ssd_log_resp_msg
957{
958 uint8_t tag;
959 uint16_t status :2;
960 uint16_t reserved1 :2; //align with the normal resp msg
961 uint16_t nr_log :12;
962 uint8_t fun;
963 uint32_t reserved;
964}__attribute__((packed))ssd_log_resp_msg_t;
965
966
967/* resp msg */
968typedef union ssd_response_msq
969{
970 ssd_resp_msg_t resp_msg;
971 ssd_log_resp_msg_t log_resp_msg;
972 uint64_t u64_msg;
973 uint32_t u32_msg[2];
974} ssd_response_msq_t;
975
976
977/* custom struct */
978typedef struct ssd_protocol_info
979{
980 uint32_t ver;
981 uint32_t init_state_reg;
982 uint32_t init_state_reg_sz;
983 uint32_t chip_info_reg;
984 uint32_t chip_info_reg_sz;
985} ssd_protocol_info_t;
986
987typedef struct ssd_hw_info
988{
989 uint32_t bridge_ver;
990 uint32_t ctrl_ver;
991
992 uint32_t cmd_fifo_sz;
993 uint32_t cmd_fifo_sz_mask;
994 uint32_t cmd_max_sg;
995 uint32_t sg_max_sec;
996 uint32_t resp_ptr_sz;
997 uint32_t resp_msg_sz;
998
999 uint16_t nr_ctrl;
1000
1001 uint16_t nr_data_ch;
1002 uint16_t nr_ch;
1003 uint16_t max_ch;
1004 uint16_t nr_chip;
1005
1006 uint8_t pcb_ver;
1007 uint8_t upper_pcb_ver;
1008
1009 uint8_t nand_vendor_id;
1010 uint8_t nand_dev_id;
1011
1012 uint8_t max_ce;
1013 uint8_t id_size;
1014 uint16_t oob_size;
1015
1016 uint16_t bbf_pages;
1017 uint16_t bbf_seek; //
1018
1019 uint16_t page_count; //per block
1020 uint32_t page_size;
1021 uint32_t block_count; //per flash
1022
1023 uint64_t ram_size;
1024 uint32_t ram_align;
1025 uint32_t ram_max_len;
1026
1027 uint64_t bbt_base;
1028 uint32_t bbt_size;
1029 uint64_t md_base; //metadata
1030 uint32_t md_size;
1031 uint32_t md_entry_sz;
1032
1033 uint32_t log_sz;
1034
1035 uint64_t nand_wbuff_base;
1036
1037 uint32_t md_reserved_blks;
1038 uint32_t reserved_blks;
1039 uint32_t valid_pages;
1040 uint32_t max_valid_pages;
1041 uint64_t size;
1042} ssd_hw_info_t;
1043
1044typedef struct ssd_hw_info_extend
1045{
1046 uint8_t board_type;
1047 uint8_t cap_type;
1048 uint8_t plp_type;
1049 uint8_t work_mode;
1050 uint8_t form_factor;
1051
1052 uint8_t pad[59];
1053}ssd_hw_info_extend_t;
1054
1055typedef struct ssd_rom_info
1056{
1057 uint32_t size;
1058 uint32_t block_size;
1059 uint16_t page_size;
1060 uint8_t nr_bridge_fw;
1061 uint8_t nr_ctrl_fw;
1062 uint8_t nr_bm_fw;
1063 uint8_t nr_smart;
1064 uint32_t bridge_fw_base;
1065 uint32_t bridge_fw_sz;
1066 uint32_t ctrl_fw_base;
1067 uint32_t ctrl_fw_sz;
1068 uint32_t bm_fw_base;
1069 uint32_t bm_fw_sz;
1070 uint32_t log_base;
1071 uint32_t log_sz;
1072 uint32_t smart_base;
1073 uint32_t smart_sz;
1074 uint32_t vp_base;
1075 uint32_t label_base;
1076} ssd_rom_info_t;
1077
1078/* debug info */
1079enum ssd_debug_type
1080{
1081 SSD_DEBUG_NONE = 0,
1082 SSD_DEBUG_READ_ERR,
1083 SSD_DEBUG_WRITE_ERR,
1084 SSD_DEBUG_RW_ERR,
1085 SSD_DEBUG_READ_TO,
1086 SSD_DEBUG_WRITE_TO,
1087 SSD_DEBUG_RW_TO,
1088 SSD_DEBUG_LOG,
1089 SSD_DEBUG_OFFLINE,
1090 SSD_DEBUG_NR
1091};
1092
1093typedef struct ssd_debug_info
1094{
1095 int type;
1096 union {
1097 struct {
1098 uint64_t off;
1099 uint32_t len;
1100 } loc;
1101 struct {
1102 int event;
1103 uint32_t extra;
1104 } log;
1105 } data;
1106}ssd_debug_info_t;
1107
1108/* label */
1109#define SSD_LABEL_FIELD_SZ 32
1110#define SSD_SN_SZ 16
1111
1112typedef struct ssd_label
1113{
1114 char date[SSD_LABEL_FIELD_SZ];
1115 char sn[SSD_LABEL_FIELD_SZ];
1116 char part[SSD_LABEL_FIELD_SZ];
1117 char desc[SSD_LABEL_FIELD_SZ];
1118 char other[SSD_LABEL_FIELD_SZ];
1119 char maf[SSD_LABEL_FIELD_SZ];
1120} ssd_label_t;
1121
1122#define SSD_LABEL_DESC_SZ 256
1123
1124typedef struct ssd_labelv3
1125{
1126 char boardtype[SSD_LABEL_FIELD_SZ];
1127 char barcode[SSD_LABEL_FIELD_SZ];
1128 char item[SSD_LABEL_FIELD_SZ];
1129 char description[SSD_LABEL_DESC_SZ];
1130 char manufactured[SSD_LABEL_FIELD_SZ];
1131 char vendorname[SSD_LABEL_FIELD_SZ];
1132 char issuenumber[SSD_LABEL_FIELD_SZ];
1133 char cleicode[SSD_LABEL_FIELD_SZ];
1134 char bom[SSD_LABEL_FIELD_SZ];
1135} ssd_labelv3_t;
1136
1137/* battery */
1138typedef struct ssd_battery_info
1139{
1140 uint32_t fw_ver;
1141} ssd_battery_info_t;
1142
1143/* ssd power stat */
1144typedef struct ssd_power_stat
1145{
1146 uint64_t nr_poweron;
1147 uint64_t nr_powerloss;
1148 uint64_t init_failed;
1149} ssd_power_stat_t;
1150
1151/* io stat */
1152typedef struct ssd_io_stat
1153{
1154 uint64_t run_time;
1155 uint64_t nr_to;
1156 uint64_t nr_ioerr;
1157 uint64_t nr_rwerr;
1158 uint64_t nr_read;
1159 uint64_t nr_write;
1160 uint64_t rsectors;
1161 uint64_t wsectors;
1162} ssd_io_stat_t;
1163
1164/* ecc */
1165typedef struct ssd_ecc_info
1166{
1167 uint64_t bitflip[SSD_ECC_MAX_FLIP];
1168} ssd_ecc_info_t;
1169
1170/* log */
1171enum ssd_log_level
1172{
1173 SSD_LOG_LEVEL_INFO = 0,
1174 SSD_LOG_LEVEL_NOTICE,
1175 SSD_LOG_LEVEL_WARNING,
1176 SSD_LOG_LEVEL_ERR,
1177 SSD_LOG_NR_LEVEL
1178};
1179
1180typedef struct ssd_log_info
1181{
1182 uint64_t nr_log;
1183 uint64_t stat[SSD_LOG_NR_LEVEL];
1184} ssd_log_info_t;
1185
1186/* S.M.A.R.T. */
1187#define SSD_SMART_MAGIC (0x5452414D53445353ull)
1188
1189typedef struct ssd_smart
1190{
1191 struct ssd_power_stat pstat;
1192 struct ssd_io_stat io_stat;
1193 struct ssd_ecc_info ecc_info;
1194 struct ssd_log_info log_info;
1195 uint64_t version;
1196 uint64_t magic;
1197} ssd_smart_t;
1198
1199/* internal log */
1200typedef struct ssd_internal_log
1201{
1202 uint32_t nr_log;
1203 void *log;
1204} ssd_internal_log_t;
1205
1206/* ssd cmd */
1207typedef struct ssd_cmd
1208{
1209 struct bio *bio;
1210 struct scatterlist *sgl;
1211 struct list_head list;
1212 void *dev;
1213 int nsegs;
1214 int flag; /*pbio(1) or bio(0)*/
1215
1216 int tag;
1217 void *msg;
1218 dma_addr_t msg_dma;
1219
1220 unsigned long start_time;
1221
1222 int errors;
1223 unsigned int nr_log;
1224
1225 struct timer_list cmd_timer;
1226 struct completion *waiting;
1227} ssd_cmd_t;
1228
1229typedef void (*send_cmd_func)(struct ssd_cmd *);
1230typedef int (*ssd_event_call)(struct gendisk *, int, int); /* gendisk, event id, event level */
1231
1232/* dcmd sz */
1233#define SSD_DCMD_MAX_SZ 32
1234
1235typedef struct ssd_dcmd
1236{
1237 struct list_head list;
1238 void *dev;
1239 uint8_t msg[SSD_DCMD_MAX_SZ];
1240} ssd_dcmd_t;
1241
1242
1243enum ssd_state {
1244 SSD_INIT_WORKQ,
1245 SSD_INIT_BD,
1246 SSD_ONLINE,
1247 /* full reset */
1248 SSD_RESETING,
1249 /* hw log */
1250 SSD_LOG_HW,
1251 /* log err */
1252 SSD_LOG_ERR
1253};
1254
1255#define SSD_QUEUE_NAME_LEN 16
1256typedef struct ssd_queue {
1257 char name[SSD_QUEUE_NAME_LEN];
1258 void *dev;
1259
1260 int idx;
1261
1262 uint32_t resp_idx;
1263 uint32_t resp_idx_mask;
1264 uint32_t resp_msg_sz;
1265
1266 void *resp_msg;
1267 void *resp_ptr;
1268
1269 struct ssd_cmd *cmd;
1270
1271 struct ssd_io_stat io_stat;
1272 struct ssd_ecc_info ecc_info;
1273} ssd_queue_t;
1274
1275typedef struct ssd_device {
1276 char name[SSD_DEV_NAME_LEN];
1277
1278 int idx;
1279 int major;
1280 int readonly;
1281
1282 int int_mode;
1283#ifdef SSD_ESCAPE_IRQ
1284 int irq_cpu;
1285#endif
1286
1287 int reload_fw;
1288
1289 int ot_delay; //in ms
1290
1291 atomic_t refcnt;
1292 atomic_t tocnt;
1293 atomic_t in_flight[2]; //r&w
1294
1295 uint64_t uptime;
1296
1297 struct list_head list;
1298 struct pci_dev *pdev;
1299
1300 unsigned long mmio_base;
1301 unsigned long mmio_len;
1302 void __iomem *ctrlp;
1303
1304 struct mutex spi_mutex;
1305 struct mutex i2c_mutex;
1306
1307 struct ssd_protocol_info protocol_info;
1308 struct ssd_hw_info hw_info;
1309 struct ssd_rom_info rom_info;
1310 struct ssd_label label;
1311
1312 struct ssd_smart smart;
1313
1314 atomic_t in_sendq;
1315 spinlock_t sendq_lock;
1316 struct ssd_blist sendq;
1317 struct task_struct *send_thread;
1318 wait_queue_head_t send_waitq;
1319
1320 atomic_t in_doneq;
1321 spinlock_t doneq_lock;
1322 struct ssd_blist doneq;
1323 struct task_struct *done_thread;
1324 wait_queue_head_t done_waitq;
1325
1326 struct ssd_dcmd *dcmd;
1327 spinlock_t dcmd_lock;
1328 struct list_head dcmd_list; /* direct cmd list */
1329 wait_queue_head_t dcmd_wq;
1330
1331 unsigned long *tag_map;
1332 wait_queue_head_t tag_wq;
1333
1334 spinlock_t cmd_lock;
1335 struct ssd_cmd *cmd;
1336 send_cmd_func scmd;
1337
1338 ssd_event_call event_call;
1339 void *msg_base;
1340 dma_addr_t msg_base_dma;
1341
1342 uint32_t resp_idx;
1343 void *resp_msg_base;
1344 void *resp_ptr_base;
1345 dma_addr_t resp_msg_base_dma;
1346 dma_addr_t resp_ptr_base_dma;
1347
1348 int nr_queue;
1349 struct msix_entry entry[SSD_MSIX_VEC];
1350 struct ssd_queue queue[SSD_MSIX_VEC];
1351
1352 struct request_queue *rq; /* The device request queue */
1353 struct gendisk *gd; /* The gendisk structure */
1354
1355 struct mutex internal_log_mutex;
1356 struct ssd_internal_log internal_log;
1357 struct workqueue_struct *workq;
1358 struct work_struct log_work; /* get log */
1359 void *log_buf;
1360
1361 unsigned long state; /* device state, for example, block device inited */
1362
1363 struct module *owner;
1364
1365 /* extend */
1366
1367 int slave;
1368 int cmajor;
1369 int save_md;
1370 int ot_protect;
1371
1372 struct kref kref;
1373
1374 struct mutex gd_mutex;
1375 struct ssd_log_info log_info; /* volatile */
1376
1377 atomic_t queue_depth;
1378 struct mutex barrier_mutex;
1379 struct mutex fw_mutex;
1380
1381 struct ssd_hw_info_extend hw_info_ext;
1382 struct ssd_labelv3 labelv3;
1383
1384 int wmode;
1385 int user_wmode;
1386 struct mutex bm_mutex;
1387 struct work_struct bm_work; /* check bm */
1388 struct timer_list bm_timer;
1389 struct sfifo log_fifo;
1390
1391 struct timer_list routine_timer;
1392 unsigned long routine_tick;
1393 unsigned long hwmon;
1394
1395 struct work_struct hwmon_work; /* check hw */
1396 struct work_struct capmon_work; /* check battery */
1397 struct work_struct tempmon_work; /* check temp */
1398
1399 /* debug info */
1400 struct ssd_debug_info db_info;
a9d1e0c7 1401 uint64_t reset_time;
a6a796ca
HSDT
1402} ssd_device_t;
1403
1404
1405/* Ioctl struct */
1406typedef struct ssd_acc_info {
1407 uint32_t threshold_l1;
1408 uint32_t threshold_l2;
1409 uint32_t val;
1410} ssd_acc_info_t;
1411
1412typedef struct ssd_reg_op_info
1413{
1414 uint32_t offset;
1415 uint32_t value;
1416} ssd_reg_op_info_t;
1417
1418typedef struct ssd_spi_op_info
1419{
1420 void __user *buf;
1421 uint32_t off;
1422 uint32_t len;
1423} ssd_spi_op_info_t;
1424
1425typedef struct ssd_i2c_op_info
1426{
1427 uint8_t saddr;
1428 uint8_t wsize;
1429 uint8_t rsize;
1430 void __user *wbuf;
1431 void __user *rbuf;
1432} ssd_i2c_op_info_t;
1433
1434typedef struct ssd_smbus_op_info
1435{
1436 uint8_t saddr;
1437 uint8_t cmd;
1438 uint8_t size;
1439 void __user *buf;
1440} ssd_smbus_op_info_t;
1441
1442typedef struct ssd_ram_op_info {
1443 uint8_t ctrl_idx;
1444 uint32_t length;
1445 uint64_t start;
1446 uint8_t __user *buf;
1447} ssd_ram_op_info_t;
1448
1449typedef struct ssd_flash_op_info {
1450 uint32_t page;
1451 uint16_t flash;
1452 uint8_t chip;
1453 uint8_t ctrl_idx;
1454 uint8_t __user *buf;
1455} ssd_flash_op_info_t;
1456
1457typedef struct ssd_sw_log_info {
1458 uint16_t event;
1459 uint16_t pad;
1460 uint32_t data;
1461} ssd_sw_log_info_t;
1462
1463typedef struct ssd_version_info
1464{
1465 uint32_t bridge_ver; /* bridge fw version */
1466 uint32_t ctrl_ver; /* controller fw version */
1467 uint32_t bm_ver; /* battery manager fw version */
1468 uint8_t pcb_ver; /* main pcb version */
1469 uint8_t upper_pcb_ver;
1470 uint8_t pad0;
1471 uint8_t pad1;
1472} ssd_version_info_t;
1473
1474typedef struct pci_addr
1475{
1476 uint16_t domain;
1477 uint8_t bus;
1478 uint8_t slot;
1479 uint8_t func;
1480} pci_addr_t;
1481
1482typedef struct ssd_drv_param_info {
1483 int mode;
1484 int status_mask;
1485 int int_mode;
1486 int threaded_irq;
1487 int log_level;
1488 int wmode;
1489 int ot_protect;
1490 int finject;
1491 int pad[8];
1492} ssd_drv_param_info_t;
1493
1494
1495/* form factor */
1496enum ssd_form_factor
1497{
1498 SSD_FORM_FACTOR_HHHL = 0,
1499 SSD_FORM_FACTOR_FHHL
1500};
1501
1502
1503/* ssd power loss protect */
1504enum ssd_plp_type
1505{
1506 SSD_PLP_SCAP = 0,
1507 SSD_PLP_CAP,
1508 SSD_PLP_NONE
1509};
1510
1511/* ssd bm */
1512#define SSD_BM_SLAVE_ADDRESS 0x16
1513#define SSD_BM_CAP 5
1514
1515/* SBS cmd */
1516#define SSD_BM_SAFETYSTATUS 0x51
1517#define SSD_BM_OPERATIONSTATUS 0x54
1518
1519/* ManufacturerAccess */
1520#define SSD_BM_MANUFACTURERACCESS 0x00
1521#define SSD_BM_ENTER_CAP_LEARNING 0x0023 /* cap learning */
1522
1523/* Data flash access */
1524#define SSD_BM_DATA_FLASH_SUBCLASS_ID 0x77
1525#define SSD_BM_DATA_FLASH_SUBCLASS_ID_PAGE1 0x78
1526#define SSD_BM_SYSTEM_DATA_SUBCLASS_ID 56
1527#define SSD_BM_CONFIGURATION_REGISTERS_ID 64
1528
1529/* min cap voltage */
1530#define SSD_BM_CAP_VOLT_MIN 500
1531
1532/*
1533enum ssd_bm_cap
1534{
1535 SSD_BM_CAP_VINA = 1,
1536 SSD_BM_CAP_JH = 3
1537};*/
1538
1539enum ssd_bmstatus
1540{
1541 SSD_BMSTATUS_OK = 0,
1542 SSD_BMSTATUS_CHARGING, /* not fully charged */
1543 SSD_BMSTATUS_WARNING
1544};
1545
1546enum sbs_unit {
1547 SBS_UNIT_VALUE = 0,
1548 SBS_UNIT_TEMPERATURE,
1549 SBS_UNIT_VOLTAGE,
1550 SBS_UNIT_CURRENT,
1551 SBS_UNIT_ESR,
1552 SBS_UNIT_PERCENT,
1553 SBS_UNIT_CAPACITANCE
1554};
1555
1556enum sbs_size {
1557 SBS_SIZE_BYTE = 1,
1558 SBS_SIZE_WORD,
1559 SBS_SIZE_BLK,
1560};
1561
1562struct sbs_cmd {
1563 uint8_t cmd;
1564 uint8_t size;
1565 uint8_t unit;
1566 uint8_t off;
1567 uint16_t mask;
1568 char *desc;
1569};
1570
1571struct ssd_bm {
1572 uint16_t temp;
1573 uint16_t volt;
1574 uint16_t curr;
1575 uint16_t esr;
1576 uint16_t rsoc;
1577 uint16_t health;
1578 uint16_t cap;
1579 uint16_t chg_curr;
1580 uint16_t chg_volt;
1581 uint16_t cap_volt[SSD_BM_CAP];
1582 uint16_t sf_alert;
1583 uint16_t sf_status;
1584 uint16_t op_status;
1585 uint16_t sys_volt;
1586};
1587
1588struct ssd_bm_manufacturer_data
1589{
1590 uint16_t pack_lot_code;
1591 uint16_t pcb_lot_code;
1592 uint16_t firmware_ver;
1593 uint16_t hardware_ver;
1594};
1595
1596struct ssd_bm_configuration_registers
1597{
1598 struct {
1599 uint16_t cc:3;
1600 uint16_t rsvd:5;
1601 uint16_t stack:1;
1602 uint16_t rsvd1:2;
1603 uint16_t temp:2;
1604 uint16_t rsvd2:1;
1605 uint16_t lt_en:1;
1606 uint16_t rsvd3:1;
1607 } operation_cfg;
1608 uint16_t pad;
1609 uint16_t fet_action;
1610 uint16_t pad1;
1611 uint16_t fault;
1612};
1613
1614#define SBS_VALUE_MASK 0xffff
1615
1616#define bm_var_offset(var) ((size_t) &((struct ssd_bm *)0)->var)
1617#define bm_var(start, offset) ((void *) start + (offset))
1618
1619static struct sbs_cmd ssd_bm_sbs[] = {
1620 {0x08, SBS_SIZE_WORD, SBS_UNIT_TEMPERATURE, bm_var_offset(temp), SBS_VALUE_MASK, "Temperature"},
1621 {0x09, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, bm_var_offset(volt), SBS_VALUE_MASK, "Voltage"},
1622 {0x0a, SBS_SIZE_WORD, SBS_UNIT_CURRENT, bm_var_offset(curr), SBS_VALUE_MASK, "Current"},
1623 {0x0b, SBS_SIZE_WORD, SBS_UNIT_ESR, bm_var_offset(esr), SBS_VALUE_MASK, "ESR"},
1624 {0x0d, SBS_SIZE_BYTE, SBS_UNIT_PERCENT, bm_var_offset(rsoc), SBS_VALUE_MASK, "RelativeStateOfCharge"},
1625 {0x0e, SBS_SIZE_BYTE, SBS_UNIT_PERCENT, bm_var_offset(health), SBS_VALUE_MASK, "Health"},
1626 {0x10, SBS_SIZE_WORD, SBS_UNIT_CAPACITANCE, bm_var_offset(cap), SBS_VALUE_MASK, "Capacitance"},
1627 {0x14, SBS_SIZE_WORD, SBS_UNIT_CURRENT, bm_var_offset(chg_curr), SBS_VALUE_MASK, "ChargingCurrent"},
1628 {0x15, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, bm_var_offset(chg_volt), SBS_VALUE_MASK, "ChargingVoltage"},
1629 {0x3b, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, (uint8_t)bm_var_offset(cap_volt[4]), SBS_VALUE_MASK, "CapacitorVoltage5"},
1630 {0x3c, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, (uint8_t)bm_var_offset(cap_volt[3]), SBS_VALUE_MASK, "CapacitorVoltage4"},
1631 {0x3d, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, (uint8_t)bm_var_offset(cap_volt[2]), SBS_VALUE_MASK, "CapacitorVoltage3"},
1632 {0x3e, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, (uint8_t)bm_var_offset(cap_volt[1]), SBS_VALUE_MASK, "CapacitorVoltage2"},
1633 {0x3f, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, (uint8_t)bm_var_offset(cap_volt[0]), SBS_VALUE_MASK, "CapacitorVoltage1"},
1634 {0x50, SBS_SIZE_WORD, SBS_UNIT_VALUE, bm_var_offset(sf_alert), 0x870F, "SafetyAlert"},
1635 {0x51, SBS_SIZE_WORD, SBS_UNIT_VALUE, bm_var_offset(sf_status), 0xE7BF, "SafetyStatus"},
1636 {0x54, SBS_SIZE_WORD, SBS_UNIT_VALUE, bm_var_offset(op_status), 0x79F4, "OperationStatus"},
1637 {0x5a, SBS_SIZE_WORD, SBS_UNIT_VOLTAGE, bm_var_offset(sys_volt), SBS_VALUE_MASK, "SystemVoltage"},
1638 {0, 0, 0, 0, 0, NULL},
1639};
1640
1641/* ssd ioctl */
1642#define SSD_CMD_GET_PROTOCOL_INFO _IOR('H', 100, struct ssd_protocol_info)
1643#define SSD_CMD_GET_HW_INFO _IOR('H', 101, struct ssd_hw_info)
1644#define SSD_CMD_GET_ROM_INFO _IOR('H', 102, struct ssd_rom_info)
1645#define SSD_CMD_GET_SMART _IOR('H', 103, struct ssd_smart)
1646#define SSD_CMD_GET_IDX _IOR('H', 105, int)
1647#define SSD_CMD_GET_AMOUNT _IOR('H', 106, int)
1648#define SSD_CMD_GET_TO_INFO _IOR('H', 107, int)
1649#define SSD_CMD_GET_DRV_VER _IOR('H', 108, char[DRIVER_VERSION_LEN])
1650
1651#define SSD_CMD_GET_BBACC_INFO _IOR('H', 109, struct ssd_acc_info)
1652#define SSD_CMD_GET_ECACC_INFO _IOR('H', 110, struct ssd_acc_info)
1653
1654#define SSD_CMD_GET_HW_INFO_EXT _IOR('H', 111, struct ssd_hw_info_extend)
1655
1656#define SSD_CMD_REG_READ _IOWR('H', 120, struct ssd_reg_op_info)
1657#define SSD_CMD_REG_WRITE _IOWR('H', 121, struct ssd_reg_op_info)
1658
1659#define SSD_CMD_SPI_READ _IOWR('H', 125, struct ssd_spi_op_info)
1660#define SSD_CMD_SPI_WRITE _IOWR('H', 126, struct ssd_spi_op_info)
1661#define SSD_CMD_SPI_ERASE _IOWR('H', 127, struct ssd_spi_op_info)
1662
1663#define SSD_CMD_I2C_READ _IOWR('H', 128, struct ssd_i2c_op_info)
1664#define SSD_CMD_I2C_WRITE _IOWR('H', 129, struct ssd_i2c_op_info)
1665#define SSD_CMD_I2C_WRITE_READ _IOWR('H', 130, struct ssd_i2c_op_info)
1666
1667#define SSD_CMD_SMBUS_SEND_BYTE _IOWR('H', 131, struct ssd_smbus_op_info)
1668#define SSD_CMD_SMBUS_RECEIVE_BYTE _IOWR('H', 132, struct ssd_smbus_op_info)
1669#define SSD_CMD_SMBUS_WRITE_BYTE _IOWR('H', 133, struct ssd_smbus_op_info)
1670#define SSD_CMD_SMBUS_READ_BYTE _IOWR('H', 135, struct ssd_smbus_op_info)
1671#define SSD_CMD_SMBUS_WRITE_WORD _IOWR('H', 136, struct ssd_smbus_op_info)
1672#define SSD_CMD_SMBUS_READ_WORD _IOWR('H', 137, struct ssd_smbus_op_info)
1673#define SSD_CMD_SMBUS_WRITE_BLOCK _IOWR('H', 138, struct ssd_smbus_op_info)
1674#define SSD_CMD_SMBUS_READ_BLOCK _IOWR('H', 139, struct ssd_smbus_op_info)
1675
1676#define SSD_CMD_BM_GET_VER _IOR('H', 140, uint16_t)
1677#define SSD_CMD_BM_GET_NR_CAP _IOR('H', 141, int)
1678#define SSD_CMD_BM_CAP_LEARNING _IOW('H', 142, int)
1679#define SSD_CMD_CAP_LEARN _IOR('H', 143, uint32_t)
1680#define SSD_CMD_GET_CAP_STATUS _IOR('H', 144, int)
1681
1682#define SSD_CMD_RAM_READ _IOWR('H', 150, struct ssd_ram_op_info)
1683#define SSD_CMD_RAM_WRITE _IOWR('H', 151, struct ssd_ram_op_info)
1684
1685#define SSD_CMD_NAND_READ_ID _IOR('H', 160, struct ssd_flash_op_info)
1686#define SSD_CMD_NAND_READ _IOWR('H', 161, struct ssd_flash_op_info) //with oob
1687#define SSD_CMD_NAND_WRITE _IOWR('H', 162, struct ssd_flash_op_info)
1688#define SSD_CMD_NAND_ERASE _IOWR('H', 163, struct ssd_flash_op_info)
1689#define SSD_CMD_NAND_READ_EXT _IOWR('H', 164, struct ssd_flash_op_info) //ingore EIO
1690
1691#define SSD_CMD_UPDATE_BBT _IOW('H', 180, struct ssd_flash_op_info)
1692
1693#define SSD_CMD_CLEAR_ALARM _IOW('H', 190, int)
1694#define SSD_CMD_SET_ALARM _IOW('H', 191, int)
1695
1696#define SSD_CMD_RESET _IOW('H', 200, int)
1697#define SSD_CMD_RELOAD_FW _IOW('H', 201, int)
1698#define SSD_CMD_UNLOAD_DEV _IOW('H', 202, int)
1699#define SSD_CMD_LOAD_DEV _IOW('H', 203, int)
1700#define SSD_CMD_UPDATE_VP _IOWR('H', 205, uint32_t)
1701#define SSD_CMD_FULL_RESET _IOW('H', 206, int)
1702
1703#define SSD_CMD_GET_NR_LOG _IOR('H', 220, uint32_t)
1704#define SSD_CMD_GET_LOG _IOR('H', 221, void *)
1705#define SSD_CMD_LOG_LEVEL _IOW('H', 222, int)
1706
1707#define SSD_CMD_OT_PROTECT _IOW('H', 223, int)
1708#define SSD_CMD_GET_OT_STATUS _IOR('H', 224, int)
1709
1710#define SSD_CMD_CLEAR_LOG _IOW('H', 230, int)
1711#define SSD_CMD_CLEAR_SMART _IOW('H', 231, int)
1712
1713#define SSD_CMD_SW_LOG _IOW('H', 232, struct ssd_sw_log_info)
1714
1715#define SSD_CMD_GET_LABEL _IOR('H', 235, struct ssd_label)
1716#define SSD_CMD_GET_VERSION _IOR('H', 236, struct ssd_version_info)
1717#define SSD_CMD_GET_TEMPERATURE _IOR('H', 237, int)
1718#define SSD_CMD_GET_BMSTATUS _IOR('H', 238, int)
1719#define SSD_CMD_GET_LABEL2 _IOR('H', 239, void *)
1720
1721
1722#define SSD_CMD_FLUSH _IOW('H', 240, int)
1723#define SSD_CMD_SAVE_MD _IOW('H', 241, int)
1724
1725#define SSD_CMD_SET_WMODE _IOW('H', 242, int)
1726#define SSD_CMD_GET_WMODE _IOR('H', 243, int)
1727#define SSD_CMD_GET_USER_WMODE _IOR('H', 244, int)
1728
1729#define SSD_CMD_DEBUG _IOW('H', 250, struct ssd_debug_info)
1730#define SSD_CMD_DRV_PARAM_INFO _IOR('H', 251, struct ssd_drv_param_info)
1731
a9d1e0c7
KM
1732#define SSD_CMD_CLEAR_WARNING _IOW('H', 260, int)
1733
a6a796ca
HSDT
1734
1735/* log */
1736#define SSD_LOG_MAX_SZ 4096
1737#define SSD_LOG_LEVEL SSD_LOG_LEVEL_NOTICE
1738
1739enum ssd_log_data
1740{
1741 SSD_LOG_DATA_NONE = 0,
1742 SSD_LOG_DATA_LOC,
1743 SSD_LOG_DATA_HEX
1744};
1745
1746typedef struct ssd_log_entry
1747{
1748 union {
1749 struct {
1750 uint32_t page:10;
1751 uint32_t block:14;
1752 uint32_t flash:8;
1753 } loc;
1754 struct {
1755 uint32_t page:12;
1756 uint32_t block:12;
1757 uint32_t flash:8;
1758 } loc1;
1759 uint32_t val;
1760 } data;
1761 uint16_t event:10;
1762 uint16_t mod:6;
1763 uint16_t idx;
1764}__attribute__((packed))ssd_log_entry_t;
1765
1766typedef struct ssd_log
1767{
1768 uint64_t time:56;
1769 uint64_t ctrl_idx:8;
1770 ssd_log_entry_t le;
1771} __attribute__((packed)) ssd_log_t;
1772
1773typedef struct ssd_log_desc
1774{
1775 uint16_t event;
1776 uint8_t level;
1777 uint8_t data;
1778 uint8_t sblock;
1779 uint8_t spage;
1780 char *desc;
1781} __attribute__((packed)) ssd_log_desc_t;
1782
1783#define SSD_LOG_SW_IDX 0xF
1784#define SSD_UNKNOWN_EVENT ((uint16_t)-1)
1785static struct ssd_log_desc ssd_log_desc[] = {
1786 /* event, level, show flash, show block, show page, desc */
1787 {0x0, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_LOC, 0, 0, "Create BBT failure"}, //g3
1788 {0x1, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_LOC, 0, 0, "Read BBT failure"}, //g3
1789 {0x2, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Mark bad block"},
1790 {0x3, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Flush BBT failure"},
1791 {0x4, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"},
1792 {0x7, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "No available blocks"},
1793 {0x8, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Bad EC header"},
1794 {0x9, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_LOC, 1, 0, "Bad VID header"}, //g3
1795 {0xa, SSD_LOG_LEVEL_INFO, SSD_LOG_DATA_LOC, 1, 0, "Wear leveling"},
1796 {0xb, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "WL read back failure"},
1797 {0x11, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Data recovery failure"}, // err
1798 {0x20, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Init: scan mapping table failure"}, // err g3
1799 {0x21, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"},
1800 {0x22, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"},
1801 {0x23, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"},
1802 {0x24, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Merge: read mapping page failure"},
1803 {0x25, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Merge: read back failure"},
1804 {0x26, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"},
1805 {0x27, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_LOC, 1, 1, "Data corrupted for abnormal power down"}, //g3
1806 {0x28, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Merge: mapping page corrupted"},
1807 {0x29, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Init: no mapping page"},
1808 {0x2a, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: mapping pages incomplete"},
1809 {0x2b, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Read back failure after programming failure"}, // err
1810 {0xf1, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Read failure without recovery"}, // err
1811 {0xf2, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 0, 0, "No available blocks"}, // maybe err g3
1812 {0xf3, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 0, "Init: RAID incomplete"}, // err g3
1813 {0xf4, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"},
1814 {0xf5, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read failure in moving data"},
1815 {0xf6, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Program failure"},
1816 {0xf7, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_LOC, 1, 1, "Init: RAID not complete"},
1817 {0xf8, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Init: data moving interrupted"},
1818 {0xfe, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Data inspection failure"},
1819 {0xff, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "IO: ECC failed"},
1820
1821 /* new */
1822 {0x2e, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 0, 0, "No available reserved blocks" }, // err
1823 {0x30, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Init: PMT membership not found"},
1824 {0x31, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Init: PMT corrupted"},
1825 {0x32, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Init: PBT membership not found"},
1826 {0x33, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Init: PBT not found"},
1827 {0x34, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Init: PBT corrupted"},
1828 {0x35, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PMT page read failure"},
1829 {0x36, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PBT page read failure"},
1830 {0x37, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PBT backup page read failure"},
1831 {0x38, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PBMT read failure"},
1832 {0x39, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Init: PBMT scan failure"}, // err
1833 {0x3a, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: first page read failure"},
1834 {0x3b, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Init: first page scan failure"}, // err
1835 {0x3c, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Init: scan unclosed block failure"}, // err
1836 {0x3d, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: write pointer mismatch"},
1837 {0x3e, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PMT recovery: PBMT read failure"},
1838 {0x3f, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Init: PMT recovery: PBMT scan failure"},
1839 {0x40, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "Init: PMT recovery: data page read failure"}, //err
1840 {0x41, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PBT write pointer mismatch"},
1841 {0x42, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: PBT latest version corrupted"},
1842 {0x43, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 0, "Init: too many unclosed blocks"},
1843 {0x44, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Init: PDW block found"},
1844 {0x45, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "Init: more than one PDW block found"}, //err
1845 {0x46, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Init: first page is blank or read failure"},
1846 {0x47, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Init: PDW block not found"},
1847
1848 {0x50, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 0, "Cache: hit error data"}, // err
1849 {0x51, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 0, "Cache: read back failure"}, // err
1850 {0x52, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Cache: unknown command"}, //?
1851 {0x53, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_LOC, 1, 1, "GC/WL read back failure"}, // err
1852
1853 {0x60, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "Erase failure"},
1854
1855 {0x70, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "LPA not matched"},
1856 {0x71, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "PBN not matched"},
1857 {0x72, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read retry failure"},
1858 {0x73, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Need raid recovery"},
1859 {0x74, SSD_LOG_LEVEL_INFO, SSD_LOG_DATA_LOC, 1, 1, "Need read retry"},
1860 {0x75, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read invalid data page"},
1861 {0x76, SSD_LOG_LEVEL_INFO, SSD_LOG_DATA_LOC, 1, 1, "ECC error, data in cache, PBN matched"},
1862 {0x77, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "ECC error, data in cache, PBN not matched"},
1863 {0x78, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "ECC error, data in flash, PBN not matched"},
1864 {0x79, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "ECC ok, data in cache, LPA not matched"},
1865 {0x7a, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "ECC ok, data in flash, LPA not matched"},
1866 {0x7b, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID data in cache, LPA not matched"},
1867 {0x7c, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID data in flash, LPA not matched"},
1868 {0x7d, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read data page status error"},
1869 {0x7e, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read blank page"},
1870 {0x7f, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Access flash timeout"},
1871
1872 {0x80, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "EC overflow"},
1873 {0x81, SSD_LOG_LEVEL_INFO, SSD_LOG_DATA_NONE, 0, 0, "Scrubbing completed"},
1874 {0x82, SSD_LOG_LEVEL_INFO, SSD_LOG_DATA_LOC, 1, 0, "Unstable block(too much bit flip)"},
1875 {0x83, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "GC: ram error"}, //?
1876 {0x84, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "GC: one PBMT read failure"},
1877
1878 {0x88, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "GC: mark bad block"},
1879 {0x89, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 0, "GC: invalid page count error"}, // maybe err
1880 {0x8a, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_NONE, 0, 0, "Warning: Bad Block close to limit"},
1881 {0x8b, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "Error: Bad Block over limit"},
1882 {0x8c, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_NONE, 0, 0, "Warning: P/E cycles close to limit"},
1883 {0x8d, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "Error: P/E cycles over limit"},
1884
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KM
1885 {0x90, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Warning: Over temperature"}, //90
1886 {0x91, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Info: Temperature is OK"}, //80
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HSDT
1887 {0x92, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_NONE, 0, 0, "Battery fault"},
1888 {0x93, SSD_LOG_LEVEL_WARNING, SSD_LOG_DATA_NONE, 0, 0, "SEU fault"}, //err
1889 {0x94, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "DDR error"}, //err
1890 {0x95, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "Controller serdes error"}, //err
1891 {0x96, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "Bridge serdes 1 error"}, //err
1892 {0x97, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_NONE, 0, 0, "Bridge serdes 2 error"}, //err
1893 {0x98, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "SEU fault (corrected)"}, //err
1894 {0x99, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Battery is OK"},
a9d1e0c7 1895 {0x9a, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Info: Temperature close to limit"}, //85
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HSDT
1896
1897 {0x9b, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "SEU fault address (low)"},
1898 {0x9c, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "SEU fault address (high)"},
1899 {0x9d, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "I2C fault" },
1900 {0x9e, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "DDR single bit error" },
1901 {0x9f, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Board voltage fault" },
1902
1903 {0xa0, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "LPA not matched"},
1904 {0xa1, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Re-read data in cache"},
1905 {0xa2, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read blank page"},
1906 {0xa3, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: Read blank page"},
1907 {0xa4, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: new data in cache"},
1908 {0xa5, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: PBN not matched"},
1909 {0xa6, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Read data with error flag"},
1910 {0xa7, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: recoverd data with error flag"},
1911 {0xa8, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Blank page in cache, PBN matched"},
1912 {0xa9, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: Blank page in cache, PBN matched"},
1913 {0xaa, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 0, 0, "Flash init failure"},
1914 {0xab, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "Mapping table recovery failure"},
1915 {0xac, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_LOC, 1, 1, "RAID recovery: ECC failed"},
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KM
1916 {0xb0, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Warning: Temperature is 95 degrees centigrade"},
1917 {0xb1, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Warning: Temperature is 100 degrees centigrade"},
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HSDT
1918
1919 {0x300, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "CMD timeout"},
1920 {0x301, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Power on"},
1921 {0x302, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Power off"},
1922 {0x303, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Clear log"},
1923 {0x304, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Set capacity"},
1924 {0x305, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Clear data"},
1925 {0x306, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "BM safety status"},
1926 {0x307, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "I/O error"},
1927 {0x308, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "CMD error"},
1928 {0x309, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Set wmode"},
1929 {0x30a, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "DDR init failed" },
1930 {0x30b, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "PCIe link status" },
1931 {0x30c, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "Controller reset sync error" },
1932 {0x30d, SSD_LOG_LEVEL_ERR, SSD_LOG_DATA_HEX, 0, 0, "Clock fault" },
1933 {0x30e, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "FPGA voltage fault status" },
1934 {0x30f, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Set capacity finished"},
1935 {0x310, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Clear data finished"},
1936 {0x311, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Reset"},
1937 {0x312, SSD_LOG_LEVEL_WARNING,SSD_LOG_DATA_HEX, 0, 0, "CAP: voltage fault"},
1938 {0x313, SSD_LOG_LEVEL_WARNING,SSD_LOG_DATA_NONE, 0, 0, "CAP: learn fault"},
1939 {0x314, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "CAP status"},
1940 {0x315, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "Board voltage fault status"},
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KM
1941 {0x316, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Info: Inlet temperature is 55 degrees centigrade"}, //55
1942 {0x317, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Info: Inlet temperature is 50 degrees centigrade"}, //50
1943 {0x318, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Info: Flash over temperature"}, //70
1944 {0x319, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Info: Flash temperature is OK"}, //65
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HSDT
1945 {0x31a, SSD_LOG_LEVEL_WARNING,SSD_LOG_DATA_NONE, 0, 0, "CAP: short circuit"},
1946 {0x31b, SSD_LOG_LEVEL_WARNING,SSD_LOG_DATA_HEX, 0, 0, "Sensor fault"},
1947 {0x31c, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Erase all data"},
1948 {0x31d, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_NONE, 0, 0, "Erase all data finished"},
1949
1950 {SSD_UNKNOWN_EVENT, SSD_LOG_LEVEL_NOTICE, SSD_LOG_DATA_HEX, 0, 0, "unknown event"},
1951};
1952/* */
1953#define SSD_LOG_OVER_TEMP 0x90
1954#define SSD_LOG_NORMAL_TEMP 0x91
1955#define SSD_LOG_WARN_TEMP 0x9a
1956#define SSD_LOG_SEU_FAULT 0x93
1957#define SSD_LOG_SEU_FAULT1 0x98
1958#define SSD_LOG_BATTERY_FAULT 0x92
1959#define SSD_LOG_BATTERY_OK 0x99
1960#define SSD_LOG_BOARD_VOLT_FAULT 0x9f
1961
1962/* software log */
1963#define SSD_LOG_TIMEOUT 0x300
1964#define SSD_LOG_POWER_ON 0x301
1965#define SSD_LOG_POWER_OFF 0x302
1966#define SSD_LOG_CLEAR_LOG 0x303
1967#define SSD_LOG_SET_CAPACITY 0x304
1968#define SSD_LOG_CLEAR_DATA 0x305
1969#define SSD_LOG_BM_SFSTATUS 0x306
1970#define SSD_LOG_EIO 0x307
1971#define SSD_LOG_ECMD 0x308
1972#define SSD_LOG_SET_WMODE 0x309
1973#define SSD_LOG_DDR_INIT_ERR 0x30a
1974#define SSD_LOG_PCIE_LINK_STATUS 0x30b
1975#define SSD_LOG_CTRL_RST_SYNC 0x30c
1976#define SSD_LOG_CLK_FAULT 0x30d
1977#define SSD_LOG_VOLT_FAULT 0x30e
1978#define SSD_LOG_SET_CAPACITY_END 0x30F
1979#define SSD_LOG_CLEAR_DATA_END 0x310
1980#define SSD_LOG_RESET 0x311
1981#define SSD_LOG_CAP_VOLT_FAULT 0x312
1982#define SSD_LOG_CAP_LEARN_FAULT 0x313
1983#define SSD_LOG_CAP_STATUS 0x314
1984#define SSD_LOG_VOLT_STATUS 0x315
1985#define SSD_LOG_INLET_OVER_TEMP 0x316
1986#define SSD_LOG_INLET_NORMAL_TEMP 0x317
1987#define SSD_LOG_FLASH_OVER_TEMP 0x318
1988#define SSD_LOG_FLASH_NORMAL_TEMP 0x319
1989#define SSD_LOG_CAP_SHORT_CIRCUIT 0x31a
1990#define SSD_LOG_SENSOR_FAULT 0x31b
1991#define SSD_LOG_ERASE_ALL 0x31c
1992#define SSD_LOG_ERASE_ALL_END 0x31d
1993
1994
1995/* sw log fifo depth */
1996#define SSD_LOG_FIFO_SZ 1024
1997
1998
1999/* done queue */
2000static DEFINE_PER_CPU(struct list_head, ssd_doneq);
2001static DEFINE_PER_CPU(struct tasklet_struct, ssd_tasklet);
2002
2003
2004/* unloading driver */
2005static volatile int ssd_exiting = 0;
2006
2007#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12))
2008static struct class_simple *ssd_class;
2009#else
2010static struct class *ssd_class;
2011#endif
2012
2013static int ssd_cmajor = SSD_CMAJOR;
2014
2015/* ssd block device major, minors */
2016static int ssd_major = SSD_MAJOR;
2017static int ssd_major_sl = SSD_MAJOR_SL;
2018static int ssd_minors = SSD_MINORS;
2019
2020/* ssd device list */
2021static struct list_head ssd_list;
2022static unsigned long ssd_index_bits[SSD_MAX_DEV / BITS_PER_LONG + 1];
2023static unsigned long ssd_index_bits_sl[SSD_MAX_DEV / BITS_PER_LONG + 1];
2024static atomic_t ssd_nr;
2025
2026/* module param */
2027enum ssd_drv_mode
2028{
2029 SSD_DRV_MODE_STANDARD = 0, /* full */
2030 SSD_DRV_MODE_DEBUG = 2, /* debug */
2031 SSD_DRV_MODE_BASE /* base only */
2032};
2033
2034enum ssd_int_mode
2035{
2036 SSD_INT_LEGACY = 0,
2037 SSD_INT_MSI,
2038 SSD_INT_MSIX
2039};
2040
2041#if (defined SSD_MSIX)
2042#define SSD_INT_MODE_DEFAULT SSD_INT_MSIX
2043#elif (defined SSD_MSI)
2044#define SSD_INT_MODE_DEFAULT SSD_INT_MSI
2045#else
2046/* auto select the defaut int mode according to the kernel version*/
2047/* suse 11 sp1 irqbalance bug: use msi instead*/
2048#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) || (defined RHEL_MAJOR && RHEL_MAJOR >= 6) || (defined RHEL_MAJOR && RHEL_MAJOR == 5 && RHEL_MINOR >= 5))
2049#define SSD_INT_MODE_DEFAULT SSD_INT_MSIX
2050#else
2051#define SSD_INT_MODE_DEFAULT SSD_INT_MSI
2052#endif
2053#endif
2054
2055static int mode = SSD_DRV_MODE_STANDARD;
2056static int status_mask = 0xFF;
2057static int int_mode = SSD_INT_MODE_DEFAULT;
2058static int threaded_irq = 0;
2059static int log_level = SSD_LOG_LEVEL_WARNING;
2060static int ot_protect = 1;
2061static int wmode = SSD_WMODE_DEFAULT;
2062static int finject = 0;
2063
2064module_param(mode, int, 0);
2065module_param(status_mask, int, 0);
2066module_param(int_mode, int, 0);
2067module_param(threaded_irq, int, 0);
2068module_param(log_level, int, 0);
2069module_param(ot_protect, int, 0);
2070module_param(wmode, int, 0);
2071module_param(finject, int, 0);
2072
2073
2074MODULE_PARM_DESC(mode, "driver mode, 0 - standard, 1 - debug, 2 - debug without IO, 3 - basic debug mode");
2075MODULE_PARM_DESC(status_mask, "command status mask, 0 - without command error, 0xff - with command error");
2076MODULE_PARM_DESC(int_mode, "preferred interrupt mode, 0 - legacy, 1 - msi, 2 - msix");
2077MODULE_PARM_DESC(threaded_irq, "threaded irq, 0 - normal irq, 1 - threaded irq");
2078MODULE_PARM_DESC(log_level, "log level to display, 0 - info and above, 1 - notice and above, 2 - warning and above, 3 - error only");
2079MODULE_PARM_DESC(ot_protect, "over temperature protect, 0 - disable, 1 - enable");
2080MODULE_PARM_DESC(wmode, "write mode, 0 - write buffer (with risk for the 6xx firmware), 1 - write buffer ex, 2 - write through, 3 - auto, 4 - default");
2081MODULE_PARM_DESC(finject, "enable fault simulation, 0 - off, 1 - on, for debug purpose only");
2082
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KM
2083// API adaption layer
2084static inline void ssd_bio_endio(struct bio *bio, int error)
2085{
2086#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
2087 bio->bi_error = error;
2088 bio_endio(bio);
2089#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24))
2090 bio_endio(bio, error);
2091#else
2092 bio_endio(bio, bio->bi_size, error);
2093#endif
2094}
2095
2096static inline int ssd_bio_has_discard(struct bio *bio)
2097{
2098#ifndef SSD_TRIM
2099 return 0;
2100#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4,8,0))
39e50a52 2101 return bio_op(bio) == REQ_OP_DISCARD;
a9d1e0c7
KM
2102#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,36))
2103 return bio->bi_rw & REQ_DISCARD;
2104#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32))
2105 return bio_rw_flagged(bio, BIO_RW_DISCARD);
2106#else
2107 return 0;
2108#endif
2109}
2110
2111static inline int ssd_bio_has_flush(struct bio *bio)
2112{
2113#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,8,0))
39e50a52 2114 return bio_op(bio) == REQ_OP_FLUSH;
a9d1e0c7
KM
2115#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,37))
2116 return bio->bi_rw & REQ_FLUSH;
2117#else
2118 return 0;
2119#endif
2120}
2121
2122static inline int ssd_bio_has_fua(struct bio *bio)
2123{
2124#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,8,0))
2125 return bio->bi_opf & REQ_FUA;
2126#else
2127 return bio->bi_rw & REQ_FUA;
2128#endif
2129}
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HSDT
2130
2131#ifndef MODULE
2132static int __init ssd_drv_mode(char *str)
2133{
2134 mode = (int)simple_strtoul(str, NULL, 0);
2135
2136 return 1;
2137}
2138
2139static int __init ssd_status_mask(char *str)
2140{
2141 status_mask = (int)simple_strtoul(str, NULL, 16);
2142
2143 return 1;
2144}
2145
2146static int __init ssd_int_mode(char *str)
2147{
2148 int_mode = (int)simple_strtoul(str, NULL, 0);
2149
2150 return 1;
2151}
2152
2153static int __init ssd_threaded_irq(char *str)
2154{
2155 threaded_irq = (int)simple_strtoul(str, NULL, 0);
2156
2157 return 1;
2158}
2159
2160static int __init ssd_log_level(char *str)
2161{
2162 log_level = (int)simple_strtoul(str, NULL, 0);
2163
2164 return 1;
2165}
2166
2167static int __init ssd_ot_protect(char *str)
2168{
2169 ot_protect = (int)simple_strtoul(str, NULL, 0);
2170
2171 return 1;
2172}
2173
2174static int __init ssd_wmode(char *str)
2175{
2176 wmode = (int)simple_strtoul(str, NULL, 0);
2177
2178 return 1;
2179}
2180
2181static int __init ssd_finject(char *str)
2182{
2183 finject = (int)simple_strtoul(str, NULL, 0);
2184
2185 return 1;
2186}
2187
2188__setup(MODULE_NAME"_mode=", ssd_drv_mode);
2189__setup(MODULE_NAME"_status_mask=", ssd_status_mask);
2190__setup(MODULE_NAME"_int_mode=", ssd_int_mode);
2191__setup(MODULE_NAME"_threaded_irq=", ssd_threaded_irq);
2192__setup(MODULE_NAME"_log_level=", ssd_log_level);
2193__setup(MODULE_NAME"_ot_protect=", ssd_ot_protect);
2194__setup(MODULE_NAME"_wmode=", ssd_wmode);
2195__setup(MODULE_NAME"_finject=", ssd_finject);
2196#endif
2197
2198
2199#ifdef CONFIG_PROC_FS
2200#include <linux/proc_fs.h>
2201#include <asm/uaccess.h>
2202
2203#define SSD_PROC_DIR MODULE_NAME
2204#define SSD_PROC_INFO "info"
2205
2206static struct proc_dir_entry *ssd_proc_dir = NULL;
2207static struct proc_dir_entry *ssd_proc_info = NULL;
2208
2209#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0))
2210static int ssd_proc_read(char *page, char **start,
2211 off_t off, int count, int *eof, void *data)
2212{
2213 struct ssd_device *dev = NULL;
2214 struct ssd_device *n = NULL;
2215 uint64_t size;
2216 int idx;
2217 int len = 0;
2218 //char type; //xx
2219
a9d1e0c7 2220 if (ssd_exiting || off != 0) {
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HSDT
2221 return 0;
2222 }
2223
2224 len += snprintf((page + len), (count - len), "Driver Version:\t%s\n", DRIVER_VERSION);
2225
2226 list_for_each_entry_safe(dev, n, &ssd_list, list) {
2227 idx = dev->idx + 1;
2228 size = dev->hw_info.size ;
2229 do_div(size, 1000000000);
2230
2231 len += snprintf((page + len), (count - len), "\n");
2232
2233 len += snprintf((page + len), (count - len), "HIO %d Size:\t%uGB\n", idx, (uint32_t)size);
2234
2235 len += snprintf((page + len), (count - len), "HIO %d Bridge FW VER:\t%03X\n", idx, dev->hw_info.bridge_ver);
2236 if (dev->hw_info.ctrl_ver != 0) {
2237 len += snprintf((page + len), (count - len), "HIO %d Controller FW VER:\t%03X\n", idx, dev->hw_info.ctrl_ver);
2238 }
2239
2240 len += snprintf((page + len), (count - len), "HIO %d PCB VER:\t.%c\n", idx, dev->hw_info.pcb_ver);
2241
2242 if (dev->hw_info.upper_pcb_ver >= 'A') {
2243 len += snprintf((page + len), (count - len), "HIO %d Upper PCB VER:\t.%c\n", idx, dev->hw_info.upper_pcb_ver);
2244 }
2245
2246 len += snprintf((page + len), (count - len), "HIO %d Device:\t%s\n", idx, dev->name);
2247 }
2248
a9d1e0c7 2249 *eof = 1;
a6a796ca
HSDT
2250 return len;
2251}
2252
2253#else
2254
2255static int ssd_proc_show(struct seq_file *m, void *v)
2256{
2257 struct ssd_device *dev = NULL;
2258 struct ssd_device *n = NULL;
2259 uint64_t size;
2260 int idx;
2261
2262 if (ssd_exiting) {
2263 return 0;
2264 }
2265
2266 seq_printf(m, "Driver Version:\t%s\n", DRIVER_VERSION);
2267
2268 list_for_each_entry_safe(dev, n, &ssd_list, list) {
2269 idx = dev->idx + 1;
2270 size = dev->hw_info.size ;
2271 do_div(size, 1000000000);
2272
2273 seq_printf(m, "\n");
2274
2275 seq_printf(m, "HIO %d Size:\t%uGB\n", idx, (uint32_t)size);
2276
2277 seq_printf(m, "HIO %d Bridge FW VER:\t%03X\n", idx, dev->hw_info.bridge_ver);
2278 if (dev->hw_info.ctrl_ver != 0) {
2279 seq_printf(m, "HIO %d Controller FW VER:\t%03X\n", idx, dev->hw_info.ctrl_ver);
2280 }
2281
2282 seq_printf(m, "HIO %d PCB VER:\t.%c\n", idx, dev->hw_info.pcb_ver);
2283
2284 if (dev->hw_info.upper_pcb_ver >= 'A') {
2285 seq_printf(m, "HIO %d Upper PCB VER:\t.%c\n", idx, dev->hw_info.upper_pcb_ver);
2286 }
2287
2288 seq_printf(m, "HIO %d Device:\t%s\n", idx, dev->name);
2289 }
2290
2291 return 0;
2292}
2293
2294static int ssd_proc_open(struct inode *inode, struct file *file)
2295{
2296#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3,9,0))
2297 return single_open(file, ssd_proc_show, PDE(inode)->data);
2298#else
2299 return single_open(file, ssd_proc_show, PDE_DATA(inode));
2300#endif
2301}
2302
2303static const struct file_operations ssd_proc_fops = {
2304 .open = ssd_proc_open,
2305 .read = seq_read,
2306 .llseek = seq_lseek,
2307 .release = single_release,
2308};
2309#endif
2310
2311
2312static void ssd_cleanup_proc(void)
2313{
2314 if (ssd_proc_info) {
2315 remove_proc_entry(SSD_PROC_INFO, ssd_proc_dir);
2316 ssd_proc_info = NULL;
2317 }
2318 if (ssd_proc_dir) {
2319 remove_proc_entry(SSD_PROC_DIR, NULL);
2320 ssd_proc_dir = NULL;
2321 }
2322}
2323static int ssd_init_proc(void)
2324{
2325 ssd_proc_dir = proc_mkdir(SSD_PROC_DIR, NULL);
2326 if (!ssd_proc_dir)
2327 goto out_proc_mkdir;
2328
2329#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0))
2330 ssd_proc_info = create_proc_entry(SSD_PROC_INFO, S_IFREG | S_IRUGO | S_IWUSR, ssd_proc_dir);
2331 if (!ssd_proc_info)
2332 goto out_create_proc_entry;
2333
2334 ssd_proc_info->read_proc = ssd_proc_read;
2335
2336/* kernel bug */
2337#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,30))
2338 ssd_proc_info->owner = THIS_MODULE;
2339#endif
2340#else
2341 ssd_proc_info = proc_create(SSD_PROC_INFO, 0600, ssd_proc_dir, &ssd_proc_fops);
2342 if (!ssd_proc_info)
2343 goto out_create_proc_entry;
2344#endif
2345
2346 return 0;
2347
2348out_create_proc_entry:
2349 remove_proc_entry(SSD_PROC_DIR, NULL);
2350out_proc_mkdir:
2351 return -ENOMEM;
2352}
2353
2354#else
2355static void ssd_cleanup_proc(void)
2356{
2357 return;
2358}
2359static int ssd_init_proc(void)
2360{
2361 return 0;
2362}
2363#endif /* CONFIG_PROC_FS */
2364
2365/* sysfs */
2366static void ssd_unregister_sysfs(struct ssd_device *dev)
2367{
2368 return;
2369}
2370
2371static int ssd_register_sysfs(struct ssd_device *dev)
2372{
2373 return 0;
2374}
2375
2376static void ssd_cleanup_sysfs(void)
2377{
2378 return;
2379}
2380
2381static int ssd_init_sysfs(void)
2382{
2383 return 0;
2384}
2385
2386static inline void ssd_put_index(int slave, int index)
2387{
2388 unsigned long *index_bits = ssd_index_bits;
2389
2390 if (slave) {
2391 index_bits = ssd_index_bits_sl;
2392 }
2393
2394 if (test_and_clear_bit(index, index_bits)) {
2395 atomic_dec(&ssd_nr);
2396 }
2397}
2398
2399static inline int ssd_get_index(int slave)
2400{
2401 unsigned long *index_bits = ssd_index_bits;
2402 int index;
2403
2404 if (slave) {
2405 index_bits = ssd_index_bits_sl;
2406 }
2407
2408find_index:
2409 if ((index = find_first_zero_bit(index_bits, SSD_MAX_DEV)) >= SSD_MAX_DEV) {
2410 return -1;
2411 }
2412
2413 if (test_and_set_bit(index, index_bits)) {
2414 goto find_index;
2415 }
2416
2417 atomic_inc(&ssd_nr);
2418
2419 return index;
2420}
2421
2422static void ssd_cleanup_index(void)
2423{
2424 return;
2425}
2426
2427static int ssd_init_index(void)
2428{
2429 INIT_LIST_HEAD(&ssd_list);
2430 atomic_set(&ssd_nr, 0);
2431 memset(ssd_index_bits, 0, (SSD_MAX_DEV / BITS_PER_LONG + 1));
2432 memset(ssd_index_bits_sl, 0, (SSD_MAX_DEV / BITS_PER_LONG + 1));
2433
2434 return 0;
2435}
2436
2437static void ssd_set_dev_name(char *name, size_t size, int idx)
2438{
2439 if(idx < SSD_ALPHABET_NUM) {
2440 snprintf(name, size, "%c", 'a'+idx);
2441 } else {
2442 idx -= SSD_ALPHABET_NUM;
2443 snprintf(name, size, "%c%c", 'a'+(idx/SSD_ALPHABET_NUM), 'a'+(idx%SSD_ALPHABET_NUM));
2444 }
2445}
2446
2447/* pci register r&w */
2448static inline void ssd_reg_write(void *addr, uint64_t val)
2449{
2450 iowrite32((uint32_t)val, addr);
2451 iowrite32((uint32_t)(val >> 32), addr + 4);
2452 wmb();
2453}
2454
2455static inline uint64_t ssd_reg_read(void *addr)
2456{
2457 uint64_t val;
2458 uint32_t val_lo, val_hi;
2459
2460 val_lo = ioread32(addr);
2461 val_hi = ioread32(addr + 4);
2462
2463 rmb();
2464 val = val_lo | ((uint64_t)val_hi << 32);
2465
2466 return val;
2467}
2468
2469
2470#define ssd_reg32_write(addr, val) writel(val, addr)
2471#define ssd_reg32_read(addr) readl(addr)
2472
2473/* alarm led */
2474static void ssd_clear_alarm(struct ssd_device *dev)
2475{
2476 uint32_t val;
2477
2478 if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) {
2479 return;
2480 }
2481
2482 val = ssd_reg32_read(dev->ctrlp + SSD_LED_REG);
2483
2484 /* firmware control */
2485 val &= ~0x2;
2486
2487 ssd_reg32_write(dev->ctrlp + SSD_LED_REG, val);
2488}
2489
2490static void ssd_set_alarm(struct ssd_device *dev)
2491{
2492 uint32_t val;
2493
2494 if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) {
2495 return;
2496 }
2497
2498 val = ssd_reg32_read(dev->ctrlp + SSD_LED_REG);
2499
2500 /* light up */
2501 val &= ~0x1;
2502 /* software control */
2503 val |= 0x2;
2504
2505 ssd_reg32_write(dev->ctrlp + SSD_LED_REG, val);
2506}
2507
2508#define u32_swap(x) \
2509 ((uint32_t)( \
2510 (((uint32_t)(x) & (uint32_t)0x000000ffUL) << 24) | \
2511 (((uint32_t)(x) & (uint32_t)0x0000ff00UL) << 8) | \
2512 (((uint32_t)(x) & (uint32_t)0x00ff0000UL) >> 8) | \
2513 (((uint32_t)(x) & (uint32_t)0xff000000UL) >> 24)))
2514
2515#define u16_swap(x) \
2516 ((uint16_t)( \
2517 (((uint16_t)(x) & (uint16_t)0x00ff) << 8) | \
2518 (((uint16_t)(x) & (uint16_t)0xff00) >> 8) ))
2519
2520
2521#if 0
2522/* No lock, for init only*/
2523static int ssd_spi_read_id(struct ssd_device *dev, uint32_t *id)
2524{
2525 uint32_t val;
2526 unsigned long st;
2527 int ret = 0;
2528
2529 if (!dev || !id) {
2530 return -EINVAL;
2531 }
2532
2533 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_READ_ID);
2534
2535 val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY);
2536 val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY);
2537 val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY);
2538 val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY);
2539
2540 st = jiffies;
2541 for (;;) {
2542 val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY);
2543 if (val == 0x1000000) {
2544 break;
2545 }
2546
2547 if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) {
2548 ret = -ETIMEDOUT;
2549 goto out;
2550 }
2551 cond_resched();
2552 }
2553
2554 val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_ID);
2555 *id = val;
2556
2557out:
2558 return ret;
2559}
2560#endif
2561
2562/* spi access */
2563static int ssd_init_spi(struct ssd_device *dev)
2564{
2565 uint32_t val;
2566 unsigned long st;
2567 int ret = 0;
2568
2569 mutex_lock(&dev->spi_mutex);
2570 st = jiffies;
2571 for(;;) {
2572 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_READ_STATUS);
2573
2574 do {
2575 val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY);
2576
2577 if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) {
2578 ret = -ETIMEDOUT;
2579 goto out;
2580 }
2581 cond_resched();
2582 } while (val != 0x1000000);
2583
2584 val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_STATUS);
2585 if (!(val & 0x1)) {
2586 break;
2587 }
2588
2589 if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) {
2590 ret = -ETIMEDOUT;
2591 goto out;
2592 }
2593 cond_resched();
2594 }
2595
2596out:
2597 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) {
2598 if (val & 0x1) {
2599 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_CLSR);
2600 }
2601 }
2602 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_DISABLE);
2603 mutex_unlock(&dev->spi_mutex);
2604
2605 ret = 0;
2606
2607 return ret;
2608}
2609
2610static int ssd_spi_page_read(struct ssd_device *dev, void *buf, uint32_t off, uint32_t size)
2611{
2612 uint32_t val;
2613 uint32_t rlen = 0;
2614 unsigned long st;
2615 int ret = 0;
2616
2617 if (!dev || !buf) {
2618 return -EINVAL;
2619 }
2620
2621 if ((off % sizeof(uint32_t)) != 0 || (size % sizeof(uint32_t)) != 0 || size == 0 ||
2622 ((uint64_t)off + (uint64_t)size) > dev->rom_info.size || size > dev->rom_info.page_size) {
2623 return -EINVAL;
2624 }
2625
2626 mutex_lock(&dev->spi_mutex);
2627 while (rlen < size) {
2628 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD_HI, ((off + rlen) >> 24));
2629 wmb();
2630 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, (((off + rlen) << 8) | SSD_SPI_CMD_READ));
2631
2632 (void)ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY);
2633 (void)ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY);
2634 (void)ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY);
2635 (void)ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY);
2636
2637 st = jiffies;
2638 for (;;) {
2639 val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY);
2640 if (val == 0x1000000) {
2641 break;
2642 }
2643
2644 if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) {
2645 ret = -ETIMEDOUT;
2646 goto out;
2647 }
2648 cond_resched();
2649 }
2650
2651 val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_RDATA);
2652 *(uint32_t *)(buf + rlen)= u32_swap(val);
2653
2654 rlen += sizeof(uint32_t);
2655 }
2656
2657out:
2658 mutex_unlock(&dev->spi_mutex);
2659 return ret;
2660}
2661
2662static int ssd_spi_page_write(struct ssd_device *dev, void *buf, uint32_t off, uint32_t size)
2663{
2664 uint32_t val;
2665 uint32_t wlen;
2666 unsigned long st;
2667 int i;
2668 int ret = 0;
2669
2670 if (!dev || !buf) {
2671 return -EINVAL;
2672 }
2673
2674 if ((off % sizeof(uint32_t)) != 0 || (size % sizeof(uint32_t)) != 0 || size == 0 ||
2675 ((uint64_t)off + (uint64_t)size) > dev->rom_info.size || size > dev->rom_info.page_size ||
2676 (off / dev->rom_info.page_size) != ((off + size - 1) / dev->rom_info.page_size)) {
2677 return -EINVAL;
2678 }
2679
2680 mutex_lock(&dev->spi_mutex);
2681
2682 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_ENABLE);
2683
2684 wlen = size / sizeof(uint32_t);
2685 for (i=0; i<(int)wlen; i++) {
2686 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_WDATA, u32_swap(*((uint32_t *)buf + i)));
2687 }
2688
2689 wmb();
2690 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD_HI, (off >> 24));
2691 wmb();
2692 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, ((off << 8) | SSD_SPI_CMD_PROGRAM));
2693
2694 udelay(1);
2695
2696 st = jiffies;
2697 for (;;) {
2698 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_READ_STATUS);
2699 do {
2700 val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY);
2701
2702 if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) {
2703 ret = -ETIMEDOUT;
2704 goto out;
2705 }
2706 cond_resched();
2707 } while (val != 0x1000000);
2708
2709 val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_STATUS);
2710 if (!(val & 0x1)) {
2711 break;
2712 }
2713
2714 if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) {
2715 ret = -ETIMEDOUT;
2716 goto out;
2717 }
2718 cond_resched();
2719 }
2720
2721 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) {
2722 if ((val >> 6) & 0x1) {
2723 ret = -EIO;
2724 goto out;
2725 }
2726 }
2727
2728out:
2729 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) {
2730 if (val & 0x1) {
2731 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_CLSR);
2732 }
2733 }
2734 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_DISABLE);
2735
2736 mutex_unlock(&dev->spi_mutex);
2737
2738 return ret;
2739}
2740
2741static int ssd_spi_block_erase(struct ssd_device *dev, uint32_t off)
2742{
2743 uint32_t val;
2744 unsigned long st;
2745 int ret = 0;
2746
2747 if (!dev) {
2748 return -EINVAL;
2749 }
2750
2751 if ((off % dev->rom_info.block_size) != 0 || off >= dev->rom_info.size) {
2752 return -EINVAL;
2753 }
2754
2755 mutex_lock(&dev->spi_mutex);
2756
2757 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_ENABLE);
2758 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_ENABLE);
2759
2760 wmb();
2761 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD_HI, (off >> 24));
2762 wmb();
2763 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, ((off << 8) | SSD_SPI_CMD_ERASE));
2764
2765 st = jiffies;
2766 for (;;) {
2767 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_READ_STATUS);
2768
2769 do {
2770 val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_READY);
2771
2772 if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) {
2773 ret = -ETIMEDOUT;
2774 goto out;
2775 }
2776 cond_resched();
2777 } while (val != 0x1000000);
2778
2779 val = ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_STATUS);
2780 if (!(val & 0x1)) {
2781 break;
2782 }
2783
2784 if (time_after(jiffies, (st + SSD_SPI_TIMEOUT))) {
2785 ret = -ETIMEDOUT;
2786 goto out;
2787 }
2788 cond_resched();
2789 }
2790
2791 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) {
2792 if ((val >> 5) & 0x1) {
2793 ret = -EIO;
2794 goto out;
2795 }
2796 }
2797
2798out:
2799 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) {
2800 if (val & 0x1) {
2801 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_CLSR);
2802 }
2803 }
2804 ssd_reg32_write(dev->ctrlp + SSD_SPI_REG_CMD, SSD_SPI_CMD_W_DISABLE);
2805
2806 mutex_unlock(&dev->spi_mutex);
2807
2808 return ret;
2809}
2810
2811static int ssd_spi_read(struct ssd_device *dev, void *buf, uint32_t off, uint32_t size)
2812{
2813 uint32_t len = 0;
2814 uint32_t roff;
2815 uint32_t rsize;
2816 int ret = 0;
2817
2818 if (!dev || !buf) {
2819 return -EINVAL;
2820 }
2821
2822 if ((off % sizeof(uint32_t)) != 0 || (size % sizeof(uint32_t)) != 0 || size == 0 ||
2823 ((uint64_t)off + (uint64_t)size) > dev->rom_info.size) {
2824 return -EINVAL;
2825 }
2826
2827 while (len < size) {
2828 roff = (off + len) % dev->rom_info.page_size;
2829 rsize = dev->rom_info.page_size - roff;
2830 if ((size - len) < rsize) {
2831 rsize = (size - len);
2832 }
2833 roff = off + len;
2834
2835 ret = ssd_spi_page_read(dev, (buf + len), roff, rsize);
2836 if (ret) {
2837 goto out;
2838 }
2839
2840 len += rsize;
2841
2842 cond_resched();
2843 }
2844
2845out:
2846 return ret;
2847}
2848
2849static int ssd_spi_write(struct ssd_device *dev, void *buf, uint32_t off, uint32_t size)
2850{
2851 uint32_t len = 0;
2852 uint32_t woff;
2853 uint32_t wsize;
2854 int ret = 0;
2855
2856 if (!dev || !buf) {
2857 return -EINVAL;
2858 }
2859
2860 if ((off % sizeof(uint32_t)) != 0 || (size % sizeof(uint32_t)) != 0 || size == 0 ||
2861 ((uint64_t)off + (uint64_t)size) > dev->rom_info.size) {
2862 return -EINVAL;
2863 }
2864
2865 while (len < size) {
2866 woff = (off + len) % dev->rom_info.page_size;
2867 wsize = dev->rom_info.page_size - woff;
2868 if ((size - len) < wsize) {
2869 wsize = (size - len);
2870 }
2871 woff = off + len;
2872
2873 ret = ssd_spi_page_write(dev, (buf + len), woff, wsize);
2874 if (ret) {
2875 goto out;
2876 }
2877
2878 len += wsize;
2879
2880 cond_resched();
2881 }
2882
2883out:
2884 return ret;
2885}
2886
2887static int ssd_spi_erase(struct ssd_device *dev, uint32_t off, uint32_t size)
2888{
2889 uint32_t len = 0;
2890 uint32_t eoff;
2891 int ret = 0;
2892
2893 if (!dev) {
2894 return -EINVAL;
2895 }
2896
2897 if (size == 0 || ((uint64_t)off + (uint64_t)size) > dev->rom_info.size ||
2898 (off % dev->rom_info.block_size) != 0 || (size % dev->rom_info.block_size) != 0) {
2899 return -EINVAL;
2900 }
2901
2902 while (len < size) {
2903 eoff = (off + len);
2904
2905 ret = ssd_spi_block_erase(dev, eoff);
2906 if (ret) {
2907 goto out;
2908 }
2909
2910 len += dev->rom_info.block_size;
2911
2912 cond_resched();
2913 }
2914
2915out:
2916 return ret;
2917}
2918
2919/* i2c access */
2920static uint32_t __ssd_i2c_reg32_read(void *addr)
2921{
2922 return ssd_reg32_read(addr);
2923}
2924
2925static void __ssd_i2c_reg32_write(void *addr, uint32_t val)
2926{
2927 ssd_reg32_write(addr, val);
2928 ssd_reg32_read(addr);
2929}
2930
2931static int __ssd_i2c_clear(struct ssd_device *dev, uint8_t saddr)
2932{
2933 ssd_i2c_ctrl_t ctrl;
2934 ssd_i2c_data_t data;
2935 uint8_t status = 0;
2936 int nr_data = 0;
2937 unsigned long st;
2938 int ret = 0;
2939
2940check_status:
2941 ctrl.bits.wdata = 0;
2942 ctrl.bits.addr = SSD_I2C_STATUS_REG;
2943 ctrl.bits.rw = SSD_I2C_CTRL_READ;
2944 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
2945
2946 st = jiffies;
2947 for (;;) {
2948 data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG);
2949 if (data.bits.valid == 0) {
2950 break;
2951 }
2952
2953 /* retry */
2954 if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) {
2955 ret = -ETIMEDOUT;
2956 goto out;
2957 }
2958 cond_resched();
2959 }
2960 status = data.bits.rdata;
2961
2962 if (!(status & 0x4)) {
2963 /* clear read fifo data */
2964 ctrl.bits.wdata = 0;
2965 ctrl.bits.addr = SSD_I2C_DATA_REG;
2966 ctrl.bits.rw = SSD_I2C_CTRL_READ;
2967 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
2968
2969 st = jiffies;
2970 for (;;) {
2971 data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG);
2972 if (data.bits.valid == 0) {
2973 break;
2974 }
2975
2976 /* retry */
2977 if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) {
2978 ret = -ETIMEDOUT;
2979 goto out;
2980 }
2981 cond_resched();
2982 }
2983
2984 nr_data++;
2985 if (nr_data <= SSD_I2C_MAX_DATA) {
2986 goto check_status;
2987 } else {
2988 goto out_reset;
2989 }
2990 }
2991
2992 if (status & 0x3) {
2993 /* clear int */
2994 ctrl.bits.wdata = 0x04;
2995 ctrl.bits.addr = SSD_I2C_CMD_REG;
2996 ctrl.bits.rw = SSD_I2C_CTRL_WRITE;
2997 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
2998 }
2999
3000 if (!(status & 0x8)) {
3001out_reset:
3002 /* reset i2c controller */
3003 ctrl.bits.wdata = 0x0;
3004 ctrl.bits.addr = SSD_I2C_RESET_REG;
3005 ctrl.bits.rw = SSD_I2C_CTRL_WRITE;
3006 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
3007 }
3008
3009out:
3010 return ret;
3011}
3012
3013static int ssd_i2c_write(struct ssd_device *dev, uint8_t saddr, uint8_t size, uint8_t *buf)
3014{
3015 ssd_i2c_ctrl_t ctrl;
3016 ssd_i2c_data_t data;
3017 uint8_t off = 0;
3018 uint8_t status = 0;
3019 unsigned long st;
3020 int ret = 0;
3021
3022 mutex_lock(&dev->i2c_mutex);
3023
3024 ctrl.val = 0;
3025
3026 /* slave addr */
3027 ctrl.bits.wdata = saddr;
3028 ctrl.bits.addr = SSD_I2C_SADDR_REG;
3029 ctrl.bits.rw = SSD_I2C_CTRL_WRITE;
3030 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
3031
3032 /* data */
3033 while (off < size) {
3034 ctrl.bits.wdata = buf[off];
3035 ctrl.bits.addr = SSD_I2C_DATA_REG;
3036 ctrl.bits.rw = SSD_I2C_CTRL_WRITE;
3037 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
3038
3039 off++;
3040 }
3041
3042 /* write */
3043 ctrl.bits.wdata = 0x01;
3044 ctrl.bits.addr = SSD_I2C_CMD_REG;
3045 ctrl.bits.rw = SSD_I2C_CTRL_WRITE;
3046 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
3047
3048 /* wait */
3049 st = jiffies;
3050 for (;;) {
3051 ctrl.bits.wdata = 0;
3052 ctrl.bits.addr = SSD_I2C_STATUS_REG;
3053 ctrl.bits.rw = SSD_I2C_CTRL_READ;
3054 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
3055
3056 for (;;) {
3057 data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG);
3058 if (data.bits.valid == 0) {
3059 break;
3060 }
3061
3062 /* retry */
3063 if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) {
3064 ret = -ETIMEDOUT;
3065 goto out_clear;
3066 }
3067 cond_resched();
3068 }
3069
3070 status = data.bits.rdata;
3071 if (status & 0x1) {
3072 break;
3073 }
3074
3075 if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) {
3076 ret = -ETIMEDOUT;
3077 goto out_clear;
3078 }
3079 cond_resched();
3080 }
3081
3082 if (!(status & 0x1)) {
3083 ret = -1;
3084 goto out_clear;
3085 }
3086
3087 /* busy ? */
3088 if (status & 0x20) {
3089 ret = -2;
3090 goto out_clear;
3091 }
3092
3093 /* ack ? */
3094 if (status & 0x10) {
3095 ret = -3;
3096 goto out_clear;
3097 }
3098
3099 /* clear */
3100out_clear:
3101 if (__ssd_i2c_clear(dev, saddr)) {
3102 if (!ret) ret = -4;
3103 }
3104
3105 mutex_unlock(&dev->i2c_mutex);
3106
3107 return ret;
3108}
3109
3110static int ssd_i2c_read(struct ssd_device *dev, uint8_t saddr, uint8_t size, uint8_t *buf)
3111{
3112 ssd_i2c_ctrl_t ctrl;
3113 ssd_i2c_data_t data;
3114 uint8_t off = 0;
3115 uint8_t status = 0;
3116 unsigned long st;
3117 int ret = 0;
3118
3119 mutex_lock(&dev->i2c_mutex);
3120
3121 ctrl.val = 0;
3122
3123 /* slave addr */
3124 ctrl.bits.wdata = saddr;
3125 ctrl.bits.addr = SSD_I2C_SADDR_REG;
3126 ctrl.bits.rw = SSD_I2C_CTRL_WRITE;
3127 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
3128
3129 /* read len */
3130 ctrl.bits.wdata = size;
3131 ctrl.bits.addr = SSD_I2C_LEN_REG;
3132 ctrl.bits.rw = SSD_I2C_CTRL_WRITE;
3133 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
3134
3135 /* read */
3136 ctrl.bits.wdata = 0x02;
3137 ctrl.bits.addr = SSD_I2C_CMD_REG;
3138 ctrl.bits.rw = SSD_I2C_CTRL_WRITE;
3139 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
3140
3141 /* wait */
3142 st = jiffies;
3143 for (;;) {
3144 ctrl.bits.wdata = 0;
3145 ctrl.bits.addr = SSD_I2C_STATUS_REG;
3146 ctrl.bits.rw = SSD_I2C_CTRL_READ;
3147 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
3148
3149 for (;;) {
3150 data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG);
3151 if (data.bits.valid == 0) {
3152 break;
3153 }
3154
3155 /* retry */
3156 if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) {
3157 ret = -ETIMEDOUT;
3158 goto out_clear;
3159 }
3160 cond_resched();
3161 }
3162
3163 status = data.bits.rdata;
3164 if (status & 0x2) {
3165 break;
3166 }
3167
3168 if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) {
3169 ret = -ETIMEDOUT;
3170 goto out_clear;
3171 }
3172 cond_resched();
3173 }
3174
3175 if (!(status & 0x2)) {
3176 ret = -1;
3177 goto out_clear;
3178 }
3179
3180 /* busy ? */
3181 if (status & 0x20) {
3182 ret = -2;
3183 goto out_clear;
3184 }
3185
3186 /* ack ? */
3187 if (status & 0x10) {
3188 ret = -3;
3189 goto out_clear;
3190 }
3191
3192 /* data */
3193 while (off < size) {
3194 ctrl.bits.wdata = 0;
3195 ctrl.bits.addr = SSD_I2C_DATA_REG;
3196 ctrl.bits.rw = SSD_I2C_CTRL_READ;
3197 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
3198
3199 st = jiffies;
3200 for (;;) {
3201 data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG);
3202 if (data.bits.valid == 0) {
3203 break;
3204 }
3205
3206 /* retry */
3207 if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) {
3208 ret = -ETIMEDOUT;
3209 goto out_clear;
3210 }
3211 cond_resched();
3212 }
3213
3214 buf[off] = data.bits.rdata;
3215
3216 off++;
3217 }
3218
3219 /* clear */
3220out_clear:
3221 if (__ssd_i2c_clear(dev, saddr)) {
3222 if (!ret) ret = -4;
3223 }
3224
3225 mutex_unlock(&dev->i2c_mutex);
3226
3227 return ret;
3228}
3229
3230static int ssd_i2c_write_read(struct ssd_device *dev, uint8_t saddr, uint8_t wsize, uint8_t *wbuf, uint8_t rsize, uint8_t *rbuf)
3231{
3232 ssd_i2c_ctrl_t ctrl;
3233 ssd_i2c_data_t data;
3234 uint8_t off = 0;
3235 uint8_t status = 0;
3236 unsigned long st;
3237 int ret = 0;
3238
3239 mutex_lock(&dev->i2c_mutex);
3240
3241 ctrl.val = 0;
3242
3243 /* slave addr */
3244 ctrl.bits.wdata = saddr;
3245 ctrl.bits.addr = SSD_I2C_SADDR_REG;
3246 ctrl.bits.rw = SSD_I2C_CTRL_WRITE;
3247 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
3248
3249 /* data */
3250 off = 0;
3251 while (off < wsize) {
3252 ctrl.bits.wdata = wbuf[off];
3253 ctrl.bits.addr = SSD_I2C_DATA_REG;
3254 ctrl.bits.rw = SSD_I2C_CTRL_WRITE;
3255 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
3256
3257 off++;
3258 }
3259
3260 /* read len */
3261 ctrl.bits.wdata = rsize;
3262 ctrl.bits.addr = SSD_I2C_LEN_REG;
3263 ctrl.bits.rw = SSD_I2C_CTRL_WRITE;
3264 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
3265
3266 /* write -> read */
3267 ctrl.bits.wdata = 0x03;
3268 ctrl.bits.addr = SSD_I2C_CMD_REG;
3269 ctrl.bits.rw = SSD_I2C_CTRL_WRITE;
3270 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
3271
3272 /* wait */
3273 st = jiffies;
3274 for (;;) {
3275 ctrl.bits.wdata = 0;
3276 ctrl.bits.addr = SSD_I2C_STATUS_REG;
3277 ctrl.bits.rw = SSD_I2C_CTRL_READ;
3278 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
3279
3280 for (;;) {
3281 data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG);
3282 if (data.bits.valid == 0) {
3283 break;
3284 }
3285
3286 /* retry */
3287 if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) {
3288 ret = -ETIMEDOUT;
3289 goto out_clear;
3290 }
3291 cond_resched();
3292 }
3293
3294 status = data.bits.rdata;
3295 if (status & 0x2) {
3296 break;
3297 }
3298
3299 if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) {
3300 ret = -ETIMEDOUT;
3301 goto out_clear;
3302 }
3303 cond_resched();
3304 }
3305
3306 if (!(status & 0x2)) {
3307 ret = -1;
3308 goto out_clear;
3309 }
3310
3311 /* busy ? */
3312 if (status & 0x20) {
3313 ret = -2;
3314 goto out_clear;
3315 }
3316
3317 /* ack ? */
3318 if (status & 0x10) {
3319 ret = -3;
3320 goto out_clear;
3321 }
3322
3323 /* data */
3324 off = 0;
3325 while (off < rsize) {
3326 ctrl.bits.wdata = 0;
3327 ctrl.bits.addr = SSD_I2C_DATA_REG;
3328 ctrl.bits.rw = SSD_I2C_CTRL_READ;
3329 __ssd_i2c_reg32_write(dev->ctrlp + SSD_I2C_CTRL_REG, ctrl.val);
3330
3331 st = jiffies;
3332 for (;;) {
3333 data.val = __ssd_i2c_reg32_read(dev->ctrlp + SSD_I2C_RDATA_REG);
3334 if (data.bits.valid == 0) {
3335 break;
3336 }
3337
3338 /* retry */
3339 if (time_after(jiffies, (st + SSD_I2C_TIMEOUT))) {
3340 ret = -ETIMEDOUT;
3341 goto out_clear;
3342 }
3343 cond_resched();
3344 }
3345
3346 rbuf[off] = data.bits.rdata;
3347
3348 off++;
3349 }
3350
3351 /* clear */
3352out_clear:
3353 if (__ssd_i2c_clear(dev, saddr)) {
3354 if (!ret) ret = -4;
3355 }
3356 mutex_unlock(&dev->i2c_mutex);
3357
3358 return ret;
3359}
3360
3361static int ssd_smbus_send_byte(struct ssd_device *dev, uint8_t saddr, uint8_t *buf)
3362{
3363 int i = 0;
3364 int ret = 0;
3365
3366 for (;;) {
3367 ret = ssd_i2c_write(dev, saddr, 1, buf);
3368 if (!ret || -ETIMEDOUT == ret) {
3369 break;
3370 }
3371
3372 i++;
3373 if (i >= SSD_SMBUS_RETRY_MAX) {
3374 break;
3375 }
3376 msleep(SSD_SMBUS_RETRY_INTERVAL);
3377 }
3378
3379 return ret;
3380}
3381
3382static int ssd_smbus_receive_byte(struct ssd_device *dev, uint8_t saddr, uint8_t *buf)
3383{
3384 int i = 0;
3385 int ret = 0;
3386
3387 for (;;) {
3388 ret = ssd_i2c_read(dev, saddr, 1, buf);
3389 if (!ret || -ETIMEDOUT == ret) {
3390 break;
3391 }
3392
3393 i++;
3394 if (i >= SSD_SMBUS_RETRY_MAX) {
3395 break;
3396 }
3397 msleep(SSD_SMBUS_RETRY_INTERVAL);
3398 }
3399
3400 return ret;
3401}
3402
3403static int ssd_smbus_write_byte(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t *buf)
3404{
3405 uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0};
3406 int i = 0;
3407 int ret = 0;
3408
3409 smb_data[0] = cmd;
3410 memcpy((smb_data + 1), buf, 1);
3411
3412 for (;;) {
3413 ret = ssd_i2c_write(dev, saddr, 2, smb_data);
3414 if (!ret || -ETIMEDOUT == ret) {
3415 break;
3416 }
3417
3418 i++;
3419 if (i >= SSD_SMBUS_RETRY_MAX) {
3420 break;
3421 }
3422 msleep(SSD_SMBUS_RETRY_INTERVAL);
3423 }
3424
3425 return ret;
3426}
3427
3428static int ssd_smbus_read_byte(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t *buf)
3429{
3430 uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0};
3431 int i = 0;
3432 int ret = 0;
3433
3434 smb_data[0] = cmd;
3435
3436 for (;;) {
3437 ret = ssd_i2c_write_read(dev, saddr, 1, smb_data, 1, buf);
3438 if (!ret || -ETIMEDOUT == ret) {
3439 break;
3440 }
3441
3442 i++;
3443 if (i >= SSD_SMBUS_RETRY_MAX) {
3444 break;
3445 }
3446 msleep(SSD_SMBUS_RETRY_INTERVAL);
3447 }
3448
3449 return ret;
3450}
3451
3452static int ssd_smbus_write_word(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t *buf)
3453{
3454 uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0};
3455 int i = 0;
3456 int ret = 0;
3457
3458 smb_data[0] = cmd;
3459 memcpy((smb_data + 1), buf, 2);
3460
3461 for (;;) {
3462 ret = ssd_i2c_write(dev, saddr, 3, smb_data);
3463 if (!ret || -ETIMEDOUT == ret) {
3464 break;
3465 }
3466
3467 i++;
3468 if (i >= SSD_SMBUS_RETRY_MAX) {
3469 break;
3470 }
3471 msleep(SSD_SMBUS_RETRY_INTERVAL);
3472 }
3473
3474 return ret;
3475}
3476
3477static int ssd_smbus_read_word(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t *buf)
3478{
3479 uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0};
3480 int i = 0;
3481 int ret = 0;
3482
3483 smb_data[0] = cmd;
3484
3485 for (;;) {
3486 ret = ssd_i2c_write_read(dev, saddr, 1, smb_data, 2, buf);
3487 if (!ret || -ETIMEDOUT == ret) {
3488 break;
3489 }
3490
3491 i++;
3492 if (i >= SSD_SMBUS_RETRY_MAX) {
3493 break;
3494 }
3495 msleep(SSD_SMBUS_RETRY_INTERVAL);
3496 }
3497
3498 return ret;
3499}
3500
3501static int ssd_smbus_write_block(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t size, uint8_t *buf)
3502{
3503 uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0};
3504 int i = 0;
3505 int ret = 0;
3506
3507 smb_data[0] = cmd;
3508 smb_data[1] = size;
3509 memcpy((smb_data + 2), buf, size);
3510
3511 for (;;) {
3512 ret = ssd_i2c_write(dev, saddr, (2 + size), smb_data);
3513 if (!ret || -ETIMEDOUT == ret) {
3514 break;
3515 }
3516
3517 i++;
3518 if (i >= SSD_SMBUS_RETRY_MAX) {
3519 break;
3520 }
3521 msleep(SSD_SMBUS_RETRY_INTERVAL);
3522 }
3523
3524 return ret;
3525}
3526
3527static int ssd_smbus_read_block(struct ssd_device *dev, uint8_t saddr, uint8_t cmd, uint8_t size, uint8_t *buf)
3528{
3529 uint8_t smb_data[SSD_SMBUS_DATA_MAX] = {0};
3530 uint8_t rsize;
3531 int i = 0;
3532 int ret = 0;
3533
3534 smb_data[0] = cmd;
3535
3536 for (;;) {
3537 ret = ssd_i2c_write_read(dev, saddr, 1, smb_data, (SSD_SMBUS_BLOCK_MAX + 1), (smb_data + 1));
3538 if (!ret || -ETIMEDOUT == ret) {
3539 break;
3540 }
3541
3542 i++;
3543 if (i >= SSD_SMBUS_RETRY_MAX) {
3544 break;
3545 }
3546 msleep(SSD_SMBUS_RETRY_INTERVAL);
3547 }
3548 if (ret) {
3549 return ret;
3550 }
3551
3552 rsize = smb_data[1];
3553
3554 if (rsize > size ) {
3555 rsize = size;
3556 }
3557
3558 memcpy(buf, (smb_data + 2), rsize);
3559
3560 return 0;
3561}
3562
3563
3564static int ssd_gen_swlog(struct ssd_device *dev, uint16_t event, uint32_t data);
3565
3566/* sensor */
3567static int ssd_init_lm75(struct ssd_device *dev, uint8_t saddr)
3568{
3569 uint8_t conf = 0;
3570 int ret = 0;
3571
3572 ret = ssd_smbus_read_byte(dev, saddr, SSD_LM75_REG_CONF, &conf);
3573 if (ret) {
3574 goto out;
3575 }
3576
3577 conf &= (uint8_t)(~1u);
3578
3579 ret = ssd_smbus_write_byte(dev, saddr, SSD_LM75_REG_CONF, &conf);
3580 if (ret) {
3581 goto out;
3582 }
3583
3584out:
3585 return ret;
3586}
3587
3588static int ssd_lm75_read(struct ssd_device *dev, uint8_t saddr, uint16_t *data)
3589{
3590 uint16_t val = 0;
3591 int ret;
3592
3593 ret = ssd_smbus_read_word(dev, saddr, SSD_LM75_REG_TEMP, (uint8_t *)&val);
3594 if (ret) {
3595 return ret;
3596 }
3597
3598 *data = u16_swap(val);
3599
3600 return 0;
3601}
3602
3603static int ssd_init_lm80(struct ssd_device *dev, uint8_t saddr)
3604{
3605 uint8_t val;
3606 uint8_t low, high;
3607 int i;
3608 int ret = 0;
3609
3610 /* init */
3611 val = 0x80;
3612 ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_CONFIG, &val);
3613 if (ret) {
3614 goto out;
3615 }
3616
3617 /* 11-bit temp */
3618 val = 0x08;
3619 ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_RES, &val);
3620 if (ret) {
3621 goto out;
3622 }
3623
3624 /* set volt limit */
3625 for (i=0; i<SSD_LM80_IN_NR; i++) {
3626 high = ssd_lm80_limit[i].high;
3627 low = ssd_lm80_limit[i].low;
3628
3629 if (SSD_LM80_IN_CAP == i) {
3630 low = 0;
3631 }
3632
3633 if (dev->hw_info.nr_ctrl <= 1 && SSD_LM80_IN_1V2 == i) {
3634 high = 0xFF;
3635 low = 0;
3636 }
3637
3638 /* high limit */
3639 ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_IN_MAX(i), &high);
3640 if (ret) {
3641 goto out;
3642 }
3643
3644 /* low limit*/
3645 ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_IN_MIN(i), &low);
3646 if (ret) {
3647 goto out;
3648 }
3649 }
3650
3651 /* set interrupt mask: allow volt in interrupt except cap in*/
3652 val = 0x81;
3653 ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_MASK1, &val);
3654 if (ret) {
3655 goto out;
3656 }
3657
3658 /* set interrupt mask: disable others */
3659 val = 0xFF;
3660 ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_MASK2, &val);
3661 if (ret) {
3662 goto out;
3663 }
3664
3665 /* start */
3666 val = 0x03;
3667 ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_CONFIG, &val);
3668 if (ret) {
3669 goto out;
3670 }
3671
3672out:
3673 return ret;
3674}
3675
3676static int ssd_lm80_enable_in(struct ssd_device *dev, uint8_t saddr, int idx)
3677{
3678 uint8_t val = 0;
3679 int ret = 0;
3680
3681 if (idx >= SSD_LM80_IN_NR || idx < 0) {
3682 return -EINVAL;
3683 }
3684
3685 ret = ssd_smbus_read_byte(dev, saddr, SSD_LM80_REG_MASK1, &val);
3686 if (ret) {
3687 goto out;
3688 }
3689
3690 val &= ~(1UL << (uint32_t)idx);
3691
3692 ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_MASK1, &val);
3693 if (ret) {
3694 goto out;
3695 }
3696
3697out:
3698 return ret;
3699}
3700
3701static int ssd_lm80_disable_in(struct ssd_device *dev, uint8_t saddr, int idx)
3702{
3703 uint8_t val = 0;
3704 int ret = 0;
3705
3706 if (idx >= SSD_LM80_IN_NR || idx < 0) {
3707 return -EINVAL;
3708 }
3709
3710 ret = ssd_smbus_read_byte(dev, saddr, SSD_LM80_REG_MASK1, &val);
3711 if (ret) {
3712 goto out;
3713 }
3714
3715 val |= (1UL << (uint32_t)idx);
3716
3717 ret = ssd_smbus_write_byte(dev, saddr, SSD_LM80_REG_MASK1, &val);
3718 if (ret) {
3719 goto out;
3720 }
3721
3722out:
3723 return ret;
3724}
3725
3726static int ssd_lm80_read_temp(struct ssd_device *dev, uint8_t saddr, uint16_t *data)
3727{
3728 uint16_t val = 0;
3729 int ret;
3730
3731 ret = ssd_smbus_read_word(dev, saddr, SSD_LM80_REG_TEMP, (uint8_t *)&val);
3732 if (ret) {
3733 return ret;
3734 }
3735
3736 *data = u16_swap(val);
3737
3738 return 0;
3739}
3740
3741static int ssd_lm80_check_event(struct ssd_device *dev, uint8_t saddr)
3742{
3743 uint32_t volt;
3744 uint16_t val = 0, status;
3745 uint8_t alarm1 = 0, alarm2 = 0;
a9d1e0c7
KM
3746 uint32_t low, high;
3747 int i,j=0;
a6a796ca
HSDT
3748 int ret = 0;
3749
3750 /* read interrupt status to clear interrupt */
3751 ret = ssd_smbus_read_byte(dev, saddr, SSD_LM80_REG_ALARM1, &alarm1);
3752 if (ret) {
3753 goto out;
3754 }
3755
3756 ret = ssd_smbus_read_byte(dev, saddr, SSD_LM80_REG_ALARM2, &alarm2);
3757 if (ret) {
3758 goto out;
3759 }
3760
3761 status = (uint16_t)alarm1 | ((uint16_t)alarm2 << 8);
3762
3763 /* parse inetrrupt status */
3764 for (i=0; i<SSD_LM80_IN_NR; i++) {
3765 if (!((status >> (uint32_t)i) & 0x1)) {
3766 if (test_and_clear_bit(SSD_HWMON_LM80(i), &dev->hwmon)) {
3767 /* enable INx irq */
3768 ret = ssd_lm80_enable_in(dev, saddr, i);
3769 if (ret) {
3770 goto out;
3771 }
3772 }
3773
3774 continue;
3775 }
3776
3777 /* disable INx irq */
3778 ret = ssd_lm80_disable_in(dev, saddr, i);
3779 if (ret) {
3780 goto out;
3781 }
3782
3783 if (test_and_set_bit(SSD_HWMON_LM80(i), &dev->hwmon)) {
3784 continue;
3785 }
3786
a9d1e0c7
KM
3787 high = (uint32_t)ssd_lm80_limit[i].high * (uint32_t)10;
3788 low = (uint32_t)ssd_lm80_limit[i].low * (uint32_t)10;
3789
3790 for (j=0; j<3; j++) {
3791 ret = ssd_smbus_read_word(dev, saddr, SSD_LM80_REG_IN(i), (uint8_t *)&val);
3792 if (ret) {
3793 goto out;
3794 }
3795 volt = SSD_LM80_CONVERT_VOLT(u16_swap(val));
3796 if ((volt>high) || (volt<=low)) {
3797 if(j<2) {
3798 msleep(SSD_LM80_CONV_INTERVAL);
3799 }
3800 } else {
3801 break;
3802 }
a6a796ca
HSDT
3803 }
3804
a9d1e0c7
KM
3805 if (j<3) {
3806 continue;
3807 }
a6a796ca
HSDT
3808
3809 switch (i) {
3810 case SSD_LM80_IN_CAP: {
3811 if (0 == volt) {
3812 ssd_gen_swlog(dev, SSD_LOG_CAP_SHORT_CIRCUIT, 0);
3813 } else {
3814 ssd_gen_swlog(dev, SSD_LOG_CAP_VOLT_FAULT, SSD_PL_CAP_VOLT(volt));
3815 }
3816 break;
3817 }
3818
3819 case SSD_LM80_IN_1V2:
3820 case SSD_LM80_IN_1V2a:
3821 case SSD_LM80_IN_1V5:
3822 case SSD_LM80_IN_1V8: {
3823 ssd_gen_swlog(dev, SSD_LOG_VOLT_STATUS, SSD_VOLT_LOG_DATA(i, 0, volt));
3824 break;
3825 }
3826 case SSD_LM80_IN_FPGA_3V3:
3827 case SSD_LM80_IN_3V3: {
3828 ssd_gen_swlog(dev, SSD_LOG_VOLT_STATUS, SSD_VOLT_LOG_DATA(i, 0, SSD_LM80_3V3_VOLT(volt)));
3829 break;
3830 }
3831 default:
3832 break;
3833 }
3834 }
3835
3836out:
3837 if (ret) {
3838 if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) {
3839 ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, (uint32_t)saddr);
3840 }
3841 } else {
3842 test_and_clear_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon);
3843 }
3844 return ret;
3845}
3846
3847static int ssd_init_sensor(struct ssd_device *dev)
3848{
3849 int ret = 0;
3850
3851 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
3852 goto out;
3853 }
3854
3855 ret = ssd_init_lm75(dev, SSD_SENSOR_LM75_SADDRESS);
3856 if (ret) {
3857 hio_warn("%s: init lm75 failed\n", dev->name);
3858 if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM75), &dev->hwmon)) {
3859 ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM75_SADDRESS);
3860 }
3861 goto out;
3862 }
3863
3864 if (dev->hw_info.pcb_ver >= 'B' || dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_HHHL) {
3865 ret = ssd_init_lm80(dev, SSD_SENSOR_LM80_SADDRESS);
3866 if (ret) {
3867 hio_warn("%s: init lm80 failed\n", dev->name);
3868 if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) {
3869 ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS);
3870 }
3871 goto out;
3872 }
3873 }
3874
3875out:
3876 /* skip error if not in standard mode */
3877 if (mode != SSD_DRV_MODE_STANDARD) {
3878 ret = 0;
3879 }
3880 return ret;
3881}
3882
3883/* board volt */
3884static int ssd_mon_boardvolt(struct ssd_device *dev)
3885{
3886 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
3887 return 0;
3888 }
3889
3890 if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') {
3891 return 0;
3892 }
3893
3894 return ssd_lm80_check_event(dev, SSD_SENSOR_LM80_SADDRESS);
3895}
3896
3897/* temperature */
3898static int ssd_mon_temp(struct ssd_device *dev)
3899{
3900 int cur;
3901 uint16_t val = 0;
3902 int ret = 0;
3903
3904 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
3905 return 0;
3906 }
3907
3908 if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') {
3909 return 0;
3910 }
3911
3912 /* inlet */
3913 ret = ssd_lm80_read_temp(dev, SSD_SENSOR_LM80_SADDRESS, &val);
3914 if (ret) {
3915 if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) {
3916 ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS);
3917 }
3918 goto out;
3919 }
3920 test_and_clear_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon);
3921
3922 cur = SSD_SENSOR_CONVERT_TEMP(val);
3923 if (cur >= SSD_INLET_OT_TEMP) {
3924 if (!test_and_set_bit(SSD_HWMON_TEMP(SSD_TEMP_INLET), &dev->hwmon)) {
3925 ssd_gen_swlog(dev, SSD_LOG_INLET_OVER_TEMP, (uint32_t)cur);
3926 }
3927 } else if(cur < SSD_INLET_OT_HYST) {
3928 if (test_and_clear_bit(SSD_HWMON_TEMP(SSD_TEMP_INLET), &dev->hwmon)) {
3929 ssd_gen_swlog(dev, SSD_LOG_INLET_NORMAL_TEMP, (uint32_t)cur);
3930 }
3931 }
3932
3933 /* flash */
3934 ret = ssd_lm75_read(dev, SSD_SENSOR_LM75_SADDRESS, &val);
3935 if (ret) {
3936 if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM75), &dev->hwmon)) {
3937 ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM75_SADDRESS);
3938 }
3939 goto out;
3940 }
3941 test_and_clear_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM75), &dev->hwmon);
3942
3943 cur = SSD_SENSOR_CONVERT_TEMP(val);
3944 if (cur >= SSD_FLASH_OT_TEMP) {
3945 if (!test_and_set_bit(SSD_HWMON_TEMP(SSD_TEMP_FLASH), &dev->hwmon)) {
3946 ssd_gen_swlog(dev, SSD_LOG_FLASH_OVER_TEMP, (uint32_t)cur);
3947 }
3948 } else if(cur < SSD_FLASH_OT_HYST) {
3949 if (test_and_clear_bit(SSD_HWMON_TEMP(SSD_TEMP_FLASH), &dev->hwmon)) {
3950 ssd_gen_swlog(dev, SSD_LOG_FLASH_NORMAL_TEMP, (uint32_t)cur);
3951 }
3952 }
3953
3954out:
3955 return ret;
3956}
3957
3958/* cmd tag */
3959static inline void ssd_put_tag(struct ssd_device *dev, int tag)
3960{
3961 test_and_clear_bit(tag, dev->tag_map);
3962 wake_up(&dev->tag_wq);
3963}
3964
3965static inline int ssd_get_tag(struct ssd_device *dev, int wait)
3966{
3967 int tag;
3968
3969find_tag:
3970 while ((tag = find_first_zero_bit(dev->tag_map, dev->hw_info.cmd_fifo_sz)) >= atomic_read(&dev->queue_depth)) {
3971 DEFINE_WAIT(__wait);
3972
3973 if (!wait) {
3974 return -1;
3975 }
3976
3977 prepare_to_wait_exclusive(&dev->tag_wq, &__wait, TASK_UNINTERRUPTIBLE);
3978 schedule();
3979
3980 finish_wait(&dev->tag_wq, &__wait);
3981 }
3982
3983 if (test_and_set_bit(tag, dev->tag_map)) {
3984 goto find_tag;
3985 }
3986
3987 return tag;
3988}
3989
3990static void ssd_barrier_put_tag(struct ssd_device *dev, int tag)
3991{
3992 test_and_clear_bit(tag, dev->tag_map);
3993}
3994
3995static int ssd_barrier_get_tag(struct ssd_device *dev)
3996{
3997 int tag = 0;
3998
3999 if (test_and_set_bit(tag, dev->tag_map)) {
4000 return -1;
4001 }
4002
4003 return tag;
4004}
4005
4006static void ssd_barrier_end(struct ssd_device *dev)
4007{
4008 atomic_set(&dev->queue_depth, dev->hw_info.cmd_fifo_sz);
4009 wake_up_all(&dev->tag_wq);
4010
4011 mutex_unlock(&dev->barrier_mutex);
4012}
4013
4014static int ssd_barrier_start(struct ssd_device *dev)
4015{
4016 int i;
4017
4018 mutex_lock(&dev->barrier_mutex);
4019
4020 atomic_set(&dev->queue_depth, 0);
4021
4022 for (i=0; i<SSD_CMD_TIMEOUT; i++) {
4023 if (find_first_bit(dev->tag_map, dev->hw_info.cmd_fifo_sz) >= dev->hw_info.cmd_fifo_sz) {
4024 return 0;
4025 }
4026
4027 __set_current_state(TASK_INTERRUPTIBLE);
4028 schedule_timeout(1);
4029 }
4030
4031 atomic_set(&dev->queue_depth, dev->hw_info.cmd_fifo_sz);
4032 wake_up_all(&dev->tag_wq);
4033
4034 mutex_unlock(&dev->barrier_mutex);
4035
4036 return -EBUSY;
4037}
4038
4039static int ssd_busy(struct ssd_device *dev)
4040{
4041 if (find_first_bit(dev->tag_map, dev->hw_info.cmd_fifo_sz) >= dev->hw_info.cmd_fifo_sz) {
4042 return 0;
4043 }
4044
4045 return 1;
4046}
4047
4048static int ssd_wait_io(struct ssd_device *dev)
4049{
4050 int i;
4051
4052 for (i=0; i<SSD_CMD_TIMEOUT; i++) {
4053 if (find_first_bit(dev->tag_map, dev->hw_info.cmd_fifo_sz) >= dev->hw_info.cmd_fifo_sz) {
4054 return 0;
4055 }
4056
4057 __set_current_state(TASK_INTERRUPTIBLE);
4058 schedule_timeout(1);
4059 }
4060
4061 return -EBUSY;
4062}
4063
4064#if 0
4065static int ssd_in_barrier(struct ssd_device *dev)
4066{
4067 return (0 == atomic_read(&dev->queue_depth));
4068}
4069#endif
4070
4071static void ssd_cleanup_tag(struct ssd_device *dev)
4072{
4073 kfree(dev->tag_map);
4074}
4075
4076static int ssd_init_tag(struct ssd_device *dev)
4077{
4078 int nr_ulongs = ALIGN(dev->hw_info.cmd_fifo_sz, BITS_PER_LONG) / BITS_PER_LONG;
4079
4080 mutex_init(&dev->barrier_mutex);
4081
4082 atomic_set(&dev->queue_depth, dev->hw_info.cmd_fifo_sz);
4083
4084 dev->tag_map = kmalloc(nr_ulongs * sizeof(unsigned long), GFP_ATOMIC);
4085 if (!dev->tag_map) {
4086 return -ENOMEM;
4087 }
4088
4089 memset(dev->tag_map, 0, nr_ulongs * sizeof(unsigned long));
4090
4091 init_waitqueue_head(&dev->tag_wq);
4092
4093 return 0;
4094}
4095
4096/* io stat */
4097static void ssd_end_io_acct(struct ssd_cmd *cmd)
4098{
4099 struct ssd_device *dev = cmd->dev;
4100 struct bio *bio = cmd->bio;
4101 unsigned long dur = jiffies - cmd->start_time;
4102 int rw = bio_data_dir(bio);
4103
4104#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6 && RHEL_MINOR >= 7))
4105 int cpu = part_stat_lock();
4106 struct hd_struct *part = disk_map_sector_rcu(dev->gd, bio_start(bio));
4107 part_round_stats(cpu, part);
4108 part_stat_add(cpu, part, ticks[rw], dur);
4109 part_dec_in_flight(part, rw);
4110 part_stat_unlock();
4111#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27))
4112 int cpu = part_stat_lock();
4113 struct hd_struct *part = &dev->gd->part0;
4114 part_round_stats(cpu, part);
4115 part_stat_add(cpu, part, ticks[rw], dur);
4116 part_stat_unlock();
4117 part->in_flight[rw] = atomic_dec_return(&dev->in_flight[rw]);
4118#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,14))
4119 preempt_disable();
4120 disk_round_stats(dev->gd);
4121 preempt_enable();
4122 disk_stat_add(dev->gd, ticks[rw], dur);
4123 dev->gd->in_flight = atomic_dec_return(&dev->in_flight[0]);
4124#else
4125 preempt_disable();
4126 disk_round_stats(dev->gd);
4127 preempt_enable();
4128 if (rw == WRITE) {
4129 disk_stat_add(dev->gd, write_ticks, dur);
4130 } else {
4131 disk_stat_add(dev->gd, read_ticks, dur);
4132 }
4133 dev->gd->in_flight = atomic_dec_return(&dev->in_flight[0]);
4134#endif
4135}
4136
4137static void ssd_start_io_acct(struct ssd_cmd *cmd)
4138{
4139 struct ssd_device *dev = cmd->dev;
4140 struct bio *bio = cmd->bio;
4141 int rw = bio_data_dir(bio);
4142
4143#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(3,0,0)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6 && RHEL_MINOR >= 7))
4144 int cpu = part_stat_lock();
4145 struct hd_struct *part = disk_map_sector_rcu(dev->gd, bio_start(bio));
4146 part_round_stats(cpu, part);
4147 part_stat_inc(cpu, part, ios[rw]);
4148 part_stat_add(cpu, part, sectors[rw], bio_sectors(bio));
4149 part_inc_in_flight(part, rw);
4150 part_stat_unlock();
4151#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27))
4152 int cpu = part_stat_lock();
4153 struct hd_struct *part = &dev->gd->part0;
4154 part_round_stats(cpu, part);
4155 part_stat_inc(cpu, part, ios[rw]);
4156 part_stat_add(cpu, part, sectors[rw], bio_sectors(bio));
4157 part_stat_unlock();
4158 part->in_flight[rw] = atomic_inc_return(&dev->in_flight[rw]);
4159#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,14))
4160 preempt_disable();
4161 disk_round_stats(dev->gd);
4162 preempt_enable();
4163 disk_stat_inc(dev->gd, ios[rw]);
4164 disk_stat_add(dev->gd, sectors[rw], bio_sectors(bio));
4165 dev->gd->in_flight = atomic_inc_return(&dev->in_flight[0]);
4166#else
4167 preempt_disable();
4168 disk_round_stats(dev->gd);
4169 preempt_enable();
4170 if (rw == WRITE) {
4171 disk_stat_inc(dev->gd, writes);
4172 disk_stat_add(dev->gd, write_sectors, bio_sectors(bio));
4173 } else {
4174 disk_stat_inc(dev->gd, reads);
4175 disk_stat_add(dev->gd, read_sectors, bio_sectors(bio));
4176 }
4177 dev->gd->in_flight = atomic_inc_return(&dev->in_flight[0]);
4178#endif
4179
4180 cmd->start_time = jiffies;
4181}
4182
4183/* io */
4184static void ssd_queue_bio(struct ssd_device *dev, struct bio *bio)
4185{
4186 spin_lock(&dev->sendq_lock);
4187 ssd_blist_add(&dev->sendq, bio);
4188 spin_unlock(&dev->sendq_lock);
4189
4190 atomic_inc(&dev->in_sendq);
4191 wake_up(&dev->send_waitq);
4192}
4193
4194static inline void ssd_end_request(struct ssd_cmd *cmd)
4195{
4196 struct ssd_device *dev = cmd->dev;
4197 struct bio *bio = cmd->bio;
4198 int errors = cmd->errors;
4199 int tag = cmd->tag;
4200
4201 if (bio) {
a9d1e0c7 4202 if (!ssd_bio_has_discard(bio)) {
a6a796ca
HSDT
4203 ssd_end_io_acct(cmd);
4204 if (!cmd->flag) {
4205 pci_unmap_sg(dev->pdev, cmd->sgl, cmd->nsegs,
4206 bio_data_dir(bio) == READ ? PCI_DMA_FROMDEVICE : PCI_DMA_TODEVICE);
4207 }
4208 }
a6a796ca
HSDT
4209
4210 cmd->bio = NULL;
4211 ssd_put_tag(dev, tag);
4212
4213 if (SSD_INT_MSIX == dev->int_mode || tag < 16 || errors) {
a9d1e0c7 4214 ssd_bio_endio(bio, errors);
a6a796ca
HSDT
4215 } else /* if (bio->bi_idx >= bio->bi_vcnt)*/ {
4216 spin_lock(&dev->doneq_lock);
4217 ssd_blist_add(&dev->doneq, bio);
4218 spin_unlock(&dev->doneq_lock);
4219
4220 atomic_inc(&dev->in_doneq);
4221 wake_up(&dev->done_waitq);
4222 }
4223 } else {
4224 if (cmd->waiting) {
4225 complete(cmd->waiting);
4226 }
4227 }
4228}
4229
4230static void ssd_end_timeout_request(struct ssd_cmd *cmd)
4231{
4232 struct ssd_device *dev = cmd->dev;
4233 struct ssd_rw_msg *msg = (struct ssd_rw_msg *)cmd->msg;
4234 int i;
4235
4236 for (i=0; i<dev->nr_queue; i++) {
4237 disable_irq(dev->entry[i].vector);
4238 }
4239
4240 atomic_inc(&dev->tocnt);
4241 //if (cmd->bio) {
4242 hio_err("%s: cmd timeout: tag %d fun %#x\n", dev->name, msg->tag, msg->fun);
4243 cmd->errors = -ETIMEDOUT;
4244 ssd_end_request(cmd);
4245 //}
4246
4247 for (i=0; i<dev->nr_queue; i++) {
4248 enable_irq(dev->entry[i].vector);
4249 }
4250
4251 /* alarm led */
4252 ssd_set_alarm(dev);
4253}
4254
4255/* cmd timer */
4256static void ssd_cmd_add_timer(struct ssd_cmd *cmd, int timeout, void (*complt)(struct ssd_cmd *))
4257{
4258 init_timer(&cmd->cmd_timer);
4259
4260 cmd->cmd_timer.data = (unsigned long)cmd;
4261 cmd->cmd_timer.expires = jiffies + timeout;
4262 cmd->cmd_timer.function = (void (*)(unsigned long)) complt;
4263
4264 add_timer(&cmd->cmd_timer);
4265}
4266
4267static int ssd_cmd_del_timer(struct ssd_cmd *cmd)
4268{
4269 return del_timer(&cmd->cmd_timer);
4270}
4271
4272static void ssd_add_timer(struct timer_list *timer, int timeout, void (*complt)(void *), void *data)
4273{
4274 init_timer(timer);
4275
4276 timer->data = (unsigned long)data;
4277 timer->expires = jiffies + timeout;
4278 timer->function = (void (*)(unsigned long)) complt;
4279
4280 add_timer(timer);
4281}
4282
4283static int ssd_del_timer(struct timer_list *timer)
4284{
4285 return del_timer(timer);
4286}
4287
4288static void ssd_cmd_timeout(struct ssd_cmd *cmd)
4289{
4290 struct ssd_device *dev = cmd->dev;
4291 uint32_t msg = *(uint32_t *)cmd->msg;
4292
4293 ssd_end_timeout_request(cmd);
4294
4295 ssd_gen_swlog(dev, SSD_LOG_TIMEOUT, msg);
4296}
4297
4298
4299static void __ssd_done(unsigned long data)
4300{
4301 struct ssd_cmd *cmd;
4302 LIST_HEAD(localq);
4303
4304 local_irq_disable();
4305#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,13,0))
4306 list_splice_init(&__get_cpu_var(ssd_doneq), &localq);
4307#else
4308 list_splice_init(this_cpu_ptr(&ssd_doneq), &localq);
4309#endif
4310 local_irq_enable();
4311
4312 while (!list_empty(&localq)) {
4313 cmd = list_entry(localq.next, struct ssd_cmd, list);
4314 list_del_init(&cmd->list);
4315
4316 ssd_end_request(cmd);
4317 }
4318}
4319
4320static void __ssd_done_db(unsigned long data)
4321{
4322 struct ssd_cmd *cmd;
4323 struct ssd_device *dev;
4324 struct bio *bio;
4325 LIST_HEAD(localq);
4326
4327 local_irq_disable();
4328#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,13,0))
4329 list_splice_init(&__get_cpu_var(ssd_doneq), &localq);
4330#else
4331 list_splice_init(this_cpu_ptr(&ssd_doneq), &localq);
4332#endif
4333 local_irq_enable();
4334
4335 while (!list_empty(&localq)) {
4336 cmd = list_entry(localq.next, struct ssd_cmd, list);
4337 list_del_init(&cmd->list);
4338
4339 dev = (struct ssd_device *)cmd->dev;
4340 bio = cmd->bio;
4341
4342 if (bio) {
4343 sector_t off = dev->db_info.data.loc.off;
4344 uint32_t len = dev->db_info.data.loc.len;
4345
4346 switch (dev->db_info.type) {
4347 case SSD_DEBUG_READ_ERR:
4348 if (bio_data_dir(bio) == READ &&
4349 !((off + len) <= bio_start(bio) || off >= (bio_start(bio) + bio_sectors(bio)))) {
4350 cmd->errors = -EIO;
4351 }
4352 break;
4353 case SSD_DEBUG_WRITE_ERR:
4354 if (bio_data_dir(bio) == WRITE &&
4355 !((off + len) <= bio_start(bio) || off >= (bio_start(bio) + bio_sectors(bio)))) {
4356 cmd->errors = -EROFS;
4357 }
4358 break;
4359 case SSD_DEBUG_RW_ERR:
4360 if (!((off + len) <= bio_start(bio) || off >= (bio_start(bio) + bio_sectors(bio)))) {
4361 if (bio_data_dir(bio) == READ) {
4362 cmd->errors = -EIO;
4363 } else {
4364 cmd->errors = -EROFS;
4365 }
4366 }
4367 break;
4368 default:
4369 break;
4370 }
4371 }
4372
4373 ssd_end_request(cmd);
4374 }
4375}
4376
4377static inline void ssd_done_bh(struct ssd_cmd *cmd)
4378{
4379 unsigned long flags = 0;
4380
4381 if (unlikely(!ssd_cmd_del_timer(cmd))) {
4382 struct ssd_device *dev = cmd->dev;
4383 struct ssd_rw_msg *msg = (struct ssd_rw_msg *)cmd->msg;
4384 hio_err("%s: unknown cmd: tag %d fun %#x\n", dev->name, msg->tag, msg->fun);
4385
4386 /* alarm led */
4387 ssd_set_alarm(dev);
4388 return;
4389 }
4390
4391 local_irq_save(flags);
4392#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,13,0))
4393 list_add_tail(&cmd->list, &__get_cpu_var(ssd_doneq));
4394 tasklet_hi_schedule(&__get_cpu_var(ssd_tasklet));
4395#else
4396 list_add_tail(&cmd->list, this_cpu_ptr(&ssd_doneq));
4397 tasklet_hi_schedule(this_cpu_ptr(&ssd_tasklet));
4398#endif
4399 local_irq_restore(flags);
4400
4401 return;
4402}
4403
4404static inline void ssd_done(struct ssd_cmd *cmd)
4405{
4406 if (unlikely(!ssd_cmd_del_timer(cmd))) {
4407 struct ssd_device *dev = cmd->dev;
4408 struct ssd_rw_msg *msg = (struct ssd_rw_msg *)cmd->msg;
4409 hio_err("%s: unknown cmd: tag %d fun %#x\n", dev->name, msg->tag, msg->fun);
4410
4411 /* alarm led */
4412 ssd_set_alarm(dev);
4413 return;
4414 }
4415
4416 ssd_end_request(cmd);
4417
4418 return;
4419}
4420
4421static inline void ssd_dispatch_cmd(struct ssd_cmd *cmd)
4422{
4423 struct ssd_device *dev = (struct ssd_device *)cmd->dev;
4424
4425 ssd_cmd_add_timer(cmd, SSD_CMD_TIMEOUT, ssd_cmd_timeout);
4426
4427 spin_lock(&dev->cmd_lock);
4428 ssd_reg_write(dev->ctrlp + SSD_REQ_FIFO_REG, cmd->msg_dma);
4429 spin_unlock(&dev->cmd_lock);
4430}
4431
4432static inline void ssd_send_cmd(struct ssd_cmd *cmd)
4433{
4434 struct ssd_device *dev = (struct ssd_device *)cmd->dev;
4435
4436 ssd_cmd_add_timer(cmd, SSD_CMD_TIMEOUT, ssd_cmd_timeout);
4437
4438 ssd_reg32_write(dev->ctrlp + SSD_REQ_FIFO_REG, ((uint32_t)cmd->tag | ((uint32_t)cmd->nsegs << 16)));
4439}
4440
4441static inline void ssd_send_cmd_db(struct ssd_cmd *cmd)
4442{
4443 struct ssd_device *dev = (struct ssd_device *)cmd->dev;
4444 struct bio *bio = cmd->bio;
4445
4446 ssd_cmd_add_timer(cmd, SSD_CMD_TIMEOUT, ssd_cmd_timeout);
4447
4448 if (bio) {
4449 switch (dev->db_info.type) {
4450 case SSD_DEBUG_READ_TO:
4451 if (bio_data_dir(bio) == READ) {
4452 return;
4453 }
4454 break;
4455 case SSD_DEBUG_WRITE_TO:
4456 if (bio_data_dir(bio) == WRITE) {
4457 return;
4458 }
4459 break;
4460 case SSD_DEBUG_RW_TO:
4461 return;
4462 break;
4463 default:
4464 break;
4465 }
4466 }
4467
4468 ssd_reg32_write(dev->ctrlp + SSD_REQ_FIFO_REG, ((uint32_t)cmd->tag | ((uint32_t)cmd->nsegs << 16)));
4469}
4470
4471
4472/* fixed for BIOVEC_PHYS_MERGEABLE */
4473#ifdef SSD_BIOVEC_PHYS_MERGEABLE_FIXED
4474#include <linux/bio.h>
4475#include <linux/io.h>
4476#include <xen/page.h>
4477
4478static bool xen_biovec_phys_mergeable_fixed(const struct bio_vec *vec1,
4479 const struct bio_vec *vec2)
4480{
4481 unsigned long mfn1 = pfn_to_mfn(page_to_pfn(vec1->bv_page));
4482 unsigned long mfn2 = pfn_to_mfn(page_to_pfn(vec2->bv_page));
4483
4484 return __BIOVEC_PHYS_MERGEABLE(vec1, vec2) &&
4485 ((mfn1 == mfn2) || ((mfn1+1) == mfn2));
4486}
4487
4488#ifdef BIOVEC_PHYS_MERGEABLE
4489#undef BIOVEC_PHYS_MERGEABLE
4490#endif
4491#define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \
4492 (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \
4493 (!xen_domain() || xen_biovec_phys_mergeable_fixed(vec1, vec2)))
4494
4495#endif
4496
4497static inline int ssd_bio_map_sg(struct ssd_device *dev, struct bio *bio, struct scatterlist *sgl)
4498{
4499#if (LINUX_VERSION_CODE < KERNEL_VERSION(3,14,0))
4500 struct bio_vec *bvec, *bvprv = NULL;
4501 struct scatterlist *sg = NULL;
4502 int i = 0, nsegs = 0;
4503
4504#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,23))
4505 sg_init_table(sgl, dev->hw_info.cmd_max_sg);
4506#endif
4507
4508 /*
4509 * for each segment in bio
4510 */
4511 bio_for_each_segment(bvec, bio, i) {
4512 if (bvprv && BIOVEC_PHYS_MERGEABLE(bvprv, bvec)) {
4513 sg->length += bvec->bv_len;
4514 } else {
4515 if (unlikely(nsegs >= (int)dev->hw_info.cmd_max_sg)) {
4516 break;
4517 }
4518
4519 sg = sg ? (sg + 1) : sgl;
4520#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24))
4521 sg_set_page(sg, bvec->bv_page, bvec->bv_len, bvec->bv_offset);
4522#else
4523 sg->page = bvec->bv_page;
4524 sg->length = bvec->bv_len;
4525 sg->offset = bvec->bv_offset;
4526#endif
4527 nsegs++;
4528 }
4529 bvprv = bvec;
4530 }
4531
4532#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,24))
4533 if (sg) {
4534 sg_mark_end(sg);
4535 }
4536#endif
4537
4538 bio->bi_idx = i;
4539
4540 return nsegs;
4541#else
4542 struct bio_vec bvec, bvprv;
4543 struct bvec_iter iter;
4544 struct scatterlist *sg = NULL;
4545 int nsegs = 0;
4546 int first = 1;
4547
4548 sg_init_table(sgl, dev->hw_info.cmd_max_sg);
4549
4550 /*
4551 * for each segment in bio
4552 */
4553 bio_for_each_segment(bvec, bio, iter) {
4554 if (!first && BIOVEC_PHYS_MERGEABLE(&bvprv, &bvec)) {
4555 sg->length += bvec.bv_len;
4556 } else {
4557 if (unlikely(nsegs >= (int)dev->hw_info.cmd_max_sg)) {
4558 break;
4559 }
4560
4561 sg = sg ? (sg + 1) : sgl;
4562
4563 sg_set_page(sg, bvec.bv_page, bvec.bv_len, bvec.bv_offset);
4564
4565 nsegs++;
4566 first = 0;
4567 }
4568 bvprv = bvec;
4569 }
4570
4571 if (sg) {
4572 sg_mark_end(sg);
4573 }
4574
4575 return nsegs;
4576#endif
4577}
4578
4579
4580static int __ssd_submit_pbio(struct ssd_device *dev, struct bio *bio, int wait)
4581{
4582 struct ssd_cmd *cmd;
4583 struct ssd_rw_msg *msg;
4584 struct ssd_sg_entry *sge;
4585 sector_t block = bio_start(bio);
4586 int tag;
4587 int i;
4588
4589 tag = ssd_get_tag(dev, wait);
4590 if (tag < 0) {
4591 return -EBUSY;
4592 }
4593
4594 cmd = &dev->cmd[tag];
4595 cmd->bio = bio;
4596 cmd->flag = 1;
4597
4598 msg = (struct ssd_rw_msg *)cmd->msg;
4599
a9d1e0c7 4600 if (ssd_bio_has_discard(bio)) {
a6a796ca
HSDT
4601 unsigned int length = bio_sectors(bio);
4602
4603 //printk(KERN_WARNING "%s: discard len %u, block %llu\n", dev->name, bio_sectors(bio), block);
4604 msg->tag = tag;
4605 msg->fun = SSD_FUNC_TRIM;
4606
4607 sge = msg->sge;
4608 for (i=0; i<(dev->hw_info.cmd_max_sg); i++) {
4609 sge->block = block;
4610 sge->length = (length >= dev->hw_info.sg_max_sec) ? dev->hw_info.sg_max_sec : length;
4611 sge->buf = 0;
4612
4613 block += sge->length;
4614 length -= sge->length;
4615 sge++;
4616
4617 if (length <= 0) {
a9d1e0c7 4618 ++i;
a6a796ca
HSDT
4619 break;
4620 }
4621 }
a9d1e0c7 4622 msg->nsegs = cmd->nsegs = i;
a6a796ca
HSDT
4623
4624 dev->scmd(cmd);
4625 return 0;
4626 }
a6a796ca
HSDT
4627
4628 //msg->nsegs = cmd->nsegs = ssd_bio_map_sg(dev, bio, sgl);
4629 msg->nsegs = cmd->nsegs = bio->bi_vcnt;
4630
4631 //xx
4632 if (bio_data_dir(bio) == READ) {
4633 msg->fun = SSD_FUNC_READ;
4634 msg->flag = 0;
4635 } else {
4636 msg->fun = SSD_FUNC_WRITE;
4637 msg->flag = dev->wmode;
4638 }
4639
4640 sge = msg->sge;
4641 for (i=0; i<bio->bi_vcnt; i++) {
4642 sge->block = block;
4643 sge->length = bio->bi_io_vec[i].bv_len >> 9;
4644 sge->buf = (uint64_t)((void *)bio->bi_io_vec[i].bv_page + bio->bi_io_vec[i].bv_offset);
4645
4646 block += sge->length;
4647 sge++;
4648 }
4649
4650 msg->tag = tag;
4651
4652#ifdef SSD_OT_PROTECT
4653 if (unlikely(dev->ot_delay > 0 && dev->ot_protect != 0)) {
4654 msleep_interruptible(dev->ot_delay);
4655 }
4656#endif
4657
4658 ssd_start_io_acct(cmd);
4659 dev->scmd(cmd);
4660
4661 return 0;
4662}
4663
4664static inline int ssd_submit_bio(struct ssd_device *dev, struct bio *bio, int wait)
4665{
4666 struct ssd_cmd *cmd;
4667 struct ssd_rw_msg *msg;
4668 struct ssd_sg_entry *sge;
4669 struct scatterlist *sgl;
4670 sector_t block = bio_start(bio);
4671 int tag;
4672 int i;
4673
4674 tag = ssd_get_tag(dev, wait);
4675 if (tag < 0) {
4676 return -EBUSY;
4677 }
4678
4679 cmd = &dev->cmd[tag];
4680 cmd->bio = bio;
4681 cmd->flag = 0;
4682
4683 msg = (struct ssd_rw_msg *)cmd->msg;
4684
4685 sgl = cmd->sgl;
4686
a9d1e0c7 4687 if (ssd_bio_has_discard(bio)) {
a6a796ca
HSDT
4688 unsigned int length = bio_sectors(bio);
4689
4690 //printk(KERN_WARNING "%s: discard len %u, block %llu\n", dev->name, bio_sectors(bio), block);
4691 msg->tag = tag;
4692 msg->fun = SSD_FUNC_TRIM;
4693
4694 sge = msg->sge;
4695 for (i=0; i<(dev->hw_info.cmd_max_sg); i++) {
4696 sge->block = block;
4697 sge->length = (length >= dev->hw_info.sg_max_sec) ? dev->hw_info.sg_max_sec : length;
4698 sge->buf = 0;
4699
4700 block += sge->length;
4701 length -= sge->length;
4702 sge++;
4703
4704 if (length <= 0) {
a9d1e0c7 4705 ++i;
a6a796ca
HSDT
4706 break;
4707 }
4708 }
a9d1e0c7 4709 msg->nsegs = cmd->nsegs = i;
a6a796ca
HSDT
4710
4711 dev->scmd(cmd);
4712 return 0;
4713 }
a6a796ca
HSDT
4714
4715 msg->nsegs = cmd->nsegs = ssd_bio_map_sg(dev, bio, sgl);
4716
4717 //xx
4718 if (bio_data_dir(bio) == READ) {
4719 msg->fun = SSD_FUNC_READ;
4720 msg->flag = 0;
4721 pci_map_sg(dev->pdev, sgl, cmd->nsegs, PCI_DMA_FROMDEVICE);
4722 } else {
4723 msg->fun = SSD_FUNC_WRITE;
4724 msg->flag = dev->wmode;
4725 pci_map_sg(dev->pdev, sgl, cmd->nsegs, PCI_DMA_TODEVICE);
4726 }
4727
4728 sge = msg->sge;
4729 for (i=0; i<cmd->nsegs; i++) {
4730 sge->block = block;
4731 sge->length = sg_dma_len(sgl) >> 9;
4732 sge->buf = sg_dma_address(sgl);
4733
4734 block += sge->length;
4735 sgl++;
4736 sge++;
4737 }
4738
4739 msg->tag = tag;
4740
4741#ifdef SSD_OT_PROTECT
4742 if (unlikely(dev->ot_delay > 0 && dev->ot_protect != 0)) {
4743 msleep_interruptible(dev->ot_delay);
4744 }
4745#endif
4746
4747 ssd_start_io_acct(cmd);
4748 dev->scmd(cmd);
4749
4750 return 0;
4751}
4752
4753/* threads */
4754static int ssd_done_thread(void *data)
4755{
4756 struct ssd_device *dev;
4757 struct bio *bio;
4758 struct bio *next;
a6a796ca
HSDT
4759
4760 if (!data) {
4761 return -EINVAL;
4762 }
4763 dev = data;
4764
a9d1e0c7 4765 current->flags |= PF_NOFREEZE;
a6a796ca
HSDT
4766 //set_user_nice(current, -5);
4767
4768 while (!kthread_should_stop()) {
4769 wait_event_interruptible(dev->done_waitq, (atomic_read(&dev->in_doneq) || kthread_should_stop()));
4770
4771 while (atomic_read(&dev->in_doneq)) {
4772 if (threaded_irq) {
4773 spin_lock(&dev->doneq_lock);
4774 bio = ssd_blist_get(&dev->doneq);
4775 spin_unlock(&dev->doneq_lock);
4776 } else {
4777 spin_lock_irq(&dev->doneq_lock);
4778 bio = ssd_blist_get(&dev->doneq);
4779 spin_unlock_irq(&dev->doneq_lock);
4780 }
4781
4782 while (bio) {
4783 next = bio->bi_next;
4784 bio->bi_next = NULL;
a9d1e0c7 4785 ssd_bio_endio(bio, 0);
a6a796ca
HSDT
4786 atomic_dec(&dev->in_doneq);
4787 bio = next;
4788 }
4789
4790 cond_resched();
4791
4792#ifdef SSD_ESCAPE_IRQ
4793 if (unlikely(smp_processor_id() == dev->irq_cpu)) {
4794#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28))
f3ffa147 4795 cpumask_var_t new_mask;
a9d1e0c7
KM
4796 if (alloc_cpumask_var(&new_mask, GFP_ATOMIC)) {
4797 cpumask_setall(new_mask);
4798 cpumask_clear_cpu(dev->irq_cpu, new_mask);
4799 set_cpus_allowed_ptr(current, new_mask);
4800 free_cpumask_var(new_mask);
4801 }
a6a796ca 4802#else
f3ffa147 4803 cpumask_t new_mask;
a6a796ca
HSDT
4804 cpus_setall(new_mask);
4805 cpu_clear(dev->irq_cpu, new_mask);
4806 set_cpus_allowed(current, new_mask);
4807#endif
4808 }
4809#endif
4810 }
4811 }
4812 return 0;
4813}
4814
4815static int ssd_send_thread(void *data)
4816{
4817 struct ssd_device *dev;
4818 struct bio *bio;
4819 struct bio *next;
a6a796ca
HSDT
4820
4821 if (!data) {
4822 return -EINVAL;
4823 }
4824 dev = data;
4825
a9d1e0c7 4826 current->flags |= PF_NOFREEZE;
a6a796ca
HSDT
4827 //set_user_nice(current, -5);
4828
4829 while (!kthread_should_stop()) {
4830 wait_event_interruptible(dev->send_waitq, (atomic_read(&dev->in_sendq) || kthread_should_stop()));
4831
4832 while (atomic_read(&dev->in_sendq)) {
4833 spin_lock(&dev->sendq_lock);
4834 bio = ssd_blist_get(&dev->sendq);
4835 spin_unlock(&dev->sendq_lock);
4836
4837 while (bio) {
4838 next = bio->bi_next;
4839 bio->bi_next = NULL;
4840#ifdef SSD_QUEUE_PBIO
4841 if (test_and_clear_bit(BIO_SSD_PBIO, &bio->bi_flags)) {
4842 __ssd_submit_pbio(dev, bio, 1);
4843 } else {
4844 ssd_submit_bio(dev, bio, 1);
4845 }
4846#else
4847 ssd_submit_bio(dev, bio, 1);
4848#endif
4849 atomic_dec(&dev->in_sendq);
4850 bio = next;
4851 }
4852
4853 cond_resched();
4854
4855#ifdef SSD_ESCAPE_IRQ
4856 if (unlikely(smp_processor_id() == dev->irq_cpu)) {
4857#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28))
f3ffa147 4858 cpumask_var_t new_mask;
a9d1e0c7
KM
4859 if (alloc_cpumask_var(&new_mask, GFP_ATOMIC)) {
4860 cpumask_setall(new_mask);
4861 cpumask_clear_cpu(dev->irq_cpu, new_mask);
4862 set_cpus_allowed_ptr(current, new_mask);
4863 free_cpumask_var(new_mask);
4864 }
a6a796ca 4865#else
f3ffa147 4866 cpumask_t new_mask;
a6a796ca
HSDT
4867 cpus_setall(new_mask);
4868 cpu_clear(dev->irq_cpu, new_mask);
4869 set_cpus_allowed(current, new_mask);
4870#endif
4871 }
4872#endif
4873 }
4874 }
4875
4876 return 0;
4877}
4878
4879static void ssd_cleanup_thread(struct ssd_device *dev)
4880{
4881 kthread_stop(dev->send_thread);
4882 kthread_stop(dev->done_thread);
4883}
4884
4885static int ssd_init_thread(struct ssd_device *dev)
4886{
4887 int ret;
4888
4889 atomic_set(&dev->in_doneq, 0);
4890 atomic_set(&dev->in_sendq, 0);
4891
4892 spin_lock_init(&dev->doneq_lock);
4893 spin_lock_init(&dev->sendq_lock);
4894
4895 ssd_blist_init(&dev->doneq);
4896 ssd_blist_init(&dev->sendq);
4897
4898 init_waitqueue_head(&dev->done_waitq);
4899 init_waitqueue_head(&dev->send_waitq);
4900
4901 dev->done_thread = kthread_run(ssd_done_thread, dev, "%s/d", dev->name);
4902 if (IS_ERR(dev->done_thread)) {
4903 ret = PTR_ERR(dev->done_thread);
4904 goto out_done_thread;
4905 }
4906
4907 dev->send_thread = kthread_run(ssd_send_thread, dev, "%s/s", dev->name);
4908 if (IS_ERR(dev->send_thread)) {
4909 ret = PTR_ERR(dev->send_thread);
4910 goto out_send_thread;
4911 }
4912
4913 return 0;
4914
4915out_send_thread:
4916 kthread_stop(dev->done_thread);
4917out_done_thread:
4918 return ret;
4919}
4920
4921/* dcmd pool */
4922static void ssd_put_dcmd(struct ssd_dcmd *dcmd)
4923{
4924 struct ssd_device *dev = (struct ssd_device *)dcmd->dev;
4925
4926 spin_lock(&dev->dcmd_lock);
4927 list_add_tail(&dcmd->list, &dev->dcmd_list);
4928 spin_unlock(&dev->dcmd_lock);
4929}
4930
4931static struct ssd_dcmd *ssd_get_dcmd(struct ssd_device *dev)
4932{
4933 struct ssd_dcmd *dcmd = NULL;
4934
4935 spin_lock(&dev->dcmd_lock);
4936 if (!list_empty(&dev->dcmd_list)) {
4937 dcmd = list_entry(dev->dcmd_list.next,
4938 struct ssd_dcmd, list);
4939 list_del_init(&dcmd->list);
4940 }
4941 spin_unlock(&dev->dcmd_lock);
4942
4943 return dcmd;
4944}
4945
4946static void ssd_cleanup_dcmd(struct ssd_device *dev)
4947{
4948 kfree(dev->dcmd);
4949}
4950
4951static int ssd_init_dcmd(struct ssd_device *dev)
4952{
4953 struct ssd_dcmd *dcmd;
4954 int dcmd_sz = sizeof(struct ssd_dcmd)*dev->hw_info.cmd_fifo_sz;
4955 int i;
4956
4957 spin_lock_init(&dev->dcmd_lock);
4958 INIT_LIST_HEAD(&dev->dcmd_list);
4959 init_waitqueue_head(&dev->dcmd_wq);
4960
4961 dev->dcmd = kmalloc(dcmd_sz, GFP_KERNEL);
4962 if (!dev->dcmd) {
4963 hio_warn("%s: can not alloc dcmd\n", dev->name);
4964 goto out_alloc_dcmd;
4965 }
4966 memset(dev->dcmd, 0, dcmd_sz);
4967
4968 for (i=0, dcmd=dev->dcmd; i<(int)dev->hw_info.cmd_fifo_sz; i++, dcmd++) {
4969 dcmd->dev = dev;
4970 INIT_LIST_HEAD(&dcmd->list);
4971 list_add_tail(&dcmd->list, &dev->dcmd_list);
4972 }
4973
4974 return 0;
4975
4976out_alloc_dcmd:
4977 return -ENOMEM;
4978}
4979
4980static void ssd_put_dmsg(void *msg)
4981{
4982 struct ssd_dcmd *dcmd = container_of(msg, struct ssd_dcmd, msg);
4983 struct ssd_device *dev = (struct ssd_device *)dcmd->dev;
4984
4985 memset(dcmd->msg, 0, SSD_DCMD_MAX_SZ);
4986 ssd_put_dcmd(dcmd);
4987 wake_up(&dev->dcmd_wq);
4988}
4989
4990static void *ssd_get_dmsg(struct ssd_device *dev)
4991{
4992 struct ssd_dcmd *dcmd = ssd_get_dcmd(dev);
4993
4994 while (!dcmd) {
4995 DEFINE_WAIT(wait);
4996 prepare_to_wait_exclusive(&dev->dcmd_wq, &wait, TASK_UNINTERRUPTIBLE);
4997 schedule();
4998
4999 dcmd = ssd_get_dcmd(dev);
5000
5001 finish_wait(&dev->dcmd_wq, &wait);
5002 }
5003 return dcmd->msg;
5004}
5005
5006/* do direct cmd */
5007static int ssd_do_request(struct ssd_device *dev, int rw, void *msg, int *done)
5008{
5009 DECLARE_COMPLETION(wait);
5010 struct ssd_cmd *cmd;
5011 int tag;
5012 int ret = 0;
5013
5014 tag = ssd_get_tag(dev, 1);
5015 if (tag < 0) {
5016 return -EBUSY;
5017 }
5018
5019 cmd = &dev->cmd[tag];
5020 cmd->nsegs = 1;
5021 memcpy(cmd->msg, msg, SSD_DCMD_MAX_SZ);
5022 ((struct ssd_rw_msg *)cmd->msg)->tag = tag;
5023
5024 cmd->waiting = &wait;
5025
5026 dev->scmd(cmd);
5027
5028 wait_for_completion(cmd->waiting);
5029 cmd->waiting = NULL;
5030
5031 if (cmd->errors == -ETIMEDOUT) {
5032 ret = cmd->errors;
5033 } else if (cmd->errors) {
5034 ret = -EIO;
5035 }
5036
5037 if (done != NULL) {
5038 *done = cmd->nr_log;
5039 }
5040 ssd_put_tag(dev, cmd->tag);
5041
5042 return ret;
5043}
5044
5045static int ssd_do_barrier_request(struct ssd_device *dev, int rw, void *msg, int *done)
5046{
5047 DECLARE_COMPLETION(wait);
5048 struct ssd_cmd *cmd;
5049 int tag;
5050 int ret = 0;
5051
5052 tag = ssd_barrier_get_tag(dev);
5053 if (tag < 0) {
5054 return -EBUSY;
5055 }
5056
5057 cmd = &dev->cmd[tag];
5058 cmd->nsegs = 1;
5059 memcpy(cmd->msg, msg, SSD_DCMD_MAX_SZ);
5060 ((struct ssd_rw_msg *)cmd->msg)->tag = tag;
5061
5062 cmd->waiting = &wait;
5063
5064 dev->scmd(cmd);
5065
5066 wait_for_completion(cmd->waiting);
5067 cmd->waiting = NULL;
5068
5069 if (cmd->errors == -ETIMEDOUT) {
5070 ret = cmd->errors;
5071 } else if (cmd->errors) {
5072 ret = -EIO;
5073 }
5074
5075 if (done != NULL) {
5076 *done = cmd->nr_log;
5077 }
5078 ssd_barrier_put_tag(dev, cmd->tag);
5079
5080 return ret;
5081}
5082
5083#ifdef SSD_OT_PROTECT
5084static void ssd_check_temperature(struct ssd_device *dev, int temp)
5085{
5086 uint64_t val;
5087 uint32_t off;
5088 int cur;
5089 int i;
5090
5091 if (mode != SSD_DRV_MODE_STANDARD) {
5092 return;
5093 }
5094
5095 if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) {
5096 }
5097
5098 for (i=0; i<dev->hw_info.nr_ctrl; i++) {
5099 off = SSD_CTRL_TEMP_REG0 + i * sizeof(uint64_t);
5100
5101 val = ssd_reg_read(dev->ctrlp + off);
5102 if (val == 0xffffffffffffffffull) {
5103 continue;
5104 }
5105
5106 cur = (int)CUR_TEMP(val);
5107 if (cur >= temp) {
5108 if (!test_and_set_bit(SSD_HWMON_TEMP(SSD_TEMP_CTRL), &dev->hwmon)) {
5109 if (dev->protocol_info.ver > SSD_PROTOCOL_V3 && dev->protocol_info.ver < SSD_PROTOCOL_V3_2_2) {
5110 hio_warn("%s: Over temperature, please check the fans.\n", dev->name);
5111 dev->ot_delay = SSD_OT_DELAY;
5112 }
5113 }
5114 return;
5115 }
5116 }
5117
5118 if (test_and_clear_bit(SSD_HWMON_TEMP(SSD_TEMP_CTRL), &dev->hwmon)) {
5119 if (dev->protocol_info.ver > SSD_PROTOCOL_V3 && dev->protocol_info.ver < SSD_PROTOCOL_V3_2_2) {
5120 hio_warn("%s: Temperature is OK.\n", dev->name);
5121 dev->ot_delay = 0;
5122 }
5123 }
5124}
5125#endif
5126
5127static int ssd_get_ot_status(struct ssd_device *dev, int *status)
5128{
5129 uint32_t off;
5130 uint32_t val;
5131 int i;
5132
5133 if (!dev || !status) {
5134 return -EINVAL;
5135 }
5136
5137 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2_2) {
5138 for (i=0; i<dev->hw_info.nr_ctrl; i++) {
5139 off = SSD_READ_OT_REG0 + (i * SSD_CTRL_REG_ZONE_SZ);
5140 val = ssd_reg32_read(dev->ctrlp + off);
5141 if ((val >> 22) & 0x1) {
5142 *status = 1;
5143 goto out;
5144 }
5145
5146
5147 off = SSD_WRITE_OT_REG0 + (i * SSD_CTRL_REG_ZONE_SZ);
5148 val = ssd_reg32_read(dev->ctrlp + off);
5149 if ((val >> 22) & 0x1) {
5150 *status = 1;
5151 goto out;
5152 }
5153 }
5154 } else {
5155 *status = !!dev->ot_delay;
5156 }
5157
5158out:
5159 return 0;
5160}
5161
5162static void ssd_set_ot_protect(struct ssd_device *dev, int protect)
5163{
5164 uint32_t off;
5165 uint32_t val;
5166 int i;
5167
5168 mutex_lock(&dev->fw_mutex);
5169
5170 dev->ot_protect = !!protect;
5171
5172 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2_2) {
5173 for (i=0; i<dev->hw_info.nr_ctrl; i++) {
5174 off = SSD_READ_OT_REG0 + (i * SSD_CTRL_REG_ZONE_SZ);
5175 val = ssd_reg32_read(dev->ctrlp + off);
5176 if (dev->ot_protect) {
5177 val |= (1U << 21);
5178 } else {
5179 val &= ~(1U << 21);
5180 }
5181 ssd_reg32_write(dev->ctrlp + off, val);
5182
5183
5184 off = SSD_WRITE_OT_REG0 + (i * SSD_CTRL_REG_ZONE_SZ);
5185 val = ssd_reg32_read(dev->ctrlp + off);
5186 if (dev->ot_protect) {
5187 val |= (1U << 21);
5188 } else {
5189 val &= ~(1U << 21);
5190 }
5191 ssd_reg32_write(dev->ctrlp + off, val);
5192 }
5193 }
5194
5195 mutex_unlock(&dev->fw_mutex);
5196}
5197
5198static int ssd_init_ot_protect(struct ssd_device *dev)
5199{
5200 ssd_set_ot_protect(dev, ot_protect);
5201
5202#ifdef SSD_OT_PROTECT
5203 ssd_check_temperature(dev, SSD_OT_TEMP);
5204#endif
5205
5206 return 0;
5207}
5208
5209/* log */
5210static int ssd_read_log(struct ssd_device *dev, int ctrl_idx, void *buf, int *nr_log)
5211{
5212 struct ssd_log_op_msg *msg;
5213 struct ssd_log_msg *lmsg;
5214 dma_addr_t buf_dma;
5215 size_t length = dev->hw_info.log_sz;
5216 int ret = 0;
5217
5218 if (ctrl_idx >= dev->hw_info.nr_ctrl) {
5219 return -EINVAL;
5220 }
5221
5222 buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_FROMDEVICE);
5223#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26))
5224 ret = dma_mapping_error(buf_dma);
5225#else
5226 ret = dma_mapping_error(&(dev->pdev->dev), buf_dma);
5227#endif
5228 if (ret) {
5229 hio_warn("%s: unable to map read DMA buffer\n", dev->name);
5230 goto out_dma_mapping;
5231 }
5232
5233 msg = (struct ssd_log_op_msg *)ssd_get_dmsg(dev);
5234
5235 if (dev->protocol_info.ver < SSD_PROTOCOL_V3) {
5236 lmsg = (struct ssd_log_msg *)msg;
5237 lmsg->fun = SSD_FUNC_READ_LOG;
5238 lmsg->ctrl_idx = ctrl_idx;
5239 lmsg->buf = buf_dma;
5240 } else {
5241 msg->fun = SSD_FUNC_READ_LOG;
5242 msg->ctrl_idx = ctrl_idx;
5243 msg->buf = buf_dma;
5244 }
5245
5246 ret = ssd_do_request(dev, READ, msg, nr_log);
5247 ssd_put_dmsg(msg);
5248
5249 pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_FROMDEVICE);
5250
5251out_dma_mapping:
5252 return ret;
5253}
5254
5255#define SSD_LOG_PRINT_BUF_SZ 256
5256static int ssd_parse_log(struct ssd_device *dev, struct ssd_log *log, int print)
5257{
5258 struct ssd_log_desc *log_desc = ssd_log_desc;
5259 struct ssd_log_entry *le;
5260 char *sn = NULL;
5261 char print_buf[SSD_LOG_PRINT_BUF_SZ];
5262 int print_len;
5263
5264 le = &log->le;
5265
5266 /* find desc */
5267 while (log_desc->event != SSD_UNKNOWN_EVENT) {
5268 if (log_desc->event == le->event) {
5269 break;
5270 }
5271 log_desc++;
5272 }
5273
5274 if (!print) {
5275 goto out;
5276 }
5277
5278 if (log_desc->level < log_level) {
5279 goto out;
5280 }
5281
5282 /* parse */
5283 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
5284 sn = dev->label.sn;
5285 } else {
5286 sn = dev->labelv3.barcode;
5287 }
5288
5289 print_len = snprintf(print_buf, SSD_LOG_PRINT_BUF_SZ, "%s (%s): <%#x>", dev->name, sn, le->event);
5290
5291 if (log->ctrl_idx != SSD_LOG_SW_IDX) {
5292 print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " controller %d", log->ctrl_idx);
5293 }
5294
5295 switch (log_desc->data) {
5296 case SSD_LOG_DATA_NONE:
5297 break;
5298 case SSD_LOG_DATA_LOC:
5299 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
5300 print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " flash %d", le->data.loc.flash);
5301 if (log_desc->sblock) {
5302 print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " block %d", le->data.loc.block);
5303 }
5304 if (log_desc->spage) {
5305 print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " page %d", le->data.loc.page);
5306 }
5307 } else {
5308 print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " flash %d", le->data.loc1.flash);
5309 if (log_desc->sblock) {
5310 print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " block %d", le->data.loc1.block);
5311 }
5312 if (log_desc->spage) {
5313 print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " page %d", le->data.loc1.page);
5314 }
5315 }
5316 break;
5317 case SSD_LOG_DATA_HEX:
5318 print_len += snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), " info %#x", le->data.val);
5319 break;
5320 default:
5321 break;
5322 }
5323 /*print_len += */snprintf((print_buf + print_len), (SSD_LOG_PRINT_BUF_SZ - print_len), ": %s", log_desc->desc);
5324
5325 switch (log_desc->level) {
5326 case SSD_LOG_LEVEL_INFO:
5327 hio_info("%s\n", print_buf);
5328 break;
5329 case SSD_LOG_LEVEL_NOTICE:
5330 hio_note("%s\n", print_buf);
5331 break;
5332 case SSD_LOG_LEVEL_WARNING:
5333 hio_warn("%s\n", print_buf);
5334 break;
5335 case SSD_LOG_LEVEL_ERR:
5336 hio_err("%s\n", print_buf);
5337 //printk(KERN_ERR MODULE_NAME": some exception occurred, please check the data or refer to FAQ.");
5338 break;
5339 default:
5340 hio_warn("%s\n", print_buf);
5341 break;
5342 }
5343
5344out:
5345 return log_desc->level;
5346}
5347
5348static int ssd_bm_get_sfstatus(struct ssd_device *dev, uint16_t *status);
5349static int ssd_switch_wmode(struct ssd_device *dev, int wmode);
5350
5351
5352static int ssd_handle_event(struct ssd_device *dev, uint16_t event, int level)
5353{
5354 int ret = 0;
5355
5356 switch (event) {
5357 case SSD_LOG_OVER_TEMP: {
5358#ifdef SSD_OT_PROTECT
5359 if (!test_and_set_bit(SSD_HWMON_TEMP(SSD_TEMP_CTRL), &dev->hwmon)) {
5360 if (dev->protocol_info.ver > SSD_PROTOCOL_V3 && dev->protocol_info.ver < SSD_PROTOCOL_V3_2_2) {
5361 hio_warn("%s: Over temperature, please check the fans.\n", dev->name);
5362 dev->ot_delay = SSD_OT_DELAY;
5363 }
5364 }
5365#endif
5366 break;
5367 }
5368
5369 case SSD_LOG_NORMAL_TEMP: {
5370#ifdef SSD_OT_PROTECT
5371 /* need to check all controller's temperature */
5372 ssd_check_temperature(dev, SSD_OT_TEMP_HYST);
5373#endif
5374 break;
5375 }
5376
5377 case SSD_LOG_BATTERY_FAULT: {
5378 uint16_t sfstatus;
5379
5380 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
5381 if (!ssd_bm_get_sfstatus(dev, &sfstatus)) {
5382 ssd_gen_swlog(dev, SSD_LOG_BM_SFSTATUS, sfstatus);
5383 }
5384 }
5385
5386 if (!test_and_set_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) {
5387 ssd_switch_wmode(dev, dev->user_wmode);
5388 }
5389 break;
5390 }
5391
5392 case SSD_LOG_BATTERY_OK: {
5393 if (test_and_clear_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) {
5394 ssd_switch_wmode(dev, dev->user_wmode);
5395 }
5396 break;
5397 }
5398
5399 case SSD_LOG_BOARD_VOLT_FAULT: {
5400 ssd_mon_boardvolt(dev);
5401 break;
5402 }
5403
5404 case SSD_LOG_CLEAR_LOG: {
5405 /* update smart */
5406 memset(&dev->smart.log_info, 0, sizeof(struct ssd_log_info));
5407 break;
5408 }
5409
5410 case SSD_LOG_CAP_VOLT_FAULT:
5411 case SSD_LOG_CAP_LEARN_FAULT:
5412 case SSD_LOG_CAP_SHORT_CIRCUIT: {
5413 if (!test_and_set_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) {
5414 ssd_switch_wmode(dev, dev->user_wmode);
5415 }
5416 break;
5417 }
5418
5419 default:
5420 break;
5421 }
5422
5423 /* ssd event call */
5424 if (dev->event_call) {
5425 dev->event_call(dev->gd, event, level);
5426
5427 /* FIXME */
5428 if (SSD_LOG_CAP_VOLT_FAULT == event || SSD_LOG_CAP_LEARN_FAULT == event || SSD_LOG_CAP_SHORT_CIRCUIT == event) {
5429 dev->event_call(dev->gd, SSD_LOG_BATTERY_FAULT, level);
5430 }
5431 }
5432
5433 return ret;
5434}
5435
5436static int ssd_save_log(struct ssd_device *dev, struct ssd_log *log)
5437{
5438 uint32_t off, size;
5439 void *internal_log;
5440 int ret = 0;
5441
5442 mutex_lock(&dev->internal_log_mutex);
5443
5444 size = sizeof(struct ssd_log);
5445 off = dev->internal_log.nr_log * size;
5446
5447 if (off == dev->rom_info.log_sz) {
5448 if (dev->internal_log.nr_log == dev->smart.log_info.nr_log) {
5449 hio_warn("%s: internal log is full\n", dev->name);
5450 }
5451 goto out;
5452 }
5453
5454 internal_log = dev->internal_log.log + off;
5455 memcpy(internal_log, log, size);
5456
5457 if (dev->protocol_info.ver > SSD_PROTOCOL_V3) {
5458 off += dev->rom_info.log_base;
5459
5460 ret = ssd_spi_write(dev, log, off, size);
5461 if (ret) {
5462 goto out;
5463 }
5464 }
5465
5466 dev->internal_log.nr_log++;
5467
5468out:
5469 mutex_unlock(&dev->internal_log_mutex);
5470 return ret;
5471}
5472
5473static int ssd_save_swlog(struct ssd_device *dev, uint16_t event, uint32_t data)
5474{
5475 struct ssd_log log;
5476 struct timeval tv;
5477 int level;
5478 int ret = 0;
5479
5480 if (unlikely(mode != SSD_DRV_MODE_STANDARD))
5481 return 0;
5482
5483 memset(&log, 0, sizeof(struct ssd_log));
5484
5485 do_gettimeofday(&tv);
5486 log.ctrl_idx = SSD_LOG_SW_IDX;
5487 log.time = tv.tv_sec;
5488 log.le.event = event;
5489 log.le.data.val = data;
5490
5491 level = ssd_parse_log(dev, &log, 0);
5492 if (level >= SSD_LOG_LEVEL) {
5493 ret = ssd_save_log(dev, &log);
5494 }
5495
5496 /* set alarm */
5497 if (SSD_LOG_LEVEL_ERR == level) {
5498 ssd_set_alarm(dev);
5499 }
5500
5501 /* update smart */
5502 dev->smart.log_info.nr_log++;
5503 dev->smart.log_info.stat[level]++;
5504
5505 /* handle event */
5506 ssd_handle_event(dev, event, level);
5507
5508 return ret;
5509}
5510
5511static int ssd_gen_swlog(struct ssd_device *dev, uint16_t event, uint32_t data)
5512{
5513 struct ssd_log_entry le;
5514 int ret;
5515
5516 if (unlikely(mode != SSD_DRV_MODE_STANDARD))
5517 return 0;
5518
5519 /* slave port ? */
5520 if (dev->slave) {
5521 return 0;
5522 }
5523
5524 memset(&le, 0, sizeof(struct ssd_log_entry));
5525 le.event = event;
5526 le.data.val = data;
5527
5528 ret = sfifo_put(&dev->log_fifo, &le);
5529 if (ret) {
5530 return ret;
5531 }
5532
5533 if (test_bit(SSD_INIT_WORKQ, &dev->state)) {
5534 queue_work(dev->workq, &dev->log_work);
5535 }
5536
5537 return 0;
5538}
5539
5540static int ssd_do_swlog(struct ssd_device *dev)
5541{
5542 struct ssd_log_entry le;
5543 int ret = 0;
5544
5545 memset(&le, 0, sizeof(struct ssd_log_entry));
5546 while (!sfifo_get(&dev->log_fifo, &le)) {
5547 ret = ssd_save_swlog(dev, le.event, le.data.val);
5548 if (ret) {
5549 break;
5550 }
5551 }
5552
5553 return ret;
5554}
5555
5556static int __ssd_clear_log(struct ssd_device *dev)
5557{
5558 uint32_t off, length;
5559 int ret;
5560
5561 if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) {
5562 return 0;
5563 }
5564
5565 if (dev->internal_log.nr_log == 0) {
5566 return 0;
5567 }
5568
5569 mutex_lock(&dev->internal_log_mutex);
5570
5571 off = dev->rom_info.log_base;
5572 length = dev->rom_info.log_sz;
5573
5574 ret = ssd_spi_erase(dev, off, length);
5575 if (ret) {
5576 hio_warn("%s: log erase: failed\n", dev->name);
5577 goto out;
5578 }
5579
5580 dev->internal_log.nr_log = 0;
5581
5582out:
5583 mutex_unlock(&dev->internal_log_mutex);
5584 return ret;
5585}
5586
5587static int ssd_clear_log(struct ssd_device *dev)
5588{
5589 int ret;
5590
5591 ret = __ssd_clear_log(dev);
5592 if(!ret) {
5593 ssd_gen_swlog(dev, SSD_LOG_CLEAR_LOG, 0);
5594 }
5595
5596 return ret;
5597}
5598
5599static int ssd_do_log(struct ssd_device *dev, int ctrl_idx, void *buf)
5600{
5601 struct ssd_log_entry *le;
5602 struct ssd_log log;
5603 struct timeval tv;
5604 int nr_log = 0;
5605 int level;
5606 int ret = 0;
5607
5608 ret = ssd_read_log(dev, ctrl_idx, buf, &nr_log);
5609 if (ret) {
5610 return ret;
5611 }
5612
5613 do_gettimeofday(&tv);
5614
5615 log.time = tv.tv_sec;
5616 log.ctrl_idx = ctrl_idx;
5617
5618 le = (ssd_log_entry_t *)buf;
5619 while (nr_log > 0) {
5620 memcpy(&log.le, le, sizeof(struct ssd_log_entry));
5621
5622 level = ssd_parse_log(dev, &log, 1);
5623 if (level >= SSD_LOG_LEVEL) {
5624 ssd_save_log(dev, &log);
5625 }
5626
5627 /* set alarm */
5628 if (SSD_LOG_LEVEL_ERR == level) {
5629 ssd_set_alarm(dev);
5630 }
5631
5632 dev->smart.log_info.nr_log++;
5633 if (SSD_LOG_SEU_FAULT != le->event && SSD_LOG_SEU_FAULT1 != le->event) {
5634 dev->smart.log_info.stat[level]++;
5635 } else {
5636 /* SEU fault */
5637
5638 /* log to the volatile log info */
5639 dev->log_info.nr_log++;
5640 dev->log_info.stat[level]++;
5641
5642 /* do something */
5643 dev->reload_fw = 1;
5644 ssd_reg32_write(dev->ctrlp + SSD_RELOAD_FW_REG, SSD_RELOAD_FLAG);
5645
5646 /*dev->readonly = 1;
5647 set_disk_ro(dev->gd, 1);
5648 hio_warn("%s: switched to read-only mode.\n", dev->name);*/
5649 }
5650
5651 /* handle event */
5652 ssd_handle_event(dev, le->event, level);
5653
5654 le++;
5655 nr_log--;
5656 }
5657
5658 return 0;
5659}
5660
5661#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20))
5662static void ssd_log_worker(void *data)
5663{
5664 struct ssd_device *dev = (struct ssd_device *)data;
5665#else
5666static void ssd_log_worker(struct work_struct *work)
5667{
5668 struct ssd_device *dev = container_of(work, struct ssd_device, log_work);
5669#endif
5670 int i;
5671 int ret;
5672
5673 if (!test_bit(SSD_LOG_ERR, &dev->state) && test_bit(SSD_ONLINE, &dev->state)) {
5674 /* alloc log buf */
5675 if (!dev->log_buf) {
5676 dev->log_buf = kmalloc(dev->hw_info.log_sz, GFP_KERNEL);
5677 if (!dev->log_buf) {
5678 hio_warn("%s: ssd_log_worker: no mem\n", dev->name);
5679 return;
5680 }
5681 }
5682
5683 /* get log */
5684 if (test_and_clear_bit(SSD_LOG_HW, &dev->state)) {
5685 for (i=0; i<dev->hw_info.nr_ctrl; i++) {
5686 ret = ssd_do_log(dev, i, dev->log_buf);
5687 if (ret) {
5688 (void)test_and_set_bit(SSD_LOG_ERR, &dev->state);
5689 hio_warn("%s: do log fail\n", dev->name);
5690 }
5691 }
5692 }
5693 }
5694
5695 ret = ssd_do_swlog(dev);
5696 if (ret) {
5697 hio_warn("%s: do swlog fail\n", dev->name);
5698 }
5699}
5700
5701static void ssd_cleanup_log(struct ssd_device *dev)
5702{
5703 if (dev->log_buf) {
5704 kfree(dev->log_buf);
5705 dev->log_buf = NULL;
5706 }
5707
5708 sfifo_free(&dev->log_fifo);
5709
5710 if (dev->internal_log.log) {
5711 vfree(dev->internal_log.log);
a9d1e0c7 5712 dev->internal_log.nr_log = 0;
a6a796ca
HSDT
5713 dev->internal_log.log = NULL;
5714 }
5715}
5716
5717static int ssd_init_log(struct ssd_device *dev)
5718{
5719 struct ssd_log *log;
5720 uint32_t off, size;
5721 uint32_t len = 0;
5722 int ret = 0;
5723
5724 mutex_init(&dev->internal_log_mutex);
5725
5726#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20))
5727 INIT_WORK(&dev->log_work, ssd_log_worker, dev);
5728#else
5729 INIT_WORK(&dev->log_work, ssd_log_worker);
5730#endif
5731
5732 off = dev->rom_info.log_base;
5733 size = dev->rom_info.log_sz;
5734
a9d1e0c7 5735 dev->internal_log.nr_log = 0;
a6a796ca
HSDT
5736 dev->internal_log.log = vmalloc(size);
5737 if (!dev->internal_log.log) {
5738 ret = -ENOMEM;
5739 goto out_alloc_log;
5740 }
5741
5742 ret = sfifo_alloc(&dev->log_fifo, SSD_LOG_FIFO_SZ, sizeof(struct ssd_log_entry));
5743 if (ret < 0) {
5744 goto out_alloc_log_fifo;
5745 }
5746
5747 if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) {
5748 return 0;
5749 }
5750
5751 log = (struct ssd_log *)dev->internal_log.log;
5752 while (len < size) {
5753 ret = ssd_spi_read(dev, log, off, sizeof(struct ssd_log));
5754 if (ret) {
5755 goto out_read_log;
5756 }
5757
5758 if (log->ctrl_idx == 0xff) {
5759 break;
5760 }
5761
5762 dev->internal_log.nr_log++;
5763 log++;
5764 len += sizeof(struct ssd_log);
5765 off += sizeof(struct ssd_log);
5766 }
5767
5768 return 0;
5769
5770out_read_log:
5771 sfifo_free(&dev->log_fifo);
5772out_alloc_log_fifo:
5773 vfree(dev->internal_log.log);
5774 dev->internal_log.log = NULL;
5775 dev->internal_log.nr_log = 0;
5776out_alloc_log:
5777 /* skip error if not in standard mode */
5778 if (mode != SSD_DRV_MODE_STANDARD) {
5779 ret = 0;
5780 }
5781 return ret;
5782}
5783
5784/* work queue */
5785static void ssd_stop_workq(struct ssd_device *dev)
5786{
5787 test_and_clear_bit(SSD_INIT_WORKQ, &dev->state);
5788 flush_workqueue(dev->workq);
5789}
5790
5791static void ssd_start_workq(struct ssd_device *dev)
5792{
5793 (void)test_and_set_bit(SSD_INIT_WORKQ, &dev->state);
5794
5795 /* log ? */
5796 queue_work(dev->workq, &dev->log_work);
5797}
5798
5799static void ssd_cleanup_workq(struct ssd_device *dev)
5800{
5801 flush_workqueue(dev->workq);
5802 destroy_workqueue(dev->workq);
5803 dev->workq = NULL;
5804}
5805
5806static int ssd_init_workq(struct ssd_device *dev)
5807{
5808 int ret = 0;
5809
5810 dev->workq = create_singlethread_workqueue(dev->name);
5811 if (!dev->workq) {
5812 ret = -ESRCH;
5813 goto out;
5814 }
5815
5816out:
5817 return ret;
5818}
5819
5820/* rom */
5821static int ssd_init_rom_info(struct ssd_device *dev)
5822{
5823 uint32_t val;
5824
5825 mutex_init(&dev->spi_mutex);
5826 mutex_init(&dev->i2c_mutex);
5827
5828 if (dev->protocol_info.ver < SSD_PROTOCOL_V3) {
5829 /* fix bug: read data to clear status */
5830 (void)ssd_reg32_read(dev->ctrlp + SSD_SPI_REG_RDATA);
5831
5832 dev->rom_info.size = SSD_ROM_SIZE;
5833 dev->rom_info.block_size = SSD_ROM_BLK_SIZE;
5834 dev->rom_info.page_size = SSD_ROM_PAGE_SIZE;
5835
5836 dev->rom_info.bridge_fw_base = SSD_ROM_BRIDGE_FW_BASE;
5837 dev->rom_info.bridge_fw_sz = SSD_ROM_BRIDGE_FW_SIZE;
5838 dev->rom_info.nr_bridge_fw = SSD_ROM_NR_BRIDGE_FW;
5839
5840 dev->rom_info.ctrl_fw_base = SSD_ROM_CTRL_FW_BASE;
5841 dev->rom_info.ctrl_fw_sz = SSD_ROM_CTRL_FW_SIZE;
5842 dev->rom_info.nr_ctrl_fw = SSD_ROM_NR_CTRL_FW;
5843
5844 dev->rom_info.log_sz = SSD_ROM_LOG_SZ;
5845
5846 dev->rom_info.vp_base = SSD_ROM_VP_BASE;
5847 dev->rom_info.label_base = SSD_ROM_LABEL_BASE;
5848 } else if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
5849 val = ssd_reg32_read(dev->ctrlp + SSD_ROM_INFO_REG);
5850 dev->rom_info.size = 0x100000 * (1U << (val & 0xFF));
5851 dev->rom_info.block_size = 0x10000 * (1U << ((val>>8) & 0xFF));
5852 dev->rom_info.page_size = (val>>16) & 0xFFFF;
5853
5854 val = ssd_reg32_read(dev->ctrlp + SSD_ROM_BRIDGE_FW_INFO_REG);
5855 dev->rom_info.bridge_fw_base = dev->rom_info.block_size * (val & 0xFFFF);
5856 dev->rom_info.bridge_fw_sz = dev->rom_info.block_size * ((val>>16) & 0x3FFF);
5857 dev->rom_info.nr_bridge_fw = ((val >> 30) & 0x3) + 1;
5858
5859 val = ssd_reg32_read(dev->ctrlp + SSD_ROM_CTRL_FW_INFO_REG);
5860 dev->rom_info.ctrl_fw_base = dev->rom_info.block_size * (val & 0xFFFF);
5861 dev->rom_info.ctrl_fw_sz = dev->rom_info.block_size * ((val>>16) & 0x3FFF);
5862 dev->rom_info.nr_ctrl_fw = ((val >> 30) & 0x3) + 1;
5863
5864 dev->rom_info.bm_fw_base = dev->rom_info.ctrl_fw_base + (dev->rom_info.nr_ctrl_fw * dev->rom_info.ctrl_fw_sz);
5865 dev->rom_info.bm_fw_sz = SSD_PV3_ROM_BM_FW_SZ;
5866 dev->rom_info.nr_bm_fw = SSD_PV3_ROM_NR_BM_FW;
5867
5868 dev->rom_info.log_base = dev->rom_info.bm_fw_base + (dev->rom_info.nr_bm_fw * dev->rom_info.bm_fw_sz);
5869 dev->rom_info.log_sz = SSD_ROM_LOG_SZ;
5870
5871 dev->rom_info.smart_base = dev->rom_info.log_base + dev->rom_info.log_sz;
5872 dev->rom_info.smart_sz = SSD_PV3_ROM_SMART_SZ;
5873 dev->rom_info.nr_smart = SSD_PV3_ROM_NR_SMART;
5874
5875 val = ssd_reg32_read(dev->ctrlp + SSD_ROM_VP_INFO_REG);
5876 dev->rom_info.vp_base = dev->rom_info.block_size * val;
5877 dev->rom_info.label_base = dev->rom_info.vp_base + dev->rom_info.block_size;
5878 if (dev->rom_info.label_base >= dev->rom_info.size) {
5879 dev->rom_info.label_base = dev->rom_info.vp_base - dev->rom_info.block_size;
5880 }
5881 } else {
5882 val = ssd_reg32_read(dev->ctrlp + SSD_ROM_INFO_REG);
5883 dev->rom_info.size = 0x100000 * (1U << (val & 0xFF));
5884 dev->rom_info.block_size = 0x10000 * (1U << ((val>>8) & 0xFF));
5885 dev->rom_info.page_size = (val>>16) & 0xFFFF;
5886
5887 val = ssd_reg32_read(dev->ctrlp + SSD_ROM_BRIDGE_FW_INFO_REG);
5888 dev->rom_info.bridge_fw_base = dev->rom_info.block_size * (val & 0xFFFF);
5889 dev->rom_info.bridge_fw_sz = dev->rom_info.block_size * ((val>>16) & 0x3FFF);
5890 dev->rom_info.nr_bridge_fw = ((val >> 30) & 0x3) + 1;
5891
5892 val = ssd_reg32_read(dev->ctrlp + SSD_ROM_CTRL_FW_INFO_REG);
5893 dev->rom_info.ctrl_fw_base = dev->rom_info.block_size * (val & 0xFFFF);
5894 dev->rom_info.ctrl_fw_sz = dev->rom_info.block_size * ((val>>16) & 0x3FFF);
5895 dev->rom_info.nr_ctrl_fw = ((val >> 30) & 0x3) + 1;
5896
5897 val = ssd_reg32_read(dev->ctrlp + SSD_ROM_VP_INFO_REG);
5898 dev->rom_info.vp_base = dev->rom_info.block_size * val;
5899 dev->rom_info.label_base = dev->rom_info.vp_base - SSD_PV3_2_ROM_SEC_SZ;
5900
5901 dev->rom_info.nr_smart = SSD_PV3_ROM_NR_SMART;
5902 dev->rom_info.smart_sz = SSD_PV3_2_ROM_SEC_SZ;
5903 dev->rom_info.smart_base = dev->rom_info.label_base - (dev->rom_info.smart_sz * dev->rom_info.nr_smart);
5904 if (dev->rom_info.smart_sz > dev->rom_info.block_size) {
5905 dev->rom_info.smart_sz = dev->rom_info.block_size;
5906 }
5907
5908 dev->rom_info.log_sz = SSD_PV3_2_ROM_LOG_SZ;
5909 dev->rom_info.log_base = dev->rom_info.smart_base - dev->rom_info.log_sz;
5910 }
5911
5912 return ssd_init_spi(dev);
5913}
5914
5915/* smart */
5916static int ssd_update_smart(struct ssd_device *dev, struct ssd_smart *smart)
5917{
5918 struct timeval tv;
5919 uint64_t run_time;
5920#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27))
5921 struct hd_struct *part;
5922 int cpu;
5923#endif
5924 int i, j;
5925 int ret = 0;
5926
5927 if (!test_bit(SSD_INIT_BD, &dev->state)) {
5928 return 0;
5929 }
5930
5931 do_gettimeofday(&tv);
5932 if ((uint64_t)tv.tv_sec < dev->uptime) {
5933 run_time = 0;
5934 } else {
5935 run_time = tv.tv_sec - dev->uptime;
5936 }
5937
5938 /* avoid frequently update */
5939 if (run_time >= 60) {
5940 ret = 1;
5941 }
5942
5943 /* io stat */
5944 smart->io_stat.run_time += run_time;
5945
5946#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,27))
5947 cpu = part_stat_lock();
5948 part = &dev->gd->part0;
5949 part_round_stats(cpu, part);
5950 part_stat_unlock();
5951
5952 smart->io_stat.nr_read += part_stat_read(part, ios[READ]);
5953 smart->io_stat.nr_write += part_stat_read(part, ios[WRITE]);
5954 smart->io_stat.rsectors += part_stat_read(part, sectors[READ]);
5955 smart->io_stat.wsectors += part_stat_read(part, sectors[WRITE]);
5956#elif (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,14))
5957 preempt_disable();
5958 disk_round_stats(dev->gd);
5959 preempt_enable();
5960
5961 smart->io_stat.nr_read += disk_stat_read(dev->gd, ios[READ]);
5962 smart->io_stat.nr_write += disk_stat_read(dev->gd, ios[WRITE]);
5963 smart->io_stat.rsectors += disk_stat_read(dev->gd, sectors[READ]);
5964 smart->io_stat.wsectors += disk_stat_read(dev->gd, sectors[WRITE]);
5965#else
5966 preempt_disable();
5967 disk_round_stats(dev->gd);
5968 preempt_enable();
5969
5970 smart->io_stat.nr_read += disk_stat_read(dev->gd, reads);
5971 smart->io_stat.nr_write += disk_stat_read(dev->gd, writes);
5972 smart->io_stat.rsectors += disk_stat_read(dev->gd, read_sectors);
5973 smart->io_stat.wsectors += disk_stat_read(dev->gd, write_sectors);
5974#endif
5975
5976 smart->io_stat.nr_to += atomic_read(&dev->tocnt);
5977
5978 for (i=0; i<dev->nr_queue; i++) {
5979 smart->io_stat.nr_rwerr += dev->queue[i].io_stat.nr_rwerr;
5980 smart->io_stat.nr_ioerr += dev->queue[i].io_stat.nr_ioerr;
5981 }
5982
5983 for (i=0; i<dev->nr_queue; i++) {
5984 for (j=0; j<SSD_ECC_MAX_FLIP; j++) {
5985 smart->ecc_info.bitflip[j] += dev->queue[i].ecc_info.bitflip[j];
5986 }
5987 }
5988
5989 //dev->uptime = tv.tv_sec;
5990
5991 return ret;
5992}
5993
5994static int ssd_clear_smart(struct ssd_device *dev)
5995{
5996 struct timeval tv;
5997 uint64_t sversion;
5998 uint32_t off, length;
5999 int i;
6000 int ret;
6001
6002 if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) {
6003 return 0;
6004 }
6005
6006 /* clear smart */
6007 off = dev->rom_info.smart_base;
6008 length = dev->rom_info.smart_sz * dev->rom_info.nr_smart;
6009
6010 ret = ssd_spi_erase(dev, off, length);
6011 if (ret) {
6012 hio_warn("%s: info erase: failed\n", dev->name);
6013 goto out;
6014 }
6015
6016 sversion = dev->smart.version;
6017
6018 memset(&dev->smart, 0, sizeof(struct ssd_smart));
6019 dev->smart.version = sversion + 1;
6020 dev->smart.magic = SSD_SMART_MAGIC;
6021
6022 /* clear all tmp acc */
6023 for (i=0; i<dev->nr_queue; i++) {
6024 memset(&(dev->queue[i].io_stat), 0, sizeof(struct ssd_io_stat));
6025 memset(&(dev->queue[i].ecc_info), 0, sizeof(struct ssd_ecc_info));
6026 }
6027
6028 atomic_set(&dev->tocnt, 0);
6029
6030 /* clear tmp log info */
6031 memset(&dev->log_info, 0, sizeof(struct ssd_log_info));
6032
6033 do_gettimeofday(&tv);
6034 dev->uptime = tv.tv_sec;
6035
6036 /* clear alarm ? */
6037 //ssd_clear_alarm(dev);
6038out:
6039 return ret;
6040}
6041
a9d1e0c7
KM
6042static int ssd_clear_warning(struct ssd_device *dev)
6043{
6044 uint32_t off, size;
6045 int i, ret = 0;
6046
6047 if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) {
6048 return 0;
6049 }
6050
6051 /* clear log_info warning */
6052 memset(&dev->smart.log_info, 0, sizeof(dev->smart.log_info));
6053
6054 /* clear io_stat warning */
6055 dev->smart.io_stat.nr_to = 0;
6056 dev->smart.io_stat.nr_rwerr = 0;
6057 dev->smart.io_stat.nr_ioerr = 0;
6058
6059 /* clear ecc_info warning */
6060 memset(&dev->smart.ecc_info, 0, sizeof(dev->smart.ecc_info));
6061
6062 /* clear queued warnings */
6063 for (i=0; i<dev->nr_queue; i++) {
6064 /* queued io_stat warning */
6065 dev->queue[i].io_stat.nr_to = 0;
6066 dev->queue[i].io_stat.nr_rwerr = 0;
6067 dev->queue[i].io_stat.nr_ioerr = 0;
6068
6069 /* queued ecc_info warning */
6070 memset(&(dev->queue[i].ecc_info), 0, sizeof(dev->queue[i].ecc_info));
6071 }
6072
6073 /* write smart back to nor */
6074 for (i = 0; i < dev->rom_info.nr_smart; i++) {
6075 off = dev->rom_info.smart_base + (dev->rom_info.smart_sz * i);
6076 size = dev->rom_info.smart_sz;
6077
6078 ret = ssd_spi_erase(dev, off, size);
6079 if (ret) {
6080 hio_warn("%s: warning erase: failed with code 1\n", dev->name);
6081 goto out;
6082 }
6083
6084 size = sizeof(struct ssd_smart);
6085
6086 ret = ssd_spi_write(dev, &dev->smart, off, size);
6087 if (ret) {
6088 hio_warn("%s: warning erase: failed with code 2\n", dev->name);
6089 goto out;
6090 }
6091 }
6092
6093 dev->smart.version++;
6094
6095 /* clear cmd timeout warning */
6096 atomic_set(&dev->tocnt, 0);
6097
6098 /* clear tmp log info */
6099 memset(&dev->log_info, 0, sizeof(dev->log_info));
6100
6101out:
6102 return ret;
6103}
6104
a6a796ca
HSDT
6105static int ssd_save_smart(struct ssd_device *dev)
6106{
6107 uint32_t off, size;
6108 int i;
6109 int ret = 0;
6110
6111 if (unlikely(mode != SSD_DRV_MODE_STANDARD))
6112 return 0;
6113
6114 if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) {
6115 return 0;
6116 }
6117
6118 if (!ssd_update_smart(dev, &dev->smart)) {
6119 return 0;
6120 }
6121
6122 dev->smart.version++;
6123
6124 for (i=0; i<dev->rom_info.nr_smart; i++) {
6125 off = dev->rom_info.smart_base + (dev->rom_info.smart_sz * i);
6126 size = dev->rom_info.smart_sz;
6127
6128 ret = ssd_spi_erase(dev, off, size);
6129 if (ret) {
6130 hio_warn("%s: info erase failed\n", dev->name);
6131 goto out;
6132 }
6133
6134 size = sizeof(struct ssd_smart);
6135
6136 ret = ssd_spi_write(dev, &dev->smart, off, size);
6137 if (ret) {
6138 hio_warn("%s: info write failed\n", dev->name);
6139 goto out;
6140 }
6141
6142 //xx
6143 }
6144
6145out:
6146 return ret;
6147}
6148
6149static int ssd_init_smart(struct ssd_device *dev)
6150{
6151 struct ssd_smart *smart;
6152 struct timeval tv;
6153 uint32_t off, size;
6154 int i;
6155 int ret = 0;
6156
6157 do_gettimeofday(&tv);
6158 dev->uptime = tv.tv_sec;
6159
6160 if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) {
6161 return 0;
6162 }
6163
6164 smart = kmalloc(sizeof(struct ssd_smart) * SSD_ROM_NR_SMART_MAX, GFP_KERNEL);
6165 if (!smart) {
6166 ret = -ENOMEM;
6167 goto out_nomem;
6168 }
6169
6170 memset(&dev->smart, 0, sizeof(struct ssd_smart));
6171
6172 /* read smart */
6173 for (i=0; i<dev->rom_info.nr_smart; i++) {
6174 memset(&smart[i], 0, sizeof(struct ssd_smart));
6175
6176 off = dev->rom_info.smart_base + (dev->rom_info.smart_sz * i);
6177 size = sizeof(struct ssd_smart);
6178
6179 ret = ssd_spi_read(dev, &smart[i], off, size);
6180 if (ret) {
6181 hio_warn("%s: info read failed\n", dev->name);
6182 goto out;
6183 }
6184
6185 if (smart[i].magic != SSD_SMART_MAGIC) {
6186 smart[i].magic = 0;
6187 smart[i].version = 0;
6188 continue;
6189 }
6190
6191 if (smart[i].version > dev->smart.version) {
6192 memcpy(&dev->smart, &smart[i], sizeof(struct ssd_smart));
6193 }
6194 }
6195
6196 if (dev->smart.magic != SSD_SMART_MAGIC) {
6197 /* first time power up */
6198 dev->smart.magic = SSD_SMART_MAGIC;
6199 dev->smart.version = 1;
6200 }
6201
6202 /* check log info */
6203 {
6204 struct ssd_log_info log_info;
6205 struct ssd_log *log = (struct ssd_log *)dev->internal_log.log;
6206
6207 memset(&log_info, 0, sizeof(struct ssd_log_info));
6208
6209 while (log_info.nr_log < dev->internal_log.nr_log) {
6210 /* skip the volatile log info */
6211 if (SSD_LOG_SEU_FAULT != log->le.event && SSD_LOG_SEU_FAULT1 != log->le.event) {
6212 log_info.stat[ssd_parse_log(dev, log, 0)]++;
6213 }
6214
6215 log_info.nr_log++;
6216 log++;
6217 }
6218
6219 /* check */
6220 for (i=(SSD_LOG_NR_LEVEL-1); i>=0; i--) {
6221 if (log_info.stat[i] > dev->smart.log_info.stat[i]) {
6222 /* unclean */
6223 memcpy(&dev->smart.log_info, &log_info, sizeof(struct ssd_log_info));
6224 dev->smart.version++;
6225 break;
6226 }
6227 }
6228 }
6229
6230 for (i=0; i<dev->rom_info.nr_smart; i++) {
6231 if (smart[i].magic == SSD_SMART_MAGIC && smart[i].version == dev->smart.version) {
6232 continue;
6233 }
6234
6235 off = dev->rom_info.smart_base + (dev->rom_info.smart_sz * i);
6236 size = dev->rom_info.smart_sz;
6237
6238 ret = ssd_spi_erase(dev, off, size);
6239 if (ret) {
6240 hio_warn("%s: info erase failed\n", dev->name);
6241 goto out;
6242 }
6243
6244 size = sizeof(struct ssd_smart);
6245 ret = ssd_spi_write(dev, &dev->smart, off, size);
6246 if (ret) {
6247 hio_warn("%s: info write failed\n", dev->name);
6248 goto out;
6249 }
6250
6251 //xx
6252 }
6253
6254 /* sync smart with alarm led */
6255 if (dev->smart.io_stat.nr_to || dev->smart.io_stat.nr_rwerr || dev->smart.log_info.stat[SSD_LOG_LEVEL_ERR]) {
6256 hio_warn("%s: some fault found in the history info\n", dev->name);
6257 ssd_set_alarm(dev);
6258 }
6259
6260out:
6261 kfree(smart);
6262out_nomem:
6263 /* skip error if not in standard mode */
6264 if (mode != SSD_DRV_MODE_STANDARD) {
6265 ret = 0;
6266 }
6267 return ret;
6268}
6269
6270/* bm */
6271static int __ssd_bm_get_version(struct ssd_device *dev, uint16_t *ver)
6272{
6273 struct ssd_bm_manufacturer_data bm_md = {0};
6274 uint16_t sc_id = SSD_BM_SYSTEM_DATA_SUBCLASS_ID;
6275 uint8_t cmd;
6276 int ret = 0;
6277
6278 if (!dev || !ver) {
6279 return -EINVAL;
6280 }
6281
6282 mutex_lock(&dev->bm_mutex);
6283
6284 cmd = SSD_BM_DATA_FLASH_SUBCLASS_ID;
6285 ret = ssd_smbus_write_word(dev, SSD_BM_SLAVE_ADDRESS, cmd, (uint8_t *)&sc_id);
6286 if (ret) {
6287 goto out;
6288 }
6289
6290 cmd = SSD_BM_DATA_FLASH_SUBCLASS_ID_PAGE1;
6291 ret = ssd_smbus_read_block(dev, SSD_BM_SLAVE_ADDRESS, cmd, sizeof(struct ssd_bm_manufacturer_data), (uint8_t *)&bm_md);
6292 if (ret) {
6293 goto out;
6294 }
6295
6296 if (bm_md.firmware_ver & 0xF000) {
6297 ret = -EIO;
6298 goto out;
6299 }
6300
6301 *ver = bm_md.firmware_ver;
6302
6303out:
6304 mutex_unlock(&dev->bm_mutex);
6305 return ret;
6306}
6307
6308static int ssd_bm_get_version(struct ssd_device *dev, uint16_t *ver)
6309{
6310 uint16_t tmp = 0;
6311 int i = SSD_BM_RETRY_MAX;
6312 int ret = 0;
6313
6314 while (i-- > 0) {
6315 ret = __ssd_bm_get_version(dev, &tmp);
6316 if (!ret) {
6317 break;
6318 }
6319 }
6320 if (ret) {
6321 return ret;
6322 }
6323
6324 *ver = tmp;
6325
6326 return 0;
6327}
6328
6329static int __ssd_bm_nr_cap(struct ssd_device *dev, int *nr_cap)
6330{
6331 struct ssd_bm_configuration_registers bm_cr;
6332 uint16_t sc_id = SSD_BM_CONFIGURATION_REGISTERS_ID;
6333 uint8_t cmd;
6334 int ret;
6335
6336 mutex_lock(&dev->bm_mutex);
6337
6338 cmd = SSD_BM_DATA_FLASH_SUBCLASS_ID;
6339 ret = ssd_smbus_write_word(dev, SSD_BM_SLAVE_ADDRESS, cmd, (uint8_t *)&sc_id);
6340 if (ret) {
6341 goto out;
6342 }
6343
6344 cmd = SSD_BM_DATA_FLASH_SUBCLASS_ID_PAGE1;
6345 ret = ssd_smbus_read_block(dev, SSD_BM_SLAVE_ADDRESS, cmd, sizeof(struct ssd_bm_configuration_registers), (uint8_t *)&bm_cr);
6346 if (ret) {
6347 goto out;
6348 }
6349
6350 if (bm_cr.operation_cfg.cc == 0 || bm_cr.operation_cfg.cc > 4) {
6351 ret = -EIO;
6352 goto out;
6353 }
6354
6355 *nr_cap = bm_cr.operation_cfg.cc + 1;
6356
6357out:
6358 mutex_unlock(&dev->bm_mutex);
6359 return ret;
6360}
6361
6362static int ssd_bm_nr_cap(struct ssd_device *dev, int *nr_cap)
6363{
6364 int tmp = 0;
6365 int i = SSD_BM_RETRY_MAX;
6366 int ret = 0;
6367
6368 while (i-- > 0) {
6369 ret = __ssd_bm_nr_cap(dev, &tmp);
6370 if (!ret) {
6371 break;
6372 }
6373 }
6374 if (ret) {
6375 return ret;
6376 }
6377
6378 *nr_cap = tmp;
6379
6380 return 0;
6381}
6382
6383static int ssd_bm_enter_cap_learning(struct ssd_device *dev)
6384{
6385 uint16_t buf = SSD_BM_ENTER_CAP_LEARNING;
6386 uint8_t cmd = SSD_BM_MANUFACTURERACCESS;
6387 int ret;
6388
6389 ret = ssd_smbus_write_word(dev, SSD_BM_SLAVE_ADDRESS, cmd, (uint8_t *)&buf);
6390 if (ret) {
6391 goto out;
6392 }
6393
6394out:
6395 return ret;
6396}
6397
6398static int ssd_bm_get_sfstatus(struct ssd_device *dev, uint16_t *status)
6399{
6400 uint16_t val = 0;
6401 uint8_t cmd = SSD_BM_SAFETYSTATUS;
6402 int ret;
6403
6404 ret = ssd_smbus_read_word(dev, SSD_BM_SLAVE_ADDRESS, cmd, (uint8_t *)&val);
6405 if (ret) {
6406 goto out;
6407 }
6408
6409 *status = val;
6410out:
6411 return ret;
6412}
6413
6414static int ssd_bm_get_opstatus(struct ssd_device *dev, uint16_t *status)
6415{
6416 uint16_t val = 0;
6417 uint8_t cmd = SSD_BM_OPERATIONSTATUS;
6418 int ret;
6419
6420 ret = ssd_smbus_read_word(dev, SSD_BM_SLAVE_ADDRESS, cmd, (uint8_t *)&val);
6421 if (ret) {
6422 goto out;
6423 }
6424
6425 *status = val;
6426out:
6427 return ret;
6428}
6429
6430static int ssd_get_bmstruct(struct ssd_device *dev, struct ssd_bm *bm_status_out)
6431{
6432 struct sbs_cmd *bm_sbs = ssd_bm_sbs;
6433 struct ssd_bm bm_status;
6434 uint8_t buf[2] = {0, };
6435 uint16_t val = 0;
6436 uint16_t cval;
6437 int ret = 0;
6438
6439 memset(&bm_status, 0, sizeof(struct ssd_bm));
6440
6441 while (bm_sbs->desc != NULL) {
6442 switch (bm_sbs->size) {
6443 case SBS_SIZE_BYTE:
6444 ret = ssd_smbus_read_byte(dev, SSD_BM_SLAVE_ADDRESS, bm_sbs->cmd, buf);
6445 if (ret) {
6446 //printf("Error: smbus read byte %#x\n", bm_sbs->cmd);
6447 goto out;
6448 }
6449 val = buf[0];
6450 break;
6451 case SBS_SIZE_WORD:
6452 ret = ssd_smbus_read_word(dev, SSD_BM_SLAVE_ADDRESS, bm_sbs->cmd, (uint8_t *)&val);
6453 if (ret) {
6454 //printf("Error: smbus read word %#x\n", bm_sbs->cmd);
6455 goto out;
6456 }
6457 //val = *(uint16_t *)buf;
6458 break;
6459 default:
6460 ret = -1;
6461 goto out;
6462 break;
6463 }
6464
6465 switch (bm_sbs->unit) {
6466 case SBS_UNIT_VALUE:
6467 *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val & bm_sbs->mask;
6468 break;
6469 case SBS_UNIT_TEMPERATURE:
6470 cval = (uint16_t)(val - 2731) / 10;
6471 *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = cval;
6472 break;
6473 case SBS_UNIT_VOLTAGE:
6474 *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val;
6475 break;
6476 case SBS_UNIT_CURRENT:
6477 *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val;
6478 break;
6479 case SBS_UNIT_ESR:
6480 *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val;
6481 break;
6482 case SBS_UNIT_PERCENT:
6483 *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val;
6484 break;
6485 case SBS_UNIT_CAPACITANCE:
6486 *(uint16_t *)bm_var(&bm_status, bm_sbs->off) = val;
6487 break;
6488 default:
6489 ret = -1;
6490 goto out;
6491 break;
6492 }
6493
6494 bm_sbs++;
6495 }
6496
6497 memcpy(bm_status_out, &bm_status, sizeof(struct ssd_bm));
6498
6499out:
6500 return ret;
6501}
6502
6503static int __ssd_bm_status(struct ssd_device *dev, int *status)
6504{
6505 struct ssd_bm bm_status = {0};
6506 int nr_cap = 0;
6507 int i;
6508 int ret = 0;
6509
6510 ret = ssd_get_bmstruct(dev, &bm_status);
6511 if (ret) {
6512 goto out;
6513 }
6514
6515 /* capacitor voltage */
6516 ret = ssd_bm_nr_cap(dev, &nr_cap);
6517 if (ret) {
6518 goto out;
6519 }
6520
6521 for (i=0; i<nr_cap; i++) {
6522 if (bm_status.cap_volt[i] < SSD_BM_CAP_VOLT_MIN) {
6523 *status = SSD_BMSTATUS_WARNING;
6524 goto out;
6525 }
6526 }
6527
6528 /* Safety Status */
6529 if (bm_status.sf_status) {
6530 *status = SSD_BMSTATUS_WARNING;
6531 goto out;
6532 }
6533
6534 /* charge status */
6535 if (!((bm_status.op_status >> 12) & 0x1)) {
6536 *status = SSD_BMSTATUS_CHARGING;
6537 }else{
6538 *status = SSD_BMSTATUS_OK;
6539 }
6540
6541out:
6542 return ret;
6543}
6544
6545static void ssd_set_flush_timeout(struct ssd_device *dev, int mode);
6546
6547#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20))
6548static void ssd_bm_worker(void *data)
6549{
6550 struct ssd_device *dev = (struct ssd_device *)data;
6551#else
6552static void ssd_bm_worker(struct work_struct *work)
6553{
6554 struct ssd_device *dev = container_of(work, struct ssd_device, bm_work);
6555#endif
6556
6557 uint16_t opstatus;
6558 int ret = 0;
6559
6560 if (mode != SSD_DRV_MODE_STANDARD) {
6561 return;
6562 }
6563
6564 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_1) {
6565 return;
6566 }
6567
6568 if (dev->hw_info_ext.plp_type != SSD_PLP_SCAP) {
6569 return;
6570 }
6571
6572 ret = ssd_bm_get_opstatus(dev, &opstatus);
6573 if (ret) {
6574 hio_warn("%s: get bm operationstatus failed\n", dev->name);
6575 return;
6576 }
6577
6578 /* need cap learning ? */
6579 if (!(opstatus & 0xF0)) {
6580 ret = ssd_bm_enter_cap_learning(dev);
6581 if (ret) {
6582 hio_warn("%s: enter capacitance learning failed\n", dev->name);
6583 return;
6584 }
6585 }
6586}
6587
6588static void ssd_bm_routine_start(void *data)
6589{
6590 struct ssd_device *dev;
6591
6592 if (!data) {
6593 return;
6594 }
6595 dev = data;
6596
6597 if (test_bit(SSD_INIT_WORKQ, &dev->state)) {
6598 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
6599 queue_work(dev->workq, &dev->bm_work);
6600 } else {
6601 queue_work(dev->workq, &dev->capmon_work);
6602 }
6603 }
6604}
6605
6606/* CAP */
6607static int ssd_do_cap_learn(struct ssd_device *dev, uint32_t *cap)
6608{
6609 uint32_t u1, u2, t;
6610 uint16_t val = 0;
6611 int wait = 0;
6612 int ret = 0;
6613
6614 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
6615 *cap = 0;
6616 return 0;
6617 }
6618
6619 if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') {
6620 *cap = 0;
6621 return 0;
6622 }
6623
6624 /* make sure the lm80 voltage value is updated */
6625 msleep(SSD_LM80_CONV_INTERVAL);
6626
6627 /* check if full charged */
6628 wait = 0;
6629 for (;;) {
6630 ret = ssd_smbus_read_word(dev, SSD_SENSOR_LM80_SADDRESS, SSD_PL_CAP_U1, (uint8_t *)&val);
6631 if (ret) {
6632 if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) {
6633 ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS);
6634 }
6635 goto out;
6636 }
6637 u1 = SSD_LM80_CONVERT_VOLT(u16_swap(val));
6638 if (SSD_PL_CAP_VOLT(u1) >= SSD_PL_CAP_VOLT_FULL) {
6639 break;
6640 }
6641
6642 wait++;
6643 if (wait > SSD_PL_CAP_CHARGE_MAX_WAIT) {
6644 ret = -ETIMEDOUT;
6645 goto out;
6646 }
6647 msleep(SSD_PL_CAP_CHARGE_WAIT);
6648 }
6649
6650 ret = ssd_smbus_read_word(dev, SSD_SENSOR_LM80_SADDRESS, SSD_PL_CAP_U2, (uint8_t *)&val);
6651 if (ret) {
6652 if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) {
6653 ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS);
6654 }
6655 goto out;
6656 }
6657 u2 = SSD_LM80_CONVERT_VOLT(u16_swap(val));
6658
6659 if (u1 == u2) {
6660 ret = -EINVAL;
6661 goto out;
6662 }
6663
6664 /* enter cap learn */
6665 ssd_reg32_write(dev->ctrlp + SSD_PL_CAP_LEARN_REG, 0x1);
6666
6667 wait = 0;
6668 for (;;) {
6669 msleep(SSD_PL_CAP_LEARN_WAIT);
6670
6671 t = ssd_reg32_read(dev->ctrlp + SSD_PL_CAP_LEARN_REG);
6672 if (!((t >> 1) & 0x1)) {
6673 break;
6674 }
6675
6676 wait++;
6677 if (wait > SSD_PL_CAP_LEARN_MAX_WAIT) {
6678 ret = -ETIMEDOUT;
6679 goto out;
6680 }
6681 }
6682
6683 if ((t >> 4) & 0x1) {
6684 ret = -ETIMEDOUT;
6685 goto out;
6686 }
6687
6688 t = (t >> 8);
6689 if (0 == t) {
6690 ret = -EINVAL;
6691 goto out;
6692 }
6693
6694 *cap = SSD_PL_CAP_LEARN(u1, u2, t);
6695
6696out:
6697 return ret;
6698}
6699
6700static int ssd_cap_learn(struct ssd_device *dev, uint32_t *cap)
6701{
6702 int ret = 0;
6703
6704 if (!dev || !cap) {
6705 return -EINVAL;
6706 }
6707
6708 mutex_lock(&dev->bm_mutex);
6709
6710 ssd_stop_workq(dev);
6711
6712 ret = ssd_do_cap_learn(dev, cap);
6713 if (ret) {
6714 ssd_gen_swlog(dev, SSD_LOG_CAP_LEARN_FAULT, 0);
6715 goto out;
6716 }
6717
6718 ssd_gen_swlog(dev, SSD_LOG_CAP_STATUS, *cap);
6719
6720out:
6721 ssd_start_workq(dev);
6722 mutex_unlock(&dev->bm_mutex);
6723
6724 return ret;
6725}
6726
6727static int ssd_check_pl_cap(struct ssd_device *dev)
6728{
6729 uint32_t u1;
6730 uint16_t val = 0;
6731 uint8_t low = 0;
6732 int wait = 0;
6733 int ret = 0;
6734
6735 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
6736 return 0;
6737 }
6738
6739 if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') {
6740 return 0;
6741 }
6742
6743 /* cap ready ? */
6744 wait = 0;
6745 for (;;) {
6746 ret = ssd_smbus_read_word(dev, SSD_SENSOR_LM80_SADDRESS, SSD_PL_CAP_U1, (uint8_t *)&val);
6747 if (ret) {
6748 if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) {
6749 ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS);
6750 }
6751 goto out;
6752 }
6753 u1 = SSD_LM80_CONVERT_VOLT(u16_swap(val));
6754 if (SSD_PL_CAP_VOLT(u1) >= SSD_PL_CAP_VOLT_READY) {
6755 break;
6756 }
6757
6758 wait++;
6759 if (wait > SSD_PL_CAP_CHARGE_MAX_WAIT) {
6760 ret = -ETIMEDOUT;
6761 ssd_gen_swlog(dev, SSD_LOG_CAP_VOLT_FAULT, SSD_PL_CAP_VOLT(u1));
6762 goto out;
6763 }
6764 msleep(SSD_PL_CAP_CHARGE_WAIT);
6765 }
6766
6767 low = ssd_lm80_limit[SSD_LM80_IN_CAP].low;
6768 ret = ssd_smbus_write_byte(dev, SSD_SENSOR_LM80_SADDRESS, SSD_LM80_REG_IN_MIN(SSD_LM80_IN_CAP), &low);
6769 if (ret) {
6770 goto out;
6771 }
6772
6773 /* enable cap INx */
6774 ret = ssd_lm80_enable_in(dev, SSD_SENSOR_LM80_SADDRESS, SSD_LM80_IN_CAP);
6775 if (ret) {
6776 if (!test_and_set_bit(SSD_HWMON_SENSOR(SSD_SENSOR_LM80), &dev->hwmon)) {
6777 ssd_gen_swlog(dev, SSD_LOG_SENSOR_FAULT, SSD_SENSOR_LM80_SADDRESS);
6778 }
6779 goto out;
6780 }
6781
6782out:
6783 /* skip error if not in standard mode */
6784 if (mode != SSD_DRV_MODE_STANDARD) {
6785 ret = 0;
6786 }
6787 return ret;
6788}
6789
6790static int ssd_check_pl_cap_fast(struct ssd_device *dev)
6791{
6792 uint32_t u1;
6793 uint16_t val = 0;
6794 int ret = 0;
6795
6796 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
6797 return 0;
6798 }
6799
6800 if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') {
6801 return 0;
6802 }
6803
6804 /* cap ready ? */
6805 ret = ssd_smbus_read_word(dev, SSD_SENSOR_LM80_SADDRESS, SSD_PL_CAP_U1, (uint8_t *)&val);
6806 if (ret) {
6807 goto out;
6808 }
6809 u1 = SSD_LM80_CONVERT_VOLT(u16_swap(val));
6810 if (SSD_PL_CAP_VOLT(u1) < SSD_PL_CAP_VOLT_READY) {
6811 ret = 1;
6812 }
6813
6814out:
6815 return ret;
6816}
6817
6818static int ssd_init_pl_cap(struct ssd_device *dev)
6819{
6820 int ret = 0;
6821
6822 /* set here: user write mode */
6823 dev->user_wmode = wmode;
6824
6825 mutex_init(&dev->bm_mutex);
6826
6827 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
6828 uint32_t val;
6829 val = ssd_reg32_read(dev->ctrlp + SSD_BM_FAULT_REG);
6830 if ((val >> 1) & 0x1) {
6831 (void)test_and_set_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon);
6832 }
6833 } else {
6834 ret = ssd_check_pl_cap(dev);
6835 if (ret) {
6836 (void)test_and_set_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon);
6837 }
6838 }
6839
6840 return 0;
6841}
6842
6843/* label */
6844static void __end_str(char *str, int len)
6845{
6846 int i;
6847
6848 for(i=0; i<len; i++) {
6849 if (*(str+i) == '\0')
6850 return;
6851 }
6852 *str = '\0';
6853}
6854
6855static int ssd_init_label(struct ssd_device *dev)
6856{
6857 uint32_t off;
6858 uint32_t size;
6859 int ret;
6860
6861 /* label location */
6862 off = dev->rom_info.label_base;
6863
6864 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
6865 size = sizeof(struct ssd_label);
6866
6867 /* read label */
6868 ret = ssd_spi_read(dev, &dev->label, off, size);
6869 if (ret) {
6870 memset(&dev->label, 0, size);
6871 goto out;
6872 }
6873
6874 __end_str(dev->label.date, SSD_LABEL_FIELD_SZ);
6875 __end_str(dev->label.sn, SSD_LABEL_FIELD_SZ);
6876 __end_str(dev->label.part, SSD_LABEL_FIELD_SZ);
6877 __end_str(dev->label.desc, SSD_LABEL_FIELD_SZ);
6878 __end_str(dev->label.other, SSD_LABEL_FIELD_SZ);
6879 __end_str(dev->label.maf, SSD_LABEL_FIELD_SZ);
6880 } else {
6881 size = sizeof(struct ssd_labelv3);
6882
6883 /* read label */
6884 ret = ssd_spi_read(dev, &dev->labelv3, off, size);
6885 if (ret) {
6886 memset(&dev->labelv3, 0, size);
6887 goto out;
6888 }
6889
6890 __end_str(dev->labelv3.boardtype, SSD_LABEL_FIELD_SZ);
6891 __end_str(dev->labelv3.barcode, SSD_LABEL_FIELD_SZ);
6892 __end_str(dev->labelv3.item, SSD_LABEL_FIELD_SZ);
6893 __end_str(dev->labelv3.description, SSD_LABEL_DESC_SZ);
6894 __end_str(dev->labelv3.manufactured, SSD_LABEL_FIELD_SZ);
6895 __end_str(dev->labelv3.vendorname, SSD_LABEL_FIELD_SZ);
6896 __end_str(dev->labelv3.issuenumber, SSD_LABEL_FIELD_SZ);
6897 __end_str(dev->labelv3.cleicode, SSD_LABEL_FIELD_SZ);
6898 __end_str(dev->labelv3.bom, SSD_LABEL_FIELD_SZ);
6899 }
6900
6901out:
6902 /* skip error if not in standard mode */
6903 if (mode != SSD_DRV_MODE_STANDARD) {
6904 ret = 0;
6905 }
6906 return ret;
6907}
6908
6909int ssd_get_label(struct block_device *bdev, struct ssd_label *label)
6910{
6911 struct ssd_device *dev;
6912
6913 if (!bdev || !label || !(bdev->bd_disk)) {
6914 return -EINVAL;
6915 }
6916
6917 dev = bdev->bd_disk->private_data;
6918
6919 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) {
6920 memset(label, 0, sizeof(struct ssd_label));
6921 memcpy(label->date, dev->labelv3.manufactured, SSD_LABEL_FIELD_SZ);
6922 memcpy(label->sn, dev->labelv3.barcode, SSD_LABEL_FIELD_SZ);
6923 memcpy(label->desc, dev->labelv3.boardtype, SSD_LABEL_FIELD_SZ);
6924 memcpy(label->maf, dev->labelv3.vendorname, SSD_LABEL_FIELD_SZ);
6925 } else {
6926 memcpy(label, &dev->label, sizeof(struct ssd_label));
6927 }
6928
6929 return 0;
6930}
6931
6932static int __ssd_get_version(struct ssd_device *dev, struct ssd_version_info *ver)
6933{
6934 uint16_t bm_ver = 0;
6935 int ret = 0;
6936
6937 if (dev->protocol_info.ver > SSD_PROTOCOL_V3 && dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
6938 ret = ssd_bm_get_version(dev, &bm_ver);
6939 if(ret){
6940 goto out;
6941 }
6942 }
6943
6944 ver->bridge_ver = dev->hw_info.bridge_ver;
6945 ver->ctrl_ver = dev->hw_info.ctrl_ver;
6946 ver->bm_ver = bm_ver;
6947 ver->pcb_ver = dev->hw_info.pcb_ver;
6948 ver->upper_pcb_ver = dev->hw_info.upper_pcb_ver;
6949
6950out:
6951 return ret;
6952
6953}
6954
6955int ssd_get_version(struct block_device *bdev, struct ssd_version_info *ver)
6956{
6957 struct ssd_device *dev;
6958 int ret;
6959
6960 if (!bdev || !ver || !(bdev->bd_disk)) {
6961 return -EINVAL;
6962 }
6963
6964 dev = bdev->bd_disk->private_data;
6965
6966 mutex_lock(&dev->fw_mutex);
6967 ret = __ssd_get_version(dev, ver);
6968 mutex_unlock(&dev->fw_mutex);
6969
6970 return ret;
6971}
6972
6973static int __ssd_get_temperature(struct ssd_device *dev, int *temp)
6974{
6975 uint64_t val;
6976 uint32_t off;
6977 int max = -300;
6978 int cur;
6979 int i;
6980
6981 if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) {
6982 *temp = 0;
6983 return 0;
6984 }
6985
6986 if (finject) {
6987 if (dev->db_info.type == SSD_DEBUG_LOG &&
6988 (dev->db_info.data.log.event == SSD_LOG_OVER_TEMP ||
6989 dev->db_info.data.log.event == SSD_LOG_NORMAL_TEMP ||
6990 dev->db_info.data.log.event == SSD_LOG_WARN_TEMP)) {
6991 *temp = (int)dev->db_info.data.log.extra;
6992 return 0;
6993 }
6994 }
6995
6996 for (i=0; i<dev->hw_info.nr_ctrl; i++) {
6997 off = SSD_CTRL_TEMP_REG0 + i * sizeof(uint64_t);
6998
6999 val = ssd_reg_read(dev->ctrlp + off);
7000 if (val == 0xffffffffffffffffull) {
7001 continue;
7002 }
7003
7004 cur = (int)CUR_TEMP(val);
7005 if (cur >= max) {
7006 max = cur;
7007 }
7008 }
7009
7010 *temp = max;
7011
7012 return 0;
7013}
7014
7015int ssd_get_temperature(struct block_device *bdev, int *temp)
7016{
7017 struct ssd_device *dev;
7018 int ret;
7019
7020 if (!bdev || !temp || !(bdev->bd_disk)) {
7021 return -EINVAL;
7022 }
7023
7024 dev = bdev->bd_disk->private_data;
7025
7026
7027 mutex_lock(&dev->fw_mutex);
7028 ret = __ssd_get_temperature(dev, temp);
7029 mutex_unlock(&dev->fw_mutex);
7030
7031 return ret;
7032}
7033
7034int ssd_set_otprotect(struct block_device *bdev, int otprotect)
7035 {
7036 struct ssd_device *dev;
7037
7038 if (!bdev || !(bdev->bd_disk)) {
7039 return -EINVAL;
7040 }
7041
7042 dev = bdev->bd_disk->private_data;
7043 ssd_set_ot_protect(dev, !!otprotect);
7044
7045 return 0;
7046 }
7047
7048int ssd_bm_status(struct block_device *bdev, int *status)
7049{
7050 struct ssd_device *dev;
7051 int ret = 0;
7052
7053 if (!bdev || !status || !(bdev->bd_disk)) {
7054 return -EINVAL;
7055 }
7056
7057 dev = bdev->bd_disk->private_data;
7058
7059 mutex_lock(&dev->fw_mutex);
7060 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) {
7061 if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) {
7062 *status = SSD_BMSTATUS_WARNING;
7063 } else {
7064 *status = SSD_BMSTATUS_OK;
7065 }
7066 } else if(dev->protocol_info.ver > SSD_PROTOCOL_V3) {
7067 ret = __ssd_bm_status(dev, status);
7068 } else {
7069 *status = SSD_BMSTATUS_OK;
7070 }
7071 mutex_unlock(&dev->fw_mutex);
7072
7073 return ret;
7074}
7075
7076int ssd_get_pciaddr(struct block_device *bdev, struct pci_addr *paddr)
7077{
7078 struct ssd_device *dev;
7079
7080 if (!bdev || !paddr || !bdev->bd_disk) {
7081 return -EINVAL;
7082 }
7083
7084 dev = bdev->bd_disk->private_data;
7085
7086 paddr->domain = pci_domain_nr(dev->pdev->bus);
7087 paddr->bus = dev->pdev->bus->number;
7088 paddr->slot = PCI_SLOT(dev->pdev->devfn);
7089 paddr->func= PCI_FUNC(dev->pdev->devfn);
7090
7091 return 0;
7092}
7093
7094/* acc */
7095static int ssd_bb_acc(struct ssd_device *dev, struct ssd_acc_info *acc)
7096{
7097 uint32_t val;
7098 int ctrl, chip;
7099
7100 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_1) {
7101 return -EOPNOTSUPP;
7102 }
7103
7104 acc->threshold_l1 = ssd_reg32_read(dev->ctrlp + SSD_BB_THRESHOLD_L1_REG);
7105 if (0xffffffffull == acc->threshold_l1) {
7106 return -EIO;
7107 }
7108 acc->threshold_l2 = ssd_reg32_read(dev->ctrlp + SSD_BB_THRESHOLD_L2_REG);
7109 if (0xffffffffull == acc->threshold_l2) {
7110 return -EIO;
7111 }
7112 acc->val = 0;
7113
7114 for (ctrl=0; ctrl<dev->hw_info.nr_ctrl; ctrl++) {
7115 for (chip=0; chip<dev->hw_info.nr_chip; chip++) {
7116 val = ssd_reg32_read(dev->ctrlp + SSD_BB_ACC_REG0 + (SSD_CTRL_REG_ZONE_SZ * ctrl) + (SSD_BB_ACC_REG_SZ * chip));
7117 if (0xffffffffull == acc->val) {
7118 return -EIO;
7119 }
7120 if (val > acc->val) {
7121 acc->val = val;
7122 }
7123 }
7124 }
7125
7126 return 0;
7127}
7128
7129static int ssd_ec_acc(struct ssd_device *dev, struct ssd_acc_info *acc)
7130{
7131 uint32_t val;
7132 int ctrl, chip;
7133
7134 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_1) {
7135 return -EOPNOTSUPP;
7136 }
7137
7138 acc->threshold_l1 = ssd_reg32_read(dev->ctrlp + SSD_EC_THRESHOLD_L1_REG);
7139 if (0xffffffffull == acc->threshold_l1) {
7140 return -EIO;
7141 }
7142 acc->threshold_l2 = ssd_reg32_read(dev->ctrlp + SSD_EC_THRESHOLD_L2_REG);
7143 if (0xffffffffull == acc->threshold_l2) {
7144 return -EIO;
7145 }
7146 acc->val = 0;
7147
7148 for (ctrl=0; ctrl<dev->hw_info.nr_ctrl; ctrl++) {
7149 for (chip=0; chip<dev->hw_info.nr_chip; chip++) {
7150 val = ssd_reg32_read(dev->ctrlp + SSD_EC_ACC_REG0 + (SSD_CTRL_REG_ZONE_SZ * ctrl) + (SSD_EC_ACC_REG_SZ * chip));
7151 if (0xffffffffull == acc->val) {
7152 return -EIO;
7153 }
7154
7155 if (val > acc->val) {
7156 acc->val = val;
7157 }
7158 }
7159 }
7160
7161 return 0;
7162}
7163
7164
7165/* ram r&w */
7166static int ssd_ram_read_4k(struct ssd_device *dev, void *buf, size_t length, loff_t ofs, int ctrl_idx)
7167{
7168 struct ssd_ram_op_msg *msg;
7169 dma_addr_t buf_dma;
7170 size_t len = length;
7171 loff_t ofs_w = ofs;
7172 int ret = 0;
7173
7174 if (ctrl_idx >= dev->hw_info.nr_ctrl || (uint64_t)(ofs + length) > dev->hw_info.ram_size
7175 || !length || length > dev->hw_info.ram_max_len
7176 || (length & (dev->hw_info.ram_align - 1)) != 0 || ((uint64_t)ofs & (dev->hw_info.ram_align - 1)) != 0) {
7177 return -EINVAL;
7178 }
7179
7180 len /= dev->hw_info.ram_align;
7181 do_div(ofs_w, dev->hw_info.ram_align);
7182
7183 buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_FROMDEVICE);
7184#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26))
7185 ret = dma_mapping_error(buf_dma);
7186#else
7187 ret = dma_mapping_error(&(dev->pdev->dev), buf_dma);
7188#endif
7189 if (ret) {
7190 hio_warn("%s: unable to map read DMA buffer\n", dev->name);
7191 goto out_dma_mapping;
7192 }
7193
7194 msg = (struct ssd_ram_op_msg *)ssd_get_dmsg(dev);
7195
7196 msg->fun = SSD_FUNC_RAM_READ;
7197 msg->ctrl_idx = ctrl_idx;
7198 msg->start = (uint32_t)ofs_w;
7199 msg->length = len;
7200 msg->buf = buf_dma;
7201
7202 ret = ssd_do_request(dev, READ, msg, NULL);
7203 ssd_put_dmsg(msg);
7204
7205 pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_FROMDEVICE);
7206
7207out_dma_mapping:
7208 return ret;
7209}
7210
7211static int ssd_ram_write_4k(struct ssd_device *dev, void *buf, size_t length, loff_t ofs, int ctrl_idx)
7212{
7213 struct ssd_ram_op_msg *msg;
7214 dma_addr_t buf_dma;
7215 size_t len = length;
7216 loff_t ofs_w = ofs;
7217 int ret = 0;
7218
7219 if (ctrl_idx >= dev->hw_info.nr_ctrl || (uint64_t)(ofs + length) > dev->hw_info.ram_size
7220 || !length || length > dev->hw_info.ram_max_len
7221 || (length & (dev->hw_info.ram_align - 1)) != 0 || ((uint64_t)ofs & (dev->hw_info.ram_align - 1)) != 0) {
7222 return -EINVAL;
7223 }
7224
7225 len /= dev->hw_info.ram_align;
7226 do_div(ofs_w, dev->hw_info.ram_align);
7227
7228 buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_TODEVICE);
7229#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26))
7230 ret = dma_mapping_error(buf_dma);
7231#else
7232 ret = dma_mapping_error(&(dev->pdev->dev), buf_dma);
7233#endif
7234 if (ret) {
7235 hio_warn("%s: unable to map write DMA buffer\n", dev->name);
7236 goto out_dma_mapping;
7237 }
7238
7239 msg = (struct ssd_ram_op_msg *)ssd_get_dmsg(dev);
7240
7241 msg->fun = SSD_FUNC_RAM_WRITE;
7242 msg->ctrl_idx = ctrl_idx;
7243 msg->start = (uint32_t)ofs_w;
7244 msg->length = len;
7245 msg->buf = buf_dma;
7246
7247 ret = ssd_do_request(dev, WRITE, msg, NULL);
7248 ssd_put_dmsg(msg);
7249
7250 pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_TODEVICE);
7251
7252out_dma_mapping:
7253 return ret;
7254
7255}
7256
7257static int ssd_ram_read(struct ssd_device *dev, void *buf, size_t length, loff_t ofs, int ctrl_idx)
7258{
7259 int left = length;
7260 size_t len;
7261 loff_t off = ofs;
7262 int ret = 0;
7263
7264 if (ctrl_idx >= dev->hw_info.nr_ctrl || (uint64_t)(ofs + length) > dev->hw_info.ram_size || !length
7265 || (length & (dev->hw_info.ram_align - 1)) != 0 || ((uint64_t)ofs & (dev->hw_info.ram_align - 1)) != 0) {
7266 return -EINVAL;
7267 }
7268
7269 while (left > 0) {
7270 len = dev->hw_info.ram_max_len;
7271 if (left < (int)dev->hw_info.ram_max_len) {
7272 len = left;
7273 }
7274
7275 ret = ssd_ram_read_4k(dev, buf, len, off, ctrl_idx);
7276 if (ret) {
7277 break;
7278 }
7279
7280 left -= len;
7281 off += len;
7282 buf += len;
7283 }
7284
7285 return ret;
7286}
7287
7288static int ssd_ram_write(struct ssd_device *dev, void *buf, size_t length, loff_t ofs, int ctrl_idx)
7289{
7290 int left = length;
7291 size_t len;
7292 loff_t off = ofs;
7293 int ret = 0;
7294
7295 if (ctrl_idx >= dev->hw_info.nr_ctrl || (uint64_t)(ofs + length) > dev->hw_info.ram_size || !length
7296 || (length & (dev->hw_info.ram_align - 1)) != 0 || ((uint64_t)ofs & (dev->hw_info.ram_align - 1)) != 0) {
7297 return -EINVAL;
7298 }
7299
7300 while (left > 0) {
7301 len = dev->hw_info.ram_max_len;
7302 if (left < (int)dev->hw_info.ram_max_len) {
7303 len = left;
7304 }
7305
7306 ret = ssd_ram_write_4k(dev, buf, len, off, ctrl_idx);
7307 if (ret) {
7308 break;
7309 }
7310
7311 left -= len;
7312 off += len;
7313 buf += len;
7314 }
7315
7316 return ret;
7317}
7318
7319
7320/* flash op */
7321static int ssd_check_flash(struct ssd_device *dev, int flash, int page, int ctrl_idx)
7322{
7323 int cur_ch = flash % dev->hw_info.max_ch;
7324 int cur_chip = flash /dev->hw_info.max_ch;
7325
7326 if (ctrl_idx >= dev->hw_info.nr_ctrl) {
7327 return -EINVAL;
7328 }
7329
7330 if (cur_ch >= dev->hw_info.nr_ch || cur_chip >= dev->hw_info.nr_chip) {
7331 return -EINVAL;
7332 }
7333
7334 if (page >= (int)(dev->hw_info.block_count * dev->hw_info.page_count)) {
7335 return -EINVAL;
7336 }
7337 return 0;
7338}
7339
7340static int ssd_nand_read_id(struct ssd_device *dev, void *id, int flash, int chip, int ctrl_idx)
7341{
7342 struct ssd_nand_op_msg *msg;
7343 dma_addr_t buf_dma;
7344 int ret = 0;
7345
7346 if (unlikely(!id))
7347 return -EINVAL;
7348
7349 buf_dma = pci_map_single(dev->pdev, id, SSD_NAND_ID_BUFF_SZ, PCI_DMA_FROMDEVICE);
7350#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26))
7351 ret = dma_mapping_error(buf_dma);
7352#else
7353 ret = dma_mapping_error(&(dev->pdev->dev), buf_dma);
7354#endif
7355 if (ret) {
7356 hio_warn("%s: unable to map read DMA buffer\n", dev->name);
7357 goto out_dma_mapping;
7358 }
7359
7360 if (dev->protocol_info.ver < SSD_PROTOCOL_V3) {
7361 flash = ((uint32_t)flash << 1) | (uint32_t)chip;
7362 chip = 0;
7363 }
7364
7365 msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev);
7366
7367 msg->fun = SSD_FUNC_NAND_READ_ID;
7368 msg->chip_no = flash;
7369 msg->chip_ce = chip;
7370 msg->ctrl_idx = ctrl_idx;
7371 msg->buf = buf_dma;
7372
7373 ret = ssd_do_request(dev, READ, msg, NULL);
7374 ssd_put_dmsg(msg);
7375
7376 pci_unmap_single(dev->pdev, buf_dma, SSD_NAND_ID_BUFF_SZ, PCI_DMA_FROMDEVICE);
7377
7378out_dma_mapping:
7379 return ret;
7380}
7381
7382#if 0
7383static int ssd_nand_read(struct ssd_device *dev, void *buf,
7384 int flash, int chip, int page, int page_count, int ctrl_idx)
7385{
7386 struct ssd_nand_op_msg *msg;
7387 dma_addr_t buf_dma;
7388 int length;
7389 int ret = 0;
7390
7391 if (!buf) {
7392 return -EINVAL;
7393 }
7394
7395 if ((page + page_count) > dev->hw_info.block_count*dev->hw_info.page_count) {
7396 return -EINVAL;
7397 }
7398
7399 ret = ssd_check_flash(dev, flash, page, ctrl_idx);
7400 if (ret) {
7401 return ret;
7402 }
7403
7404 length = page_count * dev->hw_info.page_size;
7405
7406 buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_FROMDEVICE);
7407#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26))
7408 ret = dma_mapping_error(buf_dma);
7409#else
7410 ret = dma_mapping_error(&(dev->pdev->dev), buf_dma);
7411#endif
7412 if (ret) {
7413 hio_warn("%s: unable to map read DMA buffer\n", dev->name);
7414 goto out_dma_mapping;
7415 }
7416
7417 if (dev->protocol_info.ver < SSD_PROTOCOL_V3) {
7418 flash = (flash << 1) | chip;
7419 chip = 0;
7420 }
7421
7422 msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev);
7423
7424 msg->fun = SSD_FUNC_NAND_READ;
7425 msg->ctrl_idx = ctrl_idx;
7426 msg->chip_no = flash;
7427 msg->chip_ce = chip;
7428 msg->page_no = page;
7429 msg->page_count = page_count;
7430 msg->buf = buf_dma;
7431
7432 ret = ssd_do_request(dev, READ, msg, NULL);
7433 ssd_put_dmsg(msg);
7434
7435 pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_FROMDEVICE);
7436
7437out_dma_mapping:
7438 return ret;
7439}
7440#endif
7441
7442static int ssd_nand_read_w_oob(struct ssd_device *dev, void *buf,
7443 int flash, int chip, int page, int count, int ctrl_idx)
7444{
7445 struct ssd_nand_op_msg *msg;
7446 dma_addr_t buf_dma;
7447 int length;
7448 int ret = 0;
7449
7450 if (!buf) {
7451 return -EINVAL;
7452 }
7453
7454 if ((page + count) > (int)(dev->hw_info.block_count * dev->hw_info.page_count)) {
7455 return -EINVAL;
7456 }
7457
7458 ret = ssd_check_flash(dev, flash, page, ctrl_idx);
7459 if (ret) {
7460 return ret;
7461 }
7462
7463 length = count * (dev->hw_info.page_size + dev->hw_info.oob_size);
7464
7465 buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_FROMDEVICE);
7466#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26))
7467 ret = dma_mapping_error(buf_dma);
7468#else
7469 ret = dma_mapping_error(&(dev->pdev->dev), buf_dma);
7470#endif
7471 if (ret) {
7472 hio_warn("%s: unable to map read DMA buffer\n", dev->name);
7473 goto out_dma_mapping;
7474 }
7475
7476 if (dev->protocol_info.ver < SSD_PROTOCOL_V3) {
7477 flash = ((uint32_t)flash << 1) | (uint32_t)chip;
7478 chip = 0;
7479 }
7480
7481 msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev);
7482
7483 msg->fun = SSD_FUNC_NAND_READ_WOOB;
7484 msg->ctrl_idx = ctrl_idx;
7485 msg->chip_no = flash;
7486 msg->chip_ce = chip;
7487 msg->page_no = page;
7488 msg->page_count = count;
7489 msg->buf = buf_dma;
7490
7491 ret = ssd_do_request(dev, READ, msg, NULL);
7492 ssd_put_dmsg(msg);
7493
7494 pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_FROMDEVICE);
7495
7496out_dma_mapping:
7497 return ret;
7498}
7499
7500/* write 1 page */
7501static int ssd_nand_write(struct ssd_device *dev, void *buf,
7502 int flash, int chip, int page, int count, int ctrl_idx)
7503{
7504 struct ssd_nand_op_msg *msg;
7505 dma_addr_t buf_dma;
7506 int length;
7507 int ret = 0;
7508
7509 if (dev->protocol_info.ver < SSD_PROTOCOL_V3) {
7510 return -EINVAL;
7511 }
7512
7513 if (!buf) {
7514 return -EINVAL;
7515 }
7516
7517 if (count != 1) {
7518 return -EINVAL;
7519 }
7520
7521 ret = ssd_check_flash(dev, flash, page, ctrl_idx);
7522 if (ret) {
7523 return ret;
7524 }
7525
7526 length = count * (dev->hw_info.page_size + dev->hw_info.oob_size);
7527
7528 /* write data to ram */
7529 /*ret = ssd_ram_write(dev, buf, length, dev->hw_info.nand_wbuff_base, ctrl_idx);
7530 if (ret) {
7531 return ret;
7532 }*/
7533
7534 buf_dma = pci_map_single(dev->pdev, buf, length, PCI_DMA_TODEVICE);
7535#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26))
7536 ret = dma_mapping_error(buf_dma);
7537#else
7538 ret = dma_mapping_error(&(dev->pdev->dev), buf_dma);
7539#endif
7540 if (ret) {
7541 hio_warn("%s: unable to map write DMA buffer\n", dev->name);
7542 goto out_dma_mapping;
7543 }
7544
7545 if (dev->protocol_info.ver < SSD_PROTOCOL_V3) {
7546 flash = ((uint32_t)flash << 1) | (uint32_t)chip;
7547 chip = 0;
7548 }
7549
7550 msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev);
7551
7552 msg->fun = SSD_FUNC_NAND_WRITE;
7553 msg->ctrl_idx = ctrl_idx;
7554 msg->chip_no = flash;
7555 msg->chip_ce = chip;
7556
7557 msg->page_no = page;
7558 msg->page_count = count;
7559 msg->buf = buf_dma;
7560
7561 ret = ssd_do_request(dev, WRITE, msg, NULL);
7562 ssd_put_dmsg(msg);
7563
7564 pci_unmap_single(dev->pdev, buf_dma, length, PCI_DMA_TODEVICE);
7565
7566out_dma_mapping:
7567 return ret;
7568}
7569
7570static int ssd_nand_erase(struct ssd_device *dev, int flash, int chip, int page, int ctrl_idx)
7571{
7572 struct ssd_nand_op_msg *msg;
7573 int ret = 0;
7574
7575 ret = ssd_check_flash(dev, flash, page, ctrl_idx);
7576 if (ret) {
7577 return ret;
7578 }
7579
7580 if (dev->protocol_info.ver < SSD_PROTOCOL_V3) {
7581 flash = ((uint32_t)flash << 1) | (uint32_t)chip;
7582 chip = 0;
7583 }
7584
7585 msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev);
7586
7587 msg->fun = SSD_FUNC_NAND_ERASE;
7588 msg->ctrl_idx = ctrl_idx;
7589 msg->chip_no = flash;
7590 msg->chip_ce = chip;
7591 msg->page_no = page;
7592
7593 ret = ssd_do_request(dev, WRITE, msg, NULL);
7594 ssd_put_dmsg(msg);
7595
7596 return ret;
7597}
7598
7599static int ssd_update_bbt(struct ssd_device *dev, int flash, int ctrl_idx)
7600{
7601 struct ssd_nand_op_msg *msg;
7602 struct ssd_flush_msg *fmsg;
7603 int ret = 0;
7604
7605 ret = ssd_check_flash(dev, flash, 0, ctrl_idx);
7606 if (ret) {
7607 return ret;
7608 }
7609
7610 msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev);
7611
7612 if (dev->protocol_info.ver < SSD_PROTOCOL_V3) {
7613 fmsg = (struct ssd_flush_msg *)msg;
7614
7615 fmsg->fun = SSD_FUNC_FLUSH;
7616 fmsg->flag = 0x1;
7617 fmsg->flash = flash;
7618 fmsg->ctrl_idx = ctrl_idx;
7619 } else {
7620 msg->fun = SSD_FUNC_FLUSH;
7621 msg->flag = 0x1;
7622 msg->chip_no = flash;
7623 msg->ctrl_idx = ctrl_idx;
7624 }
7625
7626 ret = ssd_do_request(dev, WRITE, msg, NULL);
7627 ssd_put_dmsg(msg);
7628
7629 return ret;
7630}
7631
7632/* flash controller init state */
7633static int __ssd_check_init_state(struct ssd_device *dev)
7634{
7635 uint32_t *init_state = NULL;
7636 int reg_base, reg_sz;
7637 int max_wait = SSD_INIT_MAX_WAIT;
7638 int init_wait = 0;
7639 int i, j, k;
7640 int ch_start = 0;
7641
7642/*
7643 for (i=0; i<dev->hw_info.nr_ctrl; i++) {
7644 ssd_reg32_write(dev->ctrlp + SSD_CTRL_TEST_REG0 + i * 8, test_data);
7645 read_data = ssd_reg32_read(dev->ctrlp + SSD_CTRL_TEST_REG0 + i * 8);
7646 if (read_data == ~test_data) {
7647 //dev->hw_info.nr_ctrl++;
7648 dev->hw_info.nr_ctrl_map |= 1<<i;
7649 }
7650 }
7651*/
7652
7653/*
7654 read_data = ssd_reg32_read(dev->ctrlp + SSD_READY_REG);
7655 j=0;
7656 for (i=0; i<dev->hw_info.nr_ctrl; i++) {
7657 if (((read_data>>i) & 0x1) == 0) {
7658 j++;
7659 }
7660 }
7661
7662 if (dev->hw_info.nr_ctrl != j) {
7663 printk(KERN_WARNING "%s: nr_ctrl mismatch: %d %d\n", dev->name, dev->hw_info.nr_ctrl, j);
7664 return -1;
7665 }
7666*/
7667
7668/*
7669 init_state = ssd_reg_read(dev->ctrlp + SSD_FLASH_INFO_REG0);
7670 for (j=1; j<dev->hw_info.nr_ctrl;j++) {
7671 if (init_state != ssd_reg_read(dev->ctrlp + SSD_FLASH_INFO_REG0 + j*8)) {
7672 printk(KERN_WARNING "SSD_FLASH_INFO_REG[%d], not match\n", j);
7673 return -1;
7674 }
7675 }
7676*/
7677
7678/* init_state = ssd_reg_read(dev->ctrlp + SSD_CHIP_INFO_REG0);
7679 for (j=1; j<dev->hw_info.nr_ctrl; j++) {
7680 if (init_state != ssd_reg_read(dev->ctrlp + SSD_CHIP_INFO_REG0 + j*16)) {
7681 printk(KERN_WARNING "SSD_CHIP_INFO_REG Lo [%d], not match\n", j);
7682 return -1;
7683 }
7684 }
7685
7686 init_state = ssd_reg_read(dev->ctrlp + SSD_CHIP_INFO_REG0 + 8);
7687 for (j=1; j<dev->hw_info.nr_ctrl; j++) {
7688 if (init_state != ssd_reg_read(dev->ctrlp + SSD_CHIP_INFO_REG0 + 8 + j*16)) {
7689 printk(KERN_WARNING "SSD_CHIP_INFO_REG Hi [%d], not match\n", j);
7690 return -1;
7691 }
7692 }
7693*/
7694
7695 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) {
7696 max_wait = SSD_INIT_MAX_WAIT_V3_2;
7697 }
7698
7699 reg_base = dev->protocol_info.init_state_reg;
7700 reg_sz = dev->protocol_info.init_state_reg_sz;
7701
7702 init_state = (uint32_t *)kmalloc(reg_sz, GFP_KERNEL);
7703 if (!init_state) {
7704 return -ENOMEM;
7705 }
7706
7707 for (i=0; i<dev->hw_info.nr_ctrl; i++) {
7708check_init:
7709 for (j=0, k=0; j<reg_sz; j+=sizeof(uint32_t), k++) {
7710 init_state[k] = ssd_reg32_read(dev->ctrlp + reg_base + j);
7711 }
7712
7713 if (dev->protocol_info.ver > SSD_PROTOCOL_V3) {
7714 /* just check the last bit, no need to check all channel */
7715 ch_start = dev->hw_info.max_ch - 1;
7716 } else {
7717 ch_start = 0;
7718 }
7719
7720 for (j=0; j<dev->hw_info.nr_chip; j++) {
7721 for (k=ch_start; k<dev->hw_info.max_ch; k++) {
7722 if (test_bit((j*dev->hw_info.max_ch + k), (void *)init_state)) {
7723 continue;
7724 }
7725
7726 init_wait++;
7727 if (init_wait <= max_wait) {
7728 msleep(SSD_INIT_WAIT);
7729 goto check_init;
7730 } else {
7731 if (k < dev->hw_info.nr_ch) {
7732 hio_warn("%s: controller %d chip %d ch %d init failed\n",
7733 dev->name, i, j, k);
7734 } else {
7735 hio_warn("%s: controller %d chip %d init failed\n",
7736 dev->name, i, j);
7737 }
7738
7739 kfree(init_state);
7740 return -1;
7741 }
7742 }
7743 }
7744 reg_base += reg_sz;
7745 }
7746 //printk(KERN_WARNING "%s: init wait %d\n", dev->name, init_wait);
7747
7748 kfree(init_state);
7749 return 0;
7750}
7751
7752static int ssd_check_init_state(struct ssd_device *dev)
7753{
7754 if (mode != SSD_DRV_MODE_STANDARD) {
7755 return 0;
7756 }
7757
7758 return __ssd_check_init_state(dev);
7759}
7760
7761static void ssd_reset_resp_ptr(struct ssd_device *dev);
7762
7763/* reset flash controller etc */
7764static int __ssd_reset(struct ssd_device *dev, int type)
7765{
a9d1e0c7 7766 struct timeval tv;
a6a796ca
HSDT
7767 if (type < SSD_RST_NOINIT || type > SSD_RST_FULL) {
7768 return -EINVAL;
7769 }
7770
7771 mutex_lock(&dev->fw_mutex);
7772
7773 if (type == SSD_RST_NOINIT) { //no init
7774 ssd_reg32_write(dev->ctrlp + SSD_RESET_REG, SSD_RESET_NOINIT);
7775 } else if (type == SSD_RST_NORMAL) { //reset & init
7776 ssd_reg32_write(dev->ctrlp + SSD_RESET_REG, SSD_RESET);
7777 } else { // full reset
7778 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
7779 mutex_unlock(&dev->fw_mutex);
7780 return -EINVAL;
7781 }
7782
7783 ssd_reg32_write(dev->ctrlp + SSD_FULL_RESET_REG, SSD_RESET_FULL);
7784
7785 /* ?? */
7786 ssd_reset_resp_ptr(dev);
7787 }
7788
7789#ifdef SSD_OT_PROTECT
7790 dev->ot_delay = 0;
7791#endif
7792
7793 msleep(1000);
7794
7795 /* xx */
7796 ssd_set_flush_timeout(dev, dev->wmode);
7797
7798 mutex_unlock(&dev->fw_mutex);
7799 ssd_gen_swlog(dev, SSD_LOG_RESET, (uint32_t)type);
a9d1e0c7
KM
7800 do_gettimeofday(&tv);
7801 dev->reset_time = tv.tv_sec;
a6a796ca
HSDT
7802
7803 return __ssd_check_init_state(dev);
7804}
7805
7806static int ssd_save_md(struct ssd_device *dev)
7807{
7808 struct ssd_nand_op_msg *msg;
7809 int ret = 0;
7810
7811 if (unlikely(mode != SSD_DRV_MODE_STANDARD))
7812 return 0;
7813
7814 if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) {
7815 return 0;
7816 }
7817
7818 if (!dev->save_md) {
7819 return 0;
7820 }
7821
7822 msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev);
7823
7824 msg->fun = SSD_FUNC_FLUSH;
7825 msg->flag = 0x2;
7826 msg->ctrl_idx = 0;
7827 msg->chip_no = 0;
7828
7829 ret = ssd_do_request(dev, WRITE, msg, NULL);
7830 ssd_put_dmsg(msg);
7831
7832 return ret;
7833}
7834
7835static int ssd_barrier_save_md(struct ssd_device *dev)
7836{
7837 struct ssd_nand_op_msg *msg;
7838 int ret = 0;
7839
7840 if (unlikely(mode != SSD_DRV_MODE_STANDARD))
7841 return 0;
7842
7843 if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) {
7844 return 0;
7845 }
7846
7847 if (!dev->save_md) {
7848 return 0;
7849 }
7850
7851 msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev);
7852
7853 msg->fun = SSD_FUNC_FLUSH;
7854 msg->flag = 0x2;
7855 msg->ctrl_idx = 0;
7856 msg->chip_no = 0;
7857
7858 ret = ssd_do_barrier_request(dev, WRITE, msg, NULL);
7859 ssd_put_dmsg(msg);
7860
7861 return ret;
7862}
7863
7864static int ssd_flush(struct ssd_device *dev)
7865{
7866 struct ssd_nand_op_msg *msg;
7867 struct ssd_flush_msg *fmsg;
7868 int ret = 0;
7869
7870 if (unlikely(mode != SSD_DRV_MODE_STANDARD))
7871 return 0;
7872
7873 msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev);
7874
7875 if (dev->protocol_info.ver < SSD_PROTOCOL_V3) {
7876 fmsg = (struct ssd_flush_msg *)msg;
7877
7878 fmsg->fun = SSD_FUNC_FLUSH;
7879 fmsg->flag = 0;
7880 fmsg->ctrl_idx = 0;
7881 fmsg->flash = 0;
7882 } else {
7883 msg->fun = SSD_FUNC_FLUSH;
7884 msg->flag = 0;
7885 msg->ctrl_idx = 0;
7886 msg->chip_no = 0;
7887 }
7888
7889 ret = ssd_do_request(dev, WRITE, msg, NULL);
7890 ssd_put_dmsg(msg);
7891
7892 return ret;
7893}
7894
7895static int ssd_barrier_flush(struct ssd_device *dev)
7896{
7897 struct ssd_nand_op_msg *msg;
7898 struct ssd_flush_msg *fmsg;
7899 int ret = 0;
7900
7901 if (unlikely(mode != SSD_DRV_MODE_STANDARD))
7902 return 0;
7903
7904 msg = (struct ssd_nand_op_msg *)ssd_get_dmsg(dev);
7905
7906 if (dev->protocol_info.ver < SSD_PROTOCOL_V3) {
7907 fmsg = (struct ssd_flush_msg *)msg;
7908
7909 fmsg->fun = SSD_FUNC_FLUSH;
7910 fmsg->flag = 0;
7911 fmsg->ctrl_idx = 0;
7912 fmsg->flash = 0;
7913 } else {
7914 msg->fun = SSD_FUNC_FLUSH;
7915 msg->flag = 0;
7916 msg->ctrl_idx = 0;
7917 msg->chip_no = 0;
7918 }
7919
7920 ret = ssd_do_barrier_request(dev, WRITE, msg, NULL);
7921 ssd_put_dmsg(msg);
7922
7923 return ret;
7924}
7925
7926#define SSD_WMODE_BUFFER_TIMEOUT 0x00c82710
7927#define SSD_WMODE_BUFFER_EX_TIMEOUT 0x000500c8
7928#define SSD_WMODE_FUA_TIMEOUT 0x000503E8
7929static void ssd_set_flush_timeout(struct ssd_device *dev, int m)
7930{
7931 uint32_t to;
7932 uint32_t val = 0;
7933
7934 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_1) {
7935 return;
7936 }
7937
7938 switch(m) {
7939 case SSD_WMODE_BUFFER:
7940 to = SSD_WMODE_BUFFER_TIMEOUT;
7941 break;
7942 case SSD_WMODE_BUFFER_EX:
7943 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2_1) {
7944 to = SSD_WMODE_BUFFER_EX_TIMEOUT;
7945 } else {
7946 to = SSD_WMODE_BUFFER_TIMEOUT;
7947 }
7948 break;
7949 case SSD_WMODE_FUA:
7950 to = SSD_WMODE_FUA_TIMEOUT;
7951 break;
7952 default:
7953 return;
7954 }
7955
7956 val = (((uint32_t)((uint32_t)m & 0x3) << 28) | to);
7957
7958 ssd_reg32_write(dev->ctrlp + SSD_FLUSH_TIMEOUT_REG, val);
7959}
7960
7961static int ssd_do_switch_wmode(struct ssd_device *dev, int m)
7962{
7963 int ret = 0;
7964
7965 ret = ssd_barrier_start(dev);
7966 if (ret) {
7967 goto out;
7968 }
7969
7970 ret = ssd_barrier_flush(dev);
7971 if (ret) {
7972 goto out_barrier_end;
7973 }
7974
7975 /* set contoller flush timeout */
7976 ssd_set_flush_timeout(dev, m);
7977
7978 dev->wmode = m;
7979 mb();
7980
7981out_barrier_end:
7982 ssd_barrier_end(dev);
7983out:
7984 return ret;
7985}
7986
7987static int ssd_switch_wmode(struct ssd_device *dev, int m)
7988{
7989 int default_wmode;
7990 int next_wmode;
7991 int ret = 0;
7992
7993 if (!test_bit(SSD_ONLINE, &dev->state)) {
7994 return -ENODEV;
7995 }
7996
7997 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
7998 default_wmode = SSD_WMODE_BUFFER;
7999 } else {
8000 default_wmode = SSD_WMODE_BUFFER_EX;
8001 }
8002
8003 if (SSD_WMODE_AUTO == m) {
8004 /* battery fault ? */
8005 if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) {
8006 next_wmode = SSD_WMODE_FUA;
8007 } else {
8008 next_wmode = default_wmode;
8009 }
8010 } else if (SSD_WMODE_DEFAULT == m) {
8011 next_wmode = default_wmode;
8012 } else {
8013 next_wmode = m;
8014 }
8015
8016 if (next_wmode != dev->wmode) {
8017 hio_warn("%s: switch write mode (%d -> %d)\n", dev->name, dev->wmode, next_wmode);
8018 ret = ssd_do_switch_wmode(dev, next_wmode);
8019 if (ret) {
8020 hio_err("%s: can not switch write mode (%d -> %d)\n", dev->name, dev->wmode, next_wmode);
8021 }
8022 }
8023
8024 return ret;
8025}
8026
8027static int ssd_init_wmode(struct ssd_device *dev)
8028{
8029 int default_wmode;
8030 int ret = 0;
8031
8032 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
8033 default_wmode = SSD_WMODE_BUFFER;
8034 } else {
8035 default_wmode = SSD_WMODE_BUFFER_EX;
8036 }
8037
8038 /* dummy mode */
8039 if (SSD_WMODE_AUTO == dev->user_wmode) {
8040 /* battery fault ? */
8041 if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) {
8042 dev->wmode = SSD_WMODE_FUA;
8043 } else {
8044 dev->wmode = default_wmode;
8045 }
8046 } else if (SSD_WMODE_DEFAULT == dev->user_wmode) {
8047 dev->wmode = default_wmode;
8048 } else {
8049 dev->wmode = dev->user_wmode;
8050 }
8051 ssd_set_flush_timeout(dev, dev->wmode);
8052
8053 return ret;
8054}
8055
8056static int __ssd_set_wmode(struct ssd_device *dev, int m)
8057{
8058 int ret = 0;
8059
8060 /* not support old fw*/
8061 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_1) {
8062 ret = -EOPNOTSUPP;
8063 goto out;
8064 }
8065
8066 if (m < SSD_WMODE_BUFFER || m > SSD_WMODE_DEFAULT) {
8067 ret = -EINVAL;
8068 goto out;
8069 }
8070
8071 ssd_gen_swlog(dev, SSD_LOG_SET_WMODE, m);
8072
8073 dev->user_wmode = m;
8074
8075 ret = ssd_switch_wmode(dev, dev->user_wmode);
8076 if (ret) {
8077 goto out;
8078 }
8079
8080out:
8081 return ret;
8082}
8083
8084int ssd_set_wmode(struct block_device *bdev, int m)
8085{
8086 struct ssd_device *dev;
8087
8088 if (!bdev || !(bdev->bd_disk)) {
8089 return -EINVAL;
8090 }
8091
8092 dev = bdev->bd_disk->private_data;
8093
8094 return __ssd_set_wmode(dev, m);
8095}
8096
8097static int ssd_do_reset(struct ssd_device *dev)
8098{
8099 int ret = 0;
8100
8101 if (test_and_set_bit(SSD_RESETING, &dev->state)) {
8102 return 0;
8103 }
8104
8105 ssd_stop_workq(dev);
8106
8107 ret = ssd_barrier_start(dev);
8108 if (ret) {
8109 goto out;
8110 }
8111
8112 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
8113 /* old reset */
8114 ret = __ssd_reset(dev, SSD_RST_NORMAL);
8115 } else {
8116 /* full reset */
8117 //ret = __ssd_reset(dev, SSD_RST_FULL);
8118 ret = __ssd_reset(dev, SSD_RST_NORMAL);
8119 }
8120 if (ret) {
8121 goto out_barrier_end;
8122 }
8123
8124out_barrier_end:
8125 ssd_barrier_end(dev);
8126out:
8127 ssd_start_workq(dev);
8128 test_and_clear_bit(SSD_RESETING, &dev->state);
8129 return ret;
8130}
8131
8132static int ssd_full_reset(struct ssd_device *dev)
8133{
8134 int ret = 0;
8135
8136 if (test_and_set_bit(SSD_RESETING, &dev->state)) {
8137 return 0;
8138 }
8139
8140 ssd_stop_workq(dev);
8141
8142 ret = ssd_barrier_start(dev);
8143 if (ret) {
8144 goto out;
8145 }
8146
8147 ret = ssd_barrier_flush(dev);
8148 if (ret) {
8149 goto out_barrier_end;
8150 }
8151
8152 ret = ssd_barrier_save_md(dev);
8153 if (ret) {
8154 goto out_barrier_end;
8155 }
8156
8157 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
8158 /* old reset */
8159 ret = __ssd_reset(dev, SSD_RST_NORMAL);
8160 } else {
8161 /* full reset */
8162 //ret = __ssd_reset(dev, SSD_RST_FULL);
8163 ret = __ssd_reset(dev, SSD_RST_NORMAL);
8164 }
8165 if (ret) {
8166 goto out_barrier_end;
8167 }
8168
8169out_barrier_end:
8170 ssd_barrier_end(dev);
8171out:
8172 ssd_start_workq(dev);
8173 test_and_clear_bit(SSD_RESETING, &dev->state);
8174 return ret;
8175}
8176
8177int ssd_reset(struct block_device *bdev)
8178{
8179 struct ssd_device *dev;
8180
8181 if (!bdev || !(bdev->bd_disk)) {
8182 return -EINVAL;
8183 }
8184
8185 dev = bdev->bd_disk->private_data;
8186
8187 return ssd_full_reset(dev);
8188}
8189
8190#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20))
8191static int ssd_issue_flush_fn(struct request_queue *q, struct gendisk *disk,
8192 sector_t *error_sector)
8193{
8194 struct ssd_device *dev = q->queuedata;
8195
8196 return ssd_flush(dev);
8197}
8198#endif
8199
8200void ssd_submit_pbio(struct request_queue *q, struct bio *bio)
8201{
8202 struct ssd_device *dev = q->queuedata;
8203#ifdef SSD_QUEUE_PBIO
8204 int ret = -EBUSY;
8205#endif
8206
8207 if (!test_bit(SSD_ONLINE, &dev->state)) {
a9d1e0c7 8208 ssd_bio_endio(bio, -ENODEV);
a6a796ca
HSDT
8209 goto out;
8210 }
8211
8212#ifdef SSD_DEBUG_ERR
8213 if (atomic_read(&dev->tocnt)) {
8214 hio_warn("%s: IO rejected because of IO timeout!\n", dev->name);
a9d1e0c7 8215 ssd_bio_endio(bio, -EIO);
a6a796ca
HSDT
8216 goto out;
8217 }
8218#endif
8219
8220#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32))
8221 if (unlikely(bio_barrier(bio))) {
a9d1e0c7 8222 ssd_bio_endio(bio, -EOPNOTSUPP);
a6a796ca
HSDT
8223 goto out;
8224 }
8225#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
8226 if (unlikely(bio_rw_flagged(bio, BIO_RW_BARRIER))) {
a9d1e0c7 8227 ssd_bio_endio(bio, -EOPNOTSUPP);
a6a796ca
HSDT
8228 goto out;
8229 }
8230#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37))
8231 if (unlikely(bio->bi_rw & REQ_HARDBARRIER)) {
a9d1e0c7 8232 ssd_bio_endio(bio, -EOPNOTSUPP);
a6a796ca
HSDT
8233 goto out;
8234 }
8235#else
8236 //xx
a9d1e0c7
KM
8237 if (unlikely(ssd_bio_has_fua(bio))) {
8238 ssd_bio_endio(bio, -EOPNOTSUPP);
a6a796ca
HSDT
8239 goto out;
8240 }
8241#endif
8242
8243 if (unlikely(dev->readonly && bio_data_dir(bio) == WRITE)) {
a9d1e0c7 8244 ssd_bio_endio(bio, -EROFS);
a6a796ca
HSDT
8245 goto out;
8246 }
8247
8248#ifdef SSD_QUEUE_PBIO
8249 if (0 == atomic_read(&dev->in_sendq)) {
8250 ret = __ssd_submit_pbio(dev, bio, 0);
8251 }
8252
8253 if (ret) {
8254 (void)test_and_set_bit(BIO_SSD_PBIO, &bio->bi_flags);
8255 ssd_queue_bio(dev, bio);
8256 }
8257#else
8258 __ssd_submit_pbio(dev, bio, 1);
8259#endif
8260
8261out:
8262 return;
8263}
8264
363ace19
KM
8265#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
8266static blk_qc_t ssd_make_request(struct request_queue *q, struct bio *bio)
8267#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))
a6a796ca 8268static void ssd_make_request(struct request_queue *q, struct bio *bio)
363ace19
KM
8269#else
8270static int ssd_make_request(struct request_queue *q, struct bio *bio)
a6a796ca
HSDT
8271#endif
8272{
8273 struct ssd_device *dev = q->queuedata;
8274 int ret = -EBUSY;
8275
8276 if (!test_bit(SSD_ONLINE, &dev->state)) {
a9d1e0c7 8277 ssd_bio_endio(bio, -ENODEV);
a6a796ca
HSDT
8278 goto out;
8279 }
8280
a9d1e0c7
KM
8281#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,3,0))
8282 blk_queue_split(q, &bio, q->bio_split);
8283#endif
8284
a6a796ca
HSDT
8285#ifdef SSD_DEBUG_ERR
8286 if (atomic_read(&dev->tocnt)) {
8287 hio_warn("%s: IO rejected because of IO timeout!\n", dev->name);
a9d1e0c7 8288 ssd_bio_endio(bio, -EIO);
a6a796ca
HSDT
8289 goto out;
8290 }
8291#endif
8292
8293#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32))
8294 if (unlikely(bio_barrier(bio))) {
a9d1e0c7 8295 ssd_bio_endio(bio, -EOPNOTSUPP);
a6a796ca
HSDT
8296 goto out;
8297 }
8298#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36))
8299 if (unlikely(bio_rw_flagged(bio, BIO_RW_BARRIER))) {
a9d1e0c7 8300 ssd_bio_endio(bio, -EOPNOTSUPP);
a6a796ca
HSDT
8301 goto out;
8302 }
8303#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,37))
8304 if (unlikely(bio->bi_rw & REQ_HARDBARRIER)) {
a9d1e0c7 8305 ssd_bio_endio(bio, -EOPNOTSUPP);
a6a796ca
HSDT
8306 goto out;
8307 }
8308#else
8309 //xx
a9d1e0c7
KM
8310 if (unlikely(ssd_bio_has_fua(bio))) {
8311 ssd_bio_endio(bio, -EOPNOTSUPP);
a6a796ca
HSDT
8312 goto out;
8313 }
8314
8315 /* writeback_cache_control.txt: REQ_FLUSH requests without data can be completed successfully without doing any work */
a9d1e0c7
KM
8316 if (unlikely(ssd_bio_has_flush(bio) && !bio_sectors(bio))) {
8317 ssd_bio_endio(bio, 0);
a6a796ca
HSDT
8318 goto out;
8319 }
8320
8321#endif
8322
8323 if (0 == atomic_read(&dev->in_sendq)) {
8324 ret = ssd_submit_bio(dev, bio, 0);
8325 }
8326
8327 if (ret) {
8328 ssd_queue_bio(dev, bio);
8329 }
8330
8331out:
363ace19
KM
8332#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,4,0))
8333 return BLK_QC_T_NONE;
8334#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0))
a6a796ca 8335 return;
363ace19
KM
8336#else
8337 return 0;
a6a796ca
HSDT
8338#endif
8339}
8340
8341#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,16))
8342static int ssd_block_getgeo(struct block_device *bdev, struct hd_geometry *geo)
8343{
8344 struct ssd_device *dev;
8345
8346 if (!bdev) {
8347 return -EINVAL;
8348 }
8349
8350 dev = bdev->bd_disk->private_data;
8351 if (!dev) {
8352 return -EINVAL;
8353 }
8354
8355 geo->heads = 4;
8356 geo->sectors = 16;
8357 geo->cylinders = (dev->hw_info.size & ~0x3f) >> 6;
8358 return 0;
8359}
8360#endif
8361
a9d1e0c7
KM
8362static int ssd_init_queue(struct ssd_device *dev);
8363static void ssd_cleanup_queue(struct ssd_device *dev);
a6a796ca
HSDT
8364static void ssd_cleanup_blkdev(struct ssd_device *dev);
8365static int ssd_init_blkdev(struct ssd_device *dev);
8366static int ssd_ioctl_common(struct ssd_device *dev, unsigned int cmd, unsigned long arg)
8367{
8368 void __user *argp = (void __user *)arg;
8369 void __user *buf = NULL;
8370 void *kbuf = NULL;
8371 int ret = 0;
8372
8373 switch (cmd) {
8374 case SSD_CMD_GET_PROTOCOL_INFO:
8375 if (copy_to_user(argp, &dev->protocol_info, sizeof(struct ssd_protocol_info))) {
8376 hio_warn("%s: copy_to_user: failed\n", dev->name);
8377 ret = -EFAULT;
8378 break;
8379 }
8380 break;
8381
8382 case SSD_CMD_GET_HW_INFO:
8383 if (copy_to_user(argp, &dev->hw_info, sizeof(struct ssd_hw_info))) {
8384 hio_warn("%s: copy_to_user: failed\n", dev->name);
8385 ret = -EFAULT;
8386 break;
8387 }
8388 break;
8389
8390 case SSD_CMD_GET_ROM_INFO:
8391 if (copy_to_user(argp, &dev->rom_info, sizeof(struct ssd_rom_info))) {
8392 hio_warn("%s: copy_to_user: failed\n", dev->name);
8393 ret = -EFAULT;
8394 break;
8395 }
8396 break;
8397
8398 case SSD_CMD_GET_SMART: {
8399 struct ssd_smart smart;
8400 int i;
8401
8402 memcpy(&smart, &dev->smart, sizeof(struct ssd_smart));
8403
8404 mutex_lock(&dev->gd_mutex);
8405 ssd_update_smart(dev, &smart);
8406 mutex_unlock(&dev->gd_mutex);
8407
8408 /* combine the volatile log info */
8409 if (dev->log_info.nr_log) {
8410 for (i=0; i<SSD_LOG_NR_LEVEL; i++) {
8411 smart.log_info.stat[i] += dev->log_info.stat[i];
8412 }
8413 }
8414
8415 if (copy_to_user(argp, &smart, sizeof(struct ssd_smart))) {
8416 hio_warn("%s: copy_to_user: failed\n", dev->name);
8417 ret = -EFAULT;
8418 break;
8419 }
8420
8421 break;
8422 }
8423
8424 case SSD_CMD_GET_IDX:
8425 if (copy_to_user(argp, &dev->idx, sizeof(int))) {
8426 hio_warn("%s: copy_to_user: failed\n", dev->name);
8427 ret = -EFAULT;
8428 break;
8429 }
8430 break;
8431
8432 case SSD_CMD_GET_AMOUNT: {
8433 int nr_ssd = atomic_read(&ssd_nr);
8434 if (copy_to_user(argp, &nr_ssd, sizeof(int))) {
8435 hio_warn("%s: copy_to_user: failed\n", dev->name);
8436 ret = -EFAULT;
8437 break;
8438 }
8439 break;
8440 }
8441
8442 case SSD_CMD_GET_TO_INFO: {
8443 int tocnt = atomic_read(&dev->tocnt);
8444
8445 if (copy_to_user(argp, &tocnt, sizeof(int))) {
8446 hio_warn("%s: copy_to_user: failed\n", dev->name);
8447 ret = -EFAULT;
8448 break;
8449 }
8450 break;
8451 }
8452
8453 case SSD_CMD_GET_DRV_VER: {
8454 char ver[] = DRIVER_VERSION;
8455 int len = sizeof(ver);
8456
8457 if (len > (DRIVER_VERSION_LEN - 1)) {
8458 len = (DRIVER_VERSION_LEN - 1);
8459 }
8460 if (copy_to_user(argp, ver, len)) {
8461 hio_warn("%s: copy_to_user: failed\n", dev->name);
8462 ret = -EFAULT;
8463 break;
8464 }
8465 break;
8466 }
8467
8468 case SSD_CMD_GET_BBACC_INFO: {
8469 struct ssd_acc_info acc;
8470
8471 mutex_lock(&dev->fw_mutex);
8472 ret = ssd_bb_acc(dev, &acc);
8473 mutex_unlock(&dev->fw_mutex);
8474 if (ret) {
8475 break;
8476 }
8477
8478 if (copy_to_user(argp, &acc, sizeof(struct ssd_acc_info))) {
8479 hio_warn("%s: copy_to_user: failed\n", dev->name);
8480 ret = -EFAULT;
8481 break;
8482 }
8483 break;
8484 }
8485
8486 case SSD_CMD_GET_ECACC_INFO: {
8487 struct ssd_acc_info acc;
8488
8489 mutex_lock(&dev->fw_mutex);
8490 ret = ssd_ec_acc(dev, &acc);
8491 mutex_unlock(&dev->fw_mutex);
8492 if (ret) {
8493 break;
8494 }
8495
8496 if (copy_to_user(argp, &acc, sizeof(struct ssd_acc_info))) {
8497 hio_warn("%s: copy_to_user: failed\n", dev->name);
8498 ret = -EFAULT;
8499 break;
8500 }
8501 break;
8502 }
8503
8504 case SSD_CMD_GET_HW_INFO_EXT:
8505 if (copy_to_user(argp, &dev->hw_info_ext, sizeof(struct ssd_hw_info_extend))) {
8506 hio_warn("%s: copy_to_user: failed\n", dev->name);
8507 ret = -EFAULT;
8508 break;
8509 }
8510 break;
8511
8512 case SSD_CMD_REG_READ: {
8513 struct ssd_reg_op_info reg_info;
8514
8515 if (copy_from_user(&reg_info, argp, sizeof(struct ssd_reg_op_info))) {
8516 hio_warn("%s: copy_from_user: failed\n", dev->name);
8517 ret = -EFAULT;
8518 break;
8519 }
8520
8521 if (reg_info.offset > dev->mmio_len-sizeof(uint32_t)) {
8522 ret = -EINVAL;
8523 break;
8524 }
8525
8526 reg_info.value = ssd_reg32_read(dev->ctrlp + reg_info.offset);
8527 if (copy_to_user(argp, &reg_info, sizeof(struct ssd_reg_op_info))) {
8528 hio_warn("%s: copy_to_user: failed\n", dev->name);
8529 ret = -EFAULT;
8530 break;
8531 }
8532
8533 break;
8534 }
8535
8536 case SSD_CMD_REG_WRITE: {
8537 struct ssd_reg_op_info reg_info;
8538
8539 if (copy_from_user(&reg_info, argp, sizeof(struct ssd_reg_op_info))) {
8540 hio_warn("%s: copy_from_user: failed\n", dev->name);
8541 ret = -EFAULT;
8542 break;
8543 }
8544
8545 if (reg_info.offset > dev->mmio_len-sizeof(uint32_t)) {
8546 ret = -EINVAL;
8547 break;
8548 }
8549
8550 ssd_reg32_write(dev->ctrlp + reg_info.offset, reg_info.value);
8551
8552 break;
8553 }
8554
8555 case SSD_CMD_SPI_READ: {
8556 struct ssd_spi_op_info spi_info;
8557 uint32_t off, size;
8558
8559 if (copy_from_user(&spi_info, argp, sizeof(struct ssd_spi_op_info))) {
8560 hio_warn("%s: copy_from_user: failed\n", dev->name);
8561 ret = -EFAULT;
8562 break;
8563 }
8564
8565 off = spi_info.off;
8566 size = spi_info.len;
8567 buf = spi_info.buf;
8568
8569 if (size > dev->rom_info.size || 0 == size || (off + size) > dev->rom_info.size) {
8570 ret = -EINVAL;
8571 break;
8572 }
8573
8574 kbuf = kmalloc(size, GFP_KERNEL);
8575 if (!kbuf) {
8576 ret = -ENOMEM;
8577 break;
8578 }
8579
8580 ret = ssd_spi_page_read(dev, kbuf, off, size);
8581 if (ret) {
8582 kfree(kbuf);
8583 break;
8584 }
8585
8586 if (copy_to_user(buf, kbuf, size)) {
8587 hio_warn("%s: copy_to_user: failed\n", dev->name);
8588 kfree(kbuf);
8589 ret = -EFAULT;
8590 break;
8591 }
8592
8593 kfree(kbuf);
8594
8595 break;
8596 }
8597
8598 case SSD_CMD_SPI_WRITE: {
8599 struct ssd_spi_op_info spi_info;
8600 uint32_t off, size;
8601
8602 if (copy_from_user(&spi_info, argp, sizeof(struct ssd_spi_op_info))) {
8603 hio_warn("%s: copy_from_user: failed\n", dev->name);
8604 ret = -EFAULT;
8605 break;
8606 }
8607
8608 off = spi_info.off;
8609 size = spi_info.len;
8610 buf = spi_info.buf;
8611
8612 if (size > dev->rom_info.size || 0 == size || (off + size) > dev->rom_info.size) {
8613 ret = -EINVAL;
8614 break;
8615 }
8616
8617 kbuf = kmalloc(size, GFP_KERNEL);
8618 if (!kbuf) {
8619 ret = -ENOMEM;
8620 break;
8621 }
8622
8623 if (copy_from_user(kbuf, buf, size)) {
8624 hio_warn("%s: copy_from_user: failed\n", dev->name);
8625 kfree(kbuf);
8626 ret = -EFAULT;
8627 break;
8628 }
8629
8630 ret = ssd_spi_page_write(dev, kbuf, off, size);
8631 if (ret) {
8632 kfree(kbuf);
8633 break;
8634 }
8635
8636 kfree(kbuf);
8637
8638 break;
8639 }
8640
8641 case SSD_CMD_SPI_ERASE: {
8642 struct ssd_spi_op_info spi_info;
8643 uint32_t off;
8644
8645 if (copy_from_user(&spi_info, argp, sizeof(struct ssd_spi_op_info))) {
8646 hio_warn("%s: copy_from_user: failed\n", dev->name);
8647 ret = -EFAULT;
8648 break;
8649 }
8650
8651 off = spi_info.off;
8652
8653 if ((off + dev->rom_info.block_size) > dev->rom_info.size) {
8654 ret = -EINVAL;
8655 break;
8656 }
8657
8658 ret = ssd_spi_block_erase(dev, off);
8659 if (ret) {
8660 break;
8661 }
8662
8663 break;
8664 }
8665
8666 case SSD_CMD_I2C_READ: {
8667 struct ssd_i2c_op_info i2c_info;
8668 uint8_t saddr;
8669 uint8_t rsize;
8670
8671 if (copy_from_user(&i2c_info, argp, sizeof(struct ssd_i2c_op_info))) {
8672 hio_warn("%s: copy_from_user: failed\n", dev->name);
8673 ret = -EFAULT;
8674 break;
8675 }
8676
8677 saddr = i2c_info.saddr;
8678 rsize = i2c_info.rsize;
8679 buf = i2c_info.rbuf;
8680
8681 if (rsize <= 0 || rsize > SSD_I2C_MAX_DATA) {
8682 ret = -EINVAL;
8683 break;
8684 }
8685
8686 kbuf = kmalloc(rsize, GFP_KERNEL);
8687 if (!kbuf) {
8688 ret = -ENOMEM;
8689 break;
8690 }
8691
8692 ret = ssd_i2c_read(dev, saddr, rsize, kbuf);
8693 if (ret) {
8694 kfree(kbuf);
8695 break;
8696 }
8697
8698 if (copy_to_user(buf, kbuf, rsize)) {
8699 hio_warn("%s: copy_to_user: failed\n", dev->name);
8700 kfree(kbuf);
8701 ret = -EFAULT;
8702 break;
8703 }
8704
8705 kfree(kbuf);
8706
8707 break;
8708 }
8709
8710 case SSD_CMD_I2C_WRITE: {
8711 struct ssd_i2c_op_info i2c_info;
8712 uint8_t saddr;
8713 uint8_t wsize;
8714
8715 if (copy_from_user(&i2c_info, argp, sizeof(struct ssd_i2c_op_info))) {
8716 hio_warn("%s: copy_from_user: failed\n", dev->name);
8717 ret = -EFAULT;
8718 break;
8719 }
8720
8721 saddr = i2c_info.saddr;
8722 wsize = i2c_info.wsize;
8723 buf = i2c_info.wbuf;
8724
8725 if (wsize <= 0 || wsize > SSD_I2C_MAX_DATA) {
8726 ret = -EINVAL;
8727 break;
8728 }
8729
8730 kbuf = kmalloc(wsize, GFP_KERNEL);
8731 if (!kbuf) {
8732 ret = -ENOMEM;
8733 break;
8734 }
8735
8736 if (copy_from_user(kbuf, buf, wsize)) {
8737 hio_warn("%s: copy_from_user: failed\n", dev->name);
8738 kfree(kbuf);
8739 ret = -EFAULT;
8740 break;
8741 }
8742
8743 ret = ssd_i2c_write(dev, saddr, wsize, kbuf);
8744 if (ret) {
8745 kfree(kbuf);
8746 break;
8747 }
8748
8749 kfree(kbuf);
8750
8751 break;
8752 }
8753
8754 case SSD_CMD_I2C_WRITE_READ: {
8755 struct ssd_i2c_op_info i2c_info;
8756 uint8_t saddr;
8757 uint8_t wsize;
8758 uint8_t rsize;
8759 uint8_t size;
8760
8761 if (copy_from_user(&i2c_info, argp, sizeof(struct ssd_i2c_op_info))) {
8762 hio_warn("%s: copy_from_user: failed\n", dev->name);
8763 ret = -EFAULT;
8764 break;
8765 }
8766
8767 saddr = i2c_info.saddr;
8768 wsize = i2c_info.wsize;
8769 rsize = i2c_info.rsize;
8770 buf = i2c_info.wbuf;
8771
8772 if (wsize <= 0 || wsize > SSD_I2C_MAX_DATA) {
8773 ret = -EINVAL;
8774 break;
8775 }
8776
8777 if (rsize <= 0 || rsize > SSD_I2C_MAX_DATA) {
8778 ret = -EINVAL;
8779 break;
8780 }
8781
8782 size = wsize + rsize;
8783
8784 kbuf = kmalloc(size, GFP_KERNEL);
8785 if (!kbuf) {
8786 ret = -ENOMEM;
8787 break;
8788 }
8789
8790 if (copy_from_user((kbuf + rsize), buf, wsize)) {
8791 hio_warn("%s: copy_from_user: failed\n", dev->name);
8792 kfree(kbuf);
8793 ret = -EFAULT;
8794 break;
8795 }
8796
8797 buf = i2c_info.rbuf;
8798
8799 ret = ssd_i2c_write_read(dev, saddr, wsize, (kbuf + rsize), rsize, kbuf);
8800 if (ret) {
8801 kfree(kbuf);
8802 break;
8803 }
8804
8805 if (copy_to_user(buf, kbuf, rsize)) {
8806 hio_warn("%s: copy_to_user: failed\n", dev->name);
8807 kfree(kbuf);
8808 ret = -EFAULT;
8809 break;
8810 }
8811
8812 kfree(kbuf);
8813
8814 break;
8815 }
8816
8817 case SSD_CMD_SMBUS_SEND_BYTE: {
8818 struct ssd_smbus_op_info smbus_info;
8819 uint8_t smb_data[SSD_SMBUS_BLOCK_MAX];
8820 uint8_t saddr;
8821 uint8_t size;
8822
8823 if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) {
8824 hio_warn("%s: copy_from_user: failed\n", dev->name);
8825 ret = -EFAULT;
8826 break;
8827 }
8828
8829 saddr = smbus_info.saddr;
8830 buf = smbus_info.buf;
8831 size = 1;
8832
8833 if (copy_from_user(smb_data, buf, size)) {
8834 hio_warn("%s: copy_from_user: failed\n", dev->name);
8835 ret = -EFAULT;
8836 break;
8837 }
8838
8839 ret = ssd_smbus_send_byte(dev, saddr, smb_data);
8840 if (ret) {
8841 break;
8842 }
8843
8844 break;
8845 }
8846
8847 case SSD_CMD_SMBUS_RECEIVE_BYTE: {
8848 struct ssd_smbus_op_info smbus_info;
8849 uint8_t smb_data[SSD_SMBUS_BLOCK_MAX];
8850 uint8_t saddr;
8851 uint8_t size;
8852
8853 if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) {
8854 hio_warn("%s: copy_from_user: failed\n", dev->name);
8855 ret = -EFAULT;
8856 break;
8857 }
8858
8859 saddr = smbus_info.saddr;
8860 buf = smbus_info.buf;
8861 size = 1;
8862
8863 ret = ssd_smbus_receive_byte(dev, saddr, smb_data);
8864 if (ret) {
8865 break;
8866 }
8867
8868 if (copy_to_user(buf, smb_data, size)) {
8869 hio_warn("%s: copy_to_user: failed\n", dev->name);
8870 ret = -EFAULT;
8871 break;
8872 }
8873
8874 break;
8875 }
8876
8877 case SSD_CMD_SMBUS_WRITE_BYTE: {
8878 struct ssd_smbus_op_info smbus_info;
8879 uint8_t smb_data[SSD_SMBUS_BLOCK_MAX];
8880 uint8_t saddr;
8881 uint8_t command;
8882 uint8_t size;
8883
8884 if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) {
8885 hio_warn("%s: copy_from_user: failed\n", dev->name);
8886 ret = -EFAULT;
8887 break;
8888 }
8889
8890 saddr = smbus_info.saddr;
8891 command = smbus_info.cmd;
8892 buf = smbus_info.buf;
8893 size = 1;
8894
8895 if (copy_from_user(smb_data, buf, size)) {
8896 hio_warn("%s: copy_from_user: failed\n", dev->name);
8897 ret = -EFAULT;
8898 break;
8899 }
8900
8901 ret = ssd_smbus_write_byte(dev, saddr, command, smb_data);
8902 if (ret) {
8903 break;
8904 }
8905
8906 break;
8907 }
8908
8909 case SSD_CMD_SMBUS_READ_BYTE: {
8910 struct ssd_smbus_op_info smbus_info;
8911 uint8_t smb_data[SSD_SMBUS_BLOCK_MAX];
8912 uint8_t saddr;
8913 uint8_t command;
8914 uint8_t size;
8915
8916 if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) {
8917 hio_warn("%s: copy_from_user: failed\n", dev->name);
8918 ret = -EFAULT;
8919 break;
8920 }
8921
8922 saddr = smbus_info.saddr;
8923 command = smbus_info.cmd;
8924 buf = smbus_info.buf;
8925 size = 1;
8926
8927 ret = ssd_smbus_read_byte(dev, saddr, command, smb_data);
8928 if (ret) {
8929 break;
8930 }
8931
8932 if (copy_to_user(buf, smb_data, size)) {
8933 hio_warn("%s: copy_to_user: failed\n", dev->name);
8934 ret = -EFAULT;
8935 break;
8936 }
8937
8938 break;
8939 }
8940
8941 case SSD_CMD_SMBUS_WRITE_WORD: {
8942 struct ssd_smbus_op_info smbus_info;
8943 uint8_t smb_data[SSD_SMBUS_BLOCK_MAX];
8944 uint8_t saddr;
8945 uint8_t command;
8946 uint8_t size;
8947
8948 if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) {
8949 hio_warn("%s: copy_from_user: failed\n", dev->name);
8950 ret = -EFAULT;
8951 break;
8952 }
8953
8954 saddr = smbus_info.saddr;
8955 command = smbus_info.cmd;
8956 buf = smbus_info.buf;
8957 size = 2;
8958
8959 if (copy_from_user(smb_data, buf, size)) {
8960 hio_warn("%s: copy_from_user: failed\n", dev->name);
8961 ret = -EFAULT;
8962 break;
8963 }
8964
8965 ret = ssd_smbus_write_word(dev, saddr, command, smb_data);
8966 if (ret) {
8967 break;
8968 }
8969
8970 break;
8971 }
8972
8973 case SSD_CMD_SMBUS_READ_WORD: {
8974 struct ssd_smbus_op_info smbus_info;
8975 uint8_t smb_data[SSD_SMBUS_BLOCK_MAX];
8976 uint8_t saddr;
8977 uint8_t command;
8978 uint8_t size;
8979
8980 if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) {
8981 hio_warn("%s: copy_from_user: failed\n", dev->name);
8982 ret = -EFAULT;
8983 break;
8984 }
8985
8986 saddr = smbus_info.saddr;
8987 command = smbus_info.cmd;
8988 buf = smbus_info.buf;
8989 size = 2;
8990
8991 ret = ssd_smbus_read_word(dev, saddr, command, smb_data);
8992 if (ret) {
8993 break;
8994 }
8995
8996 if (copy_to_user(buf, smb_data, size)) {
8997 hio_warn("%s: copy_to_user: failed\n", dev->name);
8998 ret = -EFAULT;
8999 break;
9000 }
9001
9002 break;
9003 }
9004
9005 case SSD_CMD_SMBUS_WRITE_BLOCK: {
9006 struct ssd_smbus_op_info smbus_info;
9007 uint8_t smb_data[SSD_SMBUS_BLOCK_MAX];
9008 uint8_t saddr;
9009 uint8_t command;
9010 uint8_t size;
9011
9012 if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) {
9013 hio_warn("%s: copy_from_user: failed\n", dev->name);
9014 ret = -EFAULT;
9015 break;
9016 }
9017
9018 saddr = smbus_info.saddr;
9019 command = smbus_info.cmd;
9020 buf = smbus_info.buf;
9021 size = smbus_info.size;
9022
9023 if (size > SSD_SMBUS_BLOCK_MAX) {
9024 ret = -EINVAL;
9025 break;
9026 }
9027
9028 if (copy_from_user(smb_data, buf, size)) {
9029 hio_warn("%s: copy_from_user: failed\n", dev->name);
9030 ret = -EFAULT;
9031 break;
9032 }
9033
9034 ret = ssd_smbus_write_block(dev, saddr, command, size, smb_data);
9035 if (ret) {
9036 break;
9037 }
9038
9039 break;
9040 }
9041
9042 case SSD_CMD_SMBUS_READ_BLOCK: {
9043 struct ssd_smbus_op_info smbus_info;
9044 uint8_t smb_data[SSD_SMBUS_BLOCK_MAX];
9045 uint8_t saddr;
9046 uint8_t command;
9047 uint8_t size;
9048
9049 if (copy_from_user(&smbus_info, argp, sizeof(struct ssd_smbus_op_info))) {
9050 hio_warn("%s: copy_from_user: failed\n", dev->name);
9051 ret = -EFAULT;
9052 break;
9053 }
9054
9055 saddr = smbus_info.saddr;
9056 command = smbus_info.cmd;
9057 buf = smbus_info.buf;
9058 size = smbus_info.size;
9059
9060 if (size > SSD_SMBUS_BLOCK_MAX) {
9061 ret = -EINVAL;
9062 break;
9063 }
9064
9065 ret = ssd_smbus_read_block(dev, saddr, command, size, smb_data);
9066 if (ret) {
9067 break;
9068 }
9069
9070 if (copy_to_user(buf, smb_data, size)) {
9071 hio_warn("%s: copy_to_user: failed\n", dev->name);
9072 ret = -EFAULT;
9073 break;
9074 }
9075
9076 break;
9077 }
9078
9079 case SSD_CMD_BM_GET_VER: {
9080 uint16_t ver;
9081
9082 ret = ssd_bm_get_version(dev, &ver);
9083 if (ret) {
9084 break;
9085 }
9086
9087 if (copy_to_user(argp, &ver, sizeof(uint16_t))) {
9088 hio_warn("%s: copy_to_user: failed\n", dev->name);
9089 ret = -EFAULT;
9090 break;
9091 }
9092
9093 break;
9094 }
9095
9096 case SSD_CMD_BM_GET_NR_CAP: {
9097 int nr_cap;
9098
9099 ret = ssd_bm_nr_cap(dev, &nr_cap);
9100 if (ret) {
9101 break;
9102 }
9103
9104 if (copy_to_user(argp, &nr_cap, sizeof(int))) {
9105 hio_warn("%s: copy_to_user: failed\n", dev->name);
9106 ret = -EFAULT;
9107 break;
9108 }
9109
9110 break;
9111 }
9112
9113 case SSD_CMD_BM_CAP_LEARNING: {
9114 ret = ssd_bm_enter_cap_learning(dev);
9115
9116 if (ret) {
9117 break;
9118 }
9119
9120 break;
9121 }
9122
9123 case SSD_CMD_CAP_LEARN: {
9124 uint32_t cap = 0;
9125
9126 ret = ssd_cap_learn(dev, &cap);
9127 if (ret) {
9128 break;
9129 }
9130
9131 if (copy_to_user(argp, &cap, sizeof(uint32_t))) {
9132 hio_warn("%s: copy_to_user: failed\n", dev->name);
9133 ret = -EFAULT;
9134 break;
9135 }
9136
9137 break;
9138 }
9139
9140 case SSD_CMD_GET_CAP_STATUS: {
9141 int cap_status = 0;
9142
9143 if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) {
9144 cap_status = 1;
9145 }
9146
9147 if (copy_to_user(argp, &cap_status, sizeof(int))) {
9148 hio_warn("%s: copy_to_user: failed\n", dev->name);
9149 ret = -EFAULT;
9150 break;
9151 }
9152
9153 break;
9154 }
9155
9156 case SSD_CMD_RAM_READ: {
9157 struct ssd_ram_op_info ram_info;
9158 uint64_t ofs;
9159 uint32_t length;
9160 size_t rlen, len = dev->hw_info.ram_max_len;
9161 int ctrl_idx;
9162
9163 if (copy_from_user(&ram_info, argp, sizeof(struct ssd_ram_op_info))) {
9164 hio_warn("%s: copy_from_user: failed\n", dev->name);
9165 ret = -EFAULT;
9166 break;
9167 }
9168
9169 ofs = ram_info.start;
9170 length = ram_info.length;
9171 buf = ram_info.buf;
9172 ctrl_idx = ram_info.ctrl_idx;
9173
9174 if (ofs >= dev->hw_info.ram_size || length > dev->hw_info.ram_size || 0 == length || (ofs + length) > dev->hw_info.ram_size) {
9175 ret = -EINVAL;
9176 break;
9177 }
9178
9179 kbuf = kmalloc(len, GFP_KERNEL);
9180 if (!kbuf) {
9181 ret = -ENOMEM;
9182 break;
9183 }
9184
9185 for (rlen=0; rlen<length; rlen+=len, buf+=len, ofs+=len) {
9186 if ((length - rlen) < len) {
9187 len = length - rlen;
9188 }
9189
9190 ret = ssd_ram_read(dev, kbuf, len, ofs, ctrl_idx);
9191 if (ret) {
9192 break;
9193 }
9194
9195 if (copy_to_user(buf, kbuf, len)) {
9196 ret = -EFAULT;
9197 break;
9198 }
9199 }
9200
9201 kfree(kbuf);
9202
9203 break;
9204 }
9205
9206 case SSD_CMD_RAM_WRITE: {
9207 struct ssd_ram_op_info ram_info;
9208 uint64_t ofs;
9209 uint32_t length;
9210 size_t wlen, len = dev->hw_info.ram_max_len;
9211 int ctrl_idx;
9212
9213 if (copy_from_user(&ram_info, argp, sizeof(struct ssd_ram_op_info))) {
9214 hio_warn("%s: copy_from_user: failed\n", dev->name);
9215 ret = -EFAULT;
9216 break;
9217 }
9218 ofs = ram_info.start;
9219 length = ram_info.length;
9220 buf = ram_info.buf;
9221 ctrl_idx = ram_info.ctrl_idx;
9222
9223 if (ofs >= dev->hw_info.ram_size || length > dev->hw_info.ram_size || 0 == length || (ofs + length) > dev->hw_info.ram_size) {
9224 ret = -EINVAL;
9225 break;
9226 }
9227
9228 kbuf = kmalloc(len, GFP_KERNEL);
9229 if (!kbuf) {
9230 ret = -ENOMEM;
9231 break;
9232 }
9233
9234 for (wlen=0; wlen<length; wlen+=len, buf+=len, ofs+=len) {
9235 if ((length - wlen) < len) {
9236 len = length - wlen;
9237 }
9238
9239 if (copy_from_user(kbuf, buf, len)) {
9240 ret = -EFAULT;
9241 break;
9242 }
9243
9244 ret = ssd_ram_write(dev, kbuf, len, ofs, ctrl_idx);
9245 if (ret) {
9246 break;
9247 }
9248 }
9249
9250 kfree(kbuf);
9251
9252 break;
9253 }
9254
9255 case SSD_CMD_NAND_READ_ID: {
9256 struct ssd_flash_op_info flash_info;
9257 int chip_no, chip_ce, length, ctrl_idx;
9258
9259 if (copy_from_user(&flash_info, argp, sizeof(struct ssd_flash_op_info))) {
9260 hio_warn("%s: copy_from_user: failed\n", dev->name);
9261 ret = -EFAULT;
9262 break;
9263 }
9264
9265 chip_no = flash_info.flash;
9266 chip_ce = flash_info.chip;
9267 ctrl_idx = flash_info.ctrl_idx;
9268 buf = flash_info.buf;
9269 length = dev->hw_info.id_size;
9270
9271 //kbuf = kmalloc(length, GFP_KERNEL);
9272 kbuf = kmalloc(SSD_NAND_ID_BUFF_SZ, GFP_KERNEL); //xx
9273 if (!kbuf) {
9274 ret = -ENOMEM;
9275 break;
9276 }
9277 memset(kbuf, 0, length);
9278
9279 ret = ssd_nand_read_id(dev, kbuf, chip_no, chip_ce, ctrl_idx);
9280 if (ret) {
9281 kfree(kbuf);
9282 break;
9283 }
9284
9285 if (copy_to_user(buf, kbuf, length)) {
9286 kfree(kbuf);
9287 ret = -EFAULT;
9288 break;
9289 }
9290
9291 kfree(kbuf);
9292
9293 break;
9294 }
9295
9296 case SSD_CMD_NAND_READ: { //with oob
9297 struct ssd_flash_op_info flash_info;
9298 uint32_t length;
9299 int flash, chip, page, ctrl_idx;
9300 int err = 0;
9301
9302 if (copy_from_user(&flash_info, argp, sizeof(struct ssd_flash_op_info))) {
9303 hio_warn("%s: copy_from_user: failed\n", dev->name);
9304 ret = -EFAULT;
9305 break;
9306 }
9307
9308 flash = flash_info.flash;
9309 chip = flash_info.chip;
9310 page = flash_info.page;
9311 buf = flash_info.buf;
9312 ctrl_idx = flash_info.ctrl_idx;
9313
9314 length = dev->hw_info.page_size + dev->hw_info.oob_size;
9315
9316 kbuf = kmalloc(length, GFP_KERNEL);
9317 if (!kbuf) {
9318 ret = -ENOMEM;
9319 break;
9320 }
9321
9322 err = ret = ssd_nand_read_w_oob(dev, kbuf, flash, chip, page, 1, ctrl_idx);
9323 if (ret && (-EIO != ret)) {
9324 kfree(kbuf);
9325 break;
9326 }
9327
9328 if (copy_to_user(buf, kbuf, length)) {
9329 kfree(kbuf);
9330 ret = -EFAULT;
9331 break;
9332 }
9333
9334 ret = err;
9335
9336 kfree(kbuf);
9337 break;
9338 }
9339
9340 case SSD_CMD_NAND_WRITE: {
9341 struct ssd_flash_op_info flash_info;
9342 int flash, chip, page, ctrl_idx;
9343 uint32_t length;
9344
9345 if (copy_from_user(&flash_info, argp, sizeof(struct ssd_flash_op_info))) {
9346 hio_warn("%s: copy_from_user: failed\n", dev->name);
9347 ret = -EFAULT;
9348 break;
9349 }
9350
9351 flash = flash_info.flash;
9352 chip = flash_info.chip;
9353 page = flash_info.page;
9354 buf = flash_info.buf;
9355 ctrl_idx = flash_info.ctrl_idx;
9356
9357 length = dev->hw_info.page_size + dev->hw_info.oob_size;
9358
9359 kbuf = kmalloc(length, GFP_KERNEL);
9360 if (!kbuf) {
9361 ret = -ENOMEM;
9362 break;
9363 }
9364
9365 if (copy_from_user(kbuf, buf, length)) {
9366 kfree(kbuf);
9367 ret = -EFAULT;
9368 break;
9369 }
9370
9371 ret = ssd_nand_write(dev, kbuf, flash, chip, page, 1, ctrl_idx);
9372 if (ret) {
9373 kfree(kbuf);
9374 break;
9375 }
9376
9377 kfree(kbuf);
9378 break;
9379 }
9380
9381 case SSD_CMD_NAND_ERASE: {
9382 struct ssd_flash_op_info flash_info;
9383 int flash, chip, page, ctrl_idx;
9384
9385 if (copy_from_user(&flash_info, argp, sizeof(struct ssd_flash_op_info))) {
9386 hio_warn("%s: copy_from_user: failed\n", dev->name);
9387 ret = -EFAULT;
9388 break;
9389 }
9390
9391 flash = flash_info.flash;
9392 chip = flash_info.chip;
9393 page = flash_info.page;
9394 ctrl_idx = flash_info.ctrl_idx;
9395
9396 if ((page % dev->hw_info.page_count) != 0) {
9397 ret = -EINVAL;
9398 break;
9399 }
9400
9401 //hio_warn("erase fs = %llx\n", ofs);
9402 ret = ssd_nand_erase(dev, flash, chip, page, ctrl_idx);
9403 if (ret) {
9404 break;
9405 }
9406
9407 break;
9408 }
9409
9410 case SSD_CMD_NAND_READ_EXT: { //ingore EIO
9411 struct ssd_flash_op_info flash_info;
9412 uint32_t length;
9413 int flash, chip, page, ctrl_idx;
9414
9415 if (copy_from_user(&flash_info, argp, sizeof(struct ssd_flash_op_info))) {
9416 hio_warn("%s: copy_from_user: failed\n", dev->name);
9417 ret = -EFAULT;
9418 break;
9419 }
9420
9421 flash = flash_info.flash;
9422 chip = flash_info.chip;
9423 page = flash_info.page;
9424 buf = flash_info.buf;
9425 ctrl_idx = flash_info.ctrl_idx;
9426
9427 length = dev->hw_info.page_size + dev->hw_info.oob_size;
9428
9429 kbuf = kmalloc(length, GFP_KERNEL);
9430 if (!kbuf) {
9431 ret = -ENOMEM;
9432 break;
9433 }
9434
9435 ret = ssd_nand_read_w_oob(dev, kbuf, flash, chip, page, 1, ctrl_idx);
9436 if (-EIO == ret) { //ingore EIO
9437 ret = 0;
9438 }
9439 if (ret) {
9440 kfree(kbuf);
9441 break;
9442 }
9443
9444 if (copy_to_user(buf, kbuf, length)) {
9445 kfree(kbuf);
9446 ret = -EFAULT;
9447 break;
9448 }
9449
9450 kfree(kbuf);
9451 break;
9452 }
9453
9454 case SSD_CMD_UPDATE_BBT: {
9455 struct ssd_flash_op_info flash_info;
9456 int ctrl_idx, flash;
9457
9458 if (copy_from_user(&flash_info, argp, sizeof(struct ssd_flash_op_info))) {
9459 hio_warn("%s: copy_from_user: failed\n", dev->name);
9460 ret = -EFAULT;
9461 break;
9462 }
9463
9464 ctrl_idx = flash_info.ctrl_idx;
9465 flash = flash_info.flash;
9466 ret = ssd_update_bbt(dev, flash, ctrl_idx);
9467 if (ret) {
9468 break;
9469 }
9470
9471 break;
9472 }
9473
9474 case SSD_CMD_CLEAR_ALARM:
9475 ssd_clear_alarm(dev);
9476 break;
9477
9478 case SSD_CMD_SET_ALARM:
9479 ssd_set_alarm(dev);
9480 break;
9481
9482 case SSD_CMD_RESET:
9483 ret = ssd_do_reset(dev);
9484 break;
9485
9486 case SSD_CMD_RELOAD_FW:
9487 dev->reload_fw = 1;
9488 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) {
9489 ssd_reg32_write(dev->ctrlp + SSD_RELOAD_FW_REG, SSD_RELOAD_FLAG);
9490 } else if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_1_1) {
9491 ssd_reg32_write(dev->ctrlp + SSD_RELOAD_FW_REG, SSD_RELOAD_FW);
9492
9493 }
9494 break;
9495
9496 case SSD_CMD_UNLOAD_DEV: {
9497 if (atomic_read(&dev->refcnt)) {
9498 ret = -EBUSY;
9499 break;
9500 }
9501
9502 /* save smart */
9503 ssd_save_smart(dev);
9504
9505 ret = ssd_flush(dev);
9506 if (ret) {
9507 break;
9508 }
9509
9510 /* cleanup the block device */
9511 if (test_and_clear_bit(SSD_INIT_BD, &dev->state)) {
9512 mutex_lock(&dev->gd_mutex);
9513 ssd_cleanup_blkdev(dev);
a9d1e0c7 9514 ssd_cleanup_queue(dev);
a6a796ca
HSDT
9515 mutex_unlock(&dev->gd_mutex);
9516 }
9517
9518 break;
9519 }
9520
9521 case SSD_CMD_LOAD_DEV: {
9522
9523 if (test_bit(SSD_INIT_BD, &dev->state)) {
9524 ret = -EINVAL;
9525 break;
9526 }
9527
9528 ret = ssd_init_smart(dev);
9529 if (ret) {
9530 hio_warn("%s: init info: failed\n", dev->name);
9531 break;
9532 }
9533
a9d1e0c7
KM
9534 ret = ssd_init_queue(dev);
9535 if (ret) {
9536 hio_warn("%s: init queue failed\n", dev->name);
9537 break;
9538 }
a6a796ca
HSDT
9539 ret = ssd_init_blkdev(dev);
9540 if (ret) {
9541 hio_warn("%s: register block device: failed\n", dev->name);
9542 break;
9543 }
9544 (void)test_and_set_bit(SSD_INIT_BD, &dev->state);
9545
9546 break;
9547 }
9548
9549 case SSD_CMD_UPDATE_VP: {
9550 uint32_t val;
9551 uint32_t new_vp, new_vp1 = 0;
9552
9553 if (test_bit(SSD_INIT_BD, &dev->state)) {
9554 ret = -EINVAL;
9555 break;
9556 }
9557
9558 if (copy_from_user(&new_vp, argp, sizeof(uint32_t))) {
9559 hio_warn("%s: copy_from_user: failed\n", dev->name);
9560 ret = -EFAULT;
9561 break;
9562 }
9563
9564 if (new_vp > dev->hw_info.max_valid_pages || new_vp <= 0) {
9565 ret = -EINVAL;
9566 break;
9567 }
9568
9569 while (new_vp <= dev->hw_info.max_valid_pages) {
9570 ssd_reg32_write(dev->ctrlp + SSD_VALID_PAGES_REG, new_vp);
9571 msleep(10);
9572 val = ssd_reg32_read(dev->ctrlp + SSD_VALID_PAGES_REG);
9573 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
9574 new_vp1 = val & 0x3FF;
9575 } else {
9576 new_vp1 = val & 0x7FFF;
9577 }
9578
9579 if (new_vp1 == new_vp) {
9580 break;
9581 }
9582
9583 new_vp++;
9584 /*if (new_vp == dev->hw_info.valid_pages) {
9585 new_vp++;
9586 }*/
9587 }
9588
9589 if (new_vp1 != new_vp || new_vp > dev->hw_info.max_valid_pages) {
9590 /* restore */
9591 ssd_reg32_write(dev->ctrlp + SSD_VALID_PAGES_REG, dev->hw_info.valid_pages);
9592 ret = -EINVAL;
9593 break;
9594 }
9595
9596 if (copy_to_user(argp, &new_vp, sizeof(uint32_t))) {
9597 hio_warn("%s: copy_to_user: failed\n", dev->name);
9598 ssd_reg32_write(dev->ctrlp + SSD_VALID_PAGES_REG, dev->hw_info.valid_pages);
9599 ret = -EFAULT;
9600 break;
9601 }
9602
9603 /* new */
9604 dev->hw_info.valid_pages = new_vp;
9605 dev->hw_info.size = (uint64_t)dev->hw_info.valid_pages * dev->hw_info.page_size;
9606 dev->hw_info.size *= (dev->hw_info.block_count - dev->hw_info.reserved_blks);
9607 dev->hw_info.size *= ((uint64_t)dev->hw_info.nr_data_ch * (uint64_t)dev->hw_info.nr_chip * (uint64_t)dev->hw_info.nr_ctrl);
9608
9609 break;
9610 }
9611
9612 case SSD_CMD_FULL_RESET: {
9613 ret = ssd_full_reset(dev);
9614 break;
9615 }
9616
9617 case SSD_CMD_GET_NR_LOG: {
9618 if (copy_to_user(argp, &dev->internal_log.nr_log, sizeof(dev->internal_log.nr_log))) {
9619 ret = -EFAULT;
9620 break;
9621 }
9622 break;
9623 }
9624
9625 case SSD_CMD_GET_LOG: {
9626 uint32_t length = dev->rom_info.log_sz;
9627
9628 buf = argp;
9629
9630 if (copy_to_user(buf, dev->internal_log.log, length)) {
9631 ret = -EFAULT;
9632 break;
9633 }
9634
9635 break;
9636 }
9637
9638 case SSD_CMD_LOG_LEVEL: {
9639 int level = 0;
9640 if (copy_from_user(&level, argp, sizeof(int))) {
9641 hio_warn("%s: copy_from_user: failed\n", dev->name);
9642 ret = -EFAULT;
9643 break;
9644 }
9645
9646 if (level >= SSD_LOG_NR_LEVEL || level < SSD_LOG_LEVEL_INFO) {
9647 level = SSD_LOG_LEVEL_ERR;
9648 }
9649
9650 //just for showing log, no need to protect
9651 log_level = level;
9652 break;
9653 }
9654
9655 case SSD_CMD_OT_PROTECT: {
9656 int protect = 0;
9657
9658 if (copy_from_user(&protect, argp, sizeof(int))) {
9659 hio_warn("%s: copy_from_user: failed\n", dev->name);
9660 ret = -EFAULT;
9661 break;
9662 }
9663
9664 ssd_set_ot_protect(dev, !!protect);
9665 break;
9666 }
9667
9668 case SSD_CMD_GET_OT_STATUS: {
9669 int status = ssd_get_ot_status(dev, &status);
9670
9671 if (copy_to_user(argp, &status, sizeof(int))) {
9672 hio_warn("%s: copy_to_user: failed\n", dev->name);
9673 ret = -EFAULT;
9674 break;
9675 }
9676 break;
9677 }
9678
9679 case SSD_CMD_CLEAR_LOG: {
9680 ret = ssd_clear_log(dev);
9681 break;
9682 }
9683
9684 case SSD_CMD_CLEAR_SMART: {
9685 ret = ssd_clear_smart(dev);
9686 break;
9687 }
9688
a9d1e0c7
KM
9689 case SSD_CMD_CLEAR_WARNING: {
9690 ret = ssd_clear_warning(dev);
9691 break;
9692 }
9693
a6a796ca
HSDT
9694 case SSD_CMD_SW_LOG: {
9695 struct ssd_sw_log_info sw_log;
9696
9697 if (copy_from_user(&sw_log, argp, sizeof(struct ssd_sw_log_info))) {
9698 hio_warn("%s: copy_from_user: failed\n", dev->name);
9699 ret = -EFAULT;
9700 break;
9701 }
9702
9703 ret = ssd_gen_swlog(dev, sw_log.event, sw_log.data);
9704 break;
9705 }
9706
9707 case SSD_CMD_GET_LABEL: {
9708
9709 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) {
9710 ret = -EINVAL;
9711 break;
9712 }
9713
9714 if (copy_to_user(argp, &dev->label, sizeof(struct ssd_label))) {
9715 hio_warn("%s: copy_to_user: failed\n", dev->name);
9716 ret = -EFAULT;
9717 break;
9718 }
9719 break;
9720 }
9721
9722 case SSD_CMD_GET_VERSION: {
9723 struct ssd_version_info ver;
9724
9725 mutex_lock(&dev->fw_mutex);
9726 ret = __ssd_get_version(dev, &ver);
9727 mutex_unlock(&dev->fw_mutex);
9728 if (ret) {
9729 break;
9730 }
9731
9732 if (copy_to_user(argp, &ver, sizeof(struct ssd_version_info))) {
9733 hio_warn("%s: copy_to_user: failed\n", dev->name);
9734 ret = -EFAULT;
9735 break;
9736 }
9737 break;
9738 }
9739
9740 case SSD_CMD_GET_TEMPERATURE: {
9741 int temp;
9742
9743 mutex_lock(&dev->fw_mutex);
9744 ret = __ssd_get_temperature(dev, &temp);
9745 mutex_unlock(&dev->fw_mutex);
9746 if (ret) {
9747 break;
9748 }
9749
9750 if (copy_to_user(argp, &temp, sizeof(int))) {
9751 hio_warn("%s: copy_to_user: failed\n", dev->name);
9752 ret = -EFAULT;
9753 break;
9754 }
9755 break;
9756 }
9757
9758 case SSD_CMD_GET_BMSTATUS: {
9759 int status;
9760
9761 mutex_lock(&dev->fw_mutex);
9762 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) {
9763 if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) {
9764 status = SSD_BMSTATUS_WARNING;
9765 } else {
9766 status = SSD_BMSTATUS_OK;
9767 }
9768 } else if(dev->protocol_info.ver > SSD_PROTOCOL_V3) {
9769 ret = __ssd_bm_status(dev, &status);
9770 } else {
9771 status = SSD_BMSTATUS_OK;
9772 }
9773 mutex_unlock(&dev->fw_mutex);
9774 if (ret) {
9775 break;
9776 }
9777
9778 if (copy_to_user(argp, &status, sizeof(int))) {
9779 hio_warn("%s: copy_to_user: failed\n", dev->name);
9780 ret = -EFAULT;
9781 break;
9782 }
9783 break;
9784 }
9785
9786 case SSD_CMD_GET_LABEL2: {
9787 void *label;
9788 int length;
9789
9790 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
9791 label = &dev->label;
9792 length = sizeof(struct ssd_label);
9793 } else {
9794 label = &dev->labelv3;
9795 length = sizeof(struct ssd_labelv3);
9796 }
9797
9798 if (copy_to_user(argp, label, length)) {
9799 ret = -EFAULT;
9800 break;
9801 }
9802 break;
9803 }
9804
9805 case SSD_CMD_FLUSH:
9806 ret = ssd_flush(dev);
9807 if (ret) {
9808 hio_warn("%s: ssd_flush: failed\n", dev->name);
9809 ret = -EFAULT;
9810 break;
9811 }
9812 break;
9813
9814 case SSD_CMD_SAVE_MD: {
9815 int save_md = 0;
9816
9817 if (copy_from_user(&save_md, argp, sizeof(int))) {
9818 hio_warn("%s: copy_from_user: failed\n", dev->name);
9819 ret = -EFAULT;
9820 break;
9821 }
9822
9823 dev->save_md = !!save_md;
9824 break;
9825 }
9826
9827 case SSD_CMD_SET_WMODE: {
9828 int new_wmode = 0;
9829
9830 if (copy_from_user(&new_wmode, argp, sizeof(int))) {
9831 hio_warn("%s: copy_from_user: failed\n", dev->name);
9832 ret = -EFAULT;
9833 break;
9834 }
9835
9836 ret = __ssd_set_wmode(dev, new_wmode);
9837 if (ret) {
9838 break;
9839 }
9840
9841 break;
9842 }
9843
9844 case SSD_CMD_GET_WMODE: {
9845 if (copy_to_user(argp, &dev->wmode, sizeof(int))) {
9846 hio_warn("%s: copy_to_user: failed\n", dev->name);
9847 ret = -EFAULT;
9848 break;
9849 }
9850
9851 break;
9852 }
9853
9854 case SSD_CMD_GET_USER_WMODE: {
9855 if (copy_to_user(argp, &dev->user_wmode, sizeof(int))) {
9856 hio_warn("%s: copy_to_user: failed\n", dev->name);
9857 ret = -EFAULT;
9858 break;
9859 }
9860
9861 break;
9862 }
9863
9864 case SSD_CMD_DEBUG: {
9865 struct ssd_debug_info db_info;
9866
9867 if (!finject) {
9868 ret = -EOPNOTSUPP;
9869 break;
9870 }
9871
9872 if (copy_from_user(&db_info, argp, sizeof(struct ssd_debug_info))) {
9873 hio_warn("%s: copy_from_user: failed\n", dev->name);
9874 ret = -EFAULT;
9875 break;
9876 }
9877
9878 if (db_info.type < SSD_DEBUG_NONE || db_info.type >= SSD_DEBUG_NR) {
9879 ret = -EINVAL;
9880 break;
9881 }
9882
9883 /* IO */
9884 if (db_info.type >= SSD_DEBUG_READ_ERR && db_info.type <= SSD_DEBUG_RW_ERR &&
9885 (db_info.data.loc.off + db_info.data.loc.len) > (dev->hw_info.size >> 9)) {
9886 ret = -EINVAL;
9887 break;
9888 }
9889
9890 memcpy(&dev->db_info, &db_info, sizeof(struct ssd_debug_info));
9891
9892#ifdef SSD_OT_PROTECT
9893 /* temperature */
9894 if (db_info.type == SSD_DEBUG_NONE) {
9895 ssd_check_temperature(dev, SSD_OT_TEMP);
9896 } else if (db_info.type == SSD_DEBUG_LOG) {
9897 if (db_info.data.log.event == SSD_LOG_OVER_TEMP) {
9898 dev->ot_delay = SSD_OT_DELAY;
9899 } else if (db_info.data.log.event == SSD_LOG_NORMAL_TEMP) {
9900 dev->ot_delay = 0;
9901 }
9902 }
9903#endif
9904
9905 /* offline */
9906 if (db_info.type == SSD_DEBUG_OFFLINE) {
9907 test_and_clear_bit(SSD_ONLINE, &dev->state);
9908 } else if (db_info.type == SSD_DEBUG_NONE) {
9909 (void)test_and_set_bit(SSD_ONLINE, &dev->state);
9910 }
9911
9912 /* log */
9913 if (db_info.type == SSD_DEBUG_LOG && dev->event_call && dev->gd) {
9914 dev->event_call(dev->gd, db_info.data.log.event, 0);
9915 }
9916
9917 break;
9918 }
9919
9920 case SSD_CMD_DRV_PARAM_INFO: {
9921 struct ssd_drv_param_info drv_param;
9922
9923 memset(&drv_param, 0, sizeof(struct ssd_drv_param_info));
9924
9925 drv_param.mode = mode;
9926 drv_param.status_mask = status_mask;
9927 drv_param.int_mode = int_mode;
9928 drv_param.threaded_irq = threaded_irq;
9929 drv_param.log_level = log_level;
9930 drv_param.wmode = wmode;
9931 drv_param.ot_protect = ot_protect;
9932 drv_param.finject = finject;
9933
9934 if (copy_to_user(argp, &drv_param, sizeof(struct ssd_drv_param_info))) {
9935 hio_warn("%s: copy_to_user: failed\n", dev->name);
9936 ret = -EFAULT;
9937 break;
9938 }
9939 break;
9940 }
9941
9942 default:
9943 ret = -EINVAL;
9944 break;
9945 }
9946
9947 return ret;
9948}
9949
9950
9951#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27))
9952static int ssd_block_ioctl(struct inode *inode, struct file *file,
9953 unsigned int cmd, unsigned long arg)
9954{
9955 struct ssd_device *dev;
9956 void __user *argp = (void __user *)arg;
9957 int ret = 0;
9958
9959 if (!inode) {
9960 return -EINVAL;
9961 }
9962 dev = inode->i_bdev->bd_disk->private_data;
9963 if (!dev) {
9964 return -EINVAL;
9965 }
9966#else
9967static int ssd_block_ioctl(struct block_device *bdev, fmode_t mode,
9968 unsigned int cmd, unsigned long arg)
9969{
9970 struct ssd_device *dev;
9971 void __user *argp = (void __user *)arg;
9972 int ret = 0;
9973
9974 if (!bdev) {
9975 return -EINVAL;
9976 }
9977
9978 dev = bdev->bd_disk->private_data;
9979 if (!dev) {
9980 return -EINVAL;
9981 }
9982#endif
9983
9984 switch (cmd) {
9985 case HDIO_GETGEO: {
9986 struct hd_geometry geo;
9987 geo.cylinders = (dev->hw_info.size & ~0x3f) >> 6;
9988 geo.heads = 4;
9989 geo.sectors = 16;
9990#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27))
9991 geo.start = get_start_sect(inode->i_bdev);
9992#else
9993 geo.start = get_start_sect(bdev);
9994#endif
9995 if (copy_to_user(argp, &geo, sizeof(geo))) {
9996 ret = -EFAULT;
9997 break;
9998 }
9999
10000 break;
10001 }
10002
10003 case BLKFLSBUF:
10004 ret = ssd_flush(dev);
10005 if (ret) {
10006 hio_warn("%s: ssd_flush: failed\n", dev->name);
10007 ret = -EFAULT;
10008 break;
10009 }
10010 break;
10011
10012 default:
10013 if (!dev->slave) {
10014 ret = ssd_ioctl_common(dev, cmd, arg);
10015 } else {
10016 ret = -EFAULT;
10017 }
10018 break;
10019 }
10020
10021 return ret;
10022}
10023
10024
10025static void ssd_free_dev(struct kref *kref)
10026{
10027 struct ssd_device *dev;
10028
10029 if (!kref) {
10030 return;
10031 }
10032
10033 dev = container_of(kref, struct ssd_device, kref);
10034
10035 put_disk(dev->gd);
10036
10037 ssd_put_index(dev->slave, dev->idx);
10038
10039 kfree(dev);
10040}
10041
10042static void ssd_put(struct ssd_device *dev)
10043{
10044 kref_put(&dev->kref, ssd_free_dev);
10045}
10046
10047static int ssd_get(struct ssd_device *dev)
10048{
10049 kref_get(&dev->kref);
10050 return 0;
10051}
10052
10053/* block device */
10054#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27))
10055static int ssd_block_open(struct inode *inode, struct file *filp)
10056{
10057 struct ssd_device *dev;
10058
10059 if (!inode) {
10060 return -EINVAL;
10061 }
10062
10063 dev = inode->i_bdev->bd_disk->private_data;
10064 if (!dev) {
10065 return -EINVAL;
10066 }
10067#else
10068static int ssd_block_open(struct block_device *bdev, fmode_t mode)
10069{
10070 struct ssd_device *dev;
10071
10072 if (!bdev) {
10073 return -EINVAL;
10074 }
10075
10076 dev = bdev->bd_disk->private_data;
10077 if (!dev) {
10078 return -EINVAL;
10079 }
10080#endif
10081
10082 /*if (!try_module_get(dev->owner))
10083 return -ENODEV;
10084 */
10085
10086 ssd_get(dev);
10087
10088 atomic_inc(&dev->refcnt);
10089
10090 return 0;
10091}
10092
10093#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27))
10094static int ssd_block_release(struct inode *inode, struct file *filp)
10095{
10096 struct ssd_device *dev;
10097
10098 if (!inode) {
10099 return -EINVAL;
10100 }
10101
10102 dev = inode->i_bdev->bd_disk->private_data;
10103 if (!dev) {
10104 return -EINVAL;
10105 }
10106#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(3,9,0))
10107static int ssd_block_release(struct gendisk *disk, fmode_t mode)
10108{
10109 struct ssd_device *dev;
10110
10111 if (!disk) {
10112 return -EINVAL;
10113 }
10114
10115 dev = disk->private_data;
10116 if (!dev) {
10117 return -EINVAL;
10118 }
10119#else
10120static void ssd_block_release(struct gendisk *disk, fmode_t mode)
10121{
10122 struct ssd_device *dev;
10123
10124 if (!disk) {
10125 return;
10126 }
10127
10128 dev = disk->private_data;
10129 if (!dev) {
10130 return;
10131 }
10132#endif
10133
10134 atomic_dec(&dev->refcnt);
10135
10136 ssd_put(dev);
10137
10138 //module_put(dev->owner);
10139#if (LINUX_VERSION_CODE <= KERNEL_VERSION(3,9,0))
10140 return 0;
10141#endif
10142}
10143
10144static struct block_device_operations ssd_fops = {
10145 .owner = THIS_MODULE,
10146 .open = ssd_block_open,
10147 .release = ssd_block_release,
10148 .ioctl = ssd_block_ioctl,
10149#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,16))
10150 .getgeo = ssd_block_getgeo,
10151#endif
10152};
10153
10154static void ssd_init_trim(ssd_device_t *dev)
10155{
10156#if (defined SSD_TRIM && (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,32)))
10157 if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) {
10158 return;
10159 }
10160 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, dev->rq);
10161
10162#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,33)) || (defined RHEL_MAJOR && RHEL_MAJOR >= 6))
10163 dev->rq->limits.discard_zeroes_data = 1;
10164 dev->rq->limits.discard_alignment = 4096;
10165 dev->rq->limits.discard_granularity = 4096;
10166#endif
10167 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2_4) {
10168 dev->rq->limits.max_discard_sectors = dev->hw_info.sg_max_sec;
10169 } else {
10170 dev->rq->limits.max_discard_sectors = (dev->hw_info.sg_max_sec) * (dev->hw_info.cmd_max_sg);
10171 }
10172#endif
10173}
10174
10175static void ssd_cleanup_queue(struct ssd_device *dev)
10176{
10177 ssd_wait_io(dev);
10178
10179 blk_cleanup_queue(dev->rq);
10180 dev->rq = NULL;
10181}
10182
10183static int ssd_init_queue(struct ssd_device *dev)
10184{
10185 dev->rq = blk_alloc_queue(GFP_KERNEL);
10186 if (dev->rq == NULL) {
10187 hio_warn("%s: alloc queue: failed\n ", dev->name);
10188 goto out_init_queue;
10189 }
10190
10191 /* must be first */
10192 blk_queue_make_request(dev->rq, ssd_make_request);
10193
10194#if ((LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34)) && !(defined RHEL_MAJOR && RHEL_MAJOR == 6))
10195 blk_queue_max_hw_segments(dev->rq, dev->hw_info.cmd_max_sg);
10196 blk_queue_max_phys_segments(dev->rq, dev->hw_info.cmd_max_sg);
10197 blk_queue_max_sectors(dev->rq, dev->hw_info.sg_max_sec);
10198#else
10199 blk_queue_max_segments(dev->rq, dev->hw_info.cmd_max_sg);
10200 blk_queue_max_hw_sectors(dev->rq, dev->hw_info.sg_max_sec);
10201#endif
10202
10203#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31))
10204 blk_queue_hardsect_size(dev->rq, 512);
10205#else
10206 blk_queue_logical_block_size(dev->rq, 512);
10207#endif
10208 /* not work for make_request based drivers(bio) */
10209 blk_queue_max_segment_size(dev->rq, dev->hw_info.sg_max_sec << 9);
10210
10211 blk_queue_bounce_limit(dev->rq, BLK_BOUNCE_HIGH);
10212
10213 dev->rq->queuedata = dev;
10214
10215#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20))
10216 blk_queue_issue_flush_fn(dev->rq, ssd_issue_flush_fn);
10217#endif
10218
10219#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,28))
10220 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, dev->rq);
10221#endif
10222
10223 ssd_init_trim(dev);
10224
10225 return 0;
10226
10227out_init_queue:
10228 return -ENOMEM;
10229}
10230
10231static void ssd_cleanup_blkdev(struct ssd_device *dev)
10232{
10233 del_gendisk(dev->gd);
10234}
10235
10236static int ssd_init_blkdev(struct ssd_device *dev)
10237{
10238 if (dev->gd) {
10239 put_disk(dev->gd);
10240 }
10241
10242 dev->gd = alloc_disk(ssd_minors);
10243 if (!dev->gd) {
10244 hio_warn("%s: alloc_disk fail\n", dev->name);
10245 goto out_alloc_gd;
10246 }
10247 dev->gd->major = dev->major;
10248 dev->gd->first_minor = dev->idx * ssd_minors;
10249 dev->gd->fops = &ssd_fops;
10250 dev->gd->queue = dev->rq;
10251 dev->gd->private_data = dev;
a9d1e0c7 10252
a6a796ca
HSDT
10253 snprintf (dev->gd->disk_name, sizeof(dev->gd->disk_name), "%s", dev->name);
10254
10255 set_capacity(dev->gd, dev->hw_info.size >> 9);
10256
a9d1e0c7 10257#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4,8,0))
195d6988 10258 device_add_disk(&dev->pdev->dev, dev->gd);
a9d1e0c7
KM
10259#else
10260 dev->gd->driverfs_dev = &dev->pdev->dev;
10261 add_disk(dev->gd);
195d6988 10262#endif
a6a796ca
HSDT
10263
10264 return 0;
10265
10266out_alloc_gd:
10267 return -ENOMEM;
10268}
10269
10270#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,10))
10271static int ssd_ioctl(struct inode *inode, struct file *file,
10272 unsigned int cmd, unsigned long arg)
10273#else
10274static long ssd_ioctl(struct file *file,
10275 unsigned int cmd, unsigned long arg)
10276#endif
10277{
10278 struct ssd_device *dev;
10279
10280 if (!file) {
10281 return -EINVAL;
10282 }
10283
10284 dev = file->private_data;
10285 if (!dev) {
10286 return -EINVAL;
10287 }
10288
10289 return (long)ssd_ioctl_common(dev, cmd, arg);
10290}
10291
10292static int ssd_open(struct inode *inode, struct file *file)
10293{
10294 struct ssd_device *dev = NULL;
10295 struct ssd_device *n = NULL;
10296 int idx;
10297 int ret = -ENODEV;
10298
10299 if (!inode || !file) {
10300 return -EINVAL;
10301 }
10302
10303 idx = iminor(inode);
10304
10305 list_for_each_entry_safe(dev, n, &ssd_list, list) {
10306 if (dev->idx == idx) {
10307 ret = 0;
10308 break;
10309 }
10310 }
10311
10312 if (ret) {
10313 return ret;
10314 }
10315
10316 file->private_data = dev;
10317
10318 ssd_get(dev);
10319
10320 return 0;
10321}
10322
10323static int ssd_release(struct inode *inode, struct file *file)
10324{
10325 struct ssd_device *dev;
10326
10327 if (!file) {
10328 return -EINVAL;
10329 }
10330
10331 dev = file->private_data;
10332 if (!dev) {
10333 return -EINVAL;
10334 }
10335
10336 ssd_put(dev);
10337
10338 file->private_data = NULL;
10339
10340 return 0;
10341}
10342
a9d1e0c7
KM
10343static int ssd_reload_ssd_ptr(struct ssd_device *dev)
10344{
10345 ssd_reset_resp_ptr(dev);
10346
10347 //update base reg address
10348 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3) {
10349
10350 ssd_reg_write(dev->ctrlp + SSD_MSG_BASE_REG, dev->msg_base_dma);
10351 }
10352
10353 //update response base reg address
10354 ssd_reg_write(dev->ctrlp + SSD_RESP_FIFO_REG, dev->resp_msg_base_dma);
10355 ssd_reg_write(dev->ctrlp + SSD_RESP_PTR_REG, dev->resp_ptr_base_dma);
10356
10357 return 0;
10358}
10359
a6a796ca
HSDT
10360static struct file_operations ssd_cfops = {
10361 .owner = THIS_MODULE,
10362 .open = ssd_open,
10363 .release = ssd_release,
10364#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,10))
10365 .ioctl = ssd_ioctl,
10366#else
10367 .unlocked_ioctl = ssd_ioctl,
10368#endif
10369};
10370
10371static void ssd_cleanup_chardev(struct ssd_device *dev)
10372{
10373 if (dev->slave) {
10374 return;
10375 }
10376
10377#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12))
10378 class_simple_device_remove(MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx));
10379 devfs_remove("c%s", dev->name);
10380#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,14))
10381 class_device_destroy(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx));
10382 devfs_remove("c%s", dev->name);
10383#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17))
10384 class_device_destroy(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx));
10385 devfs_remove("c%s", dev->name);
10386#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24))
10387 class_device_destroy(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx));
10388#else
10389 device_destroy(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx));
10390#endif
10391}
10392
10393static int ssd_init_chardev(struct ssd_device *dev)
10394{
10395 int ret = 0;
10396
10397 if (dev->slave) {
10398 return 0;
10399 }
10400
10401#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12))
10402 ret = devfs_mk_cdev(MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), S_IFCHR|S_IRUSR|S_IWUSR, "c%s", dev->name);
10403 if (ret) {
10404 goto out;
10405 }
10406 class_simple_device_add(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name);
10407out:
10408#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,14))
10409 ret = devfs_mk_cdev(MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), S_IFCHR|S_IRUSR|S_IWUSR, "c%s", dev->name);
10410 if (ret) {
10411 goto out;
10412 }
10413 class_device_create(ssd_class, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name);
10414out:
10415#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,17))
10416 ret = devfs_mk_cdev(MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), S_IFCHR|S_IRUSR|S_IWUSR, "c%s", dev->name);
10417 if (ret) {
10418 goto out;
10419 }
10420 class_device_create(ssd_class, NULL, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name);
10421out:
10422#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,24))
10423 class_device_create(ssd_class, NULL, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name);
10424#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,26))
10425 device_create(ssd_class, NULL, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), "c%s", dev->name);
10426#elif (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,27))
10427 device_create_drvdata(ssd_class, NULL, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name);
10428#else
10429 device_create(ssd_class, NULL, MKDEV((dev_t)dev->cmajor, (dev_t)dev->idx), NULL, "c%s", dev->name);
10430#endif
10431
10432 return ret;
10433}
10434
10435static int ssd_check_hw(struct ssd_device *dev)
10436{
10437 uint32_t test_data = 0x55AA5AA5;
10438 uint32_t read_data;
10439
10440 ssd_reg32_write(dev->ctrlp + SSD_BRIDGE_TEST_REG, test_data);
10441 read_data = ssd_reg32_read(dev->ctrlp + SSD_BRIDGE_TEST_REG);
10442 if (read_data != ~(test_data)) {
10443 //hio_warn("%s: check bridge error: %#x\n", dev->name, read_data);
10444 return -1;
10445 }
10446
10447 return 0;
10448}
10449
10450static int ssd_check_fw(struct ssd_device *dev)
10451{
10452 uint32_t val = 0;
10453 int i;
10454
10455 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_3) {
10456 return 0;
10457 }
10458
10459 for (i=0; i<SSD_CONTROLLER_WAIT; i++) {
10460 val = ssd_reg32_read(dev->ctrlp + SSD_HW_STATUS_REG);
10461 if ((val & 0x1) && ((val >> 8) & 0x1)) {
10462 break;
10463 }
10464
10465 msleep(SSD_INIT_WAIT);
10466 }
10467
10468 if (!(val & 0x1)) {
10469 /* controller fw status */
10470 hio_warn("%s: controller firmware load failed: %#x\n", dev->name, val);
10471 return -1;
10472 } else if (!((val >> 8) & 0x1)) {
10473 /* controller state */
10474 hio_warn("%s: controller state error: %#x\n", dev->name, val);
10475 return -1;
10476 }
10477
10478 val = ssd_reg32_read(dev->ctrlp + SSD_RELOAD_FW_REG);
10479 if (val) {
10480 dev->reload_fw = 1;
10481 }
10482
10483 return 0;
10484}
10485
10486static int ssd_init_fw_info(struct ssd_device *dev)
10487{
10488 uint32_t val;
10489 int ret = 0;
10490
10491 val = ssd_reg32_read(dev->ctrlp + SSD_BRIDGE_VER_REG);
10492 dev->hw_info.bridge_ver = val & 0xFFF;
10493 if (dev->hw_info.bridge_ver < SSD_FW_MIN) {
10494 hio_warn("%s: bridge firmware version %03X is not supported\n", dev->name, dev->hw_info.bridge_ver);
10495 return -EINVAL;
10496 }
10497 hio_info("%s: bridge firmware version: %03X\n", dev->name, dev->hw_info.bridge_ver);
10498
10499 ret = ssd_check_fw(dev);
10500 if (ret) {
10501 goto out;
10502 }
10503
10504out:
10505 /* skip error if not in standard mode */
10506 if (mode != SSD_DRV_MODE_STANDARD) {
10507 ret = 0;
10508 }
10509 return ret;
10510}
10511
10512static int ssd_check_clock(struct ssd_device *dev)
10513{
10514 uint32_t val;
10515 int ret = 0;
10516
10517 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_3) {
10518 return 0;
10519 }
10520
10521 val = ssd_reg32_read(dev->ctrlp + SSD_HW_STATUS_REG);
10522
10523 /* clock status */
10524 if (!((val >> 4 ) & 0x1)) {
10525 if (!test_and_set_bit(SSD_HWMON_CLOCK(SSD_CLOCK_166M_LOST), &dev->hwmon)) {
10526 hio_warn("%s: 166MHz clock losed: %#x\n", dev->name, val);
10527 ssd_gen_swlog(dev, SSD_LOG_CLK_FAULT, val);
10528 }
10529 ret = -1;
10530 }
10531
10532 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) {
10533 if (!((val >> 5 ) & 0x1)) {
10534 if (!test_and_set_bit(SSD_HWMON_CLOCK(SSD_CLOCK_166M_SKEW), &dev->hwmon)) {
10535 hio_warn("%s: 166MHz clock is skew: %#x\n", dev->name, val);
10536 ssd_gen_swlog(dev, SSD_LOG_CLK_FAULT, val);
10537 }
10538 ret = -1;
10539 }
10540 if (!((val >> 6 ) & 0x1)) {
10541 if (!test_and_set_bit(SSD_HWMON_CLOCK(SSD_CLOCK_156M_LOST), &dev->hwmon)) {
10542 hio_warn("%s: 156.25MHz clock lost: %#x\n", dev->name, val);
10543 ssd_gen_swlog(dev, SSD_LOG_CLK_FAULT, val);
10544 }
10545 ret = -1;
10546 }
10547 if (!((val >> 7 ) & 0x1)) {
10548 if (!test_and_set_bit(SSD_HWMON_CLOCK(SSD_CLOCK_156M_SKEW), &dev->hwmon)) {
10549 hio_warn("%s: 156.25MHz clock is skew: %#x\n", dev->name, val);
10550 ssd_gen_swlog(dev, SSD_LOG_CLK_FAULT, val);
10551 }
10552 ret = -1;
10553 }
10554 }
10555
10556 return ret;
10557}
10558
10559static int ssd_check_volt(struct ssd_device *dev)
10560{
10561 int i = 0;
10562 uint64_t val;
10563 uint32_t adc_val;
10564 int ret =0;
10565
10566 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
10567 return 0;
10568 }
10569
10570 for (i=0; i<dev->hw_info.nr_ctrl; i++) {
10571 /* 1.0v */
10572 if (!test_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V0), &dev->hwmon)) {
10573 val = ssd_reg_read(dev->ctrlp + SSD_FPGA_1V0_REG0 + i * SSD_CTRL_REG_ZONE_SZ);
10574 adc_val = SSD_FPGA_VOLT_MAX(val);
10575 if (adc_val < SSD_FPGA_1V0_ADC_MIN || adc_val > SSD_FPGA_1V0_ADC_MAX) {
10576 (void)test_and_set_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V0), &dev->hwmon);
10577 hio_warn("%s: controller %d 1.0V fault: %d mV.\n", dev->name, i, SSD_FPGA_VOLT(adc_val));
10578 ssd_gen_swlog(dev, SSD_LOG_VOLT_FAULT, SSD_VOLT_LOG_DATA(SSD_FPGA_1V0, i, adc_val));
10579 ret = -1;
10580 }
10581
10582 adc_val = SSD_FPGA_VOLT_MIN(val);
10583 if (adc_val < SSD_FPGA_1V0_ADC_MIN || adc_val > SSD_FPGA_1V0_ADC_MAX) {
10584 (void)test_and_set_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V0), &dev->hwmon);
10585 hio_warn("%s: controller %d 1.0V fault: %d mV.\n", dev->name, i, SSD_FPGA_VOLT(adc_val));
10586 ssd_gen_swlog(dev, SSD_LOG_VOLT_FAULT, SSD_VOLT_LOG_DATA(SSD_FPGA_1V0, i, adc_val));
10587 ret = -2;
10588 }
10589 }
10590
10591 /* 1.8v */
10592 if (!test_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V8), &dev->hwmon)) {
10593 val = ssd_reg_read(dev->ctrlp + SSD_FPGA_1V8_REG0 + i * SSD_CTRL_REG_ZONE_SZ);
10594 adc_val = SSD_FPGA_VOLT_MAX(val);
10595 if (adc_val < SSD_FPGA_1V8_ADC_MIN || adc_val > SSD_FPGA_1V8_ADC_MAX) {
10596 (void)test_and_set_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V8), &dev->hwmon);
10597 hio_warn("%s: controller %d 1.8V fault: %d mV.\n", dev->name, i, SSD_FPGA_VOLT(adc_val));
10598 ssd_gen_swlog(dev, SSD_LOG_VOLT_FAULT, SSD_VOLT_LOG_DATA(SSD_FPGA_1V8, i, adc_val));
10599 ret = -3;
10600 }
10601
10602 adc_val = SSD_FPGA_VOLT_MIN(val);
10603 if (adc_val < SSD_FPGA_1V8_ADC_MIN || adc_val > SSD_FPGA_1V8_ADC_MAX) {
10604 (void)test_and_set_bit(SSD_HWMON_FPGA(i, SSD_FPGA_1V8), &dev->hwmon);
10605 hio_warn("%s: controller %d 1.8V fault: %d mV.\n", dev->name, i, SSD_FPGA_VOLT(adc_val));
10606 ssd_gen_swlog(dev, SSD_LOG_VOLT_FAULT, SSD_VOLT_LOG_DATA(SSD_FPGA_1V8, i, adc_val));
10607 ret = -4;
10608 }
10609 }
10610 }
10611
10612 return ret;
10613}
10614
10615static int ssd_check_reset_sync(struct ssd_device *dev)
10616{
10617 uint32_t val;
10618
10619 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_3) {
10620 return 0;
10621 }
10622
10623 val = ssd_reg32_read(dev->ctrlp + SSD_HW_STATUS_REG);
10624 if (!((val >> 8) & 0x1)) {
10625 /* controller state */
10626 hio_warn("%s: controller state error: %#x\n", dev->name, val);
10627 return -1;
10628 }
10629
10630 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
10631 return 0;
10632 }
10633
10634 if (((val >> 9 ) & 0x1)) {
10635 hio_warn("%s: controller reset asynchronously: %#x\n", dev->name, val);
10636 ssd_gen_swlog(dev, SSD_LOG_CTRL_RST_SYNC, val);
10637 return -1;
10638 }
10639
10640 return 0;
10641}
10642
10643static int ssd_check_hw_bh(struct ssd_device *dev)
10644{
10645 int ret;
10646
10647 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_3) {
10648 return 0;
10649 }
10650
10651 /* clock status */
10652 ret = ssd_check_clock(dev);
10653 if (ret) {
10654 goto out;
10655 }
10656
10657out:
10658 /* skip error if not in standard mode */
10659 if (mode != SSD_DRV_MODE_STANDARD) {
10660 ret = 0;
10661 }
10662 return ret;
10663}
10664
10665static int ssd_check_controller(struct ssd_device *dev)
10666{
10667 int ret;
10668
10669 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_1_3) {
10670 return 0;
10671 }
10672
10673 /* sync reset */
10674 ret = ssd_check_reset_sync(dev);
10675 if (ret) {
10676 goto out;
10677 }
10678
10679out:
10680 /* skip error if not in standard mode */
10681 if (mode != SSD_DRV_MODE_STANDARD) {
10682 ret = 0;
10683 }
10684 return ret;
10685}
10686
10687static int ssd_check_controller_bh(struct ssd_device *dev)
10688{
10689 uint32_t test_data = 0x55AA5AA5;
10690 uint32_t val;
10691 int reg_base, reg_sz;
10692 int init_wait = 0;
10693 int i;
10694 int ret = 0;
10695
10696 if (mode != SSD_DRV_MODE_STANDARD) {
10697 return 0;
10698 }
10699
10700 /* controller */
10701 val = ssd_reg32_read(dev->ctrlp + SSD_READY_REG);
10702 if (val & 0x1) {
10703 hio_warn("%s: controller 0 not ready\n", dev->name);
10704 return -1;
10705 }
10706
10707 for (i=0; i<dev->hw_info.nr_ctrl; i++) {
10708 reg_base = SSD_CTRL_TEST_REG0 + i * SSD_CTRL_TEST_REG_SZ;
10709 ssd_reg32_write(dev->ctrlp + reg_base, test_data);
10710 val = ssd_reg32_read(dev->ctrlp + reg_base);
10711 if (val != ~(test_data)) {
10712 hio_warn("%s: check controller %d error: %#x\n", dev->name, i, val);
10713 return -1;
10714 }
10715 }
10716
10717 /* clock */
10718 ret = ssd_check_volt(dev);
10719 if (ret) {
10720 return ret;
10721 }
10722
10723 /* ddr */
10724 if (dev->protocol_info.ver > SSD_PROTOCOL_V3) {
10725 reg_base = SSD_PV3_RAM_STATUS_REG0;
10726 reg_sz = SSD_PV3_RAM_STATUS_REG_SZ;
10727
10728 for (i=0; i<dev->hw_info.nr_ctrl; i++) {
10729check_ram_status:
10730 val = ssd_reg32_read(dev->ctrlp + reg_base);
10731
10732 if (!((val >> 1) & 0x1)) {
10733 init_wait++;
10734 if (init_wait <= SSD_RAM_INIT_MAX_WAIT) {
10735 msleep(SSD_INIT_WAIT);
10736 goto check_ram_status;
10737 } else {
10738 hio_warn("%s: controller %d ram init failed: %#x\n", dev->name, i, val);
10739 ssd_gen_swlog(dev, SSD_LOG_DDR_INIT_ERR, i);
10740 return -1;
10741 }
10742 }
10743
10744 reg_base += reg_sz;
10745 }
10746 }
10747
10748 /* ch info */
10749 for (i=0; i<SSD_CH_INFO_MAX_WAIT; i++) {
10750 val = ssd_reg32_read(dev->ctrlp + SSD_CH_INFO_REG);
10751 if (!((val >> 31) & 0x1)) {
10752 break;
10753 }
10754
10755 msleep(SSD_INIT_WAIT);
10756 }
10757 if ((val >> 31) & 0x1) {
10758 hio_warn("%s: channel info init failed: %#x\n", dev->name, val);
10759 return -1;
10760 }
10761
10762 return 0;
10763}
10764
10765static int ssd_init_protocol_info(struct ssd_device *dev)
10766{
10767 uint32_t val;
10768
10769 val = ssd_reg32_read(dev->ctrlp + SSD_PROTOCOL_VER_REG);
10770 if (val == (uint32_t)-1) {
10771 hio_warn("%s: protocol version error: %#x\n", dev->name, val);
10772 return -EINVAL;
10773 }
10774 dev->protocol_info.ver = val;
10775
10776 if (dev->protocol_info.ver < SSD_PROTOCOL_V3) {
10777 dev->protocol_info.init_state_reg = SSD_INIT_STATE_REG0;
10778 dev->protocol_info.init_state_reg_sz = SSD_INIT_STATE_REG_SZ;
10779
10780 dev->protocol_info.chip_info_reg = SSD_CHIP_INFO_REG0;
10781 dev->protocol_info.chip_info_reg_sz = SSD_CHIP_INFO_REG_SZ;
10782 } else {
10783 dev->protocol_info.init_state_reg = SSD_PV3_INIT_STATE_REG0;
10784 dev->protocol_info.init_state_reg_sz = SSD_PV3_INIT_STATE_REG_SZ;
10785
10786 dev->protocol_info.chip_info_reg = SSD_PV3_CHIP_INFO_REG0;
10787 dev->protocol_info.chip_info_reg_sz = SSD_PV3_CHIP_INFO_REG_SZ;
10788 }
10789
10790 return 0;
10791}
10792
10793static int ssd_init_hw_info(struct ssd_device *dev)
10794{
10795 uint64_t val64;
10796 uint32_t val;
10797 uint32_t nr_ctrl;
10798 int ret = 0;
10799
10800 /* base info */
10801 val = ssd_reg32_read(dev->ctrlp + SSD_RESP_INFO_REG);
10802 dev->hw_info.resp_ptr_sz = 16 * (1U << (val & 0xFF));
10803 dev->hw_info.resp_msg_sz = 16 * (1U << ((val >> 8) & 0xFF));
10804
10805 if (0 == dev->hw_info.resp_ptr_sz || 0 == dev->hw_info.resp_msg_sz) {
10806 hio_warn("%s: response info error\n", dev->name);
10807 ret = -EINVAL;
10808 goto out;
10809 }
10810
10811 val = ssd_reg32_read(dev->ctrlp + SSD_BRIDGE_INFO_REG);
10812 dev->hw_info.cmd_fifo_sz = 1U << ((val >> 4) & 0xF);
10813 dev->hw_info.cmd_max_sg = 1U << ((val >> 8) & 0xF);
10814 dev->hw_info.sg_max_sec = 1U << ((val >> 12) & 0xF);
10815 dev->hw_info.cmd_fifo_sz_mask = dev->hw_info.cmd_fifo_sz - 1;
10816
10817 if (0 == dev->hw_info.cmd_fifo_sz || 0 == dev->hw_info.cmd_max_sg || 0 == dev->hw_info.sg_max_sec) {
10818 hio_warn("%s: cmd info error\n", dev->name);
10819 ret = -EINVAL;
10820 goto out;
10821 }
10822
10823 /* check hw */
10824 if (ssd_check_hw_bh(dev)) {
10825 hio_warn("%s: check hardware status failed\n", dev->name);
10826 ret = -EINVAL;
10827 goto out;
10828 }
10829
10830 if (ssd_check_controller(dev)) {
10831 hio_warn("%s: check controller state failed\n", dev->name);
10832 ret = -EINVAL;
10833 goto out;
10834 }
10835
10836 /* nr controller : read again*/
10837 val = ssd_reg32_read(dev->ctrlp + SSD_BRIDGE_INFO_REG);
10838 dev->hw_info.nr_ctrl = (val >> 16) & 0xF;
10839
10840 /* nr ctrl configured */
10841 nr_ctrl = (val >> 20) & 0xF;
10842 if (0 == dev->hw_info.nr_ctrl) {
10843 hio_warn("%s: nr controller error: %u\n", dev->name, dev->hw_info.nr_ctrl);
10844 ret = -EINVAL;
10845 goto out;
10846 } else if (0 != nr_ctrl && nr_ctrl != dev->hw_info.nr_ctrl) {
10847 hio_warn("%s: nr controller error: configured %u but found %u\n", dev->name, nr_ctrl, dev->hw_info.nr_ctrl);
10848 if (mode <= SSD_DRV_MODE_STANDARD) {
10849 ret = -EINVAL;
10850 goto out;
10851 }
10852 }
10853
10854 if (ssd_check_controller_bh(dev)) {
10855 hio_warn("%s: check controller failed\n", dev->name);
10856 ret = -EINVAL;
10857 goto out;
10858 }
10859
10860 val = ssd_reg32_read(dev->ctrlp + SSD_PCB_VER_REG);
10861 dev->hw_info.pcb_ver = (uint8_t) ((val >> 4) & 0xF) + 'A' -1;
10862 if ((val & 0xF) != 0xF) {
10863 dev->hw_info.upper_pcb_ver = (uint8_t) (val & 0xF) + 'A' -1;
10864 }
10865
10866 if (dev->hw_info.pcb_ver < 'A' || (0 != dev->hw_info.upper_pcb_ver && dev->hw_info.upper_pcb_ver < 'A')) {
10867 hio_warn("%s: PCB version error: %#x %#x\n", dev->name, dev->hw_info.pcb_ver, dev->hw_info.upper_pcb_ver);
10868 ret = -EINVAL;
10869 goto out;
10870 }
10871
10872 /* channel info */
10873 if (mode <= SSD_DRV_MODE_DEBUG) {
10874 val = ssd_reg32_read(dev->ctrlp + SSD_CH_INFO_REG);
10875 dev->hw_info.nr_data_ch = val & 0xFF;
10876 dev->hw_info.nr_ch = dev->hw_info.nr_data_ch + ((val >> 8) & 0xFF);
10877 dev->hw_info.nr_chip = (val >> 16) & 0xFF;
10878
10879 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
10880 dev->hw_info.max_ch = 1;
10881 while (dev->hw_info.max_ch < dev->hw_info.nr_ch) dev->hw_info.max_ch <<= 1;
10882 } else {
10883 /* set max channel 32 */
10884 dev->hw_info.max_ch = 32;
10885 }
10886
10887 if (0 == dev->hw_info.nr_chip) {
10888 //for debug mode
10889 dev->hw_info.nr_chip = 1;
10890 }
10891
10892 //xx
10893 dev->hw_info.id_size = SSD_NAND_ID_SZ;
10894 dev->hw_info.max_ce = SSD_NAND_MAX_CE;
10895
10896 if (0 == dev->hw_info.nr_data_ch || 0 == dev->hw_info.nr_ch || 0 == dev->hw_info.nr_chip) {
10897 hio_warn("%s: channel info error: data_ch %u ch %u chip %u\n", dev->name, dev->hw_info.nr_data_ch, dev->hw_info.nr_ch, dev->hw_info.nr_chip);
10898 ret = -EINVAL;
10899 goto out;
10900 }
10901 }
10902
10903 /* ram info */
10904 if (mode <= SSD_DRV_MODE_DEBUG) {
10905 val = ssd_reg32_read(dev->ctrlp + SSD_RAM_INFO_REG);
10906 dev->hw_info.ram_size = 0x4000000ull * (1ULL << (val & 0xF));
10907 dev->hw_info.ram_align = 1U << ((val >> 12) & 0xF);
10908 if (dev->hw_info.ram_align < SSD_RAM_ALIGN) {
10909 if (dev->protocol_info.ver < SSD_PROTOCOL_V3) {
10910 dev->hw_info.ram_align = SSD_RAM_ALIGN;
10911 } else {
10912 hio_warn("%s: ram align error: %u\n", dev->name, dev->hw_info.ram_align);
10913 ret = -EINVAL;
10914 goto out;
10915 }
10916 }
10917 dev->hw_info.ram_max_len = 0x1000 * (1U << ((val >> 16) & 0xF));
10918
10919 if (0 == dev->hw_info.ram_size || 0 == dev->hw_info.ram_align || 0 == dev->hw_info.ram_max_len || dev->hw_info.ram_align > dev->hw_info.ram_max_len) {
10920 hio_warn("%s: ram info error\n", dev->name);
10921 ret = -EINVAL;
10922 goto out;
10923 }
10924
10925 if (dev->protocol_info.ver < SSD_PROTOCOL_V3) {
10926 dev->hw_info.log_sz = SSD_LOG_MAX_SZ;
10927 } else {
10928 val = ssd_reg32_read(dev->ctrlp + SSD_LOG_INFO_REG);
10929 dev->hw_info.log_sz = 0x1000 * (1U << (val & 0xFF));
10930 }
10931 if (0 == dev->hw_info.log_sz) {
10932 hio_warn("%s: log size error\n", dev->name);
10933 ret = -EINVAL;
10934 goto out;
10935 }
10936
10937 val = ssd_reg32_read(dev->ctrlp + SSD_BBT_BASE_REG);
10938 dev->hw_info.bbt_base = 0x40000ull * (val & 0xFFFF);
10939 dev->hw_info.bbt_size = 0x40000 * (((val >> 16) & 0xFFFF) + 1) / (dev->hw_info.max_ch * dev->hw_info.nr_chip);
10940 if (dev->protocol_info.ver < SSD_PROTOCOL_V3) {
10941 if (dev->hw_info.bbt_base > dev->hw_info.ram_size || 0 == dev->hw_info.bbt_size) {
10942 hio_warn("%s: bbt info error\n", dev->name);
10943 ret = -EINVAL;
10944 goto out;
10945 }
10946 }
10947
10948 val = ssd_reg32_read(dev->ctrlp + SSD_ECT_BASE_REG);
10949 dev->hw_info.md_base = 0x40000ull * (val & 0xFFFF);
10950 if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) {
10951 dev->hw_info.md_size = 0x40000 * (((val >> 16) & 0xFFF) + 1) / (dev->hw_info.max_ch * dev->hw_info.nr_chip);
10952 } else {
10953 dev->hw_info.md_size = 0x40000 * (((val >> 16) & 0xFFF) + 1) / (dev->hw_info.nr_chip);
10954 }
10955 dev->hw_info.md_entry_sz = 8 * (1U << ((val >> 28) & 0xF));
10956 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3) {
10957 if (dev->hw_info.md_base > dev->hw_info.ram_size || 0 == dev->hw_info.md_size ||
10958 0 == dev->hw_info.md_entry_sz || dev->hw_info.md_entry_sz > dev->hw_info.md_size) {
10959 hio_warn("%s: md info error\n", dev->name);
10960 ret = -EINVAL;
10961 goto out;
10962 }
10963 }
10964
10965 if (dev->protocol_info.ver < SSD_PROTOCOL_V3) {
10966 dev->hw_info.nand_wbuff_base = dev->hw_info.ram_size + 1;
10967 } else {
10968 val = ssd_reg32_read(dev->ctrlp + SSD_NAND_BUFF_BASE);
10969 dev->hw_info.nand_wbuff_base = 0x8000ull * val;
10970 }
10971 }
10972
10973 /* flash info */
10974 if (mode <= SSD_DRV_MODE_DEBUG) {
10975 if (dev->hw_info.nr_ctrl > 1) {
10976 val = ssd_reg32_read(dev->ctrlp + SSD_CTRL_VER_REG);
10977 dev->hw_info.ctrl_ver = val & 0xFFF;
10978 hio_info("%s: controller firmware version: %03X\n", dev->name, dev->hw_info.ctrl_ver);
10979 }
10980
10981 val64 = ssd_reg_read(dev->ctrlp + SSD_FLASH_INFO_REG0);
10982 dev->hw_info.nand_vendor_id = ((val64 >> 56) & 0xFF);
10983 dev->hw_info.nand_dev_id = ((val64 >> 48) & 0xFF);
10984
10985 dev->hw_info.block_count = (((val64 >> 32) & 0xFFFF) + 1);
10986 dev->hw_info.page_count = ((val64>>16) & 0xFFFF);
10987 dev->hw_info.page_size = (val64 & 0xFFFF);
10988
10989 val = ssd_reg32_read(dev->ctrlp + SSD_BB_INFO_REG);
10990 dev->hw_info.bbf_pages = val & 0xFF;
10991 dev->hw_info.bbf_seek = (val >> 8) & 0x1;
10992
10993 if (0 == dev->hw_info.block_count || 0 == dev->hw_info.page_count || 0 == dev->hw_info.page_size || dev->hw_info.block_count > INT_MAX) {
10994 hio_warn("%s: flash info error\n", dev->name);
10995 ret = -EINVAL;
10996 goto out;
10997 }
10998
10999 //xx
11000 dev->hw_info.oob_size = SSD_NAND_OOB_SZ; //(dev->hw_info.page_size) >> 5;
11001
11002 val = ssd_reg32_read(dev->ctrlp + SSD_VALID_PAGES_REG);
11003 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
11004 dev->hw_info.valid_pages = val & 0x3FF;
11005 dev->hw_info.max_valid_pages = (val>>20) & 0x3FF;
11006 } else {
11007 dev->hw_info.valid_pages = val & 0x7FFF;
11008 dev->hw_info.max_valid_pages = (val>>15) & 0x7FFF;
11009 }
11010 if (0 == dev->hw_info.valid_pages || 0 == dev->hw_info.max_valid_pages ||
11011 dev->hw_info.valid_pages > dev->hw_info.max_valid_pages || dev->hw_info.max_valid_pages > dev->hw_info.page_count) {
11012 hio_warn("%s: valid page info error: valid_pages %d, max_valid_pages %d\n", dev->name, dev->hw_info.valid_pages, dev->hw_info.max_valid_pages);
11013 ret = -EINVAL;
11014 goto out;
11015 }
11016
11017 val = ssd_reg32_read(dev->ctrlp + SSD_RESERVED_BLKS_REG);
11018 dev->hw_info.reserved_blks = val & 0xFFFF;
11019 dev->hw_info.md_reserved_blks = (val >> 16) & 0xFF;
11020 if (dev->protocol_info.ver <= SSD_PROTOCOL_V3) {
11021 dev->hw_info.md_reserved_blks = SSD_BBT_RESERVED;
11022 }
11023 if (dev->hw_info.reserved_blks > dev->hw_info.block_count || dev->hw_info.md_reserved_blks > dev->hw_info.block_count) {
11024 hio_warn("%s: reserved blocks info error: reserved_blks %d, md_reserved_blks %d\n", dev->name, dev->hw_info.reserved_blks, dev->hw_info.md_reserved_blks);
11025 ret = -EINVAL;
11026 goto out;
11027 }
11028 }
11029
11030 /* size */
11031 if (mode < SSD_DRV_MODE_DEBUG) {
11032 dev->hw_info.size = (uint64_t)dev->hw_info.valid_pages * dev->hw_info.page_size;
11033 dev->hw_info.size *= (dev->hw_info.block_count - dev->hw_info.reserved_blks);
11034 dev->hw_info.size *= ((uint64_t)dev->hw_info.nr_data_ch * (uint64_t)dev->hw_info.nr_chip * (uint64_t)dev->hw_info.nr_ctrl);
11035 }
11036
11037 /* extend hardware info */
11038 val = ssd_reg32_read(dev->ctrlp + SSD_PCB_VER_REG);
11039 dev->hw_info_ext.board_type = (val >> 24) & 0xF;
11040
11041 dev->hw_info_ext.form_factor = SSD_FORM_FACTOR_FHHL;
11042 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2_1) {
11043 dev->hw_info_ext.form_factor = (val >> 31) & 0x1;
11044 }
11045 /*
11046 dev->hw_info_ext.cap_type = (val >> 28) & 0x3;
11047 if (SSD_BM_CAP_VINA != dev->hw_info_ext.cap_type && SSD_BM_CAP_JH != dev->hw_info_ext.cap_type) {
11048 dev->hw_info_ext.cap_type = SSD_BM_CAP_VINA;
11049 }*/
11050
11051 /* power loss protect */
11052 val = ssd_reg32_read(dev->ctrlp + SSD_PLP_INFO_REG);
11053 dev->hw_info_ext.plp_type = (val & 0x3);
11054 if (dev->protocol_info.ver >= SSD_PROTOCOL_V3_2) {
11055 /* 3 or 4 cap */
11056 dev->hw_info_ext.cap_type = ((val >> 2)& 0x1);
11057 }
11058
11059 /* work mode */
11060 val = ssd_reg32_read(dev->ctrlp + SSD_CH_INFO_REG);
11061 dev->hw_info_ext.work_mode = (val >> 25) & 0x1;
11062
11063out:
11064 /* skip error if not in standard mode */
11065 if (mode != SSD_DRV_MODE_STANDARD) {
11066 ret = 0;
11067 }
11068 return ret;
11069}
11070
11071static void ssd_cleanup_response(struct ssd_device *dev)
11072{
11073 int resp_msg_sz = dev->hw_info.resp_msg_sz * dev->hw_info.cmd_fifo_sz * SSD_MSIX_VEC;
11074 int resp_ptr_sz = dev->hw_info.resp_ptr_sz * SSD_MSIX_VEC;
11075
11076 pci_free_consistent(dev->pdev, resp_ptr_sz, dev->resp_ptr_base, dev->resp_ptr_base_dma);
11077 pci_free_consistent(dev->pdev, resp_msg_sz, dev->resp_msg_base, dev->resp_msg_base_dma);
11078}
11079
11080static int ssd_init_response(struct ssd_device *dev)
11081{
11082 int resp_msg_sz = dev->hw_info.resp_msg_sz * dev->hw_info.cmd_fifo_sz * SSD_MSIX_VEC;
11083 int resp_ptr_sz = dev->hw_info.resp_ptr_sz * SSD_MSIX_VEC;
11084
11085 dev->resp_msg_base = pci_alloc_consistent(dev->pdev, resp_msg_sz, &(dev->resp_msg_base_dma));
11086 if (!dev->resp_msg_base) {
11087 hio_warn("%s: unable to allocate resp msg DMA buffer\n", dev->name);
11088 goto out_alloc_resp_msg;
11089 }
11090 memset(dev->resp_msg_base, 0xFF, resp_msg_sz);
11091
11092 dev->resp_ptr_base = pci_alloc_consistent(dev->pdev, resp_ptr_sz, &(dev->resp_ptr_base_dma));
11093 if (!dev->resp_ptr_base){
11094 hio_warn("%s: unable to allocate resp ptr DMA buffer\n", dev->name);
11095 goto out_alloc_resp_ptr;
11096 }
11097 memset(dev->resp_ptr_base, 0, resp_ptr_sz);
11098 dev->resp_idx = *(uint32_t *)(dev->resp_ptr_base) = dev->hw_info.cmd_fifo_sz * 2 - 1;
11099
11100 ssd_reg_write(dev->ctrlp + SSD_RESP_FIFO_REG, dev->resp_msg_base_dma);
11101 ssd_reg_write(dev->ctrlp + SSD_RESP_PTR_REG, dev->resp_ptr_base_dma);
11102
11103 return 0;
11104
11105out_alloc_resp_ptr:
11106 pci_free_consistent(dev->pdev, resp_msg_sz, dev->resp_msg_base, dev->resp_msg_base_dma);
11107out_alloc_resp_msg:
11108 return -ENOMEM;
11109}
11110
11111static int ssd_cleanup_cmd(struct ssd_device *dev)
11112{
11113 int msg_sz = ALIGN(sizeof(struct ssd_rw_msg) + (dev->hw_info.cmd_max_sg - 1) * sizeof(struct ssd_sg_entry), SSD_DMA_ALIGN);
11114 int i;
11115
11116 for (i=0; i<(int)dev->hw_info.cmd_fifo_sz; i++) {
11117 kfree(dev->cmd[i].sgl);
11118 }
11119 kfree(dev->cmd);
11120 pci_free_consistent(dev->pdev, (msg_sz * dev->hw_info.cmd_fifo_sz), dev->msg_base, dev->msg_base_dma);
11121 return 0;
11122}
11123
11124static int ssd_init_cmd(struct ssd_device *dev)
11125{
11126 int sgl_sz = sizeof(struct scatterlist) * dev->hw_info.cmd_max_sg;
11127 int cmd_sz = sizeof(struct ssd_cmd) * dev->hw_info.cmd_fifo_sz;
11128 int msg_sz = ALIGN(sizeof(struct ssd_rw_msg) + (dev->hw_info.cmd_max_sg - 1) * sizeof(struct ssd_sg_entry), SSD_DMA_ALIGN);
11129 int i;
11130
11131 spin_lock_init(&dev->cmd_lock);
11132
11133 dev->msg_base = pci_alloc_consistent(dev->pdev, (msg_sz * dev->hw_info.cmd_fifo_sz), &dev->msg_base_dma);
11134 if (!dev->msg_base) {
11135 hio_warn("%s: can not alloc cmd msg\n", dev->name);
11136 goto out_alloc_msg;
11137 }
11138
11139 dev->cmd = kmalloc(cmd_sz, GFP_KERNEL);
11140 if (!dev->cmd) {
11141 hio_warn("%s: can not alloc cmd\n", dev->name);
11142 goto out_alloc_cmd;
11143 }
11144 memset(dev->cmd, 0, cmd_sz);
11145
11146 for (i=0; i<(int)dev->hw_info.cmd_fifo_sz; i++) {
11147 dev->cmd[i].sgl = kmalloc(sgl_sz, GFP_KERNEL);
11148 if (!dev->cmd[i].sgl) {
11149 hio_warn("%s: can not alloc cmd sgl %d\n", dev->name, i);
11150 goto out_alloc_sgl;
11151 }
11152
11153 dev->cmd[i].msg = dev->msg_base + (msg_sz * i);
11154 dev->cmd[i].msg_dma = dev->msg_base_dma + ((dma_addr_t)msg_sz * i);
11155
11156 dev->cmd[i].dev = dev;
11157 dev->cmd[i].tag = i;
11158 dev->cmd[i].flag = 0;
11159
11160 INIT_LIST_HEAD(&dev->cmd[i].list);
11161 }
11162
11163 if (dev->protocol_info.ver < SSD_PROTOCOL_V3) {
11164 dev->scmd = ssd_dispatch_cmd;
11165 } else {
11166 ssd_reg_write(dev->ctrlp + SSD_MSG_BASE_REG, dev->msg_base_dma);
11167 if (finject) {
11168 dev->scmd = ssd_send_cmd_db;
11169 } else {
11170 dev->scmd = ssd_send_cmd;
11171 }
11172 }
11173
11174 return 0;
11175
11176out_alloc_sgl:
11177 for (i--; i>=0; i--) {
11178 kfree(dev->cmd[i].sgl);
11179 }
11180 kfree(dev->cmd);
11181out_alloc_cmd:
11182 pci_free_consistent(dev->pdev, (msg_sz * dev->hw_info.cmd_fifo_sz), dev->msg_base, dev->msg_base_dma);
11183out_alloc_msg:
11184 return -ENOMEM;
11185}
11186
11187#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
11188static irqreturn_t ssd_interrupt_check(int irq, void *dev_id)
11189{
11190 struct ssd_queue *queue = (struct ssd_queue *)dev_id;
11191
11192 if (*(uint32_t *)queue->resp_ptr == queue->resp_idx) {
11193 return IRQ_NONE;
11194 }
11195
11196 return IRQ_WAKE_THREAD;
11197}
11198
11199static irqreturn_t ssd_interrupt_threaded(int irq, void *dev_id)
11200{
11201 struct ssd_queue *queue = (struct ssd_queue *)dev_id;
11202 struct ssd_device *dev = (struct ssd_device *)queue->dev;
11203 struct ssd_cmd *cmd;
11204 union ssd_response_msq __msg;
11205 union ssd_response_msq *msg = &__msg;
11206 uint64_t *u64_msg;
11207 uint32_t resp_idx = queue->resp_idx;
11208 uint32_t new_resp_idx = *(uint32_t *)queue->resp_ptr;
11209 uint32_t end_resp_idx;
11210
11211 if (unlikely(resp_idx == new_resp_idx)) {
11212 return IRQ_NONE;
11213 }
11214
11215 end_resp_idx = new_resp_idx & queue->resp_idx_mask;
11216
11217 do {
11218 resp_idx = (resp_idx + 1) & queue->resp_idx_mask;
11219
11220 /* the resp msg */
11221 u64_msg = (uint64_t *)(queue->resp_msg + queue->resp_msg_sz * resp_idx);
11222 msg->u64_msg = *u64_msg;
11223
11224 if (unlikely(msg->u64_msg == (uint64_t)(-1))) {
11225 hio_err("%s: empty resp msg: queue %d idx %u\n", dev->name, queue->idx, resp_idx);
11226 continue;
11227 }
11228 /* clear the resp msg */
11229 *u64_msg = (uint64_t)(-1);
11230
11231 cmd = &queue->cmd[msg->resp_msg.tag];
11232 /*if (unlikely(!cmd->bio)) {
11233 printk(KERN_WARNING "%s: unknown tag %d fun %#x\n",
11234 dev->name, msg->resp_msg.tag, msg->resp_msg.fun);
11235 continue;
11236 }*/
11237
11238 if(unlikely(msg->resp_msg.status & (uint32_t)status_mask)) {
11239 cmd->errors = -EIO;
11240 } else {
11241 cmd->errors = 0;
11242 }
11243 cmd->nr_log = msg->log_resp_msg.nr_log;
11244
11245 ssd_done(cmd);
11246
11247 if (unlikely(msg->resp_msg.fun != SSD_FUNC_READ_LOG && msg->resp_msg.log > 0)) {
11248 (void)test_and_set_bit(SSD_LOG_HW, &dev->state);
11249 if (test_bit(SSD_INIT_WORKQ, &dev->state)) {
11250 queue_work(dev->workq, &dev->log_work);
11251 }
11252 }
11253
11254 if (unlikely(msg->resp_msg.status)) {
11255 if (msg->resp_msg.fun == SSD_FUNC_READ || msg->resp_msg.fun == SSD_FUNC_WRITE) {
11256 hio_err("%s: I/O error %d: tag %d fun %#x\n",
11257 dev->name, msg->resp_msg.status, msg->resp_msg.tag, msg->resp_msg.fun);
11258
11259 /* alarm led */
11260 ssd_set_alarm(dev);
11261 queue->io_stat.nr_rwerr++;
11262 ssd_gen_swlog(dev, SSD_LOG_EIO, msg->u32_msg[0]);
11263 } else {
11264 hio_info("%s: CMD error %d: tag %d fun %#x\n",
11265 dev->name, msg->resp_msg.status, msg->resp_msg.tag, msg->resp_msg.fun);
11266
11267 ssd_gen_swlog(dev, SSD_LOG_ECMD, msg->u32_msg[0]);
11268 }
11269 queue->io_stat.nr_ioerr++;
11270 }
11271
11272 if (msg->resp_msg.fun == SSD_FUNC_READ ||
11273 msg->resp_msg.fun == SSD_FUNC_NAND_READ_WOOB ||
11274 msg->resp_msg.fun == SSD_FUNC_NAND_READ) {
11275
11276 queue->ecc_info.bitflip[msg->resp_msg.bitflip]++;
11277 }
11278 }while (resp_idx != end_resp_idx);
11279
11280 queue->resp_idx = new_resp_idx;
11281
11282 return IRQ_HANDLED;
11283}
11284#endif
11285
11286#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19))
11287static irqreturn_t ssd_interrupt(int irq, void *dev_id, struct pt_regs *regs)
11288#else
11289static irqreturn_t ssd_interrupt(int irq, void *dev_id)
11290#endif
11291{
11292 struct ssd_queue *queue = (struct ssd_queue *)dev_id;
11293 struct ssd_device *dev = (struct ssd_device *)queue->dev;
11294 struct ssd_cmd *cmd;
11295 union ssd_response_msq __msg;
11296 union ssd_response_msq *msg = &__msg;
11297 uint64_t *u64_msg;
11298 uint32_t resp_idx = queue->resp_idx;
11299 uint32_t new_resp_idx = *(uint32_t *)queue->resp_ptr;
11300 uint32_t end_resp_idx;
11301
11302 if (unlikely(resp_idx == new_resp_idx)) {
11303 return IRQ_NONE;
11304 }
11305
11306#if (defined SSD_ESCAPE_IRQ)
11307 if (SSD_INT_MSIX != dev->int_mode) {
11308 dev->irq_cpu = smp_processor_id();
11309 }
11310#endif
11311
11312 end_resp_idx = new_resp_idx & queue->resp_idx_mask;
11313
11314 do {
11315 resp_idx = (resp_idx + 1) & queue->resp_idx_mask;
11316
11317 /* the resp msg */
11318 u64_msg = (uint64_t *)(queue->resp_msg + queue->resp_msg_sz * resp_idx);
11319 msg->u64_msg = *u64_msg;
11320
11321 if (unlikely(msg->u64_msg == (uint64_t)(-1))) {
11322 hio_err("%s: empty resp msg: queue %d idx %u\n", dev->name, queue->idx, resp_idx);
11323 continue;
11324 }
11325 /* clear the resp msg */
11326 *u64_msg = (uint64_t)(-1);
11327
11328 cmd = &queue->cmd[msg->resp_msg.tag];
11329 /*if (unlikely(!cmd->bio)) {
11330 printk(KERN_WARNING "%s: unknown tag %d fun %#x\n",
11331 dev->name, msg->resp_msg.tag, msg->resp_msg.fun);
11332 continue;
11333 }*/
11334
11335 if(unlikely(msg->resp_msg.status & (uint32_t)status_mask)) {
11336 cmd->errors = -EIO;
11337 } else {
11338 cmd->errors = 0;
11339 }
11340 cmd->nr_log = msg->log_resp_msg.nr_log;
11341
11342 ssd_done_bh(cmd);
11343
11344 if (unlikely(msg->resp_msg.fun != SSD_FUNC_READ_LOG && msg->resp_msg.log > 0)) {
11345 (void)test_and_set_bit(SSD_LOG_HW, &dev->state);
11346 if (test_bit(SSD_INIT_WORKQ, &dev->state)) {
11347 queue_work(dev->workq, &dev->log_work);
11348 }
11349 }
11350
11351 if (unlikely(msg->resp_msg.status)) {
11352 if (msg->resp_msg.fun == SSD_FUNC_READ || msg->resp_msg.fun == SSD_FUNC_WRITE) {
11353 hio_err("%s: I/O error %d: tag %d fun %#x\n",
11354 dev->name, msg->resp_msg.status, msg->resp_msg.tag, msg->resp_msg.fun);
11355
11356 /* alarm led */
11357 ssd_set_alarm(dev);
11358 queue->io_stat.nr_rwerr++;
11359 ssd_gen_swlog(dev, SSD_LOG_EIO, msg->u32_msg[0]);
11360 } else {
11361 hio_info("%s: CMD error %d: tag %d fun %#x\n",
11362 dev->name, msg->resp_msg.status, msg->resp_msg.tag, msg->resp_msg.fun);
11363
11364 ssd_gen_swlog(dev, SSD_LOG_ECMD, msg->u32_msg[0]);
11365 }
11366 queue->io_stat.nr_ioerr++;
11367 }
11368
11369 if (msg->resp_msg.fun == SSD_FUNC_READ ||
11370 msg->resp_msg.fun == SSD_FUNC_NAND_READ_WOOB ||
11371 msg->resp_msg.fun == SSD_FUNC_NAND_READ) {
11372
11373 queue->ecc_info.bitflip[msg->resp_msg.bitflip]++;
11374 }
11375 }while (resp_idx != end_resp_idx);
11376
11377 queue->resp_idx = new_resp_idx;
11378
11379 return IRQ_HANDLED;
11380}
11381
11382#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19))
11383static irqreturn_t ssd_interrupt_legacy(int irq, void *dev_id, struct pt_regs *regs)
11384#else
11385static irqreturn_t ssd_interrupt_legacy(int irq, void *dev_id)
11386#endif
11387{
11388 irqreturn_t ret;
11389 struct ssd_queue *queue = (struct ssd_queue *)dev_id;
11390 struct ssd_device *dev = (struct ssd_device *)queue->dev;
11391
11392#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19))
11393 ret = ssd_interrupt(irq, dev_id, regs);
11394#else
11395 ret = ssd_interrupt(irq, dev_id);
11396#endif
11397
11398 /* clear intr */
11399 if (IRQ_HANDLED == ret) {
11400 ssd_reg32_write(dev->ctrlp + SSD_CLEAR_INTR_REG, 1);
11401 }
11402
11403 return ret;
11404}
11405
11406static void ssd_reset_resp_ptr(struct ssd_device *dev)
11407{
11408 int i;
11409
11410 for (i=0; i<dev->nr_queue; i++) {
11411 *(uint32_t *)dev->queue[i].resp_ptr = dev->queue[i].resp_idx = (dev->hw_info.cmd_fifo_sz * 2) - 1;
11412 }
11413}
11414
11415static void ssd_free_irq(struct ssd_device *dev)
11416{
11417 int i;
11418
11419#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6))
11420 if (SSD_INT_MSIX == dev->int_mode) {
11421 for (i=0; i<dev->nr_queue; i++) {
11422 irq_set_affinity_hint(dev->entry[i].vector, NULL);
11423 }
11424 }
11425#endif
11426
11427 for (i=0; i<dev->nr_queue; i++) {
11428 free_irq(dev->entry[i].vector, &dev->queue[i]);
11429 }
11430
11431 if (SSD_INT_MSIX == dev->int_mode) {
11432 pci_disable_msix(dev->pdev);
11433 } else if (SSD_INT_MSI == dev->int_mode) {
11434 pci_disable_msi(dev->pdev);
11435 }
11436
11437}
11438
11439static int ssd_init_irq(struct ssd_device *dev)
11440{
11441#if (!defined MODULE) && (defined SSD_MSIX_AFFINITY_FORCE)
a9d1e0c7 11442 const struct cpumask *cpu_mask = NULL;
a6a796ca
HSDT
11443 static int cpu_affinity = 0;
11444#endif
11445#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6))
376d62f7 11446 const struct cpumask *mask = NULL;
a6a796ca
HSDT
11447 static int cpu = 0;
11448 int j;
11449#endif
11450 int i;
11451 unsigned long flags = 0;
11452 int ret = 0;
11453
11454 ssd_reg32_write(dev->ctrlp + SSD_INTR_INTERVAL_REG, 0x800);
11455
11456#ifdef SSD_ESCAPE_IRQ
11457 dev->irq_cpu = -1;
11458#endif
11459
11460 if (int_mode >= SSD_INT_MSIX && pci_find_capability(dev->pdev, PCI_CAP_ID_MSIX)) {
11461 dev->nr_queue = SSD_MSIX_VEC;
11462 for (i=0; i<dev->nr_queue; i++) {
11463 dev->entry[i].entry = i;
11464 }
11465 for (;;) {
11466 ret = pci_enable_msix(dev->pdev, dev->entry, dev->nr_queue);
11467 if (ret == 0) {
11468 break;
11469 } else if (ret > 0) {
11470 dev->nr_queue = ret;
11471 } else {
11472 hio_warn("%s: can not enable msix\n", dev->name);
11473 /* alarm led */
11474 ssd_set_alarm(dev);
11475 goto out;
11476 }
11477 }
11478
11479#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6))
11480 mask = (dev_to_node(&dev->pdev->dev) == -1) ? cpu_online_mask : cpumask_of_node(dev_to_node(&dev->pdev->dev));
11481 if ((0 == cpu) || (!cpumask_intersects(mask, cpumask_of(cpu)))) {
11482 cpu = cpumask_first(mask);
11483 }
11484 for (i=0; i<dev->nr_queue; i++) {
11485 irq_set_affinity_hint(dev->entry[i].vector, cpumask_of(cpu));
11486 cpu = cpumask_next(cpu, mask);
11487 if (cpu >= nr_cpu_ids) {
11488 cpu = cpumask_first(mask);
11489 }
11490 }
11491#endif
11492
11493 dev->int_mode = SSD_INT_MSIX;
11494 } else if (int_mode >= SSD_INT_MSI && pci_find_capability(dev->pdev, PCI_CAP_ID_MSI)) {
11495 ret = pci_enable_msi(dev->pdev);
11496 if (ret) {
11497 hio_warn("%s: can not enable msi\n", dev->name);
11498 /* alarm led */
11499 ssd_set_alarm(dev);
11500 goto out;
11501 }
11502
11503 dev->nr_queue = 1;
11504 dev->entry[0].vector = dev->pdev->irq;
11505
11506 dev->int_mode = SSD_INT_MSI;
11507 } else {
11508 dev->nr_queue = 1;
11509 dev->entry[0].vector = dev->pdev->irq;
11510
11511 dev->int_mode = SSD_INT_LEGACY;
11512 }
11513
11514 for (i=0; i<dev->nr_queue; i++) {
11515 if (dev->nr_queue > 1) {
11516 snprintf(dev->queue[i].name, SSD_QUEUE_NAME_LEN, "%s_e100-%d", dev->name, i);
11517 } else {
11518 snprintf(dev->queue[i].name, SSD_QUEUE_NAME_LEN, "%s_e100", dev->name);
11519 }
11520
11521 dev->queue[i].dev = dev;
11522 dev->queue[i].idx = i;
11523
11524 dev->queue[i].resp_idx = (dev->hw_info.cmd_fifo_sz * 2) - 1;
11525 dev->queue[i].resp_idx_mask = dev->hw_info.cmd_fifo_sz - 1;
11526
11527 dev->queue[i].resp_msg_sz = dev->hw_info.resp_msg_sz;
11528 dev->queue[i].resp_msg = dev->resp_msg_base + dev->hw_info.resp_msg_sz * dev->hw_info.cmd_fifo_sz * i;
11529 dev->queue[i].resp_ptr = dev->resp_ptr_base + dev->hw_info.resp_ptr_sz * i;
11530 *(uint32_t *)dev->queue[i].resp_ptr = dev->queue[i].resp_idx;
11531
11532 dev->queue[i].cmd = dev->cmd;
11533 }
11534
11535#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
11536 flags = IRQF_SHARED;
11537#else
11538 flags = SA_SHIRQ;
11539#endif
11540
11541 for (i=0; i<dev->nr_queue; i++) {
11542#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,30))
11543 if (threaded_irq) {
11544 ret = request_threaded_irq(dev->entry[i].vector, ssd_interrupt_check, ssd_interrupt_threaded, flags, dev->queue[i].name, &dev->queue[i]);
11545 } else if (dev->int_mode == SSD_INT_LEGACY) {
11546 ret = request_irq(dev->entry[i].vector, &ssd_interrupt_legacy, flags, dev->queue[i].name, &dev->queue[i]);
11547 } else {
11548 ret = request_irq(dev->entry[i].vector, &ssd_interrupt, flags, dev->queue[i].name, &dev->queue[i]);
11549 }
11550#else
11551 if (dev->int_mode == SSD_INT_LEGACY) {
11552 ret = request_irq(dev->entry[i].vector, &ssd_interrupt_legacy, flags, dev->queue[i].name, &dev->queue[i]);
11553 } else {
11554 ret = request_irq(dev->entry[i].vector, &ssd_interrupt, flags, dev->queue[i].name, &dev->queue[i]);
11555 }
11556#endif
11557 if (ret) {
11558 hio_warn("%s: request irq failed\n", dev->name);
11559 /* alarm led */
11560 ssd_set_alarm(dev);
11561 goto out_request_irq;
11562 }
11563
11564#if (!defined MODULE) && (defined SSD_MSIX_AFFINITY_FORCE)
11565 cpu_mask = (dev_to_node(&dev->pdev->dev) == -1) ? cpu_online_mask : cpumask_of_node(dev_to_node(&dev->pdev->dev));
11566 if (SSD_INT_MSIX == dev->int_mode) {
11567 if ((0 == cpu_affinity) || (!cpumask_intersects(mask, cpumask_of(cpu_affinity)))) {
11568 cpu_affinity = cpumask_first(cpu_mask);
11569 }
11570
11571 irq_set_affinity(dev->entry[i].vector, cpumask_of(cpu_affinity));
11572 cpu_affinity = cpumask_next(cpu_affinity, cpu_mask);
11573 if (cpu_affinity >= nr_cpu_ids) {
11574 cpu_affinity = cpumask_first(cpu_mask);
11575 }
11576 }
11577#endif
11578 }
11579
11580 return ret;
11581
11582out_request_irq:
11583#if ((LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,35)) || (defined RHEL_MAJOR && RHEL_MAJOR == 6))
11584 if (SSD_INT_MSIX == dev->int_mode) {
11585 for (j=0; j<dev->nr_queue; j++) {
11586 irq_set_affinity_hint(dev->entry[j].vector, NULL);
11587 }
11588 }
11589#endif
11590
11591 for (i--; i>=0; i--) {
11592 free_irq(dev->entry[i].vector, &dev->queue[i]);
11593 }
11594
11595 if (SSD_INT_MSIX == dev->int_mode) {
11596 pci_disable_msix(dev->pdev);
11597 } else if (SSD_INT_MSI == dev->int_mode) {
11598 pci_disable_msi(dev->pdev);
11599 }
11600
11601out:
11602 return ret;
11603}
11604
11605static void ssd_initial_log(struct ssd_device *dev)
11606{
11607 uint32_t val;
11608 uint32_t speed, width;
11609
11610 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
11611 return;
11612 }
11613
11614 val = ssd_reg32_read(dev->ctrlp + SSD_POWER_ON_REG);
11615 if (val) {
11616 ssd_gen_swlog(dev, SSD_LOG_POWER_ON, dev->hw_info.bridge_ver);
11617 }
11618
11619 val = ssd_reg32_read(dev->ctrlp + SSD_PCIE_LINKSTATUS_REG);
11620 speed = val & 0xF;
11621 width = (val >> 4)& 0x3F;
11622 if (0x1 == speed) {
11623 hio_info("%s: PCIe: 2.5GT/s, x%u\n", dev->name, width);
11624 } else if (0x2 == speed) {
11625 hio_info("%s: PCIe: 5GT/s, x%u\n", dev->name, width);
11626 } else {
11627 hio_info("%s: PCIe: unknown GT/s, x%u\n", dev->name, width);
11628 }
11629 ssd_gen_swlog(dev, SSD_LOG_PCIE_LINK_STATUS, val);
11630
11631 return;
11632}
11633
11634#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20))
11635static void ssd_hwmon_worker(void *data)
11636{
11637 struct ssd_device *dev = (struct ssd_device *)data;
11638#else
11639static void ssd_hwmon_worker(struct work_struct *work)
11640{
11641 struct ssd_device *dev = container_of(work, struct ssd_device, hwmon_work);
11642#endif
11643
11644 if (ssd_check_hw(dev)) {
11645 //hio_err("%s: check hardware failed\n", dev->name);
11646 return;
11647 }
11648
11649 ssd_check_clock(dev);
11650 ssd_check_volt(dev);
11651
11652 ssd_mon_boardvolt(dev);
11653}
11654
11655#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20))
11656static void ssd_tempmon_worker(void *data)
11657{
11658 struct ssd_device *dev = (struct ssd_device *)data;
11659#else
11660static void ssd_tempmon_worker(struct work_struct *work)
11661{
11662 struct ssd_device *dev = container_of(work, struct ssd_device, tempmon_work);
11663#endif
11664
11665 if (ssd_check_hw(dev)) {
11666 //hio_err("%s: check hardware failed\n", dev->name);
11667 return;
11668 }
11669
11670 ssd_mon_temp(dev);
11671}
11672
11673
11674#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20))
11675static void ssd_capmon_worker(void *data)
11676{
11677 struct ssd_device *dev = (struct ssd_device *)data;
11678#else
11679static void ssd_capmon_worker(struct work_struct *work)
11680{
11681 struct ssd_device *dev = container_of(work, struct ssd_device, capmon_work);
11682#endif
11683 uint32_t cap = 0;
11684 uint32_t cap_threshold = SSD_PL_CAP_THRESHOLD;
11685 int ret = 0;
11686
11687 if (dev->protocol_info.ver < SSD_PROTOCOL_V3_2) {
11688 return;
11689 }
11690
11691 if (dev->hw_info_ext.form_factor == SSD_FORM_FACTOR_FHHL && dev->hw_info.pcb_ver < 'B') {
11692 return;
11693 }
11694
11695 /* fault before? */
11696 if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) {
11697 ret = ssd_check_pl_cap_fast(dev);
11698 if (ret) {
11699 return;
11700 }
11701 }
11702
11703 /* learn */
11704 ret = ssd_do_cap_learn(dev, &cap);
11705 if (ret) {
11706 hio_err("%s: cap learn failed\n", dev->name);
11707 ssd_gen_swlog(dev, SSD_LOG_CAP_LEARN_FAULT, 0);
11708 return;
11709 }
11710
11711 ssd_gen_swlog(dev, SSD_LOG_CAP_STATUS, cap);
11712
11713 if (SSD_PL_CAP_CP == dev->hw_info_ext.cap_type) {
11714 cap_threshold = SSD_PL_CAP_CP_THRESHOLD;
11715 }
11716
11717 //use the fw event id?
11718 if (cap < cap_threshold) {
11719 if (!test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) {
11720 ssd_gen_swlog(dev, SSD_LOG_BATTERY_FAULT, 0);
11721 }
11722 } else if (cap >= (cap_threshold + SSD_PL_CAP_THRESHOLD_HYST)) {
11723 if (test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon)) {
11724 ssd_gen_swlog(dev, SSD_LOG_BATTERY_OK, 0);
11725 }
11726 }
11727}
11728
11729static void ssd_routine_start(void *data)
11730{
11731 struct ssd_device *dev;
11732
11733 if (!data) {
11734 return;
11735 }
11736 dev = data;
11737
11738 dev->routine_tick++;
11739
11740 if (test_bit(SSD_INIT_WORKQ, &dev->state) && !ssd_busy(dev)) {
11741 (void)test_and_set_bit(SSD_LOG_HW, &dev->state);
11742 queue_work(dev->workq, &dev->log_work);
11743 }
11744
11745 if ((dev->routine_tick % SSD_HWMON_ROUTINE_TICK) == 0 && test_bit(SSD_INIT_WORKQ, &dev->state)) {
11746 queue_work(dev->workq, &dev->hwmon_work);
11747 }
11748
11749 if ((dev->routine_tick % SSD_CAPMON_ROUTINE_TICK) == 0 && test_bit(SSD_INIT_WORKQ, &dev->state)) {
11750 queue_work(dev->workq, &dev->capmon_work);
11751 }
11752
11753 if ((dev->routine_tick % SSD_CAPMON2_ROUTINE_TICK) == 0 && test_bit(SSD_HWMON_PL_CAP(SSD_PL_CAP), &dev->hwmon) && test_bit(SSD_INIT_WORKQ, &dev->state)) {
11754 /* CAP fault? check again */
11755 queue_work(dev->workq, &dev->capmon_work);
11756 }
11757
11758 if (test_bit(SSD_INIT_WORKQ, &dev->state)) {
11759 queue_work(dev->workq, &dev->tempmon_work);
11760 }
11761
11762 /* schedule routine */
11763 mod_timer(&dev->routine_timer, jiffies + msecs_to_jiffies(SSD_ROUTINE_INTERVAL));
11764}
11765
11766static void ssd_cleanup_routine(struct ssd_device *dev)
11767{
11768 if (unlikely(mode != SSD_DRV_MODE_STANDARD))
11769 return;
11770
11771 (void)ssd_del_timer(&dev->routine_timer);
11772
11773 (void)ssd_del_timer(&dev->bm_timer);
11774}
11775
11776static int ssd_init_routine(struct ssd_device *dev)
11777{
11778 if (unlikely(mode != SSD_DRV_MODE_STANDARD))
11779 return 0;
11780
11781#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20))
11782 INIT_WORK(&dev->bm_work, ssd_bm_worker, dev);
11783 INIT_WORK(&dev->hwmon_work, ssd_hwmon_worker, dev);
11784 INIT_WORK(&dev->capmon_work, ssd_capmon_worker, dev);
11785 INIT_WORK(&dev->tempmon_work, ssd_tempmon_worker, dev);
11786#else
11787 INIT_WORK(&dev->bm_work, ssd_bm_worker);
11788 INIT_WORK(&dev->hwmon_work, ssd_hwmon_worker);
11789 INIT_WORK(&dev->capmon_work, ssd_capmon_worker);
11790 INIT_WORK(&dev->tempmon_work, ssd_tempmon_worker);
11791#endif
11792
11793 /* initial log */
11794 ssd_initial_log(dev);
11795
11796 /* schedule bm routine */
11797 ssd_add_timer(&dev->bm_timer, msecs_to_jiffies(SSD_BM_CAP_LEARNING_DELAY), ssd_bm_routine_start, dev);
11798
11799 /* schedule routine */
11800 ssd_add_timer(&dev->routine_timer, msecs_to_jiffies(SSD_ROUTINE_INTERVAL), ssd_routine_start, dev);
11801
11802 return 0;
11803}
11804
11805static void
11806#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38))
11807__devexit
11808#endif
11809ssd_remove_one (struct pci_dev *pdev)
11810{
11811 struct ssd_device *dev;
11812
11813 if (!pdev) {
11814 return;
11815 }
11816
11817 dev = pci_get_drvdata(pdev);
11818 if (!dev) {
11819 return;
11820 }
11821
11822 list_del_init(&dev->list);
11823
11824 ssd_unregister_sysfs(dev);
11825
11826 /* offline firstly */
11827 test_and_clear_bit(SSD_ONLINE, &dev->state);
11828
11829 /* clean work queue first */
11830 if (!dev->slave) {
11831 test_and_clear_bit(SSD_INIT_WORKQ, &dev->state);
11832 ssd_cleanup_workq(dev);
11833 }
11834
11835 /* flush cache */
11836 (void)ssd_flush(dev);
11837 (void)ssd_save_md(dev);
11838
11839 /* save smart */
11840 if (!dev->slave) {
11841 ssd_save_smart(dev);
11842 }
11843
11844 if (test_and_clear_bit(SSD_INIT_BD, &dev->state)) {
11845 ssd_cleanup_blkdev(dev);
11846 }
11847
11848 if (!dev->slave) {
11849 ssd_cleanup_chardev(dev);
11850 }
11851
11852 /* clean routine */
11853 if (!dev->slave) {
11854 ssd_cleanup_routine(dev);
11855 }
11856
11857 ssd_cleanup_queue(dev);
11858
11859 ssd_cleanup_tag(dev);
11860 ssd_cleanup_thread(dev);
11861
11862 ssd_free_irq(dev);
11863
11864 ssd_cleanup_dcmd(dev);
11865 ssd_cleanup_cmd(dev);
11866 ssd_cleanup_response(dev);
11867
11868 if (!dev->slave) {
11869 ssd_cleanup_log(dev);
11870 }
11871
11872 if (dev->reload_fw) { //reload fw
11873 ssd_reg32_write(dev->ctrlp + SSD_RELOAD_FW_REG, SSD_RELOAD_FW);
11874 }
11875
11876 /* unmap physical adress */
11877#ifdef LINUX_SUSE_OS
11878 iounmap(dev->ctrlp);
11879#else
11880 pci_iounmap(pdev, dev->ctrlp);
11881#endif
11882
11883 release_mem_region(dev->mmio_base, dev->mmio_len);
11884
11885 pci_disable_device(pdev);
11886
11887 pci_set_drvdata(pdev, NULL);
11888
11889 ssd_put(dev);
11890}
11891
11892static int
11893#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38))
11894__devinit
11895#endif
11896ssd_init_one(struct pci_dev *pdev,
11897 const struct pci_device_id *ent)
11898{
11899 struct ssd_device *dev;
a9d1e0c7 11900 struct timeval tv;
a6a796ca
HSDT
11901 int ret = 0;
11902
11903 if (!pdev || !ent) {
11904 ret = -EINVAL;
11905 goto out;
11906 }
11907
11908 dev = kmalloc(sizeof(struct ssd_device), GFP_KERNEL);
11909 if (!dev) {
11910 ret = -ENOMEM;
11911 goto out_alloc_dev;
11912 }
11913 memset(dev, 0, sizeof(struct ssd_device));
11914
11915 dev->owner = THIS_MODULE;
11916
11917 if (SSD_SLAVE_PORT_DEVID == ent->device) {
11918 dev->slave = 1;
11919 }
11920
11921 dev->idx = ssd_get_index(dev->slave);
11922 if (dev->idx < 0) {
11923 ret = -ENOMEM;
11924 goto out_get_index;
11925 }
11926
11927 if (!dev->slave) {
11928 snprintf(dev->name, SSD_DEV_NAME_LEN, SSD_DEV_NAME);
11929 ssd_set_dev_name(&dev->name[strlen(SSD_DEV_NAME)], SSD_DEV_NAME_LEN-strlen(SSD_DEV_NAME), dev->idx);
11930
11931 dev->major = ssd_major;
11932 dev->cmajor = ssd_cmajor;
11933 } else {
11934 snprintf(dev->name, SSD_DEV_NAME_LEN, SSD_SDEV_NAME);
11935 ssd_set_dev_name(&dev->name[strlen(SSD_SDEV_NAME)], SSD_DEV_NAME_LEN-strlen(SSD_SDEV_NAME), dev->idx);
11936 dev->major = ssd_major_sl;
11937 dev->cmajor = 0;
11938 }
11939
a9d1e0c7
KM
11940 do_gettimeofday(&tv);
11941 dev->reset_time = tv.tv_sec;
11942
a6a796ca
HSDT
11943 atomic_set(&(dev->refcnt), 0);
11944 atomic_set(&(dev->tocnt), 0);
11945
11946 mutex_init(&dev->fw_mutex);
11947
11948 //xx
11949 mutex_init(&dev->gd_mutex);
11950
11951 dev->pdev = pdev;
11952 pci_set_drvdata(pdev, dev);
11953
11954 kref_init(&dev->kref);
11955
11956 ret = pci_enable_device(pdev);
11957 if (ret) {
11958 hio_warn("%s: can not enable device\n", dev->name);
11959 goto out_enable_device;
11960 }
11961
11962 pci_set_master(pdev);
11963
11964#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31))
11965 ret = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
11966#else
11967 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
11968#endif
11969 if (ret) {
11970 hio_warn("%s: set dma mask: failed\n", dev->name);
11971 goto out_set_dma_mask;
11972 }
11973
11974#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31))
11975 ret = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
11976#else
11977 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
11978#endif
11979 if (ret) {
11980 hio_warn("%s: set consistent dma mask: failed\n", dev->name);
11981 goto out_set_dma_mask;
11982 }
11983
11984 dev->mmio_base = pci_resource_start(pdev, 0);
11985 dev->mmio_len = pci_resource_len(pdev, 0);
11986
11987 if (!request_mem_region(dev->mmio_base, dev->mmio_len, SSD_DEV_NAME)) {
11988 hio_warn("%s: can not reserve MMIO region 0\n", dev->name);
11989 ret = -EBUSY;
11990 goto out_request_mem_region;
11991 }
11992
11993 /* 2.6.9 kernel bug */
11994 dev->ctrlp = pci_iomap(pdev, 0, 0);
11995 if (!dev->ctrlp) {
11996 hio_warn("%s: can not remap IO region 0\n", dev->name);
11997 ret = -ENOMEM;
11998 goto out_pci_iomap;
11999 }
12000
12001 ret = ssd_check_hw(dev);
12002 if (ret) {
12003 hio_err("%s: check hardware failed\n", dev->name);
12004 goto out_check_hw;
12005 }
12006
12007 ret = ssd_init_protocol_info(dev);
12008 if (ret) {
12009 hio_err("%s: init protocol info failed\n", dev->name);
12010 goto out_init_protocol_info;
12011 }
12012
12013 /* alarm led ? */
12014 ssd_clear_alarm(dev);
12015
12016 ret = ssd_init_fw_info(dev);
12017 if (ret) {
12018 hio_err("%s: init firmware info failed\n", dev->name);
12019 /* alarm led */
12020 ssd_set_alarm(dev);
12021 goto out_init_fw_info;
12022 }
12023
12024 /* slave port ? */
12025 if (dev->slave) {
12026 goto init_next1;
12027 }
12028
12029 ret = ssd_init_rom_info(dev);
12030 if (ret) {
12031 hio_err("%s: init rom info failed\n", dev->name);
12032 /* alarm led */
12033 ssd_set_alarm(dev);
12034 goto out_init_rom_info;
12035 }
12036
12037 ret = ssd_init_label(dev);
12038 if (ret) {
12039 hio_err("%s: init label failed\n", dev->name);
12040 /* alarm led */
12041 ssd_set_alarm(dev);
12042 goto out_init_label;
12043 }
12044
12045 ret = ssd_init_workq(dev);
12046 if (ret) {
12047 hio_warn("%s: init workq failed\n", dev->name);
12048 goto out_init_workq;
12049 }
12050 (void)test_and_set_bit(SSD_INIT_WORKQ, &dev->state);
12051
12052 ret = ssd_init_log(dev);
12053 if (ret) {
12054 hio_err("%s: init log failed\n", dev->name);
12055 /* alarm led */
12056 ssd_set_alarm(dev);
12057 goto out_init_log;
12058 }
12059
12060 ret = ssd_init_smart(dev);
12061 if (ret) {
12062 hio_err("%s: init info failed\n", dev->name);
12063 /* alarm led */
12064 ssd_set_alarm(dev);
12065 goto out_init_smart;
12066 }
12067
12068init_next1:
12069 ret = ssd_init_hw_info(dev);
12070 if (ret) {
12071 hio_err("%s: init hardware info failed\n", dev->name);
12072 /* alarm led */
12073 ssd_set_alarm(dev);
12074 goto out_init_hw_info;
12075 }
12076
12077 /* slave port ? */
12078 if (dev->slave) {
12079 goto init_next2;
12080 }
12081
12082 ret = ssd_init_sensor(dev);
12083 if (ret) {
12084 hio_err("%s: init sensor failed\n", dev->name);
12085 /* alarm led */
12086 ssd_set_alarm(dev);
12087 goto out_init_sensor;
12088 }
12089
12090 ret = ssd_init_pl_cap(dev);
12091 if (ret) {
12092 hio_err("%s: int pl_cap failed\n", dev->name);
12093 /* alarm led */
12094 ssd_set_alarm(dev);
12095 goto out_init_pl_cap;
12096 }
12097
12098init_next2:
12099 ret = ssd_check_init_state(dev);
12100 if (ret) {
12101 hio_err("%s: check init state failed\n", dev->name);
12102 /* alarm led */
12103 ssd_set_alarm(dev);
12104 goto out_check_init_state;
12105 }
12106
12107 ret = ssd_init_response(dev);
12108 if (ret) {
12109 hio_warn("%s: init resp_msg failed\n", dev->name);
12110 goto out_init_response;
12111 }
12112
12113 ret = ssd_init_cmd(dev);
12114 if (ret) {
12115 hio_warn("%s: init msg failed\n", dev->name);
12116 goto out_init_cmd;
12117 }
12118
12119 ret = ssd_init_dcmd(dev);
12120 if (ret) {
12121 hio_warn("%s: init cmd failed\n", dev->name);
12122 goto out_init_dcmd;
12123 }
12124
12125 ret = ssd_init_irq(dev);
12126 if (ret) {
12127 hio_warn("%s: init irq failed\n", dev->name);
12128 goto out_init_irq;
12129 }
12130
12131 ret = ssd_init_thread(dev);
12132 if (ret) {
12133 hio_warn("%s: init thread failed\n", dev->name);
12134 goto out_init_thread;
12135 }
12136
12137 ret = ssd_init_tag(dev);
12138 if(ret) {
12139 hio_warn("%s: init tags failed\n", dev->name);
12140 goto out_init_tags;
12141 }
12142
12143 /* */
12144 (void)test_and_set_bit(SSD_ONLINE, &dev->state);
12145
12146 ret = ssd_init_queue(dev);
12147 if (ret) {
12148 hio_warn("%s: init queue failed\n", dev->name);
12149 goto out_init_queue;
12150 }
12151
12152 /* slave port ? */
12153 if (dev->slave) {
12154 goto init_next3;
12155 }
12156
12157 ret = ssd_init_ot_protect(dev);
12158 if (ret) {
12159 hio_err("%s: int ot_protect failed\n", dev->name);
12160 /* alarm led */
12161 ssd_set_alarm(dev);
12162 goto out_int_ot_protect;
12163 }
12164
12165 ret = ssd_init_wmode(dev);
12166 if (ret) {
12167 hio_warn("%s: init write mode\n", dev->name);
12168 goto out_init_wmode;
12169 }
12170
12171 /* init routine after hw is ready */
12172 ret = ssd_init_routine(dev);
12173 if (ret) {
12174 hio_warn("%s: init routine\n", dev->name);
12175 goto out_init_routine;
12176 }
12177
12178 ret = ssd_init_chardev(dev);
12179 if (ret) {
12180 hio_warn("%s: register char device failed\n", dev->name);
12181 goto out_init_chardev;
12182 }
12183
12184init_next3:
12185 ret = ssd_init_blkdev(dev);
12186 if (ret) {
12187 hio_warn("%s: register block device failed\n", dev->name);
12188 goto out_init_blkdev;
12189 }
12190 (void)test_and_set_bit(SSD_INIT_BD, &dev->state);
12191
12192 ret = ssd_register_sysfs(dev);
12193 if (ret) {
12194 hio_warn("%s: register sysfs failed\n", dev->name);
12195 goto out_register_sysfs;
12196 }
12197
12198 dev->save_md = 1;
12199
12200 list_add_tail(&dev->list, &ssd_list);
12201
12202 return 0;
12203
12204out_register_sysfs:
12205 test_and_clear_bit(SSD_INIT_BD, &dev->state);
12206 ssd_cleanup_blkdev(dev);
12207out_init_blkdev:
12208 /* slave port ? */
12209 if (!dev->slave) {
12210 ssd_cleanup_chardev(dev);
12211 }
12212out_init_chardev:
12213 /* slave port ? */
12214 if (!dev->slave) {
12215 ssd_cleanup_routine(dev);
12216 }
12217out_init_routine:
12218out_init_wmode:
12219out_int_ot_protect:
12220 ssd_cleanup_queue(dev);
12221out_init_queue:
12222 test_and_clear_bit(SSD_ONLINE, &dev->state);
12223 ssd_cleanup_tag(dev);
12224out_init_tags:
12225 ssd_cleanup_thread(dev);
12226out_init_thread:
12227 ssd_free_irq(dev);
12228out_init_irq:
12229 ssd_cleanup_dcmd(dev);
12230out_init_dcmd:
12231 ssd_cleanup_cmd(dev);
12232out_init_cmd:
12233 ssd_cleanup_response(dev);
12234out_init_response:
12235out_check_init_state:
12236out_init_pl_cap:
12237out_init_sensor:
12238out_init_hw_info:
12239out_init_smart:
12240 /* slave port ? */
12241 if (!dev->slave) {
12242 ssd_cleanup_log(dev);
12243 }
12244out_init_log:
12245 /* slave port ? */
12246 if (!dev->slave) {
12247 test_and_clear_bit(SSD_INIT_WORKQ, &dev->state);
12248 ssd_cleanup_workq(dev);
12249 }
12250out_init_workq:
12251out_init_label:
12252out_init_rom_info:
12253out_init_fw_info:
12254out_init_protocol_info:
12255out_check_hw:
12256#ifdef LINUX_SUSE_OS
12257 iounmap(dev->ctrlp);
12258#else
12259 pci_iounmap(pdev, dev->ctrlp);
12260#endif
12261out_pci_iomap:
12262 release_mem_region(dev->mmio_base, dev->mmio_len);
12263out_request_mem_region:
12264out_set_dma_mask:
12265 pci_disable_device(pdev);
12266out_enable_device:
12267 pci_set_drvdata(pdev, NULL);
12268out_get_index:
12269 kfree(dev);
12270out_alloc_dev:
12271out:
12272 return ret;
12273}
12274
12275static void ssd_cleanup_tasklet(void)
12276{
12277 int i;
12278 for_each_online_cpu(i) {
12279 tasklet_kill(&per_cpu(ssd_tasklet, i));
12280 }
12281}
12282
12283static int ssd_init_tasklet(void)
12284{
12285 int i;
12286
12287 for_each_online_cpu(i) {
12288 INIT_LIST_HEAD(&per_cpu(ssd_doneq, i));
12289
12290 if (finject) {
12291 tasklet_init(&per_cpu(ssd_tasklet, i), __ssd_done_db, 0);
12292 } else {
12293 tasklet_init(&per_cpu(ssd_tasklet, i), __ssd_done, 0);
12294 }
12295 }
12296
12297 return 0;
12298}
12299
12300static struct pci_device_id ssd_pci_tbl[] = {
12301 { 0x10ee, 0x0007, PCI_ANY_ID, PCI_ANY_ID, }, /* g3 */
12302 { 0x19e5, 0x0007, PCI_ANY_ID, PCI_ANY_ID, }, /* v1 */
12303 //{ 0x19e5, 0x0008, PCI_ANY_ID, PCI_ANY_ID, }, /* v1 sp*/
12304 { 0x19e5, 0x0009, PCI_ANY_ID, PCI_ANY_ID, }, /* v2 */
12305 { 0x19e5, 0x000a, PCI_ANY_ID, PCI_ANY_ID, }, /* v2 dp slave*/
12306 { 0, }
12307};
a6a796ca 12308
a9d1e0c7
KM
12309/*driver power management handler for pm_ops*/
12310#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32))
12311static int ssd_hio_suspend(struct pci_dev *pdev, pm_message_t state)
12312{
12313#else
12314static int ssd_hio_suspend(struct device *ddev)
12315{
12316 struct pci_dev *pdev = to_pci_dev(ddev);
12317#endif
12318 struct ssd_device *dev;
12319
12320
12321 if (!pdev) {
12322 return -EINVAL;
12323 }
12324
12325 dev = pci_get_drvdata(pdev);
12326 if (!dev) {
12327 return -EINVAL;
12328 }
12329
12330 hio_warn("%s: suspend disk start.\n", dev->name);
12331 ssd_unregister_sysfs(dev);
12332
12333 /* offline firstly */
12334 test_and_clear_bit(SSD_ONLINE, &dev->state);
12335
12336 /* clean work queue first */
12337 if (!dev->slave) {
12338 test_and_clear_bit(SSD_INIT_WORKQ, &dev->state);
12339 ssd_cleanup_workq(dev);
12340 }
12341
12342 /* flush cache */
12343 (void)ssd_flush(dev);
12344 (void)ssd_save_md(dev);
12345
12346 /* save smart */
12347 if (!dev->slave) {
12348 ssd_save_smart(dev);
12349 }
12350
12351 /* clean routine */
12352 if (!dev->slave) {
12353 ssd_cleanup_routine(dev);
12354 }
12355
12356 ssd_cleanup_thread(dev);
12357
12358 ssd_free_irq(dev);
12359
12360 if (!dev->slave) {
12361 ssd_cleanup_log(dev);
12362 }
12363
12364 if (dev->reload_fw) { //reload fw
12365 ssd_reg32_write(dev->ctrlp + SSD_RELOAD_FW_REG, SSD_RELOAD_FW);
12366 }
12367
12368 /* unmap physical adress */
12369 if (dev->ctrlp) {
12370#ifdef LINUX_SUSE_OS
12371 iounmap(dev->ctrlp);
12372#else
12373 pci_iounmap(pdev, dev->ctrlp);
12374#endif
12375 dev->ctrlp = NULL;
12376 }
12377
12378 if (dev->mmio_base) {
12379 release_mem_region(dev->mmio_base, dev->mmio_len);
12380 dev->mmio_base = 0;
12381 }
12382
12383 pci_disable_device(pdev);
12384
12385 hio_warn("%s: suspend disk finish.\n", dev->name);
12386
12387 return 0;
12388}
12389
12390
12391#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32))
12392static int ssd_hio_resume(struct pci_dev *pdev)
12393{
12394#else
12395static int ssd_hio_resume(struct device *ddev)
12396{
12397 struct pci_dev *pdev = to_pci_dev(ddev);
12398#endif
12399 struct ssd_device *dev = NULL;
12400 int ret = 0;
12401
12402 if (!pdev ) {
12403 ret = -EINVAL;
12404 goto out;
12405 }
12406
12407 dev = pci_get_drvdata(pdev);
12408 if (!dev) {
12409 ret = -ENOMEM;
12410 goto out_alloc_dev;
12411 }
12412
12413 hio_warn("%s: resume disk start.\n", dev->name);
12414 ret = pci_enable_device(pdev);
12415 if (ret) {
12416 hio_warn("%s: can not enable device\n", dev->name);
12417 goto out_enable_device;
12418 }
12419
12420 pci_set_master(pdev);
12421
12422#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31))
12423 ret = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
12424#else
12425 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
12426#endif
12427 if (ret) {
12428 hio_warn("%s: set dma mask: failed\n", dev->name);
12429 goto out_set_dma_mask;
12430 }
12431
12432#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,31))
12433 ret = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
12434#else
12435 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
12436#endif
12437 if (ret) {
12438 hio_warn("%s: set consistent dma mask: failed\n", dev->name);
12439 goto out_set_dma_mask;
12440 }
12441
12442 dev->mmio_base = pci_resource_start(pdev, 0);
12443 dev->mmio_len = pci_resource_len(pdev, 0);
12444
12445 if (!request_mem_region(dev->mmio_base, dev->mmio_len, SSD_DEV_NAME)) {
12446 hio_warn("%s: can not reserve MMIO region 0\n", dev->name);
12447 ret = -EBUSY;
12448 goto out_request_mem_region;
12449 }
12450
12451 /* 2.6.9 kernel bug */
12452 dev->ctrlp = pci_iomap(pdev, 0, 0);
12453 if (!dev->ctrlp) {
12454 hio_warn("%s: can not remap IO region 0\n", dev->name);
12455 ret = -ENOMEM;
12456 goto out_pci_iomap;
12457 }
12458
12459 ret = ssd_check_hw(dev);
12460 if (ret) {
12461 hio_err("%s: check hardware failed\n", dev->name);
12462 goto out_check_hw;
12463 }
12464
12465 /* alarm led ? */
12466 ssd_clear_alarm(dev);
12467
12468 ret = ssd_init_fw_info(dev);
12469 if (ret) {
12470 hio_err("%s: init firmware info failed\n", dev->name);
12471 /* alarm led */
12472 ssd_set_alarm(dev);
12473 goto out_init_fw_info;
12474 }
12475
12476 /* slave port ? */
12477 if (dev->slave) {
12478 goto init_next1;
12479 }
12480
12481 ret = ssd_init_rom_info(dev);
12482 if (ret) {
12483 hio_err("%s: init rom info failed\n", dev->name);
12484 /* alarm led */
12485 ssd_set_alarm(dev);
12486 goto out_init_rom_info;
12487 }
12488
12489 ret = ssd_init_label(dev);
12490 if (ret) {
12491 hio_err("%s: init label failed\n", dev->name);
12492 /* alarm led */
12493 ssd_set_alarm(dev);
12494 goto out_init_label;
12495 }
12496
12497 ret = ssd_init_workq(dev);
12498 if (ret) {
12499 hio_warn("%s: init workq failed\n", dev->name);
12500 goto out_init_workq;
12501 }
12502 (void)test_and_set_bit(SSD_INIT_WORKQ, &dev->state);
12503
12504 ret = ssd_init_log(dev);
12505 if (ret) {
12506 hio_err("%s: init log failed\n", dev->name);
12507 /* alarm led */
12508 ssd_set_alarm(dev);
12509 goto out_init_log;
12510 }
12511
12512 ret = ssd_init_smart(dev);
12513 if (ret) {
12514 hio_err("%s: init info failed\n", dev->name);
12515 /* alarm led */
12516 ssd_set_alarm(dev);
12517 goto out_init_smart;
12518 }
12519
12520init_next1:
12521 ret = ssd_init_hw_info(dev);
12522 if (ret) {
12523 hio_err("%s: init hardware info failed\n", dev->name);
12524 /* alarm led */
12525 ssd_set_alarm(dev);
12526 goto out_init_hw_info;
12527 }
12528
12529 /* slave port ? */
12530 if (dev->slave) {
12531 goto init_next2;
12532 }
12533
12534 ret = ssd_init_sensor(dev);
12535 if (ret) {
12536 hio_err("%s: init sensor failed\n", dev->name);
12537 /* alarm led */
12538 ssd_set_alarm(dev);
12539 goto out_init_sensor;
12540 }
12541
12542 ret = ssd_init_pl_cap(dev);
12543 if (ret) {
12544 hio_err("%s: int pl_cap failed\n", dev->name);
12545 /* alarm led */
12546 ssd_set_alarm(dev);
12547 goto out_init_pl_cap;
12548 }
12549
12550init_next2:
12551 ret = ssd_check_init_state(dev);
12552 if (ret) {
12553 hio_err("%s: check init state failed\n", dev->name);
12554 /* alarm led */
12555 ssd_set_alarm(dev);
12556 goto out_check_init_state;
12557 }
12558
12559 //flush all base pointer to ssd
12560 (void)ssd_reload_ssd_ptr(dev);
12561
12562 ret = ssd_init_irq(dev);
12563 if (ret) {
12564 hio_warn("%s: init irq failed\n", dev->name);
12565 goto out_init_irq;
12566 }
12567
12568 ret = ssd_init_thread(dev);
12569 if (ret) {
12570 hio_warn("%s: init thread failed\n", dev->name);
12571 goto out_init_thread;
12572 }
12573
12574 /* */
12575 (void)test_and_set_bit(SSD_ONLINE, &dev->state);
12576
12577 /* slave port ? */
12578 if (dev->slave) {
12579 goto init_next3;
12580 }
12581
12582 ret = ssd_init_ot_protect(dev);
12583 if (ret) {
12584 hio_err("%s: int ot_protect failed\n", dev->name);
12585 /* alarm led */
12586 ssd_set_alarm(dev);
12587 goto out_int_ot_protect;
12588 }
12589
12590 ret = ssd_init_wmode(dev);
12591 if (ret) {
12592 hio_warn("%s: init write mode\n", dev->name);
12593 goto out_init_wmode;
12594 }
12595
12596 /* init routine after hw is ready */
12597 ret = ssd_init_routine(dev);
12598 if (ret) {
12599 hio_warn("%s: init routine\n", dev->name);
12600 goto out_init_routine;
12601 }
12602
12603init_next3:
12604 (void)test_and_set_bit(SSD_INIT_BD, &dev->state);
12605
12606 dev->save_md = 1;
12607
12608 hio_warn("%s: resume disk finish.\n", dev->name);
12609
12610 return 0;
12611
12612out_init_routine:
12613out_init_wmode:
12614out_int_ot_protect:
12615 ssd_cleanup_thread(dev);
12616out_init_thread:
12617 ssd_free_irq(dev);
12618out_init_irq:
12619out_check_init_state:
12620out_init_pl_cap:
12621out_init_sensor:
12622out_init_hw_info:
12623out_init_smart:
12624 /* slave port ? */
12625 if (!dev->slave) {
12626 ssd_cleanup_log(dev);
12627 }
12628out_init_log:
12629 /* slave port ? */
12630 if (!dev->slave) {
12631 test_and_clear_bit(SSD_INIT_WORKQ, &dev->state);
12632 ssd_cleanup_workq(dev);
12633 }
12634out_init_workq:
12635out_init_label:
12636out_init_rom_info:
12637out_init_fw_info:
12638out_check_hw:
12639#ifdef LINUX_SUSE_OS
12640 iounmap(dev->ctrlp);
12641#else
12642 pci_iounmap(pdev, dev->ctrlp);
12643#endif
12644out_pci_iomap:
12645 release_mem_region(dev->mmio_base, dev->mmio_len);
12646out_request_mem_region:
12647out_set_dma_mask:
12648 pci_disable_device(pdev);
12649out_enable_device:
12650out_alloc_dev:
12651out:
12652
12653 hio_warn("%s: resume disk fail.\n", dev->name);
12654
12655 return ret;
12656}
12657
12658MODULE_DEVICE_TABLE(pci, ssd_pci_tbl);
12659
12660#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32))
12661#else
12662SIMPLE_DEV_PM_OPS(hio_pm_ops, ssd_hio_suspend, ssd_hio_resume);
12663#endif
12664
12665MODULE_DEVICE_TABLE(pci, ssd_pci_tbl);
12666struct pci_driver ssd_driver = {
12667 .name = MODULE_NAME,
12668 .id_table = ssd_pci_tbl,
12669 .probe = ssd_init_one,
12670#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,38))
12671 .remove = __devexit_p(ssd_remove_one),
a6a796ca
HSDT
12672#else
12673 .remove = ssd_remove_one,
12674#endif
a9d1e0c7
KM
12675
12676#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32))
12677 .suspend = ssd_hio_suspend,
12678 .resume = ssd_hio_resume,
12679#else
12680 .driver = {
12681 .pm = &hio_pm_ops,
12682 },
12683#endif
a6a796ca
HSDT
12684};
12685
12686/* notifier block to get a notify on system shutdown/halt/reboot */
12687static int ssd_notify_reboot(struct notifier_block *nb, unsigned long event, void *buf)
12688{
12689 struct ssd_device *dev = NULL;
12690 struct ssd_device *n = NULL;
12691
12692 list_for_each_entry_safe(dev, n, &ssd_list, list) {
12693 ssd_gen_swlog(dev, SSD_LOG_POWER_OFF, 0);
12694
12695 (void)ssd_flush(dev);
12696 (void)ssd_save_md(dev);
12697
12698 /* slave port ? */
12699 if (!dev->slave) {
12700 ssd_save_smart(dev);
12701
12702 ssd_stop_workq(dev);
12703
12704 if (dev->reload_fw) {
12705 ssd_reg32_write(dev->ctrlp + SSD_RELOAD_FW_REG, SSD_RELOAD_FW);
12706 }
12707 }
12708 }
12709
12710 return NOTIFY_OK;
12711}
12712
12713static struct notifier_block ssd_notifier = {
12714 ssd_notify_reboot, NULL, 0
12715};
12716
12717static int __init ssd_init_module(void)
12718{
12719 int ret = 0;
12720
12721 hio_info("driver version: %s\n", DRIVER_VERSION);
12722
12723 ret = ssd_init_index();
12724 if (ret) {
12725 hio_warn("init index failed\n");
12726 goto out_init_index;
12727 }
12728
12729 ret = ssd_init_proc();
12730 if (ret) {
12731 hio_warn("init proc failed\n");
12732 goto out_init_proc;
12733 }
12734
12735 ret = ssd_init_sysfs();
12736 if (ret) {
12737 hio_warn("init sysfs failed\n");
12738 goto out_init_sysfs;
12739 }
12740
12741 ret = ssd_init_tasklet();
12742 if (ret) {
12743 hio_warn("init tasklet failed\n");
12744 goto out_init_tasklet;
12745 }
12746
12747#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12))
12748 ssd_class = class_simple_create(THIS_MODULE, SSD_DEV_NAME);
12749#else
12750 ssd_class = class_create(THIS_MODULE, SSD_DEV_NAME);
12751#endif
12752 if (IS_ERR(ssd_class)) {
12753 ret = PTR_ERR(ssd_class);
12754 goto out_class_create;
12755 }
12756
12757 if (ssd_cmajor > 0) {
12758 ret = register_chrdev(ssd_cmajor, SSD_CDEV_NAME, &ssd_cfops);
12759 } else {
12760 ret = ssd_cmajor = register_chrdev(ssd_cmajor, SSD_CDEV_NAME, &ssd_cfops);
12761 }
12762 if (ret < 0) {
12763 hio_warn("unable to register chardev major number\n");
12764 goto out_register_chardev;
12765 }
12766
12767 if (ssd_major > 0) {
12768 ret = register_blkdev(ssd_major, SSD_DEV_NAME);
12769 } else {
12770 ret = ssd_major = register_blkdev(ssd_major, SSD_DEV_NAME);
12771 }
12772 if (ret < 0) {
12773 hio_warn("unable to register major number\n");
12774 goto out_register_blkdev;
12775 }
12776
12777 if (ssd_major_sl > 0) {
12778 ret = register_blkdev(ssd_major_sl, SSD_SDEV_NAME);
12779 } else {
12780 ret = ssd_major_sl = register_blkdev(ssd_major_sl, SSD_SDEV_NAME);
12781 }
12782 if (ret < 0) {
12783 hio_warn("unable to register slave major number\n");
12784 goto out_register_blkdev_sl;
12785 }
12786
12787 if (mode < SSD_DRV_MODE_STANDARD || mode > SSD_DRV_MODE_BASE) {
12788 mode = SSD_DRV_MODE_STANDARD;
12789 }
12790
12791 /* for debug */
12792 if (mode != SSD_DRV_MODE_STANDARD) {
12793 ssd_minors = 1;
12794 }
12795
12796 if (int_mode < SSD_INT_LEGACY || int_mode > SSD_INT_MSIX) {
12797 int_mode = SSD_INT_MODE_DEFAULT;
12798 }
12799
12800 if (threaded_irq) {
12801 int_mode = SSD_INT_MSI;
12802 }
12803
12804 if (log_level >= SSD_LOG_NR_LEVEL || log_level < SSD_LOG_LEVEL_INFO) {
12805 log_level = SSD_LOG_LEVEL_ERR;
12806 }
12807
12808 if (wmode < SSD_WMODE_BUFFER || wmode > SSD_WMODE_DEFAULT) {
12809 wmode = SSD_WMODE_DEFAULT;
12810 }
12811
12812#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,20))
12813 ret = pci_module_init(&ssd_driver);
12814#else
12815 ret = pci_register_driver(&ssd_driver);
12816#endif
12817 if (ret) {
12818 hio_warn("pci init failed\n");
12819 goto out_pci_init;
12820 }
12821
12822 ret = register_reboot_notifier(&ssd_notifier);
12823 if (ret) {
12824 hio_warn("register reboot notifier failed\n");
12825 goto out_register_reboot_notifier;
12826 }
12827
12828 return 0;
12829
12830out_register_reboot_notifier:
12831out_pci_init:
12832 pci_unregister_driver(&ssd_driver);
12833 unregister_blkdev(ssd_major_sl, SSD_SDEV_NAME);
12834out_register_blkdev_sl:
12835 unregister_blkdev(ssd_major, SSD_DEV_NAME);
12836out_register_blkdev:
12837 unregister_chrdev(ssd_cmajor, SSD_CDEV_NAME);
12838out_register_chardev:
12839#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12))
12840 class_simple_destroy(ssd_class);
12841#else
12842 class_destroy(ssd_class);
12843#endif
12844out_class_create:
12845 ssd_cleanup_tasklet();
12846out_init_tasklet:
12847 ssd_cleanup_sysfs();
12848out_init_sysfs:
12849 ssd_cleanup_proc();
12850out_init_proc:
12851 ssd_cleanup_index();
12852out_init_index:
12853 return ret;
12854
12855}
12856
12857static void __exit ssd_cleanup_module(void)
12858{
12859
12860 hio_info("unload driver: %s\n", DRIVER_VERSION);
12861 /* exiting */
12862 ssd_exiting = 1;
12863
12864 unregister_reboot_notifier(&ssd_notifier);
12865
12866 pci_unregister_driver(&ssd_driver);
12867
12868 unregister_blkdev(ssd_major_sl, SSD_SDEV_NAME);
12869 unregister_blkdev(ssd_major, SSD_DEV_NAME);
12870 unregister_chrdev(ssd_cmajor, SSD_CDEV_NAME);
12871#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,12))
12872 class_simple_destroy(ssd_class);
12873#else
12874 class_destroy(ssd_class);
12875#endif
12876
12877 ssd_cleanup_tasklet();
12878 ssd_cleanup_sysfs();
12879 ssd_cleanup_proc();
12880 ssd_cleanup_index();
12881}
12882
12883int ssd_register_event_notifier(struct block_device *bdev, ssd_event_call event_call)
12884{
12885 struct ssd_device *dev;
12886 struct timeval tv;
a9d1e0c7 12887 struct ssd_log *le, *temp_le = NULL;
a6a796ca 12888 uint64_t cur;
a9d1e0c7 12889 int temp = 0;
a6a796ca
HSDT
12890 int log_nr;
12891
12892 if (!bdev || !event_call || !(bdev->bd_disk)) {
12893 return -EINVAL;
12894 }
12895
12896 dev = bdev->bd_disk->private_data;
12897 dev->event_call = event_call;
12898
12899 do_gettimeofday(&tv);
12900 cur = tv.tv_sec;
12901
12902 le = (struct ssd_log *)(dev->internal_log.log);
12903 log_nr = dev->internal_log.nr_log;
12904
12905 while (log_nr--) {
12906 if (le->time <= cur && le->time >= dev->uptime) {
a9d1e0c7
KM
12907 if ((le->le.event == SSD_LOG_SEU_FAULT1) && (le->time < dev->reset_time)) {
12908 le++;
12909 continue;
12910 }
12911 if (le->le.event == SSD_LOG_OVER_TEMP || le->le.event == SSD_LOG_NORMAL_TEMP || le->le.event == SSD_LOG_WARN_TEMP) {
12912 if (!temp_le || le->time >= temp_le->time) {
12913 temp_le = le;
12914 }
12915 le++;
12916 continue;
12917 }
a6a796ca
HSDT
12918 (void)dev->event_call(dev->gd, le->le.event, ssd_parse_log(dev, le, 0));
12919 }
12920 le++;
12921 }
12922
a9d1e0c7
KM
12923 ssd_get_temperature(bdev, &temp);
12924 if (temp_le && (temp >= SSD_OT_TEMP_HYST)) {
12925 (void)dev->event_call(dev->gd, temp_le->le.event, ssd_parse_log(dev, temp_le, 0));
12926 }
12927
a6a796ca
HSDT
12928 return 0;
12929}
12930
12931int ssd_unregister_event_notifier(struct block_device *bdev)
12932{
12933 struct ssd_device *dev;
12934
12935 if (!bdev || !(bdev->bd_disk)) {
12936 return -EINVAL;
12937 }
12938
12939 dev = bdev->bd_disk->private_data;
12940 dev->event_call = NULL;
12941
12942 return 0;
12943}
12944
12945EXPORT_SYMBOL(ssd_get_label);
12946EXPORT_SYMBOL(ssd_get_version);
12947EXPORT_SYMBOL(ssd_set_otprotect);
12948EXPORT_SYMBOL(ssd_bm_status);
12949EXPORT_SYMBOL(ssd_submit_pbio);
12950EXPORT_SYMBOL(ssd_get_pciaddr);
12951EXPORT_SYMBOL(ssd_get_temperature);
12952EXPORT_SYMBOL(ssd_register_event_notifier);
12953EXPORT_SYMBOL(ssd_unregister_event_notifier);
12954EXPORT_SYMBOL(ssd_reset);
12955EXPORT_SYMBOL(ssd_set_wmode);
12956
12957
12958
12959module_init(ssd_init_module);
12960module_exit(ssd_cleanup_module);
12961MODULE_VERSION(DRIVER_VERSION);
12962MODULE_LICENSE("GPL");
12963MODULE_AUTHOR("Huawei SSD DEV Team");
12964MODULE_DESCRIPTION("Huawei SSD driver");