[mirror_qemu.git] / user-exec.c

/*
 *  User emulator execution
 *
 *  Copyright (c) 2003-2005 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */
#include "config.h"
#include "cpu.h"
#include "disas/disas.h"
#include "tcg.h"
#include "qemu/bitops.h"

#undef EAX
#undef ECX
#undef EDX
#undef EBX
#undef ESP
#undef EBP
#undef ESI
#undef EDI
#undef EIP
#include <signal.h>
#ifdef __linux__
#include <sys/ucontext.h>
#endif

//#define DEBUG_SIGNAL

static void exception_action(CPUArchState *env1)
{
    CPUState *cpu = ENV_GET_CPU(env1);

#if defined(TARGET_I386)
    raise_exception_err(env1, cpu->exception_index, env1->error_code);
#else
    cpu_loop_exit(cpu);
#endif
}

/* exit the current TB from a signal handler. The host registers are
   restored in a state compatible with the CPU emulator
 */
void cpu_resume_from_signal(CPUArchState *env1, void *puc)
{
    CPUState *cpu = ENV_GET_CPU(env1);
#ifdef __linux__
    struct ucontext *uc = puc;
#elif defined(__OpenBSD__)
    struct sigcontext *uc = puc;
#endif

    if (puc) {
        /* XXX: use siglongjmp ? */
#ifdef __linux__
#ifdef __ia64
        sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
#else
        sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
#endif
#elif defined(__OpenBSD__)
        sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
#endif
    }
    cpu->exception_index = -1;
    siglongjmp(cpu->jmp_env, 1);
}

/* 'pc' is the host PC at which the exception was raised. 'address' is
   the effective address of the memory exception. 'is_write' is 1 if a
   write caused the exception and otherwise 0'. 'old_set' is the
   signal set which should be restored */
static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
                                    int is_write, sigset_t *old_set,
                                    void *puc)
{
    CPUState *cpu;
    CPUClass *cc;
    CPUArchState *env;
    int ret;

#if defined(DEBUG_SIGNAL)
    qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
                pc, address, is_write, *(unsigned long *)old_set);
#endif
    /* XXX: locking issue */
    if (is_write && h2g_valid(address)
        && page_unprotect(h2g(address), pc, puc)) {
        return 1;
    }

    /* Convert forcefully to guest address space, invalid addresses
       are still valid segv ones */
    address = h2g_nocheck(address);

    cpu = current_cpu;
    cc = CPU_GET_CLASS(cpu);
    env = cpu->env_ptr;
    /* see if it is an MMU fault */
    g_assert(cc->handle_mmu_fault);
    ret = cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX);
    if (ret < 0) {
        return 0; /* not an MMU fault */
    }
    if (ret == 0) {
        return 1; /* the MMU fault was handled without causing real CPU fault */
    }
    /* now we have a real cpu fault */
    cpu_restore_state(cpu, pc);

    /* we restore the process signal mask as the sigreturn should
       do it (XXX: use sigsetjmp) */
    sigprocmask(SIG_SETMASK, old_set, NULL);
    exception_action(env);

    /* never comes here */
    return 1;
}

#if defined(__i386__)

#if defined(__APPLE__)
#include <sys/ucontext.h>

#define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext->ss.eip))
#define TRAP_sig(context)    ((context)->uc_mcontext->es.trapno)
#define ERROR_sig(context)   ((context)->uc_mcontext->es.err)
#define MASK_sig(context)    ((context)->uc_sigmask)
#elif defined(__NetBSD__)
#include <ucontext.h>

#define EIP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_EIP])
#define TRAP_sig(context)    ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
#define ERROR_sig(context)   ((context)->uc_mcontext.__gregs[_REG_ERR])
#define MASK_sig(context)    ((context)->uc_sigmask)
#elif defined(__FreeBSD__) || defined(__DragonFly__)
#include <ucontext.h>

#define EIP_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
#define TRAP_sig(context)    ((context)->uc_mcontext.mc_trapno)
#define ERROR_sig(context)   ((context)->uc_mcontext.mc_err)
#define MASK_sig(context)    ((context)->uc_sigmask)
#elif defined(__OpenBSD__)
#define EIP_sig(context)     ((context)->sc_eip)
#define TRAP_sig(context)    ((context)->sc_trapno)
#define ERROR_sig(context)   ((context)->sc_err)
#define MASK_sig(context)    ((context)->sc_mask)
#else
#define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
#define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
#define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
#define MASK_sig(context)    ((context)->uc_sigmask)
#endif

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
    ucontext_t *uc = puc;
#elif defined(__OpenBSD__)
    struct sigcontext *uc = puc;
#else
    struct ucontext *uc = puc;
#endif
    unsigned long pc;
    int trapno;

#ifndef REG_EIP
/* for glibc 2.1 */
#define REG_EIP    EIP
#define REG_ERR    ERR
#define REG_TRAPNO TRAPNO
#endif
    pc = EIP_sig(uc);
    trapno = TRAP_sig(uc);
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             trapno == 0xe ?
                             (ERROR_sig(uc) >> 1) & 1 : 0,
                             &MASK_sig(uc), puc);
}

#elif defined(__x86_64__)

#ifdef __NetBSD__
#define PC_sig(context)       _UC_MACHINE_PC(context)
#define TRAP_sig(context)     ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
#define ERROR_sig(context)    ((context)->uc_mcontext.__gregs[_REG_ERR])
#define MASK_sig(context)     ((context)->uc_sigmask)
#elif defined(__OpenBSD__)
#define PC_sig(context)       ((context)->sc_rip)
#define TRAP_sig(context)     ((context)->sc_trapno)
#define ERROR_sig(context)    ((context)->sc_err)
#define MASK_sig(context)     ((context)->sc_mask)
#elif defined(__FreeBSD__) || defined(__DragonFly__)
#include <ucontext.h>

#define PC_sig(context)  (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
#define TRAP_sig(context)     ((context)->uc_mcontext.mc_trapno)
#define ERROR_sig(context)    ((context)->uc_mcontext.mc_err)
#define MASK_sig(context)     ((context)->uc_sigmask)
#else
#define PC_sig(context)       ((context)->uc_mcontext.gregs[REG_RIP])
#define TRAP_sig(context)     ((context)->uc_mcontext.gregs[REG_TRAPNO])
#define ERROR_sig(context)    ((context)->uc_mcontext.gregs[REG_ERR])
#define MASK_sig(context)     ((context)->uc_sigmask)
#endif

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    unsigned long pc;
#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
    ucontext_t *uc = puc;
#elif defined(__OpenBSD__)
    struct sigcontext *uc = puc;
#else
    struct ucontext *uc = puc;
#endif

    pc = PC_sig(uc);
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             TRAP_sig(uc) == 0xe ?
                             (ERROR_sig(uc) >> 1) & 1 : 0,
                             &MASK_sig(uc), puc);
}

#elif defined(_ARCH_PPC)

/***********************************************************************
 * signal context platform-specific definitions
 * From Wine
 */
#ifdef linux
/* All Registers access - only for local access */
#define REG_sig(reg_name, context)              \
    ((context)->uc_mcontext.regs->reg_name)
/* Gpr Registers access  */
#define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
/* Program counter */
#define IAR_sig(context)                       REG_sig(nip, context)
/* Machine State Register (Supervisor) */
#define MSR_sig(context)                       REG_sig(msr, context)
/* Count register */
#define CTR_sig(context)                       REG_sig(ctr, context)
/* User's integer exception register */
#define XER_sig(context)                       REG_sig(xer, context)
/* Link register */
#define LR_sig(context)                        REG_sig(link, context)
/* Condition register */
#define CR_sig(context)                        REG_sig(ccr, context)

/* Float Registers access  */
#define FLOAT_sig(reg_num, context)                                     \
    (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
#define FPSCR_sig(context) \
    (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
/* Exception Registers access */
#define DAR_sig(context)                       REG_sig(dar, context)
#define DSISR_sig(context)                     REG_sig(dsisr, context)
#define TRAP_sig(context)                      REG_sig(trap, context)
#endif /* linux */

#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
#include <ucontext.h>
#define IAR_sig(context)               ((context)->uc_mcontext.mc_srr0)
#define MSR_sig(context)               ((context)->uc_mcontext.mc_srr1)
#define CTR_sig(context)               ((context)->uc_mcontext.mc_ctr)
#define XER_sig(context)               ((context)->uc_mcontext.mc_xer)
#define LR_sig(context)                ((context)->uc_mcontext.mc_lr)
#define CR_sig(context)                ((context)->uc_mcontext.mc_cr)
/* Exception Registers access */
#define DAR_sig(context)               ((context)->uc_mcontext.mc_dar)
#define DSISR_sig(context)             ((context)->uc_mcontext.mc_dsisr)
#define TRAP_sig(context)              ((context)->uc_mcontext.mc_exc)
#endif /* __FreeBSD__|| __FreeBSD_kernel__ */

#ifdef __APPLE__
#include <sys/ucontext.h>
typedef struct ucontext SIGCONTEXT;
/* All Registers access - only for local access */
#define REG_sig(reg_name, context)              \
    ((context)->uc_mcontext->ss.reg_name)
#define FLOATREG_sig(reg_name, context)         \
    ((context)->uc_mcontext->fs.reg_name)
#define EXCEPREG_sig(reg_name, context)         \
    ((context)->uc_mcontext->es.reg_name)
#define VECREG_sig(reg_name, context)           \
    ((context)->uc_mcontext->vs.reg_name)
/* Gpr Registers access */
#define GPR_sig(reg_num, context)              REG_sig(r##reg_num, context)
/* Program counter */
#define IAR_sig(context)                       REG_sig(srr0, context)
/* Machine State Register (Supervisor) */
#define MSR_sig(context)                       REG_sig(srr1, context)
#define CTR_sig(context)                       REG_sig(ctr, context)
/* Link register */
#define XER_sig(context)                       REG_sig(xer, context)
/* User's integer exception register */
#define LR_sig(context)                        REG_sig(lr, context)
/* Condition register */
#define CR_sig(context)                        REG_sig(cr, context)
/* Float Registers access */
#define FLOAT_sig(reg_num, context)             \
    FLOATREG_sig(fpregs[reg_num], context)
#define FPSCR_sig(context)                      \
    ((double)FLOATREG_sig(fpscr, context))
/* Exception Registers access */
/* Fault registers for coredump */
#define DAR_sig(context)                       EXCEPREG_sig(dar, context)
#define DSISR_sig(context)                     EXCEPREG_sig(dsisr, context)
/* number of powerpc exception taken */
#define TRAP_sig(context)                      EXCEPREG_sig(exception, context)
#endif /* __APPLE__ */

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
    ucontext_t *uc = puc;
#else
    struct ucontext *uc = puc;
#endif
    unsigned long pc;
    int is_write;

    pc = IAR_sig(uc);
    is_write = 0;
#if 0
    /* ppc 4xx case */
    if (DSISR_sig(uc) & 0x00800000) {
        is_write = 1;
    }
#else
    if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
        is_write = 1;
    }
#endif
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, &uc->uc_sigmask, puc);
}

#elif defined(__alpha__)

int cpu_signal_handler(int host_signum, void *pinfo,
                           void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    uint32_t *pc = uc->uc_mcontext.sc_pc;
    uint32_t insn = *pc;
    int is_write = 0;

    /* XXX: need kernel patch to get write flag faster */
    switch (insn >> 26) {
    case 0x0d: /* stw */
    case 0x0e: /* stb */
    case 0x0f: /* stq_u */
    case 0x24: /* stf */
    case 0x25: /* stg */
    case 0x26: /* sts */
    case 0x27: /* stt */
    case 0x2c: /* stl */
    case 0x2d: /* stq */
    case 0x2e: /* stl_c */
    case 0x2f: /* stq_c */
        is_write = 1;
    }

    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, &uc->uc_sigmask, puc);
}
#elif defined(__sparc__)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    int is_write;
    uint32_t insn;
#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
    uint32_t *regs = (uint32_t *)(info + 1);
    void *sigmask = (regs + 20);
    /* XXX: is there a standard glibc define ? */
    unsigned long pc = regs[1];
#else
#ifdef __linux__
    struct sigcontext *sc = puc;
    unsigned long pc = sc->sigc_regs.tpc;
    void *sigmask = (void *)sc->sigc_mask;
#elif defined(__OpenBSD__)
    struct sigcontext *uc = puc;
    unsigned long pc = uc->sc_pc;
    void *sigmask = (void *)(long)uc->sc_mask;
#endif
#endif

    /* XXX: need kernel patch to get write flag faster */
    is_write = 0;
    insn = *(uint32_t *)pc;
    if ((insn >> 30) == 3) {
        switch ((insn >> 19) & 0x3f) {
        case 0x05: /* stb */
        case 0x15: /* stba */
        case 0x06: /* sth */
        case 0x16: /* stha */
        case 0x04: /* st */
        case 0x14: /* sta */
        case 0x07: /* std */
        case 0x17: /* stda */
        case 0x0e: /* stx */
        case 0x1e: /* stxa */
        case 0x24: /* stf */
        case 0x34: /* stfa */
        case 0x27: /* stdf */
        case 0x37: /* stdfa */
        case 0x26: /* stqf */
        case 0x36: /* stqfa */
        case 0x25: /* stfsr */
        case 0x3c: /* casa */
        case 0x3e: /* casxa */
            is_write = 1;
            break;
        }
    }
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, sigmask, NULL);
}

#elif defined(__arm__)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    unsigned long pc;
    int is_write;

#if defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
    pc = uc->uc_mcontext.gregs[R15];
#else
    pc = uc->uc_mcontext.arm_pc;
#endif

    /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
     * later processor; on v5 we will always report this as a read).
     */
    is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write,
                             &uc->uc_sigmask, puc);
}

#elif defined(__aarch64__)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    uint64_t pc;
    int is_write = 0; /* XXX how to determine? */

    pc = uc->uc_mcontext.pc;
    return handle_cpu_signal(pc, (uint64_t)info->si_addr,
                             is_write, &uc->uc_sigmask, puc);
}

#elif defined(__mc68000)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    unsigned long pc;
    int is_write;

    pc = uc->uc_mcontext.gregs[16];
    /* XXX: compute is_write */
    is_write = 0;
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write,
                             &uc->uc_sigmask, puc);
}

#elif defined(__ia64)

#ifndef __ISR_VALID
  /* This ought to be in <bits/siginfo.h>... */
# define __ISR_VALID    1
#endif

int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    unsigned long ip;
    int is_write = 0;

    ip = uc->uc_mcontext.sc_ip;
    switch (host_signum) {
    case SIGILL:
    case SIGFPE:
    case SIGSEGV:
    case SIGBUS:
    case SIGTRAP:
        if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
            /* ISR.W (write-access) is bit 33:  */
            is_write = (info->si_isr >> 33) & 1;
        }
        break;

    default:
        break;
    }
    return handle_cpu_signal(ip, (unsigned long)info->si_addr,
                             is_write,
                             (sigset_t *)&uc->uc_sigmask, puc);
}

#elif defined(__s390__)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    unsigned long pc;
    uint16_t *pinsn;
    int is_write = 0;

    pc = uc->uc_mcontext.psw.addr;

    /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
       of the normal 2 arguments.  The 3rd argument contains the "int_code"
       from the hardware which does in fact contain the is_write value.
       The rt signal handler, as far as I can tell, does not give this value
       at all.  Not that we could get to it from here even if it were.  */
    /* ??? This is not even close to complete, since it ignores all
       of the read-modify-write instructions.  */
    pinsn = (uint16_t *)pc;
    switch (pinsn[0] >> 8) {
    case 0x50: /* ST */
    case 0x42: /* STC */
    case 0x40: /* STH */
        is_write = 1;
        break;
    case 0xc4: /* RIL format insns */
        switch (pinsn[0] & 0xf) {
        case 0xf: /* STRL */
        case 0xb: /* STGRL */
        case 0x7: /* STHRL */
            is_write = 1;
        }
        break;
    case 0xe3: /* RXY format insns */
        switch (pinsn[2] & 0xff) {
        case 0x50: /* STY */
        case 0x24: /* STG */
        case 0x72: /* STCY */
        case 0x70: /* STHY */
        case 0x8e: /* STPQ */
        case 0x3f: /* STRVH */
        case 0x3e: /* STRV */
        case 0x2f: /* STRVG */
            is_write = 1;
        }
        break;
    }
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, &uc->uc_sigmask, puc);
}

#elif defined(__mips__)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    greg_t pc = uc->uc_mcontext.pc;
    int is_write;

    /* XXX: compute is_write */
    is_write = 0;
    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, &uc->uc_sigmask, puc);
}

#elif defined(__hppa__)

int cpu_signal_handler(int host_signum, void *pinfo,
                       void *puc)
{
    siginfo_t *info = pinfo;
    struct ucontext *uc = puc;
    unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
    uint32_t insn = *(uint32_t *)pc;
    int is_write = 0;

    /* XXX: need kernel patch to get write flag faster.  */
    switch (insn >> 26) {
    case 0x1a: /* STW */
    case 0x19: /* STH */
    case 0x18: /* STB */
    case 0x1b: /* STWM */
        is_write = 1;
        break;

    case 0x09: /* CSTWX, FSTWX, FSTWS */
    case 0x0b: /* CSTDX, FSTDX, FSTDS */
        /* Distinguish from coprocessor load ... */
        is_write = (insn >> 9) & 1;
        break;

    case 0x03:
        switch ((insn >> 6) & 15) {
        case 0xa: /* STWS */
        case 0x9: /* STHS */
        case 0x8: /* STBS */
        case 0xe: /* STWAS */
        case 0xc: /* STBYS */
            is_write = 1;
        }
        break;
    }

    return handle_cpu_signal(pc, (unsigned long)info->si_addr,
                             is_write, &uc->uc_sigmask, puc);
}

#else

#error host CPU specific signal handler needed

#endif
Commit	Line	Data
42a623c7 BS	1	/*
	2	* User emulator execution
	3	*
	4	* Copyright (c) 2003-2005 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#include "config.h"
3e457172	20	#include "cpu.h"
76cad711	21	#include "disas/disas.h"
42a623c7	22	#include "tcg.h"
023b0ae3	23	#include "qemu/bitops.h"
42a623c7 BS	24
	25	#undef EAX
	26	#undef ECX
	27	#undef EDX
	28	#undef EBX
	29	#undef ESP
	30	#undef EBP
	31	#undef ESI
	32	#undef EDI
	33	#undef EIP
	34	#include <signal.h>
	35	#ifdef __linux__
	36	#include <sys/ucontext.h>
	37	#endif
	38
	39	//#define DEBUG_SIGNAL
	40
9349b4f9	41	static void exception_action(CPUArchState *env1)
1162c041	42	{
27103424 AF	43	CPUState *cpu = ENV_GET_CPU(env1);
27103424 AF	44
5638d180	45	#if defined(TARGET_I386)
27103424	46	raise_exception_err(env1, cpu->exception_index, env1->error_code);
42a623c7	47	#else
5638d180	48	cpu_loop_exit(cpu);
42a623c7	49	#endif
1162c041	50	}
42a623c7 BS	51
	52	/* exit the current TB from a signal handler. The host registers are
	53	restored in a state compatible with the CPU emulator
	54	*/
9349b4f9	55	void cpu_resume_from_signal(CPUArchState env1, void puc)
42a623c7	56	{
6f03bef0	57	CPUState *cpu = ENV_GET_CPU(env1);
42a623c7 BS	58	#ifdef __linux__
	59	struct ucontext *uc = puc;
	60	#elif defined(__OpenBSD__)
	61	struct sigcontext *uc = puc;
	62	#endif
	63
42a623c7 BS	64	if (puc) {
	65	/* XXX: use siglongjmp ? */
	66	#ifdef __linux__
	67	#ifdef __ia64
	68	sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
	69	#else
	70	sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
	71	#endif
	72	#elif defined(__OpenBSD__)
	73	sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
	74	#endif
	75	}
27103424	76	cpu->exception_index = -1;
6f03bef0	77	siglongjmp(cpu->jmp_env, 1);
42a623c7 BS	78	}
	79
	80	/* 'pc' is the host PC at which the exception was raised. 'address' is
	81	the effective address of the memory exception. 'is_write' is 1 if a
	82	write caused the exception and otherwise 0'. 'old_set' is the
	83	signal set which should be restored */
20503968	84	static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
42a623c7 BS	85	int is_write, sigset_t *old_set,
	86	void *puc)
	87	{
7510454e AF	88	CPUState *cpu;
7510454e AF	89	CPUClass *cc;
4917cf44	90	CPUArchState *env;
42a623c7 BS	91	int ret;
42a623c7 BS	92
42a623c7 BS	93	#if defined(DEBUG_SIGNAL)
	94	qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
	95	pc, address, is_write, (unsigned long )old_set);
	96	#endif
	97	/* XXX: locking issue */
c5954819 PM	98	if (is_write && h2g_valid(address)
c5954819 PM	99	&& page_unprotect(h2g(address), pc, puc)) {
42a623c7 BS	100	return 1;
	101	}
	102
732f9e89 AG	103	/* Convert forcefully to guest address space, invalid addresses
	104	are still valid segv ones */
	105	address = h2g_nocheck(address);
	106
7510454e AF	107	cpu = current_cpu;
	108	cc = CPU_GET_CLASS(cpu);
	109	env = cpu->env_ptr;
42a623c7	110	/* see if it is an MMU fault */
7510454e AF	111	g_assert(cc->handle_mmu_fault);
7510454e AF	112	ret = cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX);
42a623c7 BS	113	if (ret < 0) {
	114	return 0; /* not an MMU fault */
	115	}
	116	if (ret == 0) {
	117	return 1; /* the MMU fault was handled without causing real CPU fault */
	118	}
	119	/* now we have a real cpu fault */
3f38f309	120	cpu_restore_state(cpu, pc);
42a623c7 BS	121
	122	/* we restore the process signal mask as the sigreturn should
	123	do it (XXX: use sigsetjmp) */
	124	sigprocmask(SIG_SETMASK, old_set, NULL);
4917cf44	125	exception_action(env);
42a623c7 BS	126
	127	/* never comes here */
	128	return 1;
	129	}
	130
	131	#if defined(__i386__)
	132
	133	#if defined(__APPLE__)
	134	#include <sys/ucontext.h>
	135
	136	#define EIP_sig(context) (((unsigned long )&(context)->uc_mcontext->ss.eip))
	137	#define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
	138	#define ERROR_sig(context) ((context)->uc_mcontext->es.err)
	139	#define MASK_sig(context) ((context)->uc_sigmask)
	140	#elif defined(__NetBSD__)
	141	#include <ucontext.h>
	142
	143	#define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
	144	#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
	145	#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
	146	#define MASK_sig(context) ((context)->uc_sigmask)
	147	#elif defined(__FreeBSD__) \|\| defined(__DragonFly__)
	148	#include <ucontext.h>
	149
	150	#define EIP_sig(context) (((unsigned long )&(context)->uc_mcontext.mc_eip))
	151	#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
	152	#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
	153	#define MASK_sig(context) ((context)->uc_sigmask)
	154	#elif defined(__OpenBSD__)
	155	#define EIP_sig(context) ((context)->sc_eip)
	156	#define TRAP_sig(context) ((context)->sc_trapno)
	157	#define ERROR_sig(context) ((context)->sc_err)
	158	#define MASK_sig(context) ((context)->sc_mask)
	159	#else
	160	#define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
	161	#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
	162	#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
	163	#define MASK_sig(context) ((context)->uc_sigmask)
	164	#endif
	165
	166	int cpu_signal_handler(int host_signum, void *pinfo,
	167	void *puc)
	168	{
	169	siginfo_t *info = pinfo;
	170	#if defined(__NetBSD__) \|\| defined(__FreeBSD__) \|\| defined(__DragonFly__)
	171	ucontext_t *uc = puc;
	172	#elif defined(__OpenBSD__)
	173	struct sigcontext *uc = puc;
	174	#else
	175	struct ucontext *uc = puc;
	176	#endif
	177	unsigned long pc;
	178	int trapno;
	179
	180	#ifndef REG_EIP
	181	/* for glibc 2.1 */
	182	#define REG_EIP EIP
	183	#define REG_ERR ERR
	184	#define REG_TRAPNO TRAPNO
	185	#endif
	186	pc = EIP_sig(uc);
	187	trapno = TRAP_sig(uc);
	188	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	189	trapno == 0xe ?
190	(ERROR_sig(uc) >> 1) & 1 : 0,
191	&MASK_sig(uc), puc);
192	}
193
194	#elif defined(__x86_64__)
195
196	#ifdef __NetBSD__
197	#define PC_sig(context) _UC_MACHINE_PC(context)
198	#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
199	#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
200	#define MASK_sig(context) ((context)->uc_sigmask)
201	#elif defined(__OpenBSD__)
202	#define PC_sig(context) ((context)->sc_rip)
203	#define TRAP_sig(context) ((context)->sc_trapno)
204	#define ERROR_sig(context) ((context)->sc_err)
205	#define MASK_sig(context) ((context)->sc_mask)
206	#elif defined(__FreeBSD__) \|\| defined(__DragonFly__)
207	#include <ucontext.h>
208
209	#define PC_sig(context) (((unsigned long )&(context)->uc_mcontext.mc_rip))
210	#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
211	#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
212	#define MASK_sig(context) ((context)->uc_sigmask)
213	#else
214	#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
215	#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
216	#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
217	#define MASK_sig(context) ((context)->uc_sigmask)
218	#endif
219
220	int cpu_signal_handler(int host_signum, void *pinfo,
221	void *puc)
222	{
223	siginfo_t *info = pinfo;
224	unsigned long pc;
225	#if defined(__NetBSD__) \|\| defined(__FreeBSD__) \|\| defined(__DragonFly__)
226	ucontext_t *uc = puc;
227	#elif defined(__OpenBSD__)
228	struct sigcontext *uc = puc;
229	#else
230	struct ucontext *uc = puc;
231	#endif
232
233	pc = PC_sig(uc);
234	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
235	TRAP_sig(uc) == 0xe ?
236	(ERROR_sig(uc) >> 1) & 1 : 0,
237	&MASK_sig(uc), puc);
238	}
239
240	#elif defined(_ARCH_PPC)
241
242	/***********************************************************************
243	* signal context platform-specific definitions
244	* From Wine
245	*/
246	#ifdef linux
247	/* All Registers access - only for local access */
248	#define REG_sig(reg_name, context) \
249	((context)->uc_mcontext.regs->reg_name)
250	/* Gpr Registers access */
251	#define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
252	/* Program counter */
253	#define IAR_sig(context) REG_sig(nip, context)
254	/* Machine State Register (Supervisor) */
255	#define MSR_sig(context) REG_sig(msr, context)
256	/* Count register */
257	#define CTR_sig(context) REG_sig(ctr, context)
258	/* User's integer exception register */
259	#define XER_sig(context) REG_sig(xer, context)
260	/* Link register */
261	#define LR_sig(context) REG_sig(link, context)
262	/* Condition register */
263	#define CR_sig(context) REG_sig(ccr, context)
264
265	/* Float Registers access */
266	#define FLOAT_sig(reg_num, context) \
267	(((double )((char )((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
268	#define FPSCR_sig(context) \
269	((int )((char )((context)->uc_mcontext.regs + (48 + 32 2) * 4)))
270	/* Exception Registers access */
271	#define DAR_sig(context) REG_sig(dar, context)
272	#define DSISR_sig(context) REG_sig(dsisr, context)
273	#define TRAP_sig(context) REG_sig(trap, context)
274	#endif /* linux */
275
276	#if defined(__FreeBSD__) \|\| defined(__FreeBSD_kernel__)
277	#include <ucontext.h>
278	#define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
279	#define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
280	#define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
281	#define XER_sig(context) ((context)->uc_mcontext.mc_xer)
282	#define LR_sig(context) ((context)->uc_mcontext.mc_lr)
283	#define CR_sig(context) ((context)->uc_mcontext.mc_cr)
284	/* Exception Registers access */
285	#define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
286	#define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
287	#define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
288	#endif /* __FreeBSD__\|\| __FreeBSD_kernel__ */
289
290	#ifdef __APPLE__
291	#include <sys/ucontext.h>
292	typedef struct ucontext SIGCONTEXT;
293	/* All Registers access - only for local access */
294	#define REG_sig(reg_name, context) \
295	((context)->uc_mcontext->ss.reg_name)
296	#define FLOATREG_sig(reg_name, context) \
297	((context)->uc_mcontext->fs.reg_name)
298	#define EXCEPREG_sig(reg_name, context) \
299	((context)->uc_mcontext->es.reg_name)
300	#define VECREG_sig(reg_name, context) \
301	((context)->uc_mcontext->vs.reg_name)
302	/* Gpr Registers access */
303	#define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
304	/* Program counter */
305	#define IAR_sig(context) REG_sig(srr0, context)
306	/* Machine State Register (Supervisor) */
307	#define MSR_sig(context) REG_sig(srr1, context)
308	#define CTR_sig(context) REG_sig(ctr, context)
309	/* Link register */
310	#define XER_sig(context) REG_sig(xer, context)
311	/* User's integer exception register */
312	#define LR_sig(context) REG_sig(lr, context)
313	/* Condition register */
314	#define CR_sig(context) REG_sig(cr, context)
315	/* Float Registers access */
316	#define FLOAT_sig(reg_num, context) \
317	FLOATREG_sig(fpregs[reg_num], context)
318	#define FPSCR_sig(context) \
319	((double)FLOATREG_sig(fpscr, context))
320	/* Exception Registers access */
321	/* Fault registers for coredump */
322	#define DAR_sig(context) EXCEPREG_sig(dar, context)
323	#define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
324	/* number of powerpc exception taken */
325	#define TRAP_sig(context) EXCEPREG_sig(exception, context)
326	#endif /* __APPLE__ */
327
328	int cpu_signal_handler(int host_signum, void *pinfo,
329	void *puc)
330	{
331	siginfo_t *info = pinfo;
332	#if defined(__FreeBSD__) \|\| defined(__FreeBSD_kernel__)
333	ucontext_t *uc = puc;
334	#else
335	struct ucontext *uc = puc;
336	#endif
337	unsigned long pc;
338	int is_write;
339
340	pc = IAR_sig(uc);
341	is_write = 0;
342	#if 0
343	/* ppc 4xx case */
344	if (DSISR_sig(uc) & 0x00800000) {
345	is_write = 1;
346	}
347	#else
348	if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
349	is_write = 1;
350	}
351	#endif
352	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
353	is_write, &uc->uc_sigmask, puc);
354	}
355
356	#elif defined(__alpha__)
357
358	int cpu_signal_handler(int host_signum, void *pinfo,
359	void *puc)
360	{
361	siginfo_t *info = pinfo;
362	struct ucontext *uc = puc;
363	uint32_t *pc = uc->uc_mcontext.sc_pc;
364	uint32_t insn = *pc;
365	int is_write = 0;
366
367	/* XXX: need kernel patch to get write flag faster */
368	switch (insn >> 26) {
369	case 0x0d: /* stw */
370	case 0x0e: /* stb */
371	case 0x0f: /* stq_u */
372	case 0x24: /* stf */
373	case 0x25: /* stg */
374	case 0x26: /* sts */
375	case 0x27: /* stt */
376	case 0x2c: /* stl */
377	case 0x2d: /* stq */
378	case 0x2e: /* stl_c */
379	case 0x2f: /* stq_c */
380	is_write = 1;
381	}
382
383	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
384	is_write, &uc->uc_sigmask, puc);
385	}
386	#elif defined(__sparc__)
387
388	int cpu_signal_handler(int host_signum, void *pinfo,
389	void *puc)
390	{
391	siginfo_t *info = pinfo;
392	int is_write;
393	uint32_t insn;
394	#if !defined(__arch64__) \|\| defined(CONFIG_SOLARIS)
395	uint32_t regs = (uint32_t )(info + 1);
396	void *sigmask = (regs + 20);
397	/* XXX: is there a standard glibc define ? */
398	unsigned long pc = regs[1];
399	#else
400	#ifdef __linux__
401	struct sigcontext *sc = puc;
402	unsigned long pc = sc->sigc_regs.tpc;
403	void sigmask = (void )sc->sigc_mask;
404	#elif defined(__OpenBSD__)
405	struct sigcontext *uc = puc;
406	unsigned long pc = uc->sc_pc;
407	void sigmask = (void )(long)uc->sc_mask;
408	#endif
409	#endif
410
411	/* XXX: need kernel patch to get write flag faster */
412	is_write = 0;
413	insn = (uint32_t )pc;
414	if ((insn >> 30) == 3) {
415	switch ((insn >> 19) & 0x3f) {
416	case 0x05: /* stb */
417	case 0x15: /* stba */
418	case 0x06: /* sth */
419	case 0x16: /* stha */
420	case 0x04: /* st */
421	case 0x14: /* sta */
422	case 0x07: /* std */
423	case 0x17: /* stda */
424	case 0x0e: /* stx */
425	case 0x1e: /* stxa */
426	case 0x24: /* stf */
427	case 0x34: /* stfa */
428	case 0x27: /* stdf */
429	case 0x37: /* stdfa */
430	case 0x26: /* stqf */
431	case 0x36: /* stqfa */
432	case 0x25: /* stfsr */
433	case 0x3c: /* casa */
434	case 0x3e: /* casxa */
435	is_write = 1;
436	break;
437	}
438	}
439	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
440	is_write, sigmask, NULL);
441	}
442
443	#elif defined(__arm__)
444
445	int cpu_signal_handler(int host_signum, void *pinfo,
446	void *puc)
447	{
448	siginfo_t *info = pinfo;
449	struct ucontext *uc = puc;
450	unsigned long pc;
451	int is_write;
452
e12cdb1b	453	#if defined(__GLIBC__) && (__GLIBC__ < 2 \|\| (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
42a623c7 BS	454	pc = uc->uc_mcontext.gregs[R15];
	455	#else
	456	pc = uc->uc_mcontext.arm_pc;
	457	#endif
023b0ae3 PM	458
	459	/* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
	460	* later processor; on v5 we will always report this as a read).
	461	*/
	462	is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
42a623c7 BS	463	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	464	is_write,
	465	&uc->uc_sigmask, puc);
	466	}
	467
f129061c CF	468	#elif defined(__aarch64__)
	469
	470	int cpu_signal_handler(int host_signum, void *pinfo,
	471	void *puc)
	472	{
	473	siginfo_t *info = pinfo;
	474	struct ucontext *uc = puc;
	475	uint64_t pc;
	476	int is_write = 0; /* XXX how to determine? */
	477
	478	pc = uc->uc_mcontext.pc;
	479	return handle_cpu_signal(pc, (uint64_t)info->si_addr,
	480	is_write, &uc->uc_sigmask, puc);
	481	}
	482
42a623c7 BS	483	#elif defined(__mc68000)
	484
	485	int cpu_signal_handler(int host_signum, void *pinfo,
	486	void *puc)
	487	{
	488	siginfo_t *info = pinfo;
	489	struct ucontext *uc = puc;
	490	unsigned long pc;
	491	int is_write;
	492
	493	pc = uc->uc_mcontext.gregs[16];
	494	/* XXX: compute is_write */
	495	is_write = 0;
	496	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	497	is_write,
	498	&uc->uc_sigmask, puc);
	499	}
	500
	501	#elif defined(__ia64)
	502
	503	#ifndef __ISR_VALID
	504	/* This ought to be in <bits/siginfo.h>... */
	505	# define __ISR_VALID 1
	506	#endif
	507
	508	int cpu_signal_handler(int host_signum, void pinfo, void puc)
	509	{
	510	siginfo_t *info = pinfo;
	511	struct ucontext *uc = puc;
	512	unsigned long ip;
	513	int is_write = 0;
	514
	515	ip = uc->uc_mcontext.sc_ip;
	516	switch (host_signum) {
	517	case SIGILL:
	518	case SIGFPE:
	519	case SIGSEGV:
	520	case SIGBUS:
	521	case SIGTRAP:
	522	if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
	523	/* ISR.W (write-access) is bit 33: */
	524	is_write = (info->si_isr >> 33) & 1;
	525	}
	526	break;
	527
	528	default:
	529	break;
	530	}
	531	return handle_cpu_signal(ip, (unsigned long)info->si_addr,
	532	is_write,
	533	(sigset_t *)&uc->uc_sigmask, puc);
	534	}
	535
	536	#elif defined(__s390__)
	537
	538	int cpu_signal_handler(int host_signum, void *pinfo,
	539	void *puc)
	540	{
	541	siginfo_t *info = pinfo;
	542	struct ucontext *uc = puc;
	543	unsigned long pc;
	544	uint16_t *pinsn;
	545	int is_write = 0;
	546
547	pc = uc->uc_mcontext.psw.addr;
548
549	/* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
550	of the normal 2 arguments. The 3rd argument contains the "int_code"
551	from the hardware which does in fact contain the is_write value.
552	The rt signal handler, as far as I can tell, does not give this value
553	at all. Not that we could get to it from here even if it were. */
554	/* ??? This is not even close to complete, since it ignores all
555	of the read-modify-write instructions. */
556	pinsn = (uint16_t *)pc;
557	switch (pinsn[0] >> 8) {
558	case 0x50: /* ST */
559	case 0x42: /* STC */
560	case 0x40: /* STH */
561	is_write = 1;
562	break;
563	case 0xc4: /* RIL format insns */
564	switch (pinsn[0] & 0xf) {
565	case 0xf: /* STRL */
566	case 0xb: /* STGRL */
567	case 0x7: /* STHRL */
568	is_write = 1;
569	}
570	break;
571	case 0xe3: /* RXY format insns */
572	switch (pinsn[2] & 0xff) {
573	case 0x50: /* STY */
574	case 0x24: /* STG */
575	case 0x72: /* STCY */
576	case 0x70: /* STHY */
577	case 0x8e: /* STPQ */
578	case 0x3f: /* STRVH */
579	case 0x3e: /* STRV */
580	case 0x2f: /* STRVG */
581	is_write = 1;
582	}
583	break;
584	}
585	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
586	is_write, &uc->uc_sigmask, puc);
587	}
588
589	#elif defined(__mips__)
590
591	int cpu_signal_handler(int host_signum, void *pinfo,
592	void *puc)
593	{
594	siginfo_t *info = pinfo;
595	struct ucontext *uc = puc;
596	greg_t pc = uc->uc_mcontext.pc;
597	int is_write;
598
599	/* XXX: compute is_write */
600	is_write = 0;
601	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
602	is_write, &uc->uc_sigmask, puc);
603	}
604
605	#elif defined(__hppa__)
606
607	int cpu_signal_handler(int host_signum, void *pinfo,
608	void *puc)
609	{
02d2bd5d	610	siginfo_t *info = pinfo;
42a623c7 BS	611	struct ucontext *uc = puc;
	612	unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
	613	uint32_t insn = (uint32_t )pc;
	614	int is_write = 0;
	615
	616	/* XXX: need kernel patch to get write flag faster. */
	617	switch (insn >> 26) {
	618	case 0x1a: /* STW */
	619	case 0x19: /* STH */
	620	case 0x18: /* STB */
	621	case 0x1b: /* STWM */
	622	is_write = 1;
	623	break;
	624
	625	case 0x09: /* CSTWX, FSTWX, FSTWS */
	626	case 0x0b: /* CSTDX, FSTDX, FSTDS */
	627	/* Distinguish from coprocessor load ... */
	628	is_write = (insn >> 9) & 1;
	629	break;
	630
	631	case 0x03:
	632	switch ((insn >> 6) & 15) {
	633	case 0xa: /* STWS */
	634	case 0x9: /* STHS */
	635	case 0x8: /* STBS */
	636	case 0xe: /* STWAS */
	637	case 0xc: /* STBYS */
	638	is_write = 1;
	639	}
	640	break;
	641	}
	642
	643	return handle_cpu_signal(pc, (unsigned long)info->si_addr,
	644	is_write, &uc->uc_sigmask, puc);
	645	}
	646
	647	#else
	648
	649	#error host CPU specific signal handler needed
	650
	651	#endif