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qcow2: insert assert into qcow2_get_specific_info()
[mirror_qemu.git] / user-exec.c
CommitLineData
42a623c7
BS		 1/*
2 * User emulator execution
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include "config.h"
3e457172 20#include "cpu.h"
76cad711 21#include "disas/disas.h"
42a623c7 22#include "tcg.h"
023b0ae3 23#include "qemu/bitops.h"
f08b6170 24#include "exec/cpu_ldst.h"
1652b974 25#include "translate-all.h"
42a623c7
BS		 26
27#undef EAX
28#undef ECX
29#undef EDX
30#undef EBX
31#undef ESP
32#undef EBP
33#undef ESI
34#undef EDI
35#undef EIP
36#include <signal.h>
37#ifdef __linux__
38#include <sys/ucontext.h>
39#endif
40
41//#define DEBUG_SIGNAL
42
2ef1f68d 43static void exception_action(CPUState *cpu)
1162c041 44{
5638d180 45#if defined(TARGET_I386)
2ef1f68d
AF		 46 X86CPU *x86_cpu = X86_CPU(cpu);
47 CPUX86State *env1 = &x86_cpu->env;
48
27103424 49 raise_exception_err(env1, cpu->exception_index, env1->error_code);
42a623c7 50#else
5638d180 51 cpu_loop_exit(cpu);
42a623c7 52#endif
1162c041 53}
42a623c7
BS		 54
55/* exit the current TB from a signal handler. The host registers are
56 restored in a state compatible with the CPU emulator
57 */
0ea8cb88 58void cpu_resume_from_signal(CPUState *cpu, void *puc)
42a623c7
BS		 59{
60#ifdef __linux__
61 struct ucontext *uc = puc;
62#elif defined(__OpenBSD__)
63 struct sigcontext *uc = puc;
64#endif
65
42a623c7
BS		 66 if (puc) {
67 /* XXX: use siglongjmp ? */
68#ifdef __linux__
69#ifdef __ia64
70 sigprocmask(SIG_SETMASK, (sigset_t *)&uc->uc_sigmask, NULL);
71#else
72 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
73#endif
74#elif defined(__OpenBSD__)
75 sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
76#endif
77 }
27103424 78 cpu->exception_index = -1;
6f03bef0 79 siglongjmp(cpu->jmp_env, 1);
42a623c7
BS		 80}
81
82/* 'pc' is the host PC at which the exception was raised. 'address' is
83 the effective address of the memory exception. 'is_write' is 1 if a
84 write caused the exception and otherwise 0'. 'old_set' is the
85 signal set which should be restored */
20503968 86static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
42a623c7
BS		 87 int is_write, sigset_t *old_set,
88 void *puc)
89{
7510454e
AF		 90 CPUState *cpu;
91 CPUClass *cc;
42a623c7
BS		 92 int ret;
93
42a623c7 94#if defined(DEBUG_SIGNAL)
71baf787
PM		 95 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
96 pc, address, is_write, *(unsigned long *)old_set);
42a623c7
BS		 97#endif
98 /* XXX: locking issue */
c5954819
PM		 99 if (is_write && h2g_valid(address)
100 && page_unprotect(h2g(address), pc, puc)) {
42a623c7
BS		 101 return 1;
102 }
103
732f9e89
AG		 104 /* Convert forcefully to guest address space, invalid addresses
105 are still valid segv ones */
106 address = h2g_nocheck(address);
107
7510454e
AF		 108 cpu = current_cpu;
109 cc = CPU_GET_CLASS(cpu);
42a623c7 110 /* see if it is an MMU fault */
7510454e
AF		 111 g_assert(cc->handle_mmu_fault);
112 ret = cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX);
42a623c7
BS		 113 if (ret < 0) {
114 return 0; /* not an MMU fault */
115 }
116 if (ret == 0) {
117 return 1; /* the MMU fault was handled without causing real CPU fault */
118 }
119 /* now we have a real cpu fault */
3f38f309 120 cpu_restore_state(cpu, pc);
42a623c7
BS		 121
122 /* we restore the process signal mask as the sigreturn should
123 do it (XXX: use sigsetjmp) */
124 sigprocmask(SIG_SETMASK, old_set, NULL);
2ef1f68d 125 exception_action(cpu);
42a623c7
BS		 126
127 /* never comes here */
128 return 1;
129}
130
131#if defined(__i386__)
132
133#if defined(__APPLE__)
134#include <sys/ucontext.h>
135
136#define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext->ss.eip))
137#define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
138#define ERROR_sig(context) ((context)->uc_mcontext->es.err)
139#define MASK_sig(context) ((context)->uc_sigmask)
140#elif defined(__NetBSD__)
141#include <ucontext.h>
142
143#define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
144#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
145#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
146#define MASK_sig(context) ((context)->uc_sigmask)
147#elif defined(__FreeBSD__) || defined(__DragonFly__)
148#include <ucontext.h>
149
150#define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
151#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
152#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
153#define MASK_sig(context) ((context)->uc_sigmask)
154#elif defined(__OpenBSD__)
155#define EIP_sig(context) ((context)->sc_eip)
156#define TRAP_sig(context) ((context)->sc_trapno)
157#define ERROR_sig(context) ((context)->sc_err)
158#define MASK_sig(context) ((context)->sc_mask)
159#else
160#define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
161#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
162#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
163#define MASK_sig(context) ((context)->uc_sigmask)
164#endif
165
166int cpu_signal_handler(int host_signum, void *pinfo,
167 void *puc)
168{
169 siginfo_t *info = pinfo;
170#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
171 ucontext_t *uc = puc;
172#elif defined(__OpenBSD__)
173 struct sigcontext *uc = puc;
174#else
175 struct ucontext *uc = puc;
176#endif
177 unsigned long pc;
178 int trapno;
179
180#ifndef REG_EIP
181/* for glibc 2.1 */
182#define REG_EIP EIP
183#define REG_ERR ERR
184#define REG_TRAPNO TRAPNO
185#endif
186 pc = EIP_sig(uc);
187 trapno = TRAP_sig(uc);
188 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
189 trapno == 0xe ?
190 (ERROR_sig(uc) >> 1) & 1 : 0,
191 &MASK_sig(uc), puc);
192}
193
194#elif defined(__x86_64__)
195
196#ifdef __NetBSD__
197#define PC_sig(context) _UC_MACHINE_PC(context)
198#define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
199#define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
200#define MASK_sig(context) ((context)->uc_sigmask)
201#elif defined(__OpenBSD__)
202#define PC_sig(context) ((context)->sc_rip)
203#define TRAP_sig(context) ((context)->sc_trapno)
204#define ERROR_sig(context) ((context)->sc_err)
205#define MASK_sig(context) ((context)->sc_mask)
206#elif defined(__FreeBSD__) || defined(__DragonFly__)
207#include <ucontext.h>
208
209#define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
210#define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
211#define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
212#define MASK_sig(context) ((context)->uc_sigmask)
213#else
214#define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
215#define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
216#define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
217#define MASK_sig(context) ((context)->uc_sigmask)
218#endif
219
220int cpu_signal_handler(int host_signum, void *pinfo,
221 void *puc)
222{
223 siginfo_t *info = pinfo;
224 unsigned long pc;
225#if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
226 ucontext_t *uc = puc;
227#elif defined(__OpenBSD__)
228 struct sigcontext *uc = puc;
229#else
230 struct ucontext *uc = puc;
231#endif
232
233 pc = PC_sig(uc);
234 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
235 TRAP_sig(uc) == 0xe ?
236 (ERROR_sig(uc) >> 1) & 1 : 0,
237 &MASK_sig(uc), puc);
238}
239
240#elif defined(_ARCH_PPC)
241
242/***********************************************************************
243 * signal context platform-specific definitions
244 * From Wine
245 */
246#ifdef linux
247/* All Registers access - only for local access */
248#define REG_sig(reg_name, context) \
249 ((context)->uc_mcontext.regs->reg_name)
250/* Gpr Registers access */
251#define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
252/* Program counter */
253#define IAR_sig(context) REG_sig(nip, context)
254/* Machine State Register (Supervisor) */
255#define MSR_sig(context) REG_sig(msr, context)
256/* Count register */
257#define CTR_sig(context) REG_sig(ctr, context)
258/* User's integer exception register */
259#define XER_sig(context) REG_sig(xer, context)
260/* Link register */
261#define LR_sig(context) REG_sig(link, context)
262/* Condition register */
263#define CR_sig(context) REG_sig(ccr, context)
264
265/* Float Registers access */
266#define FLOAT_sig(reg_num, context) \
267 (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
268#define FPSCR_sig(context) \
269 (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
270/* Exception Registers access */
271#define DAR_sig(context) REG_sig(dar, context)
272#define DSISR_sig(context) REG_sig(dsisr, context)
273#define TRAP_sig(context) REG_sig(trap, context)
274#endif /* linux */
275
276#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
277#include <ucontext.h>
278#define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
279#define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
280#define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
281#define XER_sig(context) ((context)->uc_mcontext.mc_xer)
282#define LR_sig(context) ((context)->uc_mcontext.mc_lr)
283#define CR_sig(context) ((context)->uc_mcontext.mc_cr)
284/* Exception Registers access */
285#define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
286#define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
287#define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
288#endif /* __FreeBSD__|| __FreeBSD_kernel__ */
289
290#ifdef __APPLE__
291#include <sys/ucontext.h>
292typedef struct ucontext SIGCONTEXT;
293/* All Registers access - only for local access */
294#define REG_sig(reg_name, context) \
295 ((context)->uc_mcontext->ss.reg_name)
296#define FLOATREG_sig(reg_name, context) \
297 ((context)->uc_mcontext->fs.reg_name)
298#define EXCEPREG_sig(reg_name, context) \
299 ((context)->uc_mcontext->es.reg_name)
300#define VECREG_sig(reg_name, context) \
301 ((context)->uc_mcontext->vs.reg_name)
302/* Gpr Registers access */
303#define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
304/* Program counter */
305#define IAR_sig(context) REG_sig(srr0, context)
306/* Machine State Register (Supervisor) */
307#define MSR_sig(context) REG_sig(srr1, context)
308#define CTR_sig(context) REG_sig(ctr, context)
309/* Link register */
310#define XER_sig(context) REG_sig(xer, context)
311/* User's integer exception register */
312#define LR_sig(context) REG_sig(lr, context)
313/* Condition register */
314#define CR_sig(context) REG_sig(cr, context)
315/* Float Registers access */
316#define FLOAT_sig(reg_num, context) \
317 FLOATREG_sig(fpregs[reg_num], context)
318#define FPSCR_sig(context) \
319 ((double)FLOATREG_sig(fpscr, context))
320/* Exception Registers access */
321/* Fault registers for coredump */
322#define DAR_sig(context) EXCEPREG_sig(dar, context)
323#define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
324/* number of powerpc exception taken */
325#define TRAP_sig(context) EXCEPREG_sig(exception, context)
326#endif /* __APPLE__ */
327
328int cpu_signal_handler(int host_signum, void *pinfo,
329 void *puc)
330{
331 siginfo_t *info = pinfo;
332#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
333 ucontext_t *uc = puc;
334#else
335 struct ucontext *uc = puc;
336#endif
337 unsigned long pc;
338 int is_write;
339
340 pc = IAR_sig(uc);
341 is_write = 0;
342#if 0
343 /* ppc 4xx case */
344 if (DSISR_sig(uc) & 0x00800000) {
345 is_write = 1;
346 }
347#else
348 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
349 is_write = 1;
350 }
351#endif
352 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
353 is_write, &uc->uc_sigmask, puc);
354}
355
356#elif defined(__alpha__)
357
358int cpu_signal_handler(int host_signum, void *pinfo,
359 void *puc)
360{
361 siginfo_t *info = pinfo;
362 struct ucontext *uc = puc;
363 uint32_t *pc = uc->uc_mcontext.sc_pc;
364 uint32_t insn = *pc;
365 int is_write = 0;
366
367 /* XXX: need kernel patch to get write flag faster */
368 switch (insn >> 26) {
369 case 0x0d: /* stw */
370 case 0x0e: /* stb */
371 case 0x0f: /* stq_u */
372 case 0x24: /* stf */
373 case 0x25: /* stg */
374 case 0x26: /* sts */
375 case 0x27: /* stt */
376 case 0x2c: /* stl */
377 case 0x2d: /* stq */
378 case 0x2e: /* stl_c */
379 case 0x2f: /* stq_c */
380 is_write = 1;
381 }
382
383 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
384 is_write, &uc->uc_sigmask, puc);
385}
386#elif defined(__sparc__)
387
388int cpu_signal_handler(int host_signum, void *pinfo,
389 void *puc)
390{
391 siginfo_t *info = pinfo;
392 int is_write;
393 uint32_t insn;
394#if !defined(__arch64__) || defined(CONFIG_SOLARIS)
395 uint32_t *regs = (uint32_t *)(info + 1);
396 void *sigmask = (regs + 20);
397 /* XXX: is there a standard glibc define ? */
398 unsigned long pc = regs[1];
399#else
400#ifdef __linux__
401 struct sigcontext *sc = puc;
402 unsigned long pc = sc->sigc_regs.tpc;
403 void *sigmask = (void *)sc->sigc_mask;
404#elif defined(__OpenBSD__)
405 struct sigcontext *uc = puc;
406 unsigned long pc = uc->sc_pc;
407 void *sigmask = (void *)(long)uc->sc_mask;
7ccfb495
TN		 408#elif defined(__NetBSD__)
409 ucontext_t *uc = puc;
410 unsigned long pc = _UC_MACHINE_PC(uc);
411 void *sigmask = (void *)&uc->uc_sigmask;
42a623c7
BS		 412#endif
413#endif
414
415 /* XXX: need kernel patch to get write flag faster */
416 is_write = 0;
417 insn = *(uint32_t *)pc;
418 if ((insn >> 30) == 3) {
419 switch ((insn >> 19) & 0x3f) {
420 case 0x05: /* stb */
421 case 0x15: /* stba */
422 case 0x06: /* sth */
423 case 0x16: /* stha */
424 case 0x04: /* st */
425 case 0x14: /* sta */
426 case 0x07: /* std */
427 case 0x17: /* stda */
428 case 0x0e: /* stx */
429 case 0x1e: /* stxa */
430 case 0x24: /* stf */
431 case 0x34: /* stfa */
432 case 0x27: /* stdf */
433 case 0x37: /* stdfa */
434 case 0x26: /* stqf */
435 case 0x36: /* stqfa */
436 case 0x25: /* stfsr */
437 case 0x3c: /* casa */
438 case 0x3e: /* casxa */
439 is_write = 1;
440 break;
441 }
442 }
443 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
444 is_write, sigmask, NULL);
445}
446
447#elif defined(__arm__)
448
7ccfb495
TN		 449#if defined(__NetBSD__)
450#include <ucontext.h>
451#endif
452
42a623c7
BS		 453int cpu_signal_handler(int host_signum, void *pinfo,
454 void *puc)
455{
456 siginfo_t *info = pinfo;
7ccfb495
TN		 457#if defined(__NetBSD__)
458 ucontext_t *uc = puc;
459#else
42a623c7 460 struct ucontext *uc = puc;
7ccfb495 461#endif
42a623c7
BS		 462 unsigned long pc;
463 int is_write;
464
7ccfb495
TN		 465#if defined(__NetBSD__)
466 pc = uc->uc_mcontext.__gregs[_REG_R15];
467#elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
42a623c7
BS		 468 pc = uc->uc_mcontext.gregs[R15];
469#else
470 pc = uc->uc_mcontext.arm_pc;
471#endif
023b0ae3
PM		 472
473 /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
474 * later processor; on v5 we will always report this as a read).
475 */
476 is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
42a623c7
BS		 477 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
478 is_write,
479 &uc->uc_sigmask, puc);
480}
481
f129061c
CF		 482#elif defined(__aarch64__)
483
661f7fa4 484int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
f129061c
CF		 485{
486 siginfo_t *info = pinfo;
487 struct ucontext *uc = puc;
661f7fa4
RH		 488 uintptr_t pc = uc->uc_mcontext.pc;
489 uint32_t insn = *(uint32_t *)pc;
490 bool is_write;
491
492 /* XXX: need kernel patch to get write flag faster. */
493 is_write = ( (insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */
494 || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */
495 || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
496 || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */
497 || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */
498 || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */
499 || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */
500 /* Ingore bits 10, 11 & 21, controlling indexing. */
501 || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
502 || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */
503 /* Ignore bits 23 & 24, controlling indexing. */
504 || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
505
506 return handle_cpu_signal(pc, (uintptr_t)info->si_addr,
f129061c
CF		 507 is_write, &uc->uc_sigmask, puc);
508}
509
42a623c7
BS		 510#elif defined(__mc68000)
511
512int cpu_signal_handler(int host_signum, void *pinfo,
513 void *puc)
514{
515 siginfo_t *info = pinfo;
516 struct ucontext *uc = puc;
517 unsigned long pc;
518 int is_write;
519
520 pc = uc->uc_mcontext.gregs[16];
521 /* XXX: compute is_write */
522 is_write = 0;
523 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
524 is_write,
525 &uc->uc_sigmask, puc);
526}
527
528#elif defined(__ia64)
529
530#ifndef __ISR_VALID
531 /* This ought to be in <bits/siginfo.h>... */
532# define __ISR_VALID 1
533#endif
534
535int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
536{
537 siginfo_t *info = pinfo;
538 struct ucontext *uc = puc;
539 unsigned long ip;
540 int is_write = 0;
541
542 ip = uc->uc_mcontext.sc_ip;
543 switch (host_signum) {
544 case SIGILL:
545 case SIGFPE:
546 case SIGSEGV:
547 case SIGBUS:
548 case SIGTRAP:
549 if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
550 /* ISR.W (write-access) is bit 33: */
551 is_write = (info->si_isr >> 33) & 1;
552 }
553 break;
554
555 default:
556 break;
557 }
558 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
559 is_write,
560 (sigset_t *)&uc->uc_sigmask, puc);
561}
562
563#elif defined(__s390__)
564
565int cpu_signal_handler(int host_signum, void *pinfo,
566 void *puc)
567{
568 siginfo_t *info = pinfo;
569 struct ucontext *uc = puc;
570 unsigned long pc;
571 uint16_t *pinsn;
572 int is_write = 0;
573
574 pc = uc->uc_mcontext.psw.addr;
575
576 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
577 of the normal 2 arguments. The 3rd argument contains the "int_code"
578 from the hardware which does in fact contain the is_write value.
579 The rt signal handler, as far as I can tell, does not give this value
580 at all. Not that we could get to it from here even if it were. */
581 /* ??? This is not even close to complete, since it ignores all
582 of the read-modify-write instructions. */
583 pinsn = (uint16_t *)pc;
584 switch (pinsn[0] >> 8) {
585 case 0x50: /* ST */
586 case 0x42: /* STC */
587 case 0x40: /* STH */
588 is_write = 1;
589 break;
590 case 0xc4: /* RIL format insns */
591 switch (pinsn[0] & 0xf) {
592 case 0xf: /* STRL */
593 case 0xb: /* STGRL */
594 case 0x7: /* STHRL */
595 is_write = 1;
596 }
597 break;
598 case 0xe3: /* RXY format insns */
599 switch (pinsn[2] & 0xff) {
600 case 0x50: /* STY */
601 case 0x24: /* STG */
602 case 0x72: /* STCY */
603 case 0x70: /* STHY */
604 case 0x8e: /* STPQ */
605 case 0x3f: /* STRVH */
606 case 0x3e: /* STRV */
607 case 0x2f: /* STRVG */
608 is_write = 1;
609 }
610 break;
611 }
612 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
613 is_write, &uc->uc_sigmask, puc);
614}
615
616#elif defined(__mips__)
617
618int cpu_signal_handler(int host_signum, void *pinfo,
619 void *puc)
620{
621 siginfo_t *info = pinfo;
622 struct ucontext *uc = puc;
623 greg_t pc = uc->uc_mcontext.pc;
624 int is_write;
625
626 /* XXX: compute is_write */
627 is_write = 0;
628 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
629 is_write, &uc->uc_sigmask, puc);
630}
631
632#elif defined(__hppa__)
633
634int cpu_signal_handler(int host_signum, void *pinfo,
635 void *puc)
636{
02d2bd5d 637 siginfo_t *info = pinfo;
42a623c7
BS		 638 struct ucontext *uc = puc;
639 unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
640 uint32_t insn = *(uint32_t *)pc;
641 int is_write = 0;
642
643 /* XXX: need kernel patch to get write flag faster. */
644 switch (insn >> 26) {
645 case 0x1a: /* STW */
646 case 0x19: /* STH */
647 case 0x18: /* STB */
648 case 0x1b: /* STWM */
649 is_write = 1;
650 break;
651
652 case 0x09: /* CSTWX, FSTWX, FSTWS */
653 case 0x0b: /* CSTDX, FSTDX, FSTDS */
654 /* Distinguish from coprocessor load ... */
655 is_write = (insn >> 9) & 1;
656 break;
657
658 case 0x03:
659 switch ((insn >> 6) & 15) {
660 case 0xa: /* STWS */
661 case 0x9: /* STHS */
662 case 0x8: /* STBS */
663 case 0xe: /* STWAS */
664 case 0xc: /* STBYS */
665 is_write = 1;
666 }
667 break;
668 }
669
670 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
671 is_write, &uc->uc_sigmask, puc);
672}
673
674#else
675
676#error host CPU specific signal handler needed
677
678#endif
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