[mirror_qemu.git] / util / bufferiszero.c

/*
 * Simple C functions to supplement the C library
 *
 * Copyright (c) 2006 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "qemu/osdep.h"
#include "qemu-common.h"
#include "qemu/cutils.h"
#include "qemu/bswap.h"

static bool
buffer_zero_int(const void *buf, size_t len)
{
    if (unlikely(len < 8)) {
        /* For a very small buffer, simply accumulate all the bytes.  */
        const unsigned char *p = buf;
        const unsigned char *e = buf + len;
        unsigned char t = 0;

        do {
            t |= *p++;
        } while (p < e);

        return t == 0;
    } else {
        /* Otherwise, use the unaligned memory access functions to
           handle the beginning and end of the buffer, with a couple
           of loops handling the middle aligned section.  */
        uint64_t t = ldq_he_p(buf);
        const uint64_t *p = (uint64_t *)(((uintptr_t)buf + 8) & -8);
        const uint64_t *e = (uint64_t *)(((uintptr_t)buf + len) & -8);

        for (; p + 8 <= e; p += 8) {
            __builtin_prefetch(p + 8);
            if (t) {
                return false;
            }
            t = p[0] | p[1] | p[2] | p[3] | p[4] | p[5] | p[6] | p[7];
        }
        while (p < e) {
            t |= *p++;
        }
        t |= ldq_he_p(buf + len - 8);

        return t == 0;
    }
}

#if defined(CONFIG_AVX2_OPT) || defined(__SSE2__)
/* Do not use push_options pragmas unnecessarily, because clang
 * does not support them.
 */
#ifdef CONFIG_AVX2_OPT
#pragma GCC push_options
#pragma GCC target("sse2")
#endif
#include <emmintrin.h>

/* Note that each of these vectorized functions require len >= 64.  */

static bool
buffer_zero_sse2(const void *buf, size_t len)
{
    __m128i t = _mm_loadu_si128(buf);
    __m128i *p = (__m128i *)(((uintptr_t)buf + 5 * 16) & -16);
    __m128i *e = (__m128i *)(((uintptr_t)buf + len) & -16);
    __m128i zero = _mm_setzero_si128();

    /* Loop over 16-byte aligned blocks of 64.  */
    while (likely(p <= e)) {
        __builtin_prefetch(p);
        t = _mm_cmpeq_epi8(t, zero);
        if (unlikely(_mm_movemask_epi8(t) != 0xFFFF)) {
            return false;
        }
        t = p[-4] | p[-3] | p[-2] | p[-1];
        p += 4;
    }

    /* Finish the aligned tail.  */
    t |= e[-3];
    t |= e[-2];
    t |= e[-1];

    /* Finish the unaligned tail.  */
    t |= _mm_loadu_si128(buf + len - 16);

    return _mm_movemask_epi8(_mm_cmpeq_epi8(t, zero)) == 0xFFFF;
}
#ifdef CONFIG_AVX2_OPT
#pragma GCC pop_options
#endif

#ifdef CONFIG_AVX2_OPT
/* Note that due to restrictions/bugs wrt __builtin functions in gcc <= 4.8,
 * the includes have to be within the corresponding push_options region, and
 * therefore the regions themselves have to be ordered with increasing ISA.
 */
#pragma GCC push_options
#pragma GCC target("sse4")
#include <smmintrin.h>

static bool
buffer_zero_sse4(const void *buf, size_t len)
{
    __m128i t = _mm_loadu_si128(buf);
    __m128i *p = (__m128i *)(((uintptr_t)buf + 5 * 16) & -16);
    __m128i *e = (__m128i *)(((uintptr_t)buf + len) & -16);

    /* Loop over 16-byte aligned blocks of 64.  */
    while (likely(p <= e)) {
        __builtin_prefetch(p);
        if (unlikely(!_mm_testz_si128(t, t))) {
            return false;
        }
        t = p[-4] | p[-3] | p[-2] | p[-1];
        p += 4;
    }

    /* Finish the aligned tail.  */
    t |= e[-3];
    t |= e[-2];
    t |= e[-1];

    /* Finish the unaligned tail.  */
    t |= _mm_loadu_si128(buf + len - 16);

    return _mm_testz_si128(t, t);
}

#pragma GCC pop_options
#pragma GCC push_options
#pragma GCC target("avx2")
#include <immintrin.h>

static bool
buffer_zero_avx2(const void *buf, size_t len)
{
    /* Begin with an unaligned head of 32 bytes.  */
    __m256i t = _mm256_loadu_si256(buf);
    __m256i *p = (__m256i *)(((uintptr_t)buf + 5 * 32) & -32);
    __m256i *e = (__m256i *)(((uintptr_t)buf + len) & -32);

    if (likely(p <= e)) {
        /* Loop over 32-byte aligned blocks of 128.  */
        do {
            __builtin_prefetch(p);
            if (unlikely(!_mm256_testz_si256(t, t))) {
                return false;
            }
            t = p[-4] | p[-3] | p[-2] | p[-1];
            p += 4;
        } while (p <= e);
    } else {
        t |= _mm256_loadu_si256(buf + 32);
        if (len <= 128) {
            goto last2;
        }
    }

    /* Finish the last block of 128 unaligned.  */
    t |= _mm256_loadu_si256(buf + len - 4 * 32);
    t |= _mm256_loadu_si256(buf + len - 3 * 32);
 last2:
    t |= _mm256_loadu_si256(buf + len - 2 * 32);
    t |= _mm256_loadu_si256(buf + len - 1 * 32);

    return _mm256_testz_si256(t, t);
}
#pragma GCC pop_options
#endif /* CONFIG_AVX2_OPT */

/* Note that for test_buffer_is_zero_next_accel, the most preferred
 * ISA must have the least significant bit.
 */
#define CACHE_AVX2    1
#define CACHE_SSE4    2
#define CACHE_SSE2    4

/* Make sure that these variables are appropriately initialized when
 * SSE2 is enabled on the compiler command-line, but the compiler is
 * too old to support <cpuid.h>.
 */
#ifdef CONFIG_AVX2_OPT
# define INIT_CACHE 0
# define INIT_ACCEL buffer_zero_int
#else
# ifndef __SSE2__
#  error "ISA selection confusion"
# endif
# define INIT_CACHE CACHE_SSE2
# define INIT_ACCEL buffer_zero_sse2
#endif

static unsigned cpuid_cache = INIT_CACHE;
static bool (*buffer_accel)(const void *, size_t) = INIT_ACCEL;

static void init_accel(unsigned cache)
{
    bool (*fn)(const void *, size_t) = buffer_zero_int;
    if (cache & CACHE_SSE2) {
        fn = buffer_zero_sse2;
    }
#ifdef CONFIG_AVX2_OPT
    if (cache & CACHE_SSE4) {
        fn = buffer_zero_sse4;
    }
    if (cache & CACHE_AVX2) {
        fn = buffer_zero_avx2;
    }
#endif
    buffer_accel = fn;
}

#ifdef CONFIG_AVX2_OPT
#include <cpuid.h>
static void __attribute__((constructor)) init_cpuid_cache(void)
{
    int max = __get_cpuid_max(0, NULL);
    int a, b, c, d;
    unsigned cache = 0;

    if (max >= 1) {
        __cpuid(1, a, b, c, d);
        if (d & bit_SSE2) {
            cache |= CACHE_SSE2;
        }
#ifdef CONFIG_AVX2_OPT
        if (c & bit_SSE4_1) {
            cache |= CACHE_SSE4;
        }

        /* We must check that AVX is not just available, but usable.  */
        if ((c & bit_OSXSAVE) && (c & bit_AVX) && max >= 7) {
            int bv;
            __asm("xgetbv" : "=a"(bv), "=d"(d) : "c"(0));
            __cpuid_count(7, 0, a, b, c, d);
            if ((bv & 6) == 6 && (b & bit_AVX2)) {
                cache |= CACHE_AVX2;
            }
        }
#endif
    }
    cpuid_cache = cache;
    init_accel(cache);
}
#endif /* CONFIG_AVX2_OPT */

bool test_buffer_is_zero_next_accel(void)
{
    /* If no bits set, we just tested buffer_zero_int, and there
       are no more acceleration options to test.  */
    if (cpuid_cache == 0) {
        return false;
    }
    /* Disable the accelerator we used before and select a new one.  */
    cpuid_cache &= cpuid_cache - 1;
    init_accel(cpuid_cache);
    return true;
}

static bool select_accel_fn(const void *buf, size_t len)
{
    if (likely(len >= 64)) {
        return buffer_accel(buf, len);
    }
    return buffer_zero_int(buf, len);
}

#else
#define select_accel_fn  buffer_zero_int
bool test_buffer_is_zero_next_accel(void)
{
    return false;
}
#endif

/*
 * Checks if a buffer is all zeroes
 */
bool buffer_is_zero(const void *buf, size_t len)
{
    if (unlikely(len == 0)) {
        return true;
    }

    /* Fetch the beginning of the buffer while we select the accelerator.  */
    __builtin_prefetch(buf);

    /* Use an optimized zero check if possible.  Note that this also
       includes a check for an unrolled loop over 64-bit integers.  */
    return select_accel_fn(buf, len);
}
Commit	Line	Data
88ca8e80 RH	1	/*
	2	* Simple C functions to supplement the C library
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "qemu/osdep.h"
	25	#include "qemu-common.h"
	26	#include "qemu/cutils.h"
5e33a872	27	#include "qemu/bswap.h"
88ca8e80	28
5e33a872 RH	29	static bool
	30	buffer_zero_int(const void *buf, size_t len)
	31	{
	32	if (unlikely(len < 8)) {
	33	/* For a very small buffer, simply accumulate all the bytes. */
	34	const unsigned char *p = buf;
	35	const unsigned char *e = buf + len;
	36	unsigned char t = 0;
	37
	38	do {
	39	t \|= *p++;
	40	} while (p < e);
	41
	42	return t == 0;
	43	} else {
	44	/* Otherwise, use the unaligned memory access functions to
	45	handle the beginning and end of the buffer, with a couple
	46	of loops handling the middle aligned section. */
	47	uint64_t t = ldq_he_p(buf);
	48	const uint64_t p = (uint64_t )(((uintptr_t)buf + 8) & -8);
	49	const uint64_t e = (uint64_t )(((uintptr_t)buf + len) & -8);
	50
	51	for (; p + 8 <= e; p += 8) {
	52	__builtin_prefetch(p + 8);
	53	if (t) {
	54	return false;
	55	}
	56	t = p[0] \| p[1] \| p[2] \| p[3] \| p[4] \| p[5] \| p[6] \| p[7];
	57	}
	58	while (p < e) {
	59	t \|= *p++;
	60	}
	61	t \|= ldq_he_p(buf + len - 8);
	62
	63	return t == 0;
	64	}
	65	}
	66
d9911d14	67	#if defined(CONFIG_AVX2_OPT) \|\| defined(__SSE2__)
5e33a872 RH	68	/* Do not use push_options pragmas unnecessarily, because clang
	69	* does not support them.
	70	*/
d9911d14	71	#ifdef CONFIG_AVX2_OPT
5e33a872 RH	72	#pragma GCC push_options
	73	#pragma GCC target("sse2")
	74	#endif
	75	#include <emmintrin.h>
d9911d14 RH	76
	77	/* Note that each of these vectorized functions require len >= 64. */
	78
	79	static bool
	80	buffer_zero_sse2(const void *buf, size_t len)
	81	{
	82	__m128i t = _mm_loadu_si128(buf);
	83	__m128i p = (__m128i )(((uintptr_t)buf + 5 * 16) & -16);
	84	__m128i e = (__m128i )(((uintptr_t)buf + len) & -16);
	85	__m128i zero = _mm_setzero_si128();
	86
	87	/* Loop over 16-byte aligned blocks of 64. */
	88	while (likely(p <= e)) {
	89	__builtin_prefetch(p);
	90	t = _mm_cmpeq_epi8(t, zero);
	91	if (unlikely(_mm_movemask_epi8(t) != 0xFFFF)) {
	92	return false;
	93	}
	94	t = p[-4] \| p[-3] \| p[-2] \| p[-1];
	95	p += 4;
	96	}
	97
	98	/* Finish the aligned tail. */
	99	t \|= e[-3];
	100	t \|= e[-2];
	101	t \|= e[-1];
	102
	103	/* Finish the unaligned tail. */
	104	t \|= _mm_loadu_si128(buf + len - 16);
	105
	106	return _mm_movemask_epi8(_mm_cmpeq_epi8(t, zero)) == 0xFFFF;
	107	}
	108	#ifdef CONFIG_AVX2_OPT
5e33a872 RH	109	#pragma GCC pop_options
5e33a872 RH	110	#endif
88ca8e80	111
5e33a872	112	#ifdef CONFIG_AVX2_OPT
d9911d14 RH	113	/* Note that due to restrictions/bugs wrt __builtin functions in gcc <= 4.8,
	114	* the includes have to be within the corresponding push_options region, and
	115	* therefore the regions themselves have to be ordered with increasing ISA.
	116	*/
86444f08 PB	117	#pragma GCC push_options
	118	#pragma GCC target("sse4")
	119	#include <smmintrin.h>
86444f08	120
d9911d14 RH	121	static bool
	122	buffer_zero_sse4(const void *buf, size_t len)
	123	{
	124	__m128i t = _mm_loadu_si128(buf);
	125	__m128i p = (__m128i )(((uintptr_t)buf + 5 * 16) & -16);
	126	__m128i e = (__m128i )(((uintptr_t)buf + len) & -16);
	127
	128	/* Loop over 16-byte aligned blocks of 64. */
	129	while (likely(p <= e)) {
	130	__builtin_prefetch(p);
	131	if (unlikely(!_mm_testz_si128(t, t))) {
	132	return false;
	133	}
	134	t = p[-4] \| p[-3] \| p[-2] \| p[-1];
	135	p += 4;
	136	}
	137
	138	/* Finish the aligned tail. */
	139	t \|= e[-3];
	140	t \|= e[-2];
	141	t \|= e[-1];
	142
	143	/* Finish the unaligned tail. */
	144	t \|= _mm_loadu_si128(buf + len - 16);
	145
	146	return _mm_testz_si128(t, t);
	147	}
	148
	149	#pragma GCC pop_options
88ca8e80 RH	150	#pragma GCC push_options
88ca8e80 RH	151	#pragma GCC target("avx2")
88ca8e80	152	#include <immintrin.h>
d9911d14 RH	153
	154	static bool
	155	buffer_zero_avx2(const void *buf, size_t len)
	156	{
	157	/* Begin with an unaligned head of 32 bytes. */
	158	__m256i t = _mm256_loadu_si256(buf);
	159	__m256i p = (__m256i )(((uintptr_t)buf + 5 * 32) & -32);
	160	__m256i e = (__m256i )(((uintptr_t)buf + len) & -32);
	161
	162	if (likely(p <= e)) {
	163	/* Loop over 32-byte aligned blocks of 128. */
	164	do {
	165	__builtin_prefetch(p);
	166	if (unlikely(!_mm256_testz_si256(t, t))) {
	167	return false;
	168	}
	169	t = p[-4] \| p[-3] \| p[-2] \| p[-1];
	170	p += 4;
	171	} while (p <= e);
	172	} else {
	173	t \|= _mm256_loadu_si256(buf + 32);
	174	if (len <= 128) {
	175	goto last2;
	176	}
	177	}
	178
	179	/* Finish the last block of 128 unaligned. */
	180	t \|= _mm256_loadu_si256(buf + len - 4 * 32);
	181	t \|= _mm256_loadu_si256(buf + len - 3 * 32);
	182	last2:
	183	t \|= _mm256_loadu_si256(buf + len - 2 * 32);
	184	t \|= _mm256_loadu_si256(buf + len - 1 * 32);
	185
	186	return _mm256_testz_si256(t, t);
	187	}
5e33a872	188	#pragma GCC pop_options
d9911d14 RH	189	#endif /* CONFIG_AVX2_OPT */
	190
	191	/* Note that for test_buffer_is_zero_next_accel, the most preferred
	192	* ISA must have the least significant bit.
	193	*/
	194	#define CACHE_AVX2 1
	195	#define CACHE_SSE4 2
	196	#define CACHE_SSE2 4
	197
	198	/* Make sure that these variables are appropriately initialized when
	199	* SSE2 is enabled on the compiler command-line, but the compiler is
	200	* too old to support <cpuid.h>.
	201	*/
	202	#ifdef CONFIG_AVX2_OPT
	203	# define INIT_CACHE 0
	204	# define INIT_ACCEL buffer_zero_int
	205	#else
	206	# ifndef __SSE2__
	207	# error "ISA selection confusion"
	208	# endif
	209	# define INIT_CACHE CACHE_SSE2
	210	# define INIT_ACCEL buffer_zero_sse2
5e33a872	211	#endif
88ca8e80	212
d9911d14 RH	213	static unsigned cpuid_cache = INIT_CACHE;
d9911d14 RH	214	static bool (buffer_accel)(const void , size_t) = INIT_ACCEL;
88ca8e80	215
d9911d14 RH	216	static void init_accel(unsigned cache)
	217	{
	218	bool (fn)(const void , size_t) = buffer_zero_int;
	219	if (cache & CACHE_SSE2) {
	220	fn = buffer_zero_sse2;
	221	}
	222	#ifdef CONFIG_AVX2_OPT
	223	if (cache & CACHE_SSE4) {
	224	fn = buffer_zero_sse4;
	225	}
	226	if (cache & CACHE_AVX2) {
	227	fn = buffer_zero_avx2;
	228	}
	229	#endif
	230	buffer_accel = fn;
	231	}
88ca8e80	232
d9911d14 RH	233	#ifdef CONFIG_AVX2_OPT
d9911d14 RH	234	#include <cpuid.h>
5e33a872	235	static void __attribute__((constructor)) init_cpuid_cache(void)
88ca8e80	236	{
5e33a872 RH	237	int max = __get_cpuid_max(0, NULL);
	238	int a, b, c, d;
	239	unsigned cache = 0;
88ca8e80	240
5e33a872 RH	241	if (max >= 1) {
	242	__cpuid(1, a, b, c, d);
	243	if (d & bit_SSE2) {
	244	cache \|= CACHE_SSE2;
	245	}
	246	#ifdef CONFIG_AVX2_OPT
	247	if (c & bit_SSE4_1) {
	248	cache \|= CACHE_SSE4;
88ca8e80	249	}
88ca8e80	250
5e33a872	251	/* We must check that AVX is not just available, but usable. */
d9911d14 RH	252	if ((c & bit_OSXSAVE) && (c & bit_AVX) && max >= 7) {
	253	int bv;
	254	__asm("xgetbv" : "=a"(bv), "=d"(d) : "c"(0));
	255	__cpuid_count(7, 0, a, b, c, d);
	256	if ((bv & 6) == 6 && (b & bit_AVX2)) {
	257	cache \|= CACHE_AVX2;
5e33a872	258	}
88ca8e80	259	}
5e33a872	260	#endif
88ca8e80	261	}
5e33a872	262	cpuid_cache = cache;
d9911d14	263	init_accel(cache);
88ca8e80	264	}
d9911d14	265	#endif /* CONFIG_AVX2_OPT */
88ca8e80	266
efad6682 RH	267	bool test_buffer_is_zero_next_accel(void)
	268	{
	269	/* If no bits set, we just tested buffer_zero_int, and there
	270	are no more acceleration options to test. */
	271	if (cpuid_cache == 0) {
	272	return false;
	273	}
	274	/* Disable the accelerator we used before and select a new one. */
	275	cpuid_cache &= cpuid_cache - 1;
d9911d14	276	init_accel(cpuid_cache);
efad6682 RH	277	return true;
	278	}
	279
5e33a872	280	static bool select_accel_fn(const void *buf, size_t len)
88ca8e80	281	{
d9911d14 RH	282	if (likely(len >= 64)) {
d9911d14 RH	283	return buffer_accel(buf, len);
5e33a872 RH	284	}
5e33a872 RH	285	return buffer_zero_int(buf, len);
88ca8e80 RH	286	}
88ca8e80 RH	287
5e33a872 RH	288	#else
5e33a872 RH	289	#define select_accel_fn buffer_zero_int
efad6682 RH	290	bool test_buffer_is_zero_next_accel(void)
	291	{
	292	return false;
	293	}
	294	#endif
	295
88ca8e80 RH	296	/*
88ca8e80 RH	297	* Checks if a buffer is all zeroes
88ca8e80 RH	298	*/
	299	bool buffer_is_zero(const void *buf, size_t len)
	300	{
5e33a872 RH	301	if (unlikely(len == 0)) {
5e33a872 RH	302	return true;
88ca8e80 RH	303	}
88ca8e80 RH	304
083d012a RH	305	/* Fetch the beginning of the buffer while we select the accelerator. */
	306	__builtin_prefetch(buf);
	307
5e33a872 RH	308	/* Use an optimized zero check if possible. Note that this also
	309	includes a check for an unrolled loop over 64-bit integers. */
	310	return select_accel_fn(buf, len);
88ca8e80	311	}