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[rustc.git] / vendor / packed_simd / src / codegen / reductions / mask / arm.rs
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1//! Mask reductions implementation for `arm` targets
2
3/// Implementation for ARM + v7 + NEON for 64-bit or 128-bit wide vectors with
4/// more than two elements.
5macro_rules! arm_128_v7_neon_impl {
6 ($id:ident, $half:ident, $vpmin:ident, $vpmax:ident) => {
7 impl All for $id {
8 #[inline]
9 #[target_feature(enable = "v7,neon")]
10 unsafe fn all(self) -> bool {
11 use crate::arch::arm::$vpmin;
12 use crate::mem::transmute;
13 union U {
14 halves: ($half, $half),
15 vec: $id,
16 }
17 let halves = U { vec: self }.halves;
18 let h: $half = transmute($vpmin(
19 transmute(halves.0),
20 transmute(halves.1),
21 ));
22 h.all()
23 }
24 }
25 impl Any for $id {
26 #[inline]
27 #[target_feature(enable = "v7,neon")]
28 unsafe fn any(self) -> bool {
29 use crate::arch::arm::$vpmax;
30 use crate::mem::transmute;
31 union U {
32 halves: ($half, $half),
33 vec: $id,
34 }
35 let halves = U { vec: self }.halves;
36 let h: $half = transmute($vpmax(
37 transmute(halves.0),
38 transmute(halves.1),
39 ));
40 h.any()
41 }
42 }
43 };
44}
45
46/// Mask reduction implementation for `arm` targets
47macro_rules! impl_mask_reductions {
48 // 128-bit wide masks
49 (m8x16) => { arm_128_v7_neon_impl!(m8x16, m8x8, vpmin_u8, vpmax_u8); };
50 (m16x8) => { arm_128_v7_neon_impl!(m16x8, m16x4, vpmin_u16, vpmax_u16); };
51 (m32x4) => { arm_128_v7_neon_impl!(m32x4, m32x2, vpmin_u32, vpmax_u32); };
52 // Fallback to LLVM's default code-generation:
53 ($id:ident) => { fallback_impl!($id); };
54}